T7800

T7100 INTEL | Alldatasheet

Document overview

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• PDF pages: 87

Technical content

Datasheet sections

• 1.1 Terminology
• 1.2 References
• 2 Low Power Features
• 2.1 Clock Control and Low Power States
• 2.1.1 Core Low Power State Descriptions
• 2.1.2 Package Low Power State Descriptions
• 2.2 Enhanced Intel SpeedStep® Technology
• 2.2.1 Dynamic FSB Frequency Switching
• 2.2.2 Intel® Dynamic Acceleration Technology
• 2.3 Extended Low Power States
• 2.4 FSB Low Power Enhancements
• 2.5 VID-x
• 2.6 Processor Power Status Indicator (PSI-2) Signal
• 3 Electrical Specifications
• 3.1 Power and Ground Pins
• 3.2 FSB Clock (BCLK[1:0]) and Processor Clocking
• 3.3 Voltage Identification
• 3.4 Catastrophic Thermal Protection
• 3.5 Reserved and Unused Pins
• 3.6 FSB Frequency Select Signals (BSEL[2:0])
• 3.7 FSB Signal Groups
• 3.8 CMOS Signals
• 3.9 Maximum Ratings
• 3.10 Processor DC Specifications
• 4 Package Mechanical Specific ations and Pin Information
• 4.1 Package Mechanical Specifications
• 4.2 Processor Pinout and Pin List
• 4.3 Alphabetical Signals Reference
• 5 Thermal Specifications and Design Considerations
• 5.1 Thermal Specifications
• 5.1.1 Thermal Diode
• 5.1.2 Thermal Diode Offset
• 5.1.3 Intel® Thermal Monitor
• 5.1.4 Digital Thermal Sensor
• 5.1.5 Out of Specification Detection
• 5.1.6 PROCHOT# Signal Pin

Intel® Core™2 Duo Processors and Intel® Core™2 Extreme Processors for Platforms Based on Mobile Intel®

965 Express Chipset Family

Document Number: 316745-005

2 Datasheet

Legal Lines and Disclaimers INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information. The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality. Enhanced Intel SpeedStep® Technology for specified units of this processor available Q2/06. See the Processor Spec Finder at http:// processorfinder.intel.com or contact your Intel representative for more information. Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) and, for some uses, certain platform software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update. Software applications may not be compatible with all operating systems. Please check with your application vendor. This device is protected by U.S. patent numbers 5,315,448 and 6,516,132, and other intellectual property rights. The use of Macrovision's copy protection technology in the device must be authorized by Macrovision and is intended for home and other limited pay-per-view uses only, unless otherwise authorized in writing by Macrovision. Reverse engineering or disassembly is prohibited. 64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled for Intel® 64 architecture. Processors will not operate (including 32-bit operation) without an Intel® 64 architecture-enabled BIOS. Performance will vary depending on your hardware and software configurations. Consult with your system vendor for more information. Intel, Pentium, Intel Core, Intel Core 2, Intel SpeedStep and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2007 - 2008, Intel Corporation. All rights reserved.

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3 Active VCC and ICC Loadline Intel Core 2 Duo Processors - Standard Voltage,

Low Voltage and Ultra Low Voltage and Intel Core 2 Extreme Processors |

4 Deeper Sleep VCC and ICC Loadline Intel Core 2 Duo Processors -

5 Deeper Sleep VCC and ICC Loadlin e Intel Core 2 Duo Processor -

6 Voltage and Current Specifications for the Intel Core 2 Duo Processors -

7 Voltage and Current Specifications for the Intel Core 2 Duo Processors -

8 Voltage and Current Specifications for the Intel Core 2 Duo -Ultra Low

14 The Coordinates of the Processor Pins as Viewed from the Top of the Package

15 The Coordinates of the Processor Pins as Viewed from the Top of the Package

Revision History

316745 -001 • Initial Release May 2007 316745 -002

• Updates — Chapter 1 added Intel® Core™2 Duo processor - Ultra Low Voltage information — Chapter 3 added Table 8 with Intel Core 2 Duo processor - Ultra Low Voltage U7600 and U7500 specifications — Chapter 3 updated Figure 3 and 5 with Intel Core 2 Duo processor - Ultra Low Voltage information — Chapter 5 added Table 19 with Intel Core 2 Duo processor -Ultra Low Voltage U7600 and U7500 specifications June 2007 316745 -003
• Updates — Chapter 1 added Intel® Core™2 Extreme processor — Chapter 3 added Table 9 with Intel Core 2 Extreme processor X7800 specifications — Chapter 3 updated Figure 3 and 4 with Intel Core 2 Extreme processor information — Chapter 5 added Table 20 wi th Intel Core 2 Extreme processor X7800 specifications — Corrected the pin diagram for 4-MB Micro-FCPGA and 2-MB Micro-FCPGA Processor Package Drawings July 2007 316745 -004
• Updates — Chapter 3 added Intel Core 2 Extreme processor X7900 and Low Voltage processor L7700 specifications — Chapter 5 added Intel Core 2 Extreme processor X7900 and Low Voltage processor L7700 specifications August 2007 316745 -005
• Updates — Chapter 3 added Table 8 with Intel Core 2 Duo processor - Ultra Low Voltage U7700 specifications — Chapter 5 added Table 21 with Intel Core 2 Duo processor -Ultra Low Voltage U7700 specifications January 2007

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1 Introduction

The Intel® Core™2 Duo processor on 65-nm process technology is the next generation high-performance, low-power processor based on the Intel® Core™ microarchitecture. The Intel Core 2 Duo processor supports the Mobile Intel® 965 Express Chipset and Intel® 82801HBM ICH8M Controller Hub Based Systems. This document contains electrical, mechanical and thermal specifications for the following processors:

• Intel Core 2 Duo processor - Standard Voltage
• Intel Core 2 Duo processor - Low Voltage
• Intel Core 2 Duo processor - Ultra Low Voltage
• Intel Core 2 Extreme processor Note: In this document, the Intel Core 2 Duo and Intel Core 2 Extreme processors are referred to as the processor and Mobile Intel® 965 Express Chipset family is referred to as the (G)MCH. The following list provides some of the key features on this processor:
• Dual core processor for mobile with enhanced performance
• Intel architecture with Intel® Wide Dynamic Execution
• L1 Cache to Cache (C2C) transfer
• On-die, primary 32-KB instruction cache and 32-KB write-back data cache in each core
• On-die, up to 4-MB second level shared cache with advanced transfer cache architecture
• Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3) and Supplemental Streaming SIMD Extensions 3 (SSSE3)
• 800-MHz Source-Synchronous Front Side Bus (FSB) for Intel Core 2 Extreme processors, Intel Core 2 Duo standard and low voltage processors. 533-MHz FSB for Intel Core 2 Duo ultra low voltage processors
• Advanced power management features including Enhanced Intel SpeedStep® Technology and Dynamic FSB frequency switching.
• Intel Enhanced Deeper Sleep state with P_LVL5 I/O support
• Digital Thermal Sensor (DTS)
• Intel® 64 Technology
• Enhanced Intel® Virtualization Technology
• Intel® Dynamic Acceleration Technology
• Enhanced Multi Threaded Thermal Management (EMTTM)
• PSI2 functionality
• Standard voltage processors are offered in Micro-FCPGA and Micro-FCBGA packaging. Low voltage and Ultra low voltage processors are offered in Micro- FCBGA packaging only. Intel Core 2 Extreme processors are offered in Micro-FCPGA packaging only.
• Execute Disable Bit support for enhanced security

8 Datasheet

1.1 Terminology

A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the “#” symbol implies that the signal is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and D[3:0]# = “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level). XXXX means that the specification or value is yet to be determined. Front Side Bus (FSB) Refers to the interface between the processor and system core logic (also known as the chipset components). AGTL+ Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+ signaling technology on some Intel processors. Storage Conditions Refers to a non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor landings should not be connected to any supply voltages, have any I/Os biased or receive any clocks. Upon exposure to “free air” (i.e., unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material. Enhanced Intel SpeedStep® Technology Technology that provides power management capabilities to laptops. Processor Core Processor core die with integrated L1 and L2 cache. All AC timing and signal integrity specifications are at the pads of the processor core. Intel® 64 Technology 64-bit memory extensions to the IA-32 architecture. Intel® Virtualization Technology Processor virtualization which when used in conjunction with Virtual Machine Monitor software enables multiple, robust independent software environments inside a single platform. TDP Thermal Design Power V CC The processor core power supply VSS The processor ground

1.2 References

Material and concepts available in the following documents may be beneficial when reading this document. NOTES: 1. Contact your local Intel representative fo r the latest revision of this document. Document Document Number 1,2 Intel® Core™ 2 Duo Proc essors For Intel® Centrino® Duo Processor Technology Specification Update 314079 Mobile Intel® 965 Express Chipset Family Datasheet 316273 Mobile Intel® 965 Express Chipset Family Specification Update 316274 Intel® I/O Controller Hub 8 (ICH8)/ I/O Controller Hub 8M (ICH8M) Datasheet See http:// www.intel.com/design/ chipsets/datashts/ 313056.htm Intel® I/O Controller Hub 8 (ICH8)/ I/O Controller Hub 8M (ICH8M) Specification Update See http:// www.intel.com/design/ chipsets/specupdt/ 313057.htm Intel® 64 and IA-32 Architectures Software Developer’s Manual See http:// www.intel.com/design/ pentium4/manuals/ index_new.htm Intel® 64 and IA-32 Architectures Software Developer's Manuals Documentation Change See http:// developer.intel.com/ design/processor/ specupdt/252046.htm Volume 1: Basic Architecture 253665 Volume 2A: Instruction Set Reference, A-M 253666 Volume 2B: Instruction Set Reference, N-Z 253667 Volume 3A: System Programming Guide 253668 Volume 3B: System Programming Guide 253669

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2 Low Power Features

2.1 Clock Control and Low Power States

The processor supports low power states both at the individual core level and the package level for optimal power management. A core may independently enter the C1/AutoHALT, C1/MWAIT, C2, C3, and C4 low power states. When both cores coincide in a common core low power state, the central power management logic ensures that the entire processor enters the respective package low power state by initiating a P_LVLx (P_LVL2, P_LVL3, P_LVL4, or P_LVL5) I/O read to the chipset. The processor implements two software interfaces for requesting low power states: MWAIT instruction extensions with sub-state hints or P_LVLx reads to the ACPI P_BLK register block mapped in the processor’s I/O address space. The P_LVLx I/O reads are converted to equivalent MWAIT C-state requests inside the processor and do not directly result in I/O reads on the processor FSB. The P_LVLx I/O monitor address does not need to be set up before using the P_LVLx I/O read interface. The sub-state hints used for each P_LVLx read can be configured through the Model Specific Register (MSR). If a core encounters a chipset break event while STPCLK# is asserted, then it asserts the PBE# output signal. Assertion of PBE# when STPCLK# is asserted indicates to system logic that individual cores should return to the C0 state and the processor should return to the Normal state. Figure 1 shows the core low power states and Figure 2 shows the package low power states. Table 1 maps the core low power states to the package low power states.

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Figure 1. Core Low Power States † — STPCLK# assertion and de-assertion have no effect if a core is in C2, C3, or C4. ‡ — Core C4 state supports the package level Intel Enhanced Deeper Sleep state. Ø — P_LVL5 read is issued once the L2 cache is reduced to zero.

2.1.1 Core Low Power State Descriptions

2.1.1.1 Core C0 State

This is the normal operating state for cores in the processor.

2.1.1.2 Core C1/AutoHALT Powerdown State

C1/AutoHALT is a low power state entered when a core executes the HALT instruction. Figure 2. Package Low Power States Table 1. Coordination of Core Low Power States at the Package Level † — Deeper Sleep includes the Deeper Sleep state and Intel Enhanced Deeper Sleep state.

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A System Management Interrupt (SMI) handler returns execution to either Normal state or the AutoHALT Powerdown state. See the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A/3B: System Programmer's Guide for more information. The system can generate a STPCLK# while the processor is in the AutoHALT Powerdown state. When the system deasserts the STPCLK# interrupt, the processor returns execution to the HALT state. While in AutoHALT Powerdown state, the dual core processor processes bus snoops and snoops from the other core. The processor enters a snoopable sub-state (not shown in Figure 1) to process the snoop and then return to the AutoHALT Powerdown state.

2.1.1.3 Core C1/MWAIT Powerdown State

C1/MWAIT is a low power state entered when the processor core executes the MWAIT(C1) instruction. Processor behavior in the MWAIT state is identical to the AutoHALT state except that Monitor events can cause the processor core to return to the C0 state. See the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A: Instruction Set Reference, A-M and Volume 2B: Instruction Set Reference, N-Z, for more information.

2.1.1.4 Core C2 State

Individual cores of the dual core processor can enter the C2 state by initiating a P_LVL2 I/O read to the P_BLK or an MWAIT(C2) instruction, but the processor does not issue a Stop-Grant Acknowledge special bus cycle unless the STPCLK# pin is also asserted. While in the C2 state, the dual core processor processes bus snoops and snoops from the other core. The processor enters a snoopable sub-state (not shown in Figure 1) to process the snoop and then return to the C2 state.

2.1.1.5 Core C3 State

Individual cores of the dual core processor can enter the C3 state by initiating a P_LVL3 I/O read to the P_BLK or an MWAIT(C3) instruction. Before entering C3, the processor core flushes the contents of its L1 caches into the processor’s L2 cache. Except for the caches, the processor core maintains all its architectural state in the C3 state. The monitor remains armed if it is configured. All of the clocks in the processor core are stopped in the C3 state. Because the core’s caches are flushed the processor keeps the core in the C3 state when the processor detects a snoop on the FSB or when the other core of the dual core processor accesses cacheable memory. The processor core transitions to the C0 state upon occurrence of a Monitor event, SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# causes the processor to immediately initialize itself.

2.1.1.6 Core C4 State

Individual cores of the dual core processor can enter the C4 state by initiating a P_LVL4 I/O read to the P_BLK or an MWAIT(C4) instruction. The processor core behavior in the C4 state is nearly identical to the behavior in the C3 state. The only difference is that if both processor cores are in C4, then the central power management logic requests that the entire processor enter the Deeper Sleep package low power state (see Section 2.1.2.6). To enable the package level Intel Enhanced Deeper Sleep state, Dynamic Cache Sizing and Intel Enhanced Deeper Sleep state fields must be configured in the software programmable MSR. Refer to Section 2.1.2.6 for further details on Intel Enhanced Deeper Sleep state.

2.1.2 Package Low Power State Descriptions

2.1.2.1 Normal State

This is the normal operating state for the processor. The processor remains in the Normal state when at least one of its cores is in the C0, C1/AutoHALT, or C1/MWAIT state.

2.1.2.2 Stop-Grant State

When the STPCLK# pin is asserted by the chipset, each core of the dual core processor enters the Stop-Grant state within 20-bus clocks after the response phase of the processor-issued Stop-Grant Acknowledge special bus cycle. Processor cores that are already in the C2, C3, or C4 state remain in their current low power state. When the STPCLK# pin is deasserted, each core returns to its previous core low power state. Since the AGTL+ signal pins receive power from the FSB, these pins should not be driven (allowing the level to return to V CCP) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the FSB should be driven to the inactive state. RESET# causes the processor to immediately initialize itself, but the processor stays in Stop-Grant state. When RESET# is asserted by the system, the STPCLK#, SLP#, DPSLP#, and DPRSTP# pins must be deasserted prior to RESET# deassertion. When re-entering the Stop-Grant state from the Sleep state, STPCLK# should be deasserted after the deassertion of SLP#. While in Stop-Grant state, the processor services snoops and latch interrupts delivered on the FSB. The processor latches SMI#, INIT# and LINT[1:0] interrupts and services only one of each upon return to the Normal state. The PBE# signal may be driven when the processor is in Stop-Grant state. PBE# asserts if there is any pending interrupt or Monitor event latched within the processor. Pending interrupts that are blocked by the EFLAGS.IF bit being clear causes assertion of PBE#. Assertion of PBE# indicates to system logic that the entire processor should return to the Normal state. A transition to the Stop-Grant Snoop state occurs when the processor detects a snoop occurs with the assertion of the SLP# signal.

2.1.2.3 Stop-Grant Snoop State

The processor responds to snoop or interrupt transactions on the FSB while in Stop- Grant state by entering the Stop-Grant Snoop state. The processor stays in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the FSB) or the interrupt has been latched. The processor returns to the Stop- Grant state once the snoop has been serviced or the interrupt has been latched.

2.1.2.4 Sleep State

The Sleep state is a low power state in which the processor maintains its context, maintains the phase-locked loop (PLL), and stops all internal clocks. The Sleep state is entered through assertion of the SLP# signal while in the Stop-Grant state. The SLP# pin should only be asserted when the processor is in the Stop-Grant state. SLP# assertions while the processor is not in the Stop-Grant state is out of specification and may result in unapproved operation.

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In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals (with the exception of SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep state. Snoop events that occur while in Sleep state or during a transition into or out of Sleep state causes unpredictable behavior. Any transition on an input signal before the processor has returned to the Stop-Grant state results in unpredictable behavior. If RESET# is driven active while the processor is in the Sleep state, and held active, then the processor resets itself, ignoring the transition through Stop-Grant state. If RESET# is driven active while the processor is in the Sleep state, the SLP# and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the processor correctly executes the Reset sequence. While in the Sleep state, the processor is capable of entering an even lower power state, the Deep Sleep state, by asserting the DPSLP# pin (See Section 2.1.2.5). While the processor is in the Sleep state, the SLP# pin must be deasserted if another asynchronous FSB event needs to occur.

2.1.2.5 Deep Sleep State

The Deep Sleep state is entered through assertion of the DPSLP# pin while in the Sleep state. BCLK may be stopped during the Deep Sleep state for additional platform-level power savings. BCLK stop/restart timings on appropriate chipset based platforms with the CK505 clock chip are as follows:

• Deep Sleep entry: the system clock chip may stop/tristate BCLK within 2 BCLKs of DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep.
• Deep Sleep exit: the system clock chip mu st drive BCLK to differential DC levels within 2-3 ns of DPSLP# deassertion and start toggling BCLK within 10 BCLK periods. To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be re- started after DPSLP# deassertion as described above. A period of 15 microseconds (to allow for PLL stabilization) must occur before the processor can be considered to be in the Sleep state. Once in the Sleep state, the SLP# pin must be deasserted to re-enter the Stop-Grant state. While in Deep Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions of signals are allowed on the FSB while the processor is in Deep Sleep state. When the processor is in Deep Sleep state, it does not respond to interrupts or snoop transactions. Any transition on an input signal before the processor has returned to Stop-Grant state results in unpredictable behavior.

2.1.2.6 Deeper Sleep State

The Deeper Sleep state is similar to the Deep Sleep state but further reduces core voltage levels. One of the potential lower core voltage levels is achieved by entering the base Deeper Sleep state. The Deeper Sleep state is entered through assertion of the DPRSTP# pin while in the Deep Sleep state. The other lower core voltage level, the lowest possible in the processor, is achieved by entering the Intel Enhanced Deeper Sleep state which is a sub-state of Deeper Sleep state. Intel Enhanced Deeper Sleep state is entered through assertion of the DPRSTP# pin while in the Deep Sleep only Section 2.1.2.6.2 for further details on reducing the L2 cache and entering Intel Enhanced Deeper Sleep state. In response to entering Deeper Sleep, the processor drives the VID code corresponding to the Deeper Sleep core voltage on the VID[6:0] pins.

Exit from Deeper Sleep or Intel Enhanced Deeper Sleep state is initiated by DPRSTP# deassertion when either core requests a core state other than C4 or either core requests a processor performance state other than the lowest operating point.

2.1.2.6.1 Intel Enhanced Deeper Sleep State

Intel Enhanced Deeper Sleep state is a sub-state of Deeper Sleep that extends power- saving capabilities by allowing the processor to further reduce core voltage once the L2 cache has been reduced to zero ways and completely shut down. The following events occur when the processor enters Intel Enhanced Deeper Sleep state:

• The last core entering C4 causes the package to issue a P_LVL4 IO Read.
• Every concurrent package C4 entry re duces the L2 Cache a certain number of cache ways, after which another P_LVL4 IO Read is issued to the chipset. By default, half the cache is flushed per concurrent C4 entry.
• Once the cache is flushed, P_LVL4 IO Reads continue to be issued.
• The processor drives the VID code corre sponding to the Intel Enhanced Deeper Sleep state core voltage on the VID[6:0] pins. At this point, snoops to the L2 are still serviced, which reduces the amount of time the processor can reside at the Intel Enhanced Deeper Sleep state core voltage. To improve the Intel Enhanced Deeper Sleep state residency, the (G)MCH features P_LVL5 IO Read support. When enabled, the CPU issues a P_LVL5 IO read, once the L2 cache is flushed. The P_LVL5 IO read triggers a special chipset sequence to notify the chipset to redirect all FSB traffic, except APIC messages, to memory instead of L2 cache. Therefore, the processor remains at the Intel Enhanced Deeper Sleep state core voltage for a longer period of time.

2.1.2.6.2 Dynamic Cache Sizing

Dynamic Cache Sizing allows the processor to flush and disable a programmable number of L2 cache ways upon each Deeper Sleep entry under the following conditions:

• The second core is already in C4 and the Intel Enhanced Deeper Sleep state is enabled (as specified in Section 2.1.1.6).
• The C0 timer, which tracks continuous residency in the Normal package state, has not expired. This timer is cleared during the first entry into Deeper Sleep to allow consecutive Deeper Sleep entries to shrink the L2 cache as needed.
• The FSB speed to processor core speed ratio is below the predefined L2 shrink threshold. If the FSB speed to processor core speed ratio is above the predefined L2 shrink threshold, then L2 cache expansion is requested. If the ratio is zero, then the ratio is not taken into account for Dynamic Cache Sizing decisions. Upon STPCLK# deassertion, the first core exiting Intel Enhanced Deeper Sleep state expands the L2 cache to two ways and invalidate previously disabled cache ways. If the L2 cache reduction conditions stated above still exist when the last core returns to C4 and the package enters Intel Enhanced Deeper Sleep state, then the L2 is shrunk to zero again. If a core requests a processor performance state resulting in a higher ratio than the predefined L2 shrink threshold, the C0 timer expires, or the second core (not the one currently entering the interrupt routine) requests the C1, C2, or C3 states, then all of L2 expands upon the next interrupt event. L2 cache shrink prevention may be enabled as needed on occasion through an MWAIT(C4) sub-state field. If shrink prevention is enabled the processor does not enter Intel Enhanced Deeper Sleep state because the L2 cache remains valid and in full size.

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2.2 Enhanced Intel SpeedStep® Technology

The processor features Enhanced Intel SpeedStep Technology. Following are the key features of Enhanced Intel SpeedStep Technology:

• Multiple voltage and frequency operating points provide optimal performance at the lowest power.
• Voltage and frequency selection is software-controlled by writing to processor MSRs: — If the target frequency is higher than the current frequency, Vcc is ramped up in steps by placing new values on the VID pins, and the PLL then locks to the new frequency. — If the target frequency is lower than th e current frequency, the PLL locks to the new frequency, and the VCC is changed through the VID pin mechanism. — Software transitions are accepted at any time. If a previous transition is in progress the new transition is deferred until the previous transition completes.
• The processor controls voltage ramp rates internally to ensure glitch-free transitions.
• Low transition latency and large number of transitions possible per second: — Processor core (including L2 cache) is unavailable for up to 10 ms during the frequency transition. — The bus protocol (BNR# mechanism) is used to block snooping.
• Improved Intel® Thermal Monitor mode: — When the on-die thermal sensor indicates that the die temperature is too high, the processor can automatically perform a transition to a lower frequency and voltage specified in a software-programmable MSR. — The processor waits for a fixed time period. If the die temperature is down to acceptable levels, an up-transition to the previous frequency and voltage point occurs. — An interrupt is generated for the up and down Intel Thermal Monitor transitions enabling better system-level thermal management.
• Enhanced thermal management features: — Digital Thermal Sensor and Out of Specification detection — Intel Thermal Monitor 1 in addition to Intel Thermal Monitor 2 in case of unsuccessful Intel Thermal Monitor 2 transition. — Dual core thermal management synchronization. Each core in the dual processor implements an independent MSR for controlling Enhanced Intel SpeedStep Technology, but both cores must operate at the same frequency and voltage. The processor has performance state coordination logic to resolve frequency and voltage requests from the two cores into a single frequency and voltage request for the package as a whole. If both cores request the same frequency and voltage, then the processor transitions to the requested common frequency and voltage. If the two cores have different frequency and voltage requests, then the processor takes the highest of the two frequencies and voltages as the resolved request, and transition to that frequency and voltage. The processor also supports Dynamic FSB Frequency Switching and Intel® Dynamic Acceleration Technology mode on select SKUS. The operating system can take advantage of these features and request a lower operating point called SuperLFM (due to Dynamic FSB Frequency Switching) and a higher operating point Intel Dynamic Acceleration Technology mode.

2.2.1 Dynamic FSB Frequency Switching

Dynamic FSB frequency switching effectively reduces the internal bus clock frequency in half to further decrease the minimum processor operating frequency from the Enhanced Intel SpeedStep Technology performance states and achieve the Super Low Frequency Mode (SuperLFM). This feature is supported at FSB frequencies of 800-MHz and does not entail a change in the external bus signal (BCLK) frequency. Instead, both the processor and (G)MCH internally lower their BCLK reference frequency to 50% of the externally visible frequency. Both the processor and (G)MCH maintain a virtual BCLK signal (“VBCLK”) that is aligned to the external BCLK but at half the frequency. After a downward shift, it would appear externally as if the bus is running with a 100-MHz base clock in all aspects, except that the actual external BCLK remains at 200 MHz. The transition into SuperLFM, a “down-shift”, is done following a handshake between the processor and (G)MCH. A similar handshake is used to indicate an “up- shift”, a change back to normal operating mode.

2.2.2 Intel® Dynamic Acceleration Technology

The processor supports Intel Dynamic Acceleration Technology mode on select platforms. The Intel Dynamic Acceleration Technology mode feature allows one core of the processor to temporarily operate at a higher frequency point when the other core is inactive and the operating system requests increased performance. This higher frequency is called the opportunistic frequency and the maximum rated operating frequency is the guaranteed frequency. Note: Intel Core 2 Extreme processors do not support Intel Dynamic Acceleration mode. Intel Dynamic Acceleration Technology mode enabling requires:

• Exposure, via BIOS, of the opportunistic frequency as the highest ACPI P state.
• Enhanced Multi-Threaded Th ermal Management (EMTTM).
• Intel Dynamic Acceleration Technology mode and EMTTM MSR configuration via BIOS. When in Intel Dynamic Acceleration Technology mode, it is possible for both cores to be active under certain internal conditions. In such a scenario the processor may draw a Instantaneous current (I CC_CORE_INST) for a short duration of tINST; however, the average ICC current is lesser than or equal to ICCDES current specification. Please refer to the Processor DC Specifications section for more details.

2.3 Extended Low Power States

Extended low power states (CxE) optimize for power by forcibly reducing the performance state of the processor when it enters a package low power state. Instead of directly transitioning into the package low power state, the extended package low power state first reduces the performance state of the processor by performing an Enhanced Intel SpeedStep Technology transition down to the lowest operating point. Upon receiving a break event from the package low power state, control returns to the software while an Enhanced Intel SpeedStep Technology transition up to the initial operating point occurs. The advantage of this feature is that it significantly reduces leakage while in low power states. Note: Long-term reliability cannot be assured unless all the Extended Low Power states are enabled.

20 Datasheet

The processor implements two software interfaces for requesting extended package low power states: MWAIT instruction extensions with sub-state hints and via BIOS by configuring MSR bits to automatically promote package low power states to extended package low power states. Extended Stop-Grant and Extended Deeper Sleep must be enabled via the BIOS for the processor to remain within specification. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor. As processor technology changes, enabling the extended low power states becomes increasingly crucial when building computer systems. Maintaining the proper BIOS configuration is key to reliable, long-term system operation. Not complying with this guideline may affect the long-term reliability of the processor. Enhanced Intel SpeedStep Technology transitions are multistep processes that require clocked control. These transitions cannot occur when the processor is in the Sleep or Deep Sleep package low power states since processor clocks are not active in these states. Extended Deeper Sleep state configuration lowers core voltage to the Deeper Sleep level while in Deeper Sleep and, upon exit, automatically transitions to the lowest operating voltage and frequency to reduce snoop service latency. The transition to the lowest operating point or back to the original software requested point may not be instantaneous. Furthermore, upon very frequent transitions between active and idle states, the transitions may lag behind the idle state entry resulting in the processor either executing for a longer time at the lowest operating point or running idle at a high operating point. Observations and analyses show this behavior should not significantly impact total power savings or performance score while providing power benefits in most other cases.

2.4 FSB Low Power Enhancements

The processor incorporates FSB low power enhancements:

• D y n a m i c F S B P o w e r D o w n
• BPRI# control for address and control input buffers
• Dynamic Bus Parking
• Dynamic On Die Termination disabling
• L o w V CCP (I/O termination voltage) The processor incorporates the DPWR# signal that controls the data bus input buffers on the processor. The DPWR# signal disables the buffers when not used and activates them only when data bus activity occurs, resulting in significant power savings with no performance impact. BPRI# control also allows the processor address and control input buffers to be turned off when the BPRI# signal is inactive. Dynamic Bus Parking allows a reciprocal power reduction in chipset address and control input buffers when the processor deasserts its BR0# pin. The On Die Termination on the processor FSB buffers is disabled when the signals are driven low, resulting in additional power savings. The low I/O termination voltage is on a dedicated voltage plane, independent of the core voltage, enabling low I/O switching power at all times.

2.5 VID-x

The processor implements the VID-x feature when in Intel Dynamic Acceleration Technology mode. VID-x provides the ability for the processor to request core voltage level reductions greater than one VID tick. The quantity of VID ticks to be reduced depends on the specific performance state in which the processor is running. This improved voltage regulator efficiency during periods of reduced power

consumption allows for leakage current reduction, which results in platform power savings and extended battery life. There is no platform-level change required to support this feature as long as the VR vendor supports the VID-x feature.

2.6 Processor Power Status Indicator (PSI-2) Signal

The processor incorporates the PSI# signal that is asserted when the processor is in a reduced power consumption state. PSI# can be used to improve intermediate and light load efficiency of the voltage regulator, resulting in platform power savings and extended battery life. The algorithm that the processor uses for determining when to assert PSI# is different from the algorithm used in previous mobile processors. PSI-2 functionality improves overall voltage regulator efficiency over a wide power range based on the C-state and P-state of the two cores. The combined C-state and P-state of both cores are used to dynamically predict processor power. PSI-2 functionality is expanded further to support three processor states:

• Both cores are in idle state
• Only one core is in active state
• Both cores are in active state

22 Datasheet

3 Electrical Specifications

3.1 Power and Ground Pins

supplied the voltage determined by the VID (Voltage ID) pins.

3.2 FSB Clock (BCLK[1:0] ) and Processor Clocking

3.3 Voltage Identification

Table 2. Voltage Identification Definition (Sheet 1 of 4)

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Table 2. Voltage Identification Definition (Sheet 2 of 4)

Table 2. Voltage Identification Definition (Sheet 3 of 4)

26 Datasheet

3.4 Catastrophic Thermal Protection

processor cannot be protected in all conditions without power removal to the processor. PWRGOOD signal is not asserted.

3.5 Reserved and Unused Pins

processor and the location of all RSVD pins. through an oscilloscope connection. Table 2. Voltage Identification Definition (Sheet 4 of 4)

3.6 FSB Frequency Select Signals (BSEL[2:0])

chipset on the platform. The BSEL encoding for BCLK[1:0] is shown in Table 3.

3.7 FSB Signal Groups

to the AGTL+ output group as well as the AGTL+ I/O group when driving. Table 3. BSEL[2:0] Encoding for BCLK Frequency

28 Datasheet

1. Refer to Chapter 4 for signal descriptions and termination requirements.
2. In processor systems where there is no debug port implemented on the system board, these signals are

board, these signals are no connects.

1. BPM[2:1]# and PRDY# are AG TL+ output only signals.
2. PROCHOT# signal type is open drain output and CMOS input.
3. On die termination differs from other AGTL+ signals.

Table 4. FSB Pin Groups

3.8 CMOS Signals

3.9 Maximum Ratings

functional operation limits, functionality and long-term reliability can be expected. functionality nor long term reliability can be expected. Caution: Precautions should always be taken to avoid high static voltages or electric fields.

1. For functional operation, all processor electr ical, signal quality, mechanical and thermal

specifications must be satisfied.

1. Storage temperature is applic able to storage conditions only. In this scenario, the

processor must not receive a clock, and no lands can be connected to a voltage bias. functional operation, please refer to the processor case temperature specifications.

1. This rating applies to th e processor and does not include any tray or packaging.
2. Failure to adhere to this specification can affect the long term reliability of the processor.

Table 5. Processor Absolute Maximum Ratings

30 Datasheet

3.10 Processor DC Specifications

all notes associated with each parameter. Table 6. Voltage and Current Specifications for the Intel Core 2 Duo Processors -

2.6 GHz & V

2.4 GHz & VCCHFM

2.2 GHz & VCCHFM

2.0 GHz & VCCHFM

1.8 GHz & VCCHFM

1.2 GHz & VCCLFM

0.8 GHz & VCCSLFM

1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at

in such a way that two processors at the same frequency may have different settings within the VID range. Thermal Monitor 2, Enhanced Intel SpeedStep Technology, or Extended Halt State).

1. The voltage specifications are as sumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with

a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-mΩ minimum impedance. the system is not coupled in the scope probe.

1. Specified at the nominal V
2. Instantaneous current I CC_CORE_INST of 55 A has to be sustained for short time (tINST) of 10 µs. Average
3. Measured at the bulk capa citors on the motherboard.
4. The maximum delta between Intel Enhanced Deeper Sl eep and LFM on the processor is lesser than or
5. Based on simulations and averaged over the durati on of any change in current. Specified by design/

characterization at nominal VCC. Not 100% tested.

1. This is a power-up peak current spec ification, which is applicable when VCCP is high and VCC_CORE is low.
2. This is a steady-state I CC current specification, which is applicable when both VCCP and VCC_CORE are high.
3. Processor I CC requirements in Intel Dynamic Acceleration Technology mode is lesser than ICC in HFM.

32 Datasheet

1. Each processor is programmed with a maximum valid vo ltage identification value (VID), which is set at

Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt State). Table 7. Voltage and Current Specifications for the Intel Core 2 Duo Processors - Low

1.6 GHz & VCCHFM

1.4 GHz & VCCHFM

1. The voltage specifications are as sumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with

a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-mΩ minimum impedance. the system is not coupled in the scope probe.

1. Specified at the nominal V CC.
2. Measured at the bulk capa citors on the motherboard.
3. Based on simulations and averaged over the durati on of any change in current. Specified by design/

characterization at nominal VCC. Not 100% tested.

1. This is a power-up peak current spec ification, which is applicable when VCCP is high and VCC_CORE is low.
2. This is a steady-state I CC current specification, which is applicable when both VCCP and VCC_CORE are high.
3. Processor I CC requirements in Intel Dynamic Acceleration Technology mode is lesser than Icc in HFM.
4. The maximum delta between Intel Enhanced Deeper Sl eep and LFM on the processor is lesser than or

Table 8. Voltage and Current Specifications fo r the Intel Core 2 Duo -Ultra Low Voltage

1.33 GHz & VCCHFM

1.20 GHz & VCCHFM

1.06 GHz & VCCHFM

0.80 GHz & VCCLFM

34 Datasheet

1. Each processor is programmed with a maximum valid vo ltage identification value (VID), which is set at

Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt State).

1. The voltage specifications are assumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with

a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-mΩ minimum impedance. the system is not coupled in the scope probe.

1. Specified at the nominal V
2. Instantaneous current I CC_CORE_INST of 21 A has to be sustained for short time (tINST) of 10 µs. Average
3. Measured at the bulk capacitors on the motherboard.
4. Based on simulations and averaged over the durati on of any change in current. Specified by design/
5. This is a power-up peak current spec ification, which is applicable when VCCP is high and VCC_CORE is low.
6. This is a steady-state I CC current specification, which is applicable when both VCCP and VCC_CORE are high.
7. Processor I CC requirements in Intel Dynamic Acceleration Technology mode is lesser than ICC in HFM.
8. The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor is lesser than or
9. Dynamic FSB Frequency Switching not supported.

Table 9. Voltage and Current Specifications for the Intel Core 2 Extreme Processors

1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at

Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt State).

1. The voltage specifications are as sumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with

a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-mΩ minimum impedance. the system is not coupled in the scope probe.

1. Specified at the nominal V
2. Measured at the bulk capa citors on the motherboard.
3. The maximum delta between Intel Enhanced Deeper Sl eep and LFM on the processor is lesser than or
4. Based on simulations and averaged over the durati on of any change in current. Specified by design/

characterization at nominal VCC. Not 100% tested.

1. This is a power-up peak current spec ification, which is applicable when VCCP is high and VCC_CORE is low.
2. This is a steady-state Icc current specification, which is applicable when both VCCP and VCC_CORE are high.
3. Intel Dynamic Acceleration Technology not supported.

2.80 GHz & VCCHFM

2.60 GHz & VCCHFM

1.20 GHz & VCCLFM

0.80 GHz & VCCSLFM

36 Datasheet

Figure 3. Active V CC and ICC Loadline Intel Core 2 Duo Processors - Standard Voltage, Differential Remote Sense required.

NOTE: Deeper Sleep mode tolerance depends on VID value. Figure 4. Deeper Sleep V CC and ICC Loadline Intel Core 2 Duo Processors - Standard Differential Remote Sense required. Differential Remote Sense required.

38 Datasheet

NOTE: Deeper Sleep mode tolerance depends on VID value.

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Crossing Voltage is defined as absolute voltag e where rising edge of BCLK0 is equal to the
3. For Vin between 0 V and V IH.
4. Cpad includes die capacitance only. No package parasitics are included.
5. ΔVCROSS is defined as the total variation of all crossing voltages as defined in Note 2.
6. Measurement taken from differential waveform.
7. Measurement taken from single-ended waveform.
8. Only applies to the differe ntial rising edge (Clock rising and Clock# falling).

Figure 5. Deeper Sleep V CC and ICC Loadline Intel Core 2 Duo Processor - Low Voltage Table 10. FSB Differentia l BCLK Specifications

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. V IL is defined as the maximum voltage level at a receiving agent that is interpreted as a
3. V IH is defined as the minimum voltage level at a receiving agent that is interpreted as a
4. V IH and VOH may experience excursions above VCCP. However, input signal drivers must

comply with the signal quality specifications.

1. GTLREF should be generated from V CCP with a 1%-tolerance resistor divider. The VCCP

referred to in these specifications is the instantaneous VCCP.

1. R TT is the on-die termination resistance measured at VOL of the AGTL+ output driver.

Measured at 0.31*VCCP. RTT is connected to VCCP on die.

1. Specified with on die R TT and RON turned off. Vin between 0 and VCCP.
2. Cpad includes die capaci tance only. No package parasitics are included.
3. This is the external re sistor on the comp pins.
4. On die termination resist ance measured at 0.33*VCCP.

Table 11. AGTL+ Signal Group DC Specifications

40 Datasheet

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The V CCP referred to in these specifications refers to instantaneous VCCP.
3. Cpad2 includes die capacitance for all other CMOS input signals. No package parasitics are
4. For Vin between 0 V and V CCP. Measured when the driver is tristated.
5. Cpad1 includes die capacitance only fo r DPRSTP#, DPSLP#, PWRGOOD. No package
6. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

OH is determined by value of the external pull-up resistor to VCCP.

1. For Vin between 0 V and V OH.
2. Cpad includes die capacitance only. No package parasitics are included.

Table 12. CMOS Signal Group DC Specifications Table 13. Open Drain Signal Group DC Specifications

Package Mechanical Specifications and Pin Information

4 Package Mechanical

4.1 Package Mechanical Specifications

The processor is available in 4-MB and 2-MB, 478-pin Micro-FCPGA packages as well as 4-MB and 2-MB, 479-ball Micro-FCBGA packages. The package mechanical dimensions, keep-out zones, processor mass specifications, and package loading specifications are shown in Figure 6 through Figure 13. The mechanical package pressure specifications are in a direction normal to the surface of the processor. This requirement is to protect the processor die from fracture risk due to uneven die pressure distribution under tilt, stack-up tolerances and other similar conditions. These specifications assume that a mechanical attach is designed specifically to load one type of processor. Intel also specifies that 15-lbf load limit should not be exceeded on any of Intel’s BGA packages so as to not impact solder joint reliability after reflow. This load limit ensures that impact to the package solder joints due to transient bend, shock, or tensile loading is minimized. The 15-lbf metric should be used in parallel with the 689-kPa (100 psi) pressure limit as long as neither limits are exceeded. Moreover, the processor package substrate should not be used as a mechanical reference or load-bearing surface for the thermal or mechanical solution. Please refer to the Santa Rosa Platform Mechanical Design Guide for more details. Caution: The Micro-FCBGA package incorporates land-side capacitors. The land-side capacitors are electrically conductive so care should be taken to avoid contacting the capacitors with other electrically conductive materials on the motherboard. Doing so may short the capacitors and possibly damage the device or render it inactive. Note: For E-step based processors refer the 4-MB and Fused 2-MB package drawings. For M- step based processors refer to the 2-MB package drawings.

42 Datasheet

Figure 6. 4-MB and Fused 2-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2)

Figure 7. 4-MB and Fused 2-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2)

44 Datasheet

Figure 8. 2-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2)

Figure 9. 2-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2)

46 Datasheet

Figure 10. 4-MB and Fused 2-MB Micro-FCBGA Processor Package Drawing (Sheet 1 of 2)

Figure 11. 4-MB and Fused 2-MB Micro-FCBGA Processor Package Drawing (Sheet 2 of 2)

48 Datasheet

Figure 12. 2-MB Micro-FCBGA Processor Package Drawing (Sheet 1 of 2)

4.2 Processor Pinout and Pin List

list, arranged in two different formats, is shown in the following pages. Figure 13. 2-MB Micro-FC BGA Processor Package Drawing (Sheet 2 of 2)

50 Datasheet

Table 14. The Coordinates of the Processor Pi ns as Viewed from the Top of the Package

Table 15. The Coordinates of the Processor Pi ns as Viewed from the Top of the Package

Package Mechanical Specifications and Pin Information

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This page is intentionally left blank.

Table 16. Pin Listin g by Pin Name Table 16. Pin Listing by Pin Name

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Table 17. Pin Listing by Pin Number

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Table 17. Pin Listin g by Pin Number

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68 Datasheet

4.3 Alphabetical Signals Reference

Table 18. Signal Description (Sheet 1 of 7) assertion of the corresponding Input/Output Write bus transaction. snoop, or deferred reply ID match operations associated with the new transaction. falling edges. Strobes are associated with signals as shown below. agents must receive these signals to drive their outputs and latch their inputs. cannot issue any new transactions. BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. debug or performance monitoring tools. releases the bus by deasserting BPRI#. processor (Symmetric Agent) and (G)MCH (High Priority Agent).

70 Datasheet

BSEL[2:0] (Bus Select) are used to select the processor input clock frequency. between the FSB agents, and must connect the appropriate pins on both agents. The data driver asserts DRDY# to indicate a valid data transfer. the system, DBR# is a no-connect in the system. DBR# is not a processor signal. appropriate pins of both FSB agents. Table 18. Signal Descript ion (Sheet 2 of 7)

half the bits, within the covered group, would change level in the next cycle. 82801HBM ICH8M I/O Controller Hub based chipset. must be deasserted. DPSLP# is driven by the Intel 82801HBM ICH8M chipset. appropriate pins of both FSB agents. Data strobe used to latch in D[63:0]#. Data strobe used to latch in D[63:0]#. Table 18. Signal Description (Sheet 3 of 7)

72 Datasheet

FERR#/PBE# indicates that the processor should be returned to the Normal state. is a logical 0 or logical 1. IERR# (Internal Error) is asserted by a processor as the result of an internal error. of RESET#, BINIT#, or INIT#. floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set. assertion of the corresponding Input/Output Write bus transaction. must connect the appropriate pins of both FSB agents. Table 18. Signal Descript ion (Sheet 4 of 7)

Pentium® processor. Both signals are asynchronous. end of the last transaction. PRDY# Output Probe Ready signal used by debug tools to determine processor debug readiness. until the system deasserts PROCHOT#. via the BIOS for PROCHOT# to be configured as bidirectional. This signal may require voltage translation on the motherboard. throughout boundary scan operation. transaction type. These signals are source synchronous to ADSTB[0]#. Table 18. Signal Description (Sheet 5 of 7)

74 Datasheet

(nominal) on die pull-up resistor on this signal. appropriate pins of both FSB agents. signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. the processor exits the Sleep state and transition to the Deep Sleep state. SMI# (System Management Interrupt) is asserted asynchronously by system logic. STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input. serial input needed for JTAG specification support. the serial output needed for JTAG specification support. is accessible through an oscilloscope connection. THRMDA Other Thermal Diode Anode. THRMDC Other Thermal Diode Cathode. Table 18. Signal Descript ion (Sheet 6 of 7)

by the THERMTRIP# (Thermal Trip) pin. TMS Input TMS (Test Mode Select) is a JTAG spec ification support signal used by debug tools. appropriate pins of both FSB agents. VCC Input Processor core power supply. VSS Input Processor core ground node. VCCA Input V CCA provides isolated power for the internal processor core PLL’s. VCCP Input Processor I/O Power Supply. voltage near the silicon with little noise. requested by the pins, or disable itself. ground near the silicon with little noise. Table 18. Signal Description (Sheet 7 of 7)

Package Mechanical Specifications and Pin Information

76 Datasheet

5 Thermal Specifications and

listed in Table 19 through Table 20. processor and potentially other components in the system.

1. The TDP specification should be used to design the processor thermal solution. The TDP is not the

maximum theoretical power the processor can generate.

1. Not 100% tested. These power specifications are dete rmined by characterization of the processor currents

at higher temperatures and extrapolating the values for the temperature indicated.

1. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic

mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for details.

1. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within

Table 19. Power Specifications for the Inte l Core 2 Duo Processor - Standard Voltage

2.6 GHz & HFM V

2.4 GHz & HFM VCC

2.2 GHz & HFM VCC

2.0 GHz & HFM VCC

1.8 GHz & HFM VCC

1.2 GHZ & LFM VCC

0.80 GHZ & SuperLFM VCC

78 Datasheet

1. Processor TDP requirements in Intel Dynamic Accelera tion Technology mode is lesser than TDP in HFM.
2. The TDP specification should be used to design the processor thermal solution. The TDP is not the

maximum theoretical power the processor can generate.

1. Not 100% tested. These power specifications are dete rmined by characterization of the processor currents

at higher temperatures and extrapolating the values for the temperature indicated.

1. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic

mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details.

1. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within
2. Processor TDP requirements in Intel Dynamic Accelera tion Technology mode is lesser than TDP in HFM.

Table 20. Power Specifications for the In tel Core 2 Duo Processor - Low Voltage

1.8 GHz & HFM V

1.6 GHz & HFM VCC

1.4 GHz & HFM VCC

1. The TDP specification should be used to design the processor thermal solution. The TDP is not the

maximum theoretical power the processor can generate.

1. Not 100% tested. These power specifications are dete rmined by characterization of the processor currents

at higher temperatures and extrapolating the values for the temperature indicated.

1. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic

mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details.

1. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within
2. Processor TDP requirements in Intel Dynamic Accelera tion Technology mode is lesser than TDP in HFM.

Table 21. Power Specifications for the Inte l Core 2 Duo Processor - Ultra Low Voltage

1.33 GHz & HFM V

1.20 GHz & HFM VCC

1.06 GHz & HFM VCC

0.80 GHZ & LFM VCC

80 Datasheet

1. The TDP specification should be used to design the processor thermal solution. The TDP is not the

maximum theoretical power the processor can generate.

1. Not 100% tested. These power specifications are dete rmined by characterization of the processor currents

at higher temperatures and extrapolating the values for the temperature indicated.

1. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic

mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details.

1. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within
2. Intel Dynamic Acceleration mode is not supported.

5.1 Thermal Specifications

• T h e r m a l D i o d e
• Intel Thermal Monitor
• Digital Thermal Sensor

Table 22. Power Specifications for the Intel Core 2 Extreme Processor

2.8 GHz & HFM VCC

2.6 GHz & HFM VCC

0.80 GHZ & SuperLFM VCCc

5.1.1 Thermal Diode

recommendation when the PROCHOT# signal is not asserted. processor Model Specific Register (MSR). Table 23. Thermal Diode Interface

82 Datasheet

1. Intel does not support or re commend operation of the thermal diode under reverse bias.

power supplies are not within their specified tolerance range.

1. Characterized across a temperature range of 50-100°C.
2. Not 100% tested. Specified by design characterization.
3. The ideality factor, n, represents the deviat ion from ideal diode behavior as exemplified by

Boltzmann Constant, and T = absolute temperature (Kelvin).

1. The series resistance, R T, is provided to allow for a more accurate measurement of the

Constant, q = electronic charge. Table 24. Thermal Diode Parameters Using Diode Model

1. Intel does not support or recommend operation of the thermal diode under reverse bias.
2. Characterized acro ss a temperature range of 50-100°C.
3. Not 100% tested. Specified by design characterization.
4. The ideality factor, nQ, represents the devi ation from ideal transistor model behavior as
5. The series resistance, R T, provided in the Diode Model Table (Table 24) can be used for

more accurate readings as needed.

5.1.2 Thermal Diode Offset

processor thermal diode is evaluated for its behavior relative to the theoretical diode. actual ideality of the particular processor is calculated. Table 25. Thermal Diode Parame ters Using Transistor Model

84 Datasheet

defined in the temperature sensor manufacturer’s datasheet. The ntrim used to calculate the Diode Correction Toffset are listed in Table 26.

5.1.3 Intel® Thermal Monitor

the TCC is active continuously. Monitor 2. These modes are selected by writing values to the MSRs of the processor. temperature reaches the maximum allowed value for operation. clocks modulates by alternately turning the clocks off and on at a 50% duty cycle. amount as the duty cycle when the TCC is active. processor performs an Enhanced Intel SpeedStep Technology transition to the LFM. Enhanced Intel SpeedStep Technology transition to the last requested operating point. The processor also supports Enhanced Multi Threaded Thermal Monitoring (EMTTM). Table 26. Thermal Diode n

Thermal Specifications and Design Considerations EMTTM is a processor feature that enhances Intel Thermal Monitor 2 with a processor throttling algorithm known as Adaptive Intel Thermal Monitor 2. Adaptive Intel Thermal Monitor 2 transitions to intermediate operating points, rather than directly to the LFM, once the processor has reached its thermal limit and subsequently searches for the highest possible operating point. Please ensure this feature is enabled and supported in the BIOS. Also with EMTTM enabled, the operating system can request the processor to throttling to any point between Intel Dynamic Acceleration Technology frequency and SuperLFM frequency as long as these features are enabled in the BIOS and supported by the processor. The Intel Thermal Monitor automatic mode and Enhanced Multi Threaded Thermal Monitoring must be enabled through BIOS for the processor to be operating within specifications. Note: Intel Thermal Monitor 1, Intel Thermal Monitor 2 and EMTTM features are collectively referred to as Adaptive Thermal Monitoring features. Intel recommends Intel Thermal Monitor 1 and 2 be enabled on the processors. Intel Thermal Monitor 1 and 2 can co-exist within the processor. If both Intel Thermal Monitor 1 and 2 bits are enabled in the auto-throttle MSR, Intel Thermal Monitor 2 takes precedence over Intel Thermal Monitor 1. However, if Force Intel Thermal Monitor 1 over Intel Thermal Monitor 2 is enabled in MSRs via BIOS and Intel Thermal Monitor 2 is not sufficient to cool the processor below the maximum operating temperature, then Intel Thermal Monitor 1 also activates to help cool down the processor. If a processor load based Enhanced Intel SpeedStep Technology transition (through MSR write) is initiated when a Intel Thermal Monitor 2 period is active, there are two possible results: 1. If the processor load based Enhanced Intel SpeedStep Technology transition target frequency is higher than the Intel Thermal Monitor 2 transition-based target frequency, the processor load-based transition deferrs until the Intel Thermal Monitor 2 event has been completed. 2. If the processor load-based Enhanced Intel SpeedStep Technology transition target frequency is lower than the Intel Thermal Monitor 2 transition-based target frequency, the processor transitions to the processor load-based Enhanced Intel SpeedStep Technology target frequency point. The TCC may also be activated via on-demand mode. If bit 4 of the ACPI Intel Thermal Monitor control register is written to a 1, the TCC activates immediately independent of the processor temperature. When using on-demand mode to activate the TCC, the duty cycle of the clock modulation is programmable via bits 3:1 of the same ACPI Intel Thermal Monitor control register. In automatic mode, the duty cycle is fixed at 50% on, 50% off, however in on-demand mode, the duty cycle can be programmed from 12.5% used at the same time automatic mode is enabled, however, if the system tries to enable the TCC via on-demand mode at the same time automatic mode is enabled and a high temperature condition exists, automatic mode takes precedence. An external signal, PROCHOT# (processor hot) is asserted when the processor detects that its temperature is above the thermal trip point. Bus snooping and interrupt latching are also active while the TCC is active. Besides the thermal sensor and thermal control circuit, the Intel Thermal Monitor also includes one ACPI register, one performance counter register, three MSR, and one I/O pin (PROCHOT#). All are available to monitor and control the state of the Intel Thermal Monitor feature. The Intel Thermal Monitor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#. PROCHOT# is not be asserted when the processor is in the Stop Grant, Sleep, Deep Sleep, and Deeper Sleep low power states, hence the thermal diode reading must be used as a safeguard to maintain the processor junction temperature within maximum specification. If the platform thermal solution is not able to maintain the processor

Thermal Specifications and Design Considerations

86 Datasheet

junction temperature within the maximum specification, the system must initiate an orderly shutdown to prevent damage. If the processor enters one of the above low power states with PROCHOT# already asserted, PROCHOT# will remain asserted until the processor exits the low power state and the processor junction temperature drops below the thermal trip point. If Intel Thermal Monitor automatic mode is disabled, the processor will be operating out of specification. Regardless of enabling the automatic or on-demand modes, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature of approximately 125°C. At this point the THERMTRIP# signal will go active. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles. When THERMTRIP# is asserted, the processor core voltage must be shut down within the time specified in Chapter 3 In all cases the Intel Thermal Monitor feature must be enabled for the processor to remain within specification.

5.1.4 Digital Thermal Sensor

The processor also contains an on die Digital Thermal Sensor (DTS) that can be read via an MSR (no I/O interface). Each core of the processor will have a unique digital thermal sensor whose temperature is accessible via the processor MSRs. The DTS is the preferred method of reading the processor die temperature since it can be located much closer to the hottest portions of the die and can thus more accurately track the die temperature and potential activation of processor core clock modulation via the Intel Thermal Monitor. The DTS is only valid while the processor is in the normal operating state (the Normal package level low power state). Unlike traditional thermal devices, the DTS will output a temperature relative to the maximum supported operating temperature of the processor (T J,max). It is the responsibility of software to convert the relative temperature to an absolute temperature. The temperature returned by the DTS will always be at or below TJ,max. Catastrophic temperature conditions are detectable via an Out Of Spec status bit. This bit is also part of the DTS MSR. When this bit is set, the processor is operating out of specification and immediate shutdown of the system should occur. The processor operation and code execution is not guaranteed once the activation of the Out of Spec status bit is set. The DTS-relative temperature readout corresponds to the Intel Thermal Monitor 1/Intel Thermal Monitor 2 trigger point. When the DTS indicates maximum processor core temperature has been reached, the Intel Thermal Monitor 1 or 2 hardware thermal control mechanism will activate. The DTS and Intel Thermal Monitor 1/Intel Thermal Monitor 2 temperature may not correspond to the thermal diode reading because the thermal diode is located in a separate portion of the die and thermal gradient between the individual core DTS. Additionally, the thermal gradient from DTS to thermal diode can vary substantially due to changes in processor power, mechanical and thermal attach, and software application. The system designer is required to use the DTS to guarantee proper operation of the processor within its temperature operating specifications. Changes to the temperature can be detected via two programmable thresholds located in the processor MSRs. These thresholds have the capability of generating interrupts via the core's local APIC. Refer to the Intel® 64 and IA-32 Architectures Software Developer’s Manual for specific register and programming details.

Thermal Specifications and Design Considerations

5.1.5 Out of Specification Detection

Overheat detection is performed by monitoring the processor temperature and temperature gradient. This feature is intended for graceful shut down before the THERMTRIP# is activated. If the processor’s Intel Thermal Monitor 1 or 2 are triggered and the temperature remains high, an “Out Of Spec” status and sticky bit are latched in the status MSR register and generates thermal interrupt.

5.1.6 PROCHOT# Signal Pin

An external signal, PROCHOT# (processor hot), is asserted when the processor die temperature has reached its maximum operating temperature. If Intel Thermal Monitor 1 or 2 is enabled, then the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#. Refer to the Intel® 64 and IA-32 Architectures Software Developer’s Manual for specific register and programming details. The processor implements a bi-directional PROCHOT# capability to allow system designs to protect various components from overheating situations. The PROCHOT# signal is bi-directional in that it can either signal when the processor has reached its maximum operating temperature or be driven from an external source to activate the TCC. The ability to activate the TCC via PROCHOT# can provide a means for thermal protection of system components. Only a single PROCHOT# pin exists at a package level of the processor. When either core's thermal sensor trips, the PROCHOT# signal will be driven by the processor package. If only Intel Thermal Monitor 1 is enabled, PROCHOT# will be asserted and only the core that is above TCC temperature trip point will have its core clocks modulated. If Intel Thermal Monitor 2 is enabled, then regardless of which core(s) are above TCC temperature trip point, both cores will enter the lowest programmed Intel Thermal Monitor 2 performance state. It is important to note that Intel recommends both Intel Thermal Monitor 1 and 2 to be enabled. When PROCHOT# is driven by an external agent, if only Intel Thermal Monitor 1 is enabled on both cores, then both processor cores will have their core clocks modulated. If Intel Thermal Monitor 2 is enabled on both cores, then both processor cores will enter the lowest programmed Intel Thermal Monitor 2 performance state. It should be noted that Force Intel Thermal Monitor 1 on Intel Thermal Monitor 2, enabled via BIOS, does not have any effect on external PROCHOT#. If PROCHOT# is driven by an external agent when Intel Thermal Monitor 1, Intel Thermal Monitor 2, and Force Intel Thermal Monitor 1 on Intel Thermal Monitor 2 are all enabled, then the processor will still apply only Intel Thermal Monitor 2. PROCHOT# may be used for thermal protection of voltage regulators (VR). System designers can create a circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR is reached. By asserting PROCHOT# (pulled-low) and activating the TCC, the VR will cool down as a result of reduced processor power consumption. Bi-directional PROCHOT# can allow VR thermal designs to target maximum sustained current instead of maximum current. Systems should still provide proper cooling for the VR and rely on bi-directional PROCHOT# only as a backup in case of system cooling failure. The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its TDP. With a properly designed and characterized thermal solution, it is anticipated that bi-directional PROCHOT# would only be asserted for very short periods of time when running the most power intensive applications. An under-designed thermal solution that is not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may cause a noticeable performance loss.