UPI-C42 INTEL | Alldatasheet
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Table 1. Pin Description XTAL 1 2 3 19 O OUTPUT: Output from the oscillator amplifier. zero, and force the UPI-C42 from the suspend power down mode. RESET is also used during EPROM programming and verification. Mode by applying 12.5V to it. out of several connected to a common data bus. status words from the OUTPUT DATA BUS BUFFER or status register. (A0 e 1, F1 is set). A 0 e 0 during program and verify operations. command words to the UPI INPUT DATA BUS BUFFER. synchronize single step operation. interface the UPI microcomputer to an 8-bit master system data bus.
Table 1. Pin Description (Continued) strobe to the 8243. This pin should be tied high if unused. VCC 40 44 17 POWER: a5V main power supply pin. operation. Low power standby supply pin. VSS 20 22 38 GROUND: Circuit ground potential. Figure 4. Block Diagram
UPI-C42/L42 PRODUCT SELECTION GUIDE UPI-C42: Low power CHMOS version of the UPI-42. Device Package ROM OTP Comments 80C42 N, P S 4K ROM Device 82C42PC N, P, S Phoenix MultiKey/42 firmware, PS/2 style mouse support 82C42PD N, P, S Phoenix MultiKey/42L firmware, KBC and SCC for portable apps. 82C42PE N, P, S Phoenix MultiKey/42G firmware, Energy Efficient KBC solution 87C42 N, P, S 4K One Time Programmable Version UPI-L42: The low voltage 3.3V version of the UPI-C42. Device Package ROM OTP Comments 80L42 N, P S 4K ROM Device 82L42PC N, P, S Phoenix MultiKey/42 firmware, PS/2 style mouse support 82L42PD N, P, S Phoenix MultiKey/42L firmware, KBC and SCC for portable apps. 87L42 N, P, S 4K One Time Programmable Version N e 44 lead PLCC, P e 40 lead PDIP, S e 44 lead QFP, D e 40 lead CERDIP KBC e Key Board Control, SCC e Scan Code Control THE INTEL 82C42 As shown in the UPI-C42 product matrix, the UPI- C42 is offered as a pre-programmed 80C42 with var- ious versions of MultiKey/42 keyboard controller firmware developed by Phoenix Technologies Ltd. The 82C42PC provides a low powered solution for industry standard keyboard and PS/2 style mouse control. The 82C42PD provides a cost effective means for keyboard and scan code control for note- book platforms. The 82C42PE allows a quick time to market, low cost solution for energy efficient desk- top designs.
UPI-42 COMPATIBLE FEATURES 1. Two Data Bus Buffers, one for input and one for output. This allows a much cleaner Master/Slave protocol. 290414–5 2. 8 Bits of Status ST7 ST6 ST5 ST4 F1 F0 IBF OBF D7 D6 D5 D4 D3 D2 D1 D0 ST4 –ST7 are user definable status bits. These bits are defined by the ‘‘MOV STS, A’’ single byte, single cycle instruction. Bits 4–7 of the acccumulator are moved to bits 4–7 of the status register. Bits 0–3 of the status register are not affected. MOV STS, A Op Code: 90H 1 001000 0 D7 D0 3. RD and WR are edge triggered. IBF, OBF, F 1 and INT change internally after the trailing edge of RD or WR . During the time that the host CPU is reading the status register, the UPI is prevented from updat- ing this register or is ‘locked out.’ 290414–6 4. P24 and P 25 are port pins or Buffer Flag pins which can be used to interrupt a master proces- sor. These pins default to port pins on Reset. If the ‘‘EN FLAGS’’ instruction has been execut- ed, P 24 becomes the OBF (Output Buffer Full) pin. A ‘‘1’’ written to P 24 enables the OBF pin (the pin outputs the OBF Status Bit). A ‘‘0’’ written to P 24 disables the OBF pin (the pin remains low). This pin can be used to indicate that valid data is available from the UPI (in Output Data Bus Buff- er). If ‘‘EN FLAGS’’ has been executed, P 25 be- comes the IBF (Input Buffer Full) pin. A ‘‘1’’ writ- ten to P 25 enables the IBF pin (the pin outputs the inverse of the IBF Status Bit. A ‘‘0’’ written to P 25 disables the IBF pin (the pin remains low). This pin can be used to indicate that the UPI is ready for data. Data Bus Buffer Interrupt Capability 290414–7 EN FLAGS Op Code: 0F5H 1 111010 1 D7 D0 5. P26 and P 27 are port pins or DMA handshake pins for use with a DMA controller. These pins default to port pins on Reset. If the ‘‘EN DMA’’ instruction has been executed, P 26 becomes the DRQ (DMA Request) pin. A ‘‘1’’ written to P 26 causes a DMA request (DRQ is activated). DRQ is deactivated by DACK #RD, DACK#WR, or execution of the ‘‘EN DMA’’ in- struction. DMA Handshake Capability 290414–8
as a pure output pin with read only characteristics. quences and UPI-C42 responses. Table 1. D1 Command Sequences
1 W D1h 0 n (1) Set A20 Sequence
0 W DFh 0 1 Only DB1 Is Processed
1 W FFH
1 W D1h 0 n Clear A20 Sequence
0 W DDh 0 0
1 W FFh 0 n
1 W D1h 0 n Double Trigger Set
1 W D1h 0 n Sequence
0 W DFh 0 1
1 W D1h 0 n Invalid Sequence
1 W XXh
0 W DDh 1 n of A20 Bit
- Indicates that P2.1 remains at the previous logic level.
- Only FFh commands in a valid A20 sequence have no
logic has been enabled via the A20EN instruction. running and the internal CPU operation is stopped. mode. This mode can only be exited by RESET. UPI-C42 exits from the suspend power down mode.
outlined in Chapter 4 of the UPI-42AH users manual. Table 2. Suspend Mode Pin States
- DBB outputs are Tristate unless CS Ý and RD Ý are ac-
- A ‘‘disabled’’ input will not cause current to be drawn
regardless of input level (within the supply range).
- Weak pull-ups have current capability of typically 5 mA.
ing code in order to use any new functionality. feature. Will remain enabled until device is reset.
This circuitry gives the host direct control of port 2 bit 1 (P2.1) without intervention by the internal CPU. When this opcode is executed, P2.1 becomes a ded- icated output pin. The status of this pin is read-able but can only be altered through a valid ‘‘D1’’ com- mand sequence (see Table 1). SUSPEND Invoke Suspend Power Down Mode OPCODE 1000 0010 (82h) or 1110 0010 (E2h) Enables device to enter micro power mode. In this mode the external oscillator is off, CPU operation is stopped, and the Port pins are tristated. This mode can only be exited via a RESET signal. PROGRAMMING AND VERIFYING THE UPI-C42 The UPI-C42 programming will differ from the NMOS device in three ways. First, the C42 will have a 4K user programmable array. The UPI-C42 will also be programmed using the Intel Quick-Pulse Program- ming Algorithm. Finally, port 2 bit three (P2.3) will be used during program as the extra address pin re- quired to program the upper 2K bank of additional memory. None of these differences have any effect on the full CHMOS to NMOS device compatibility. The extra memory is fully transparent to the user who does not need, or want, to use the extra memo- ry space of the UPI-C42. In brief, the programming process consists of: acti- vating the program mode, applying an address, latching the address, applying data, and applying a programming pulse. Each word is programmed com- pletely before moving on to the next and is followed by a verification step. The following is a list of the pins used for programming and a description of their functions: Pin Function XTAL 2 Clock Input Reset Initialization and Address Latching Test 0 Selection of Program or Verify Mode EA Activation of Program/Verify Signature Row/Security Bit Modes BUS Address and Data Input Data Output During Verify P20–23 Address Input VDD Programming Power Supply PROG Program Pulse Input WARNING An attempt to program a missocketed UPI-C42 will result in severe damage to the part. An indication of a properly socketed part is the appearance of the SYNC clock output. The lack of this clock may be used to disable the program- mer. The Program/Verify sequence is: 1. Insert 87C42 in programming socket 2. CS e 5V, V CC e 5V, V DD e 5V, RESET e 0V, A0 e 0V, TEST 0 e 5V, clock applied or inter- nal oscillator operating, BUS floating, PROG e 5V. 3. TEST 0 e 0V (select program mode) 4. EA e 12.75V (active program mode) 5. V CC e 6.25V (programming supply) 6. V DD e 12.75V (programming power) 7. Address applied to BUS and P 20–23 8. RESET e 5V (latch address) 9. Data applied to BUS 10. PROG e 5V followed by one 100 ms pulse to 11. TEST 0 e 5V (verify mode) 12. Read and verify data on BUS 13. TEST 0 e 0V 14. RESET e 0V and repeat from step 6 15. Programmer should be at conditions of step 1 when the 87C42 is removed from socket Please follow the Quick-Pulse Programming flow chart for proper programming procedure shown in Figure 6.
Figure 6. Quick-Pulse Programming Algorithm thorughput time in production programming. to program the NMOS UPI-42AH OTP devices. a. Read the security byte of the signature mode.
b. Apply access code to appropriate inputs to put the device into security mode. c. Apply high voltage to EA and V DD pins. d. Follow the programming procedure as per the Quick-Pulse Programming Algorithm with known data on the databus. Not only the security bit, but also the security byte of the signature row is pro- grammed. e. Verify that the security byte of the signature mode contains the same data as appeared on the data bus. (If DB0–DB7 e high, the security byte will contain FFH.) f. Read two consecutive known bytes from the EPROM array and verify that the wrong data are retrieved in at least one verification. If the EPROM can still be read, the security bit may have not been fully programmed though the se- curity byte in the signature mode has. Verification Since the security bit address overlaps the address of the security byte of the signature mode, it can be used to check indirectly whether the security bit has been programmed or not. Therefore, the security bit verification is a mere read operation of the security byte of the signature row (0FFH e security bit pro- grammed; 00H e security bit unprogrammed). Note that during the security bit programming, the reading of the security byte does not necessarily indicate that the security bit has been successfully pro- grammed. Thus, it is recommended that two consec- utive known bytes in the EPROM array be read and the wrong data should be read at least once, be- cause it is highly improbable that random data coin- cides with the correct ones twice. SIGNATURE MODE The UPI-C42 has an additional 64 bytes of EPROM available for Intel and user signatures and miscella- neous purposes. The 64 bytes are partitioned as fol- lows: A. Test code/checksumÐ This can accommodate up to 25 bytes of code for testing the internal nodes that are not testable by executing from the external memory. The test code/checksum is present on ROMs, and OTPs. B. Intel signature ÐThis allows the programmer to read from the UPI-41AH/42AH/C42 the manu- facturer of the device and the exact product name. It facilitates automatic device identification and will be present in the ROM and OTP ver- sions. Location 10H contains the manufacturer code. For Intel, it is 89H. Location 11H contains the device code. The code is 43H and 42H for the 8042AH/80C42 and OTP 8742AH/87C42, respectively. The code is 44H for any device with the security bit set by Intel. C. User signature ÐThe user signature memory is implemented in the EPROM and consists of 2 bytes for the customer to program his own signa- ture code (for identification purposes and quick sorting of previously programmed materials). D. Test signature ÐThis memory is used to store testing information such as: test data, bin num- ber, etc. (for use in quality and manufacturing control). E. Security byte ÐThis byte is used to check whether the security bit has been programmed (see the security bit section). F. UPI-C42 Intel Signature ÐApplies only to CHMOS device. Location 20H contains the man- ufacturer code and location 21H contains the de- vice code. The Intel UPI-C42 manufacturer’s code is 99H. The device ID’s are 82H for the OTP version and 83H for the ROM version. The device ID’s are the same for the UPI-L42. The signature mode can be accessed by setting P10 e 0, P11–P17 e 1, and then following the pro- gramming and/or verification procedures. The loca- tion of the various address partitions are as shown in Table 3. SYNC MODE The Sync Mode is provided to ease the design of multiple controller circuits by allowing the designer to force the device into known phase and state time. The Sync Mode may also be utilized by automatic test equipment (ATE) for quick, easy, and efficient synchronizing between the tester and the DUT (de- vice under test). Sync Mode is enabled when SS pin is raised to high voltage level of a12 volts. To begin synchroniza- tion, T0 is raised to 5 volts at least four clock cycles after SS . T0 must be high for at least four X2 clock cycles to fully reset the prescaler and time state generators. T0 may then be brought down during low state of X2. Two clock cycles later, with the ris- ing edge of X2, the device enters into Time State 1, Phase 1. SS is then brought down to 5 volts 4 clocks later after T0. RESET is allowed to go high 5 tCY (75 clocks) later for normal execution of code.
Table 3. Signature Mode Table
ABSOLUTE MAXIMUM RATINGS * Ambient Temperature Under Bias ÀÀÀÀ0 §Ct o a70§C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b65§Ct o a150§C Voltage on Any Pin with Respect to GroundÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b0.5V to a7V Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5 W NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. DC CHARACTERISTICS TA e 0§Ct o a70§C, V CC e VDD ea 5V g10%; a3.3V g10% UPI-L42 Symbol Parameter UPI-C42 UPI-L42 Units Notes Min Max Min Max VIL Input Low Voltage b0.5 0.8 b0.3 a0.8 V All Pins VIH Input High Voltage 2.0 V CC 2.0 V CC a 0.3 V (Except XTAL2, RESET) VIH1 Input High Voltage 3.5 V CC 2.0 V CC a 0.3 V (XTAL2, RESET) VOL Output Low Voltage (D 0 –D7) 0.45 0.45 V I OL e 2.0 mA UPI-C42 IOL e 1.3 mA UPI-L42 VOL1 Output Low Voltage 0.45 0.45 V I OL e 1.6 mA UPI-C42 (P10P17,P 20P27, Sync) I OL e 1 mA UPI-L42 VOL2 Output Low Voltage (PROG) 0.45 0.45 V I OL e 1.0 mA UPI-C42 IOL e 0.7 mA UPI-L42 VOH Output High Voltage (D 0 –D7) 2.4 2.4 V I OH eb 400 mA UPI-C42 IOH eb 260 mA UPI-L42 VOH1 Output High Voltage 2.4 2.4 I OH eb 50 mA UPI-C42 (All Other Outputs) I OH eb 25 mA UPI-L42 IIL Input Leakage Current g10 g10 mAV SS s VIN s VCC (T0,T 1, RD, WR, CS, A 0, EA) IOFL Output Leakage Current g10 g10 mAV SS a 0.45 s VOUT s VCC (D0 –D7, High Z State) ILI Low Input Load Current b50 b250 b35 b175 mA Port Pins (P10P17,P 20P27) Min V IN e 2.4V Max V IN e 0.45V ILI1 Low Input Load Current b40 b40 mAV IN s VIL (RESET, SS) IHI Port Sink Current 5.0 mA VCC e 3.0V (P10P17,P 20P27)V IH e 5.0V IDD VDD Supply Current 4 2.5 mA
TA e 0§Ct o a70§C, V CC e VDD ea 5V g10%; a3.3V g10% UPI-L42 (Continued) Symbol Parameter UPI-C42 UPI-L42 Units Notes Min Max Min Max ICC a IDD Total Supply Current: Active Mode @ 12.5 MHz 30 20 mA Typical 14 mA UPI-C42, 9 mA UPI-L42 Suspend Mode 40 26 mA Osc. Off (1, 4) IDD Standby Power Down 5 3.5 mA NMOS Compatible Power Down ModeSupply Current IIH Input Leakage Current 100 100 mAV IN e VCC (P10 –P17,P 20 –P27) CIN Input Capacitance 10 10 pF T A e 25§C (1) CIO I/O Capacitance 20 20 pF T A e 25§C (1) NOTE: 1. Sampled, not 100% tested. DC CHARACTERISTICSÐPROGRAMMING (UPI-C42 AND UPI-L42) TA e 25§C g5§C, V CC e 6.25V g0.25V, V DD e 12.75V g0.25V Symbol Parameter Min Max Units VDDH VDD Program Voltage High Level 12.5 13 V (1) VDDL VDD Voltage Low Level 4.75 5.25 V VPH PROG Program Voltage High Level 2.0 5.5 V VPL PROG Voltage Low Level b0.5 0.8 V VEAH Input High Voltage for EA 12.0 13.0 V (2) VEAL EA Voltage Low Level b0.5 5.25 V IDD VDD High Voltage Supply Current 50.0 mA IEA EA High Voltage Supply Current 1.0 mA (4) NOTES: 1. Voltages over 13V applied to pin V DD will permanently damage the device. 2. V EAH must be applied to EA before V DDH and removed after V DDL. 3. V CC must be applied simultaneously or before V DD and must be removed simultaneously or after V DD. 4. Sampled, not 100% tested.
TA e 0§Ct o a70§C, V SS e 0V, V CC e VDD ea 5V g10%; a3.3V g10% for the UPI-L42 NOTE: All AC Characteristics apply to both the UPI-C42 and UPI-L42 DBB READ Symbol Parameter Min Max Units tAR CS, A 0 Setup to RD v 0n s tRA CS, A 0 Hold After RD u 0n s tRR RD Pulse Width 160 ns tAD CS, A 0 to Data Out Delay 130 ns tRD RDvto Data Out Delay 0 130 ns tDF RDuto Data Float Delay 85 ns DBB WRITE Symbol Parameter Min Max Units tAW CS, A 0 Setup to WR v 0n s tWA CS, A 0 Hold After WR u 0n s tWW WR Pulse Width 160 ns tDW Data Setup to WR u 130 ns tWD Data Hold After WR u 0n s
TA e 0§Ct o a70§C, V SS e 0V, V CC e VDD ea 5V g10%; a3.3V g10% for the UPI-L42 (Continued) CLOCK Symbol Parameter Min Max Units tCY UPI-C42/UPI-L42 Cycle Time 1.2 9.20 ms(1) tCYC UPI-C42/UPI-L42 Clock Period 80 613 ns tPWH Clock High Time 30 ns tPWL Clock Low Time 30 ns tR Clock Rise Time 10 ns tF Clock Fall Time 10 ns NOTE: 1. t CY e 15/f(XTAL) AC CHARACTERISTICS DMA Symbol Parameter Min Max Units tACC DACK to WR or RD 0 ns tCAC RD or WR to DACK 0 ns tACD DACK to Data Valid 0 130 ns tCRQ RD or WR to DRQ Cleared 110 ns (1) NOTE: 1. C L e 150 pF. AC CHARACTERISTICS PORT 2 Symbol Parameter f(t CY)(3) Min Max Units tCP Port Control Setup Before Falling Edge of PROG 1/15 t CYb28 55 ns (1) tPC Port Control Hold After Falling Edge of PROG 1/10 t CY 125 ns (2) tPR PROG to Time P2 Input Must Be Valid 8/15 t CYb16 650 ns (1) tPF Input Data Hold Time 0 150 ns (2) tDP Output Data Setup Time 2/10 t CY 250 ns (1) tPD Output Data Hold Time 1/10 t CYb80 45 ns (2) tPP PROG Pulse Width 6/10 t CY 750 ns NOTES: 1. C L e 80 pF. 2. C L e 20 pF. 3. t CY e 1.25 ms.
AC CHARACTERISTICSÐPROGRAMMING (UPI-C42 AND UPI-L42) (87C42/87L42 ONLY) Symbol Parameter Min Max Units tAW Address Setup Time to RESET u 4tCY tWA Address Hold Time after RESET u 4tCY tDW Data in Setup Time to PROG v 4tCY tWD Data in Hold Time after PROG u 4tCY tPW Initial Program Pulse Width 95 105 ms tTW Test 0 Setup Time for Program Mode 4t CY tWT Test 0 Hold Time after Program Mode 4t CY tDO Test 0 to Data Out Delay 4t CY tWW RESET Pulse Width to Latch Address 4t CY tr,t f PROG Rise and Fall Times 0.5 100 ms tCY CPU Operation Cycle Time 2.5 3.75 ms tRE RESET Setup Time before EA u 4tCY tOPW Overprogram Pulse Width 2.85 78.75 ms (1) tDE EA High to V DD High 1t CY NOTES: 1. This variation is a function of the iteration counter value, X. 2. If TEST 0 is high, t DO can be triggered by RESET u. AC TESTING INPUT/OUTPUT WAVEFORM INPUT/OUTPUT 290414–16 AC TESTING LOAD CIRCUIT 290414–17
DRIVING FROM AN EXTERNAL SOURCE 290414–18 NOTE: See XTAL1 Configuration Table. 290414–19 Rise and Fall Times Should Not Exceed 10 ns. Resistors to V CC are Needed to Ensure V IH e 3.5V if TTL Circuitry is Used. LC OSCILLATOR MODE L C NOMINAL f e 1 2q0LCÊ45 H 20 pF 5.2 MHz 120 H 20 pF 3.2 MHz CÊ e C a 3Cpp Cpp j 5–10 pF Pin-to-Pin Capacitance 290414–20 Each C Should be Approximately 20 pF, including Stray Capacitance. CRYSTAL OSCILLATOR MODE 290414–21 C1 5 pF (STRAY 5 pF) C2 (CRYSTAL a STRAY) 8 pF C3 20–30 pF INCLUDING STRAY Crystal Series Resistance Should be Less Than 30 X at 12.5 MHz. XTAL1 Configuration Table XTAL1 Connection 1) to Ground 2) 10 K X Resistor 3) Not Connectedto Ground Not recommended for CHMOS Recommended configuration for Low power configuration designs. Causes approximately designs which will use both recommended for CHMOS only 16 mA of additional current flow NMOS and CHMOS parts. This designs to provide lowest through the XTAL1 pin on UPI- configuration limits the additional possible power consumption. C42 and approximately 11 mA of current through the XTAL1 pin to This configuration will not work additional current through XTAL1 approximately 1 mA, while with the NMOS device. on the UPI-L42. maintaining compatibility with the NMOS device.
READ OPERATIONÐDATA BUS BUFFER REGISTER 290414–22 WRITE OPERATIONÐDATA BUS BUFFER REGISTER 290414–23 CLOCK TIMING 290414–24
WAVEFORMS (Continued) COMBINATION PROGRAM/VERIFY MODE 290414–25 NOTES: 1. A 0 must be held low (0V) during program/verify modes. 2. For V IH,V IH1,V IL,V IL1,V DDH, and V DDL, please consult the D.C. Characteristics Table. 3. When programming the 87C42, a 0.1 mF capacitor is required across V DD and ground to suppress spurious voltage transients which can damage the device. VERIFY MODE 290414–26 NOTES: 1. PROG must float if EA is low. 2. PROG must float or e 5V when EA is high. 3. P 10 –P17 e 5V or must float. 4. P 24 –P27 e 5V or must float. 5. A 0 must be held low during programming/verify modes.
WAVEFORMS (Continued) DMA 290414–27 PORT 2 290414–28 PORT TIMING DURING EXTERNAL ACCESS (EA) 290414–29 On the Rising Edge of SYNC and EA is Enabled, Port Data is Valid and can be Strobed. On the Trailing Edge of Sync the Program Counter Contents are Available.
Table 4. UPI Instruction Set
Table 4. UPI Instruction Set (Continued)
- Delete all references to standby power down
- Added information on keyboard controller prod-
- Added I HI specification for the UPI-L42.
- Added UPI-L42 references and specification.