80C186EC INTEL | Alldatasheet
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*Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. May 1996COPYRIGHT © INTEL CORPORATION, 1996 Order Number: 272434-004 80C186EC/80C188EC AND 80L186EC/80L188EC 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS X Fully Static Operation X True CMOS Inputs and Outputs Y Integrated Feature Set: Ð Low-Power, Static, Enhanced 8086 CPU Core Ð Two Independent DMA Supported UARTs, each with an Integral Baud Rate Generator Ð Four Independent DMA Channels Ð 22 Multiplexed I/O Port Pins Ð Two 8259A Compatible Programmable Interrupt Controllers Ð Three Programmable 16-Bit Timer/ Counters Ð 32-Bit Watchdog Timer Ð Ten Programmable Chip Selects with Integral Wait-State Generator Ð Memory Refresh Control Unit Ð Power Management Unit Ð On-Chip Oscillator Ð System Level Testing Support (ONCE Mode) Y Direct Addressing Capability to 1 Mbyte Memory and 64 Kbyte I/O Y Low-Power Operating Modes: Ð Idle Mode Freezes CPU Clocks but Keeps Peripherals Active Ð Powerdown Mode Freezes All Internal Clocks Ð Powersave Mode Divides All Clocks by Programmable Prescalar Y Available in Extended Temperature Range ( b40§Ct o a85§C) Y Supports 80C187 Numerics Processor Extension (80C186EC only) Y Package Types: Ð 100-Pin EIAJ Quad Flat Pack (QFP) Ð 100-Pin Plastic Quad Flat Pack (PQFP) Ð 100-Pin Shrink Quad Flat Pack (SQFP) Y Speed Versions Available (5V): Ð 25 MHz (80C186EC25/80C188EC25) Ð 20 MHz (80C186EC20/80C188EC20) Ð 13 MHz (80C186EC13/80C188EC13) Y Speed Version Available (3V): Ð 16 MHz (80L186EC16/80L188EC16) Ð 13 MHz (80L186EC13/80L188EC13) The 80C186EC is a member of the 186 Integrated Processor Family. The 186 Integrated Processor Family incorporates several different VLSI devices all of which share a common CPU architecture: the 8086/8088. The 80C186EC uses the latest high density CHMOS technology to integrate several of the most common system peripherals with an enhanced 8086 CPU core to create a powerful system on a single monolithic silicon die.
80C186EC/80C188EC and 80L186EC/80L188EC 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR CONTENTS PAGE INTRODUCTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4 80C186EC CORE ARCHITECTURE ÀÀÀÀÀÀÀ 4 Bus Interface Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4 Clock Generator ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4 80C186EC PERIPHERAL ARCHITECTURE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5 Programmable Interrupt Controllers ÀÀÀÀÀÀÀÀÀ 7 Timer/Counter Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7 Serial Communications Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7 DMA Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7 Chip-Select Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7 I/O Port Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7 Refresh Control Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7 Watchdog Timer Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7 Power Management Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8 80C187 Interface (80C186EC only) ÀÀÀÀÀÀÀÀÀ 8 ONCE Test Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8 PACKAGE INFORMATION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8 Prefix Identification ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8 Pin Descriptions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8 Pinout ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 15 Package Thermal Specifications ÀÀÀÀÀÀÀÀÀÀÀ 24 ELECTRICAL SPECIFICATIONS ÀÀÀÀÀÀÀÀÀ 25 Absolute Maximum Ratings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 25 CONTENTS PAGE Recommended Connections ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 25 DC SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 26 ICC versus Frequency and Voltage ÀÀÀÀÀÀÀÀÀ 29 PDTMR Pin Delay Calculation ÀÀÀÀÀÀÀÀÀÀÀÀÀ 29 AC SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 30 AC CharacteristicsÐ80C186EC25 ÀÀÀÀÀÀÀÀÀ 30 AC CharacteristicsÐ80C186EC20/13 ÀÀÀÀÀ 32 AC CharacteristicsÐ80L186EC13 ÀÀÀÀÀÀÀÀÀ 33 AC CharacteristicsÐ80L186EC16 ÀÀÀÀÀÀÀÀÀ 34 Relative Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 35 Serial Port Mode 0 Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 36 AC TEST CONDITIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 37 AC TIMING WAVEFORMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 37 DERATING CURVES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 40 RESET ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 40 BUS CYCLE WAVEFORMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 43 EXECUTION TIMINGS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 50 INSTRUCTION SET SUMMARY ÀÀÀÀÀÀÀÀÀÀ 51 ERRATA ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 57 REVISION HISTORY ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 57
Figure 1. 80C186EC/80L186EC Block Diagram
80C186EC/188EC, 80L186EC/188EC INTRODUCTION Unless specifically noted, all references to the 80C186EC apply to the 80C188EC, 80L186EC, and 80L188EC. References to pins that differ between the 80C186EC/80L186EC and the 80C188EC/ 80L188EC are given in parentheses. The ‘‘L’’ in the part number denotes low voltage operation. Physi- cally and functionally, the ‘‘C’’ and ‘‘L’’ devices are identical. The 80C186EC is one of the highest integration members of the 186 Integrated Processor Family. Two serial ports are provided for services such as interprocessor communication, diagnostics and mo- dem interfacing. Four DMA channels allow for high speed data movement as well as support of the on- board serial ports. A flexible chip select unit simpli- fies memory and peripheral interfacing. The three general purpose timer/counters can be used for a variety of time measurement and waveform genera- tion tasks. A watchdog timer is provided to insure system integrity even in the most hostile of environ- ments. Two 8259A compatible interrupt controllers handle internal interrupts, and, up to 57 external in- terrupt requests. A DRAM refresh unit and 24 multi- plexed I/O ports round out the feature set of the 80C186EC. The future set of the 80C186EC meets the needs of low-power, space-critical applications. Low-power applications benefit from the static design of the CPU and the integrated peripherals as well as low voltage operation. Minimum current consumption is achieved by providing a powerdown mode that halts operaton of the device and freezes the clock cir- cuits. Peripheral design enhancements ensure that non-initialized peripherals consume little current. The 80L186EC is the 3V version of the 80C186EC. The 80L186EC is functionally identical to the 80C186EC embedded processor. Current 80C186EC users can easily upgrade their designs to use the 80L186EC and benefit from the reduced power consumption inherent in 3V operation. Figure 1 shows a block diagram of the 80C186EC/ 80C188EC. The execution unit (EU) is an enhanced
8086 CPU core that includes: dedicated hardware to
speed up effective address calculations, enhanced execution speed for multiple-bit shift and rotate in- structions and for multiply and divide instructions, string move instructions that operate at full bus bandwidth, ten new instructions and fully static oper- ation. The bus interface unit (BIU) is the same as that found on the original 186 family products, ex- cept the queue-status mode has been deleted and buffer interface control has been changed to ease system design timings. An independent internal bus is used for communication between the BIU and on- chip peripherals. 80C186EC CORE ARCHITECTURE Bus Interface Unit The 80C186EC core incorporates a bus controller that generates local bus control signals. In addition, it employs a HOLD/HLDA protocol to share the local bus with other bus masters. The bus controller is responsible for generating 20 bits of address, read and write strobes, bus cycle status information and data (for write operations) in- formation. It is also responsible for reading data from the local bus during a read operation. A ready input pin is provided to extend a bus cycle beyond the minimum four states (clocks). The bus controller also generates two control sig- nals (DEN and DT/R ) when interfacing to external transceiver chips. This capability allows the addition of transceivers for simple buffering of the multi- plexed address/data bus. Clock Generator The 80C186EC provides an on-chip clock generator for both internal and external clock generation. The clock generator features a crystal oscillator, a divide- by-two counter and three low-power operating modes. The oscillator circuit is designed to be used with ei- ther a parallel resonant fundamental or third-over- tone mode crystal network. Alternatively, the oscilla- tor circuit may be driven from an external clock source. Figure 2 shows the various operating modes of the oscillator circuit. The crystal or clock frequency chosen must be twice the required processor operating frequency due to the internal divide-by-two counter. This counter is used to drive all internal phase clocks and the exter- nal CLKOUT signal. CLKOUT is a 50% duty cycle processor clock and can be used to drive other sys- tem components. All AC timings are referenced to CLKOUT. The following parameters are recommended when choosing a crystal: Temperature Range: Application Specific ESR (Equivalent Series Res.): 40 X max C0 (Shunt Capacitance of Crystal): 7.0 pF max C L (Load Capacitance): 20 pF g2p F Drive Level: 1 mW (max)
Figure 3. Peripheral Control Block Registers
80C186EC/188EC, 80L186EC/188EC Programmable Interrupt Controllers The 80C186EC utilizes two 8259A compatible Pro- grammable Interrupt Controllers (PIC) to manage both internal and external interrupts. The 8259A modules are configured in a master/slave arrange- ment. Seven of the external interrupt pins, INT0 through INT6, are connected to the master 8259A module. The eighth external interrupt pin, INT7, is connected to the slave 8259A module. There are a total of 11 internal interrupt sources from the integrated peripherals: 4 Serial, 4 DMA and 3 Timer/Counter. Timer/Counter Unit The 80C186EC Timer/Counter Unit (TCU) provides three 16-bit programmable timers. Two of these are highly flexible and are connected to external pins for external control or clocking. The third timer is not connected to any external pins and can only be clocked internally. However, it can be used to clock the other two timer channels. The TCU can be used to count external events, time external events, gen- erate non-repetitive waveforms or generate timed in- terrupts. Serial Communications Unit The 80C186EC Serial Communications Unit (SCU) contains two independent channels. Each channel is identical in operation except that only channel 0 is directly supported by the integrated interrupt control- ler (the channel 1 interrupts are routed to external interrupt pins). Each channel has its own baud rate generator and can be internally or externally clocked up to one half the processor operating frequency. Both serial channels can request service from the DMA unit thus providing block reception and trans- mission without CPU intervention. Independent baud rate generators are provided for each of the serial channels. For the asynchronous modes, the generator supplies an 8x baud clock to both the receive and transmit shifting register logic. A 1x baud clock is provided in the synchronous mode. DMA Unit The four channel Direct Memory Access (DMA) Unit is comprised of two modules with two channels each. All four channels are identical in operation. DMA transfers can take place from memory to mem- ory, I/O to memory, memory to I/O or I/O to I/O. DMA requests can be external (on the DRQ pins), internal (from Timer 2 or a serial channel) or soft- ware initiated. The DMA Unit transfers data as bytes only. Each data transfer requires at least two bus cycles, one to fetch data and one to deposit. The minimum clock count for each transfer is 8, but this will vary depend- ing on synchronization and wait states. Chip-Select Unit The 80C186EC Chip-Select Unit (CSU) integrates logic which provides up to ten programmable chip- selects to access both memories and peripherals. In addition, each chip-select can be programmed to automatically insert additional clocks (wait states) into the current bus cycle, and/or automatically ter- minate a bus cycle independent of the condition of the READY input pin. I/O Port Unit The I/O Port Unit on the 80C186EC supports two 8-bit channels and one 6-bit channel of input, output or input/output operation. Port 1 is multiplexed with the chip select pins and is output only. Port 2 is mul- tiplexed with the pins for serial channels 1 and 2. All Port 2 pins are input/output. Port 3 has a total of 6 pins: four that are multiplexed with DMA and serial port interrupts and two that are non-multiplexed, open drain I/O. Refresh Control Unit The Refresh Control Unit (RCU) automatically gen- erates a periodic memory read bus cycle to keep dynamic or pseudo-static memory refreshed. A 9-bit counter controls the number of clocks between re- fresh requests. A 12-bit address generator is maintained by the RCU and is presented on the A12:1 address lines during the refresh bus cycle. Address bits A19:13 are pro- grammable to allow the refresh address block to be located on any 8 Kbyte boundary. Watchdog Timer Unit The Watchdog Timer Unit (WDT) allows for graceful recovery from unexpected hardware and software upsets. The WDT consists of a 32-bit counter that decrements every clock cycle. If the counter reach- es zero before being reset, the WDTOUT pin is
80C186EC/188EC, 80L186EC/188EC pulled low for four clock cycles. Logically ANDing the WDTOUT pin with the power-on reset signal al- lows the WDT to reset the device in the event of a WDT timeout. If a less drastic method of recovery is desired, WDTOUT can be connected directly to NMI or one of the INT input pins. The WDT may also be used as a general purpose timer. Power Management Unit The 80C186EC Power Management Unit (PMU) is provided to control the power consumption of the device. The PMU provides four power management modes: Active, Powersave, Idle and Powerdown. Active Mode indicates that all units on the 80C186EC are operating at (/2 the CLKIN frequency. Idle Mode freezes the clocks of the Execution and Bus units at a logic zero state (all peripherals contin- ue to operate normally). The Powerdown Mode freezes all internal clocks at a logic zero level and disables the crystal oscillator. In Powersave Mode, all internal clock signals are di- vided by a programmable prescalar (up to (/64 the normal frequency). Powersave Mode can be used with Idle Mode as well as during normal (Active Mode) operation. 80C187 Interface (80C186EC only) The 80C186EC supports the direct connection of the 80C187 Numerics Processor Extension. The 80C187 can dramatically improve the performance of calculation intensive applications. ONCE Test Mode To facilitate testing and inspection of devices when fixed into a target system, the 80C186EC has a test mode available which forces all output and input/ output pins to be placed in the high-impedance state. ONCE stands for ‘‘ON Circuit Emulation’’. The ONCE mode is selected by forcing the A19/S6/ONCE pin low during a processor reset (this pin is weakly held high during reset to prevent inadvertant entrance into ONCE Mode).
PACKAGE INFORMATION
This section describes the pin functions, pinout and thermal characteristics for the 80C186EC in the Plastic Quad Flat Pack (JEDEC PQFP), the EIAJ Quad Flat Pack (QFP) and the Shrink Quad Flat Pack (SQFP). For complete package specifications and information, see the Intel Packaging Outlines and Dimensions Guide (Order Number: 231369). Prefix Identification Table 1 lists the prefix identifications. Table 1. Prefix Identification
- The 5V 25 MHz version is only available in commercial
- There are four columns for each entry in the Pin
pins have more than 1 function.
Descriptions is shown in Table 1. tional (i.e. have both an input and output function). be synchronized to CLKOUT for proper operation. the processor is in the Hold Acknowledge state. Mode (with the exception of OSCOUT). Table 1. Pin Description Nomenclature
Table 2. Pin Descriptions crystal connections to an internal Pierce oscillator. any bus cycle in progress and assume an initialized state. to be serviced by the CPU. NMI is latched internally. Pin names in parentheses apply to the 80C188EC/80L188EC.
Table 2. Pin Descriptions (Continued) These pins are used as inputs during factory test; driving(A15:8) P(0) these pins low during reset will cause unspecified operation. AD12:0 I/O S(L) H(Z) These pins provide a multiplexed ADDRESS and DATA bus. the bus and can be latched using ALE. Data information isP(0) transferred during the data phase of the bus cycle. indicate a refresh bus cycle. Pin names in parentheses apply to the 80C188EC/80L188EC.
configured as a weakly held high input while RESIN is activeP(X) and must not be driven low. boundaries that are not LOCKed. control signals allowing another bus master to drive theP(0) signals directly. exist on the 80C188EC/80L188EC. Pin names in parentheses apply to the 80C188EC/80L188EC.
be active for memory accesses between 0FFC00H andP(1) 0FFFFFH. can be configured as level or edge sensitive. P3.5 I/O A(L) H(X) Bidirectional, open-drain port pins. Pin names in parentheses apply to the 80C188EC/80L188EC.
BCLK input frequency cannot exceed (/2 the operatingP(X) frequency of the processor . P2.5/TXD1 I/O A(L) H(Q) Transmit Data output provides serial data information. and will become an output for transmission of data (TXDP(X) becomes the clock). programmed synchronization mode.
- READY is A(E) for the rising edge of CLKOUT, S(E) for the falling edge of CLKOUT.
- Pin names in parentheses apply to the 80C188EC/80L188EC.
Table 3. PQFP Pin Functions with Location
Table 4. PQFP Pin Locations with Pin Name
1 DRQ3
2 T0OUT
3 T0IN
4 T1OUT
5 T1IN
6 CLKOUT
7 RESOUT
8 RESIN
9 PDTMR
10 CLKIN
11 OSCOUT
13 V CC
14 V CC
15 V SS
30 INT0
31 INT1
32 INT2
33 INT3
34 INTA
36 WDTOUT
37 V SS
38 V CC
39 V SS
40 INT4
41 INT5
42 INT6
43 INT7
44 HOLD
45 HLDA
46 DT/R
47 DEN
48 LOCK
51 BHE (RFSH)
52 ALE
53 AD15 (A15)
54 AD14 (A14)
55 AD13 (A13)
56 AD12 (A12)
57 AD11 (A11)
58 AD10 (A10)
59 AD9 (A9)
60 AD8 (A8)
62 V CC
63 AD7
64 AD6
65 AD5
66 AD4
68 V SS
69 V CC
70 AD3
71 AD2
72 AD1
73 AD0
74 A19/S6/ONCE
75 A18/S5
76 A17/S4
77 A16/S3
81 PEREQ (V SS)
82 NMI
83 TEST
84 ERROR (VCC)
85 READY
87 V SS
88 UCS
89 LCS
98 DRQ0
99 DRQ1
100 DRQ2
This is the FPO number location (indicated by X’s). Figure 4. 100-Pin Plastic Quad Flat Pack Package (PQFP)
Table 5. QFP Pin Names with Package Location
Table 6. QFP Package Location with Pin Names
1 DRQ0
2 DRQ1
3 DRQ2
4 DRQ3
5 T0OUT
6 T0IN
7 T1OUT
8 T1IN
9 CLKOUT
10 RESOUT
11 RESIN
12 PDTMR
13 CLKIN
14 OSCOUT
16 V CC
17 V CC
18 V SS
33 INT0
34 INT1
35 INT2
36 INT3
37 INTA
39 WDTOUT
40 V SS
41 V CC
42 V SS
43 INT4
44 INT5
45 INT6
46 INT7
47 HOLD
48 HLDA
49 DT/R
50 DEN
51 LOCK
54 BHE (RFSH)
55 ALE
56 AD15 (A15)
57 AD14 (A14)
58 AD13 (A13)
59 AD12 (A12)
60 AD11 (A11)
61 AD10 (A10)
62 AD9 (A9)
63 AD8 (A8)
65 V CC
66 AD7
67 AD6
68 AD5
69 AD4
71 V SS
72 V CC
73 AD3
74 AD2
75 AD1
76 AD0
77 A19/S6/ONCE
78 A18/S5
79 A17/S4
80 A16/S3
84 PEREQ (V SS)
85 NMI
86 TEST
87 ERROR (VCC)
88 READY
90 V SS
91 UCS
92 LCS
This is the FPO number location (indicated by X’s). Figure 5. Quad Flat Pack (EIAJ) Pinout Diagram
Table 7. SQFP Pin Functions with Location
Table 8. SQFP Pin Locations with Pin Names
63 AD7 (A7)
64 AD6 (A6)
74 A19/ONCE
75 AD18
76 A17
77 A16
82 MNI
Figure 6. 100-Pin Shrink Quad Flat Pack Package (SQFP)
Table 9. Thermal Resistance ( iCA) at Various Airflows (in §C/Watt)
80C186EC/188EC, 80L186EC/188EC ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b65§Ct o a150§C Case Temperature Under BiasÀÀÀ b65§Ct o a100§C Supply Voltage with Respect to V SS ÀÀÀÀÀÀÀÀÀÀÀb0.5V to a6.5V Voltage on Other Pins with Respect to V SS ÀÀÀÀÀÀb0.5V to V CC a 0.5V NOTICE: This data sheet contains preliminary infor- mation on new products in production. The specifica- tions are subject to change without notice. Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. Recommended Connections Power and ground connections must be made to multiple V CC and V SS pins. Every 80C186EC-based circuit board should include separate power (V CC) and ground (V SS) planes. Every V CC pin must be connected to the power plane, and every V SS pin must be connected to the ground plane. Liberal de- coupling capacitance should be placed near the processor. The processor can cause transient pow- er surges when its output buffers transition, particu- larly when connected to large capacitive loads. Low inductance capacitors and interconnects are recommended for best high frequency electrical per- formance. Inductance is reduced by placing the de- coupling capacitors as close as possible to the proc- essor V CC and V SS package pins. Always connect any unused input to an appropriate signal level. In particular, unused interrupt inputs (NMI, INT0:7) should be connected to V SS through a pull-down resistor. Leave any unused output pin un- connected.
80C186EC/188EC, 80L186EC/188EC DC SPECIFICATIONS (80C186EC/80C188EC) Symbol Parameter Min Max Units Notes VCC Supply Voltage 4.5 5.5 V VIL Input Low Voltage b0.5 0.3 V CC V VIH Input High Voltage 0.7 V CC VCC a 0.5 V VOL Output Low Voltage 0.45 V I OL e 3 mA (Min) VOH Output High Voltage V CC b 0.5 V I OH eb 2 mA (Min) VHYR Input Hysteresis on RESIN 0.5 V ILI Input Leakage Current for Pins: g15 mA0 s VIN s VCC AD15:0 (AD7:0, A15:8), READY, HOLD, RESIN , CLKIN, TEST /BUSY, NMI, INT7:0, T0IN, T1IN, P2.7–P2.0, P3.5–P3.0, DRQ3:0, PEREQ, ERROR ILIU Input Leakage for Pins with Pullups b0.275 b5m A V IN e 0.7 V CC Active During Reset: (Note 1) A19:16, LOCK ILO Output Leakage for Floated Output g15 mA 0.45 s VOUT s VCC Pins (Note 2) ICC Supply Current Cold (in RESET) 80C186EC25 125 mA (Notes 3, 7) 80C186EC20 100 mA (Note 3) 80C186EC13 70 mA (Note 3) IID Supply Current in Idle Mode 80C186EC25 92 mA (Notes 4, 7) 80C186EC20 76 mA (Note 4) 80C186EC13 50 mA (Note 4) IPD Supply Current in Powerdown Mode 80C186EC25 100 mA (Notes 5, 7) 80C186EC20 100 mA (Note 5) 80C186EC13 100 mA (Note 5) CIN Input Pin Capacitance 0 15 pF T F e 1 MHz COUT Output Pin Capacitance 0 15 pF T F e 1 MHz (Note 6) NOTES: 1. These pins have an internal pull-up device that is active while RESIN is low and ONCE Mode is not active. Sourcing more current than specified (on any of these pins) may invoke a factory test mode. 2. Tested by outputs being floated by invoking ONCE Mode or by asserting HOLD. 3. Measured with the device in RESET and at worst case frequency, V CC, and temperature with ALL outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V CC or GND. 4. Measured with the device in HALT (IDLE Mode active) and at worst case frequency, V CC, and temperature with ALL outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V CC or GND. 5. Measured with the device in HALT (Powerdown Mode active) and at worst case frequency, V CC, and temperature with ALL outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V CC or GND. 6. Output Capacitance is the capacitive load of a floating output pin. 7. Operating conditions for 25 MHz is 0 §Ct o a70§C, V CC e 5.0 g10%.
80C186EC/188EC, 80L186EC/188EC DC SPECIFICATIONS (80L186EC13/80L188EC13) Symbol Parameter Min Max Units Notes VCC Supply Voltage 2.7 5.5 V VIL Input Low Voltage b0.5 0.3 V CC V VIH Input High Voltage 0.7 V CC VCC a 0.5 V VOL Output Low Voltage 0.45 V I OL e 3 mA (Min) VOH Output High Voltage V CC b 0.5 V I OH eb 2 mA (Min) VHYR Input Hysteresis on RESIN 0.5 V ILI Input Leakage Current for Pins: g15 mA0 s VIN s VCC AD15:0 (AD7:0, A15:8), READY, HOLD, RESIN , CLKIN, TEST/BUSY, NMI, INT7:0, T0IN, T1IN, P2.7–P2.0, P3.5–P3.0, DRQ3:0, PEREQ, ERROR ILIU Input Leakage for Pins with Pullups b0.275 b5m A V IN e 0.7 V CC Active During Reset: (Note 1) A19:16, LOCK ILO Output Leakage for Floated Output g15 mA 0.45 s VOUT s VCC Pins (Note 2) ICC Supply Current Cold (in RESET) (Note 3) 80L186EC-13 36 mA IID Supply Current in Idle Mode (Note 4) 80L186EC-13 24 mA IPD Supply Current in Powerdown Mode (Note 5) 80L186EC-13 30 mA CIN Input Pin Capacitance 0 15 pF T F e 1 MHz COUT Output Pin Capacitance 0 15 pF T F e 1 MHz (Note 6) NOTES: 1. These pins have an internal pull-up device that is active while RESIN is low and ONCE Mode is not active. Sourcing more current than specified (on any of these pins) may invoke a factory test mode. 2. Tested by outputs being floated by invoking ONCE Mode or by asserting HOLD. 3. Measured with the device in RESET and at worst case frequency, V CC, and temperature with ALL outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V CC or GND. 4. Measured with the device in HALT (IDLE Mode active) and at worst case frequency, V CC, and temperature with ALL outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V CC or GND. 5. Measured with the device in HALT (Powerdown Mode active) and at worst case frequency, V CC, and temperature with ALL outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V CC or GND. 6. Output Capacitance is the capacitive load of a floating output pin.
80C186EC/188EC, 80L186EC/188EC DC SPECIFICATIONS (80L186EC16/80L188EC16) (Operating Temperature 0 §Ct o7 0 §C) Symbol Parameter Min Max Units Notes VCC Supply Voltage 3.0 5.5 V VIL Input Low Voltage b0.5 0.3 V CC V VIH Input High Voltage 0.7 V CC VCC a 0.5 V VOL Output Low Voltage 0.45 V I OL e 3 mA (Min) VOH Output High Voltage V CC b 0.5 V I OH eb 2 mA (Min) VHYR Input Hysteresis on RESIN 0.5 V ILI Input Leakage Current for Pins: g15 mA0 s VIN s VCC AD15:0 (AD7:0, A15:8), READY, HOLD, RESIN , CLKIN, TEST/BUSY, NMI, INT7:0, T0IN, T1IN, P2.7–P2.0, P3.5–P3.0, DRQ3:0, PEREQ, ERROR ILIU Input Leakage for Pins with Pullups b0.275 b5m A V IN e 0.7 V CC Active During Reset: (Note 1) A19:16, LOCK ILO Output Leakage for Floated Output g15 mA 0.45 s VOUT s VCC Pins (Note 2) ICC Supply Current Cold (in RESET) (Note 3) 80L186EC-16 45 mA IID Supply Current in Idle Mode (Note 4) 80L186EC-16 35 mA IPD Supply Current in Powerdown Mode (Note 5) 80L186EC-16 50 mA CIN Input Pin Capacitance 0 15 pF T F e 1 MHz COUT Output Pin Capacitance 0 15 pF T F e 1 MHz (Note 6) NOTES: 1. These pins have an internal pull-up device that is active while RESIN is low and ONCE Mode is not active. Sourcing more current than specified (on any of these pins) may invoke a factory test mode. 2. Tested by outputs being floated by invoking ONCE Mode or by asserting HOLD. 3. Measured with the device in RESET and at worst case frequency, V CC, and temperature with ALL outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V CC or GND. 4. Measured with the device in HALT (IDLE Mode active) and at worst case frequency, V CC, and temperature with ALL outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V CC or GND. 5. Measured with the device in HALT (Powerdown Mode active) and at worst case frequency, V CC, and temperature with ALL outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V CC or GND. 6. Output Capacitance is the capacitive load of a floating output pin.
80C186EC/188EC, 80L186EC/188EC ICC versus Frequency and Voltage The I CC consumed by the processor is composed of two components: 1. I PDÐThe quiescent current that represents inter- nal device leakage. Measured with all inputs at either V CC or ground and no clock applied. 2. I CCSÐThe switching current used to charge and discharge internal parasitic capacitance when changing logic levels. I CCS is related to both the frequency of operation and the device supply voltage (V CC). I CCS is given by the formula: Power e V * I e V2 * CDEV * f ... ICCS e V * CDEV * f Where: V e Supply Voltage (V CC) CDEV e Device Capacitance f e Operating Frequency Measuring C PD on a device like the 80C186EC would be difficult. Instead, C PD is calculated using the above formula with I CC values measured at known V CC and frequency. Using the C PD value, the user can calculate I CC at any voltage and frequency within the specified operating range. Example. Calculate typical I CC at 14 MHz, 5.2V V CC. ICC e IPD a ICCS e 0.1 mA a 5.2V * 0.77 * 14 MHz e 56.2 mA PDTMR Pin Delay Calculation The PDTMR pin provides a delay between the as- sertion of NMI and the enabling of the internal clocks when exiting Powerdown Mode. A delay is required only when using the on chip oscillator to allow the crystal or resonator circuit to stabilize. NOTE: The PDTMR pin function does not apply when RESIN is asserted (i.e. a device reset while in Pow- erdown is similar to a cold reset and RESIN must remain active until after the oscillator has stabilized. To calculate the value of capacitor to use to provide a desired delay, use the equation: 440 c t e CPD (5V, 25 §C) Where: t e desired delay in seconds CPD e capacitive load on PDTMR in microfarads Example. For a delay of 300 ms, a capacitor value of CPD e 440 c (300 c 10b6 e 0.132 mF is required. Round up to a standard (available) capacitor value. NOTE: The above equation applies to delay time longer than 10 ms and will compute the TYPICAL capaci- tance needed to achieve the desired delay. A delay variance of a50% to b25% can occur due to temperature, voltage, and device process ex- tremes. In general, higher V CC and/or lower tem- peratures will decrease delay time, while lower V CC and/or higher temperature will increase delay time. Parameter Typical Max Units Notes CPD 0.77 1.37 mA/V *MHz 1, 2 CPD (Idle Mode) 0.55 0.96 mA/V *MHz 1, 2 NOTES: 1. Maximum C PD is measured at b40§C with all outputs loaded as specified in the AC test conditions and the device in reset (or Idle Mode). Due to tester limitations, CLKOUT and OSCOUT also have 50 pF loads that increase I CC by V *C*F. 2. Typical C PD is calculated at 25 §C assuming no loads on CLKOUT or OSCOUT and the device in reset (or Idle Mode).
80C186EC/188EC, 80L186EC/188EC AC SPECIFICATIONS AC CharacteristicsÐ80C186EC25 Symbol Parameter
25 MHz
TF CLKIN Frequency 0 50 MHz 1 TC CLKIN Period 20 % ns 1 TCH CLKIN High Time 8 % ns 1, 2 TCL CLKIN Low Time 8 % ns 1, 2 TCR CLKIN Rise Time 1 10 ns 1, 3 TCF CLKIN Fall Time 1 10 ns 1, 3 OUTPUT CLOCK TCD CLKIN to CLKOUT Delay 0 17 ns 1, 4 T CLKOUT Period 2 *TC ns 1 TPH CLKOUT High Time (T/2) b 5 (T/2) a 5n s 1 TPL CLKOUT Low Time (T/2) b 5 (T/2) a 5n s 1 TPR CLKOUT Rise Time 1 6 ns 1, 5 TPF CLKOUT Fall Time 1 6 ns 1, 5 OUTPUT DELAYS TCHOV1 ALE, S2:0 , DEN , DT/R , 3 17 ns 1, 4, 6, 7 BHE (RFSH), LOCK , A19:16 TCHOV2 GCS0:7, LCS , UCS , NCS ,R D ,W R 3 2 0 n s 1 ,4 ,6 ,8 TCLOV1 BHE (RFSH), DEN , LOCK , RESOUT, 3 17 ns 1, 4, 6 HLDA, T0OUT, T1OUT, A19:16 TCLOV2 RD,W R , GCS7:0 , LCS , UCS , AD15:0 3 20 ns 1, 4, 6 (AD7:0, A15:8), NCS , INTA1:0 , S2:0 TCHOF RD,W R , BHE (RFSH), DT/R , 0 20 ns 1 LOCK, S2:0 , A19:16 TCLOF DEN, AD15:0 (AD7:0, A15:8) 0 20 ns 1
80C186EC/188EC, 80L186EC/188EC AC SPECIFICATIONS AC CharacteristicsÐ80C186EC25 (Continued) Symbol Parameter TCHIS TEST, NMI, INT4:0, BCLK1:0, T1:0IN, READY, CTS1:0 ,1 0 n s 1 , 9 P2.6, P2.7 TCHIH TEST, NMI, INT4:0, BCLK1:0, T1:0IN, READY, CTS1:0 3n s 1 , 9 TCLIS AD15:0 (AD7:0), READY 10 ns 1, 10 TCLIH READY, AD15:0 (AD7:0) 3 ns 1, 10 TCLIS HOLD, PEREQ, ERROR 10 ns 1, 9 TCLIH HOLD, PEREQ, ERROR 3n s 1 , 9 NOTES: 1. See AC Timing Waveforms , for waveforms and definition. 2. Measure at V IH for high time, V IL for low time. 3. Only required to guarantee I CC. Maximum limits are bounded by T C,T CH and T CL. 4. Specified for a 50 pF load, see Figure 13 for capacitive derating information. 5. Specified for a 50 pF load, see Figure 14 for rise and fall times outside 50 pF. 6. See Figure 14 for rise and fall times. 7. T CHOV1 applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release. 8. T CHOV2 applies to RD and WR only after a HOLD release. 9. Setup and Hold are required to guarantee recognition. 10. Setup and Hold are required for proper operation.
80C186EC/188EC, 80L186EC/188EC AC SPECIFICATIONS AC CharacteristicsÐ80C186EC-20/80C186EC-13 Symbol Parameter Min Max Min Max Unit Notes INPUT CLOCK 20 MHz 13 MHz TF CLKIN Frequency 0 40 0 26 MHz 1 TC CLKIN Period 25 % 38.5 % ns 1 TCH CLKIN High Time 10 % 12 % ns 1, 2 TCL CLKIN Low Time 10 % 12 % ns 1, 2 TCR CLKIN Rise Time 1 10 1 10 ns 1, 3 TCF CLKIN Fall Time 1 10 1 10 ns 1, 3 OUTPUT CLOCK TCD CLKIN to CLKOUT Delay 0 17 0 23 ns 1, 4 T CLKOUT Period 2 * TC 2 * TC ns 1 TPH CLKOUT High Time (T/2) b 5 (T/2) a 5 (T/2) b 5 (T/2) a 5n s 1 TPL CLKOUT Low Time (T/2) b 5 (T/2) a 5 (T/2) b 5 (T/2) a 5n s 1 TPR CLKOUT Rise Time 1616 n s 1 , 5 TPF CLKOUT Fall Time 1616 n s 1 , 5 OUTPUT DELAYS TCHOV1 ALE, S2:0 , DEN , DT/R , 3 2 0 3 2 5 n s 1 ,4 ,6 ,7 BHE (RFSH), LOCK , A19:16 TCHOV2 GCS7:0, LCS , UCS , 3 2 3 3 3 0 n s 1 ,4 ,6 ,8 RD,W R , NCS , WDTOUT TCLOV1 BHE (RFSH), DEN , LOCK , RESOUT, 3 20 3 25 ns 1, 4, 6 HLDA, T0OUT, T1OUT TCLOV2 RD,W R , GSC7:0 , LCS , UCS , AD15:0 3 23 3 30 ns 1, 4, 6 (AD7:0, A15:8), NCS , INTA , S2:0 , A19:16 TCHOF RD,W R , BHE (RFSH), DT/R , LOCK , 02 503 0 n s 1 S2:0, A19:16 TCLOF DEN, AD15:0 (AD7:0, A15:8) 0 25 0 30 ns 1 INPUT REQUIREMENTS TCHIS TEST, NMI, T1IN, T0IN, READY, 10 10 ns 1, 9 CTS1:0, BCLK1:0, P3.4, P3.5 TCHIH TEST, NMI, T1IN, T0IN, READY, 3 3 ns 1, 9 CTS1:0, BCLK1:0, P3.4, P3.5 TCLIS AD15:0 (AD7:0), READY 10 10 ns 1, 10 TCLIH AD15:0 (AD7:0), READY 3 3 ns 1, 10 TCLIS HOLD, RESIN , PEREQ, ERROR , DRQ3:0 10 10 ns 1, 9 TCLIH HOLD, RESIN , REREQ, ERROR , DRQ3:0 3 3 ns 1, 9 NOTES: 1. See AC Timing Waveforms , for waveforms and definition. 2. Measure at V IH for high time, V IL for low time. 3. Only required to guarantee I CC. Maximum limits are bounded by T C,T CH and T CL. 4. Specified for a 50 pF load, see Figure 14 for capacitive derating information. 5. Specified for a 50 pF load, see Figure 15 for rise and fall times outside 50 pF. 6. See Figure 15 for rise and fall times. 7. T CHOV1 applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release. 8. T CHOV2 applies to RD and WR only after a HOLD release. 9. Setup and Hold are required to guarantee recognition. 10. Setup and Hold are required for proper operation.
80C186EC/188EC, 80L186EC/188EC AC CharacteristicsÐ80L186EC13 Symbol Parameter Min Max Unit Notes INPUT CLOCK 13 MHz TF CLKIN Frequency 0 26 MHz 1 TC CLKIN Period 38.5 % ns 1 TCH CLKIN High Time 15 % ns 1, 2 TCL CLKIN Low Time 15 % ns 1, 2 TCR CLKIN Rise Time 1 10 ns 1, 3 TCF CLKIN Fall Time 1 10 ns 1, 3 OUTPUT CLOCK TCD CLKIN to CLKOUT Delay 0 20 ns 1, 4 T CLKOUT Period 2 * TC ns 1 TPH CLKOUT High Time (T/2) b 5 (T/2) a 5n s 1 TPL CLKOUT Low Time (T/2) b 5 (T/2) a 5n s 1 TPR CLKOUT Rise Time 1 10 ns 1, 5 TPF CLKOUT Fall Time 1 10 ns 1, 5 OUTPUT DELAYS TCHOV1 S2:0, DT/R , BHE , LOCK 3 2 8 n s 1 ,4 ,6 ,7 TCHOV2 LCS, UCS , DEN , A19:16, RD ,W R , NCS , 3 32 ns 1, 4, 6, 8 WDTOUT, ALE TCHOV3 GCS7:0 3 3 4 n s 1 ,4 ,6 TCLOV1 LOCK, RESOUT, HLDA, T0OUT, T1OUT 3 28 ns 1, 4, 6 TCLOV2 RD,W R , AD15:0 (AD7:0, A15:8), BHE 3 3 2 n s 1 ,4 ,6 (RFSH), NCS , INTA , DEN TCLOV3 GSC7:0, LCS , UCS 3 3 4 n s 1 ,4 ,6 TCLOV4 S2:0, A19:16 3 37 ns 1, 4, 6 TCHOF RD,W R , BHE (RFSH), DT/R , LOCK , 0 30 ns 1 S2:0, A19:16 TCLOF DEN, AD15:0 (AD7:0, A15:8) 0 35 ns 1 INPUT REQUIREMENTS TCHIS TEST, NMI, T1IN, T0IN, READY, 20 ns 1, 9 CTS1:0, BCLK1:0, P3.4, P3.5 TCHIH TEST, NMI, T1IN, T0IN, READY, 3 ns 1, 9 CTS1:0, BCLK1:0, P3.4, P3.5 TCLIS AD15:0 (AD7:0), READY 20 ns 1, 10 TCLIH AD15:0 (AD7:0), READY 3 ns 1, 10 TCLIS HOLD, RESIN , PEREQ, ERROR , DRQ3:0 20 ns 1, 9 TCLIH HOLD, RESIN , REREQ, ERROR , DRQ3:0 3 ns 1, 9 NOTES: 1. See AC Timing Waveforms , for waveforms and definition. 2. Measure at V IH for high time, V IL for low time. 3. Only required to guarantee I CC. Maximum limits are bounded by T C,T CH and T CL. 4. Specified for a 50 pF load, see Figure 14 for capacitive derating information. 5. Specified for a 50 pF load, see Figure 15 for rise and fall times outside 50 pF.
80C186EC/188EC, 80L186EC/188EC AC CharacteristicsÐ80L186EC13 (Continued) NOTES: 6. See Figure 15 for rise and fall times. 7. T CHOV1 applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release. 8. T CHOV2 applies to RD and WR only after a HOLD release. 9. Setup and Hold are required to guarantee recognition. 10. Setup and Hold are required for proper operation. AC CharacteristicsÐ80L186EC16 (Operating Temperature 0 §Ct o7 0 §C) Symbol Parameter Min Max Unit Notes INPUT CLOCK 16 MHz TF CLKIN Frequency 0 32 MHz 1 TC CLKIN Period 31.25 % ns 1 TCH CLKIN High Time 13 % ns 1, 2 TCL CLKIN Low Time 13 % ns 1, 2 TCR CLKIN Rise Time 1 10 ns 1, 3 TCF CLKIN Fall Time 1 10 ns 1, 3 OUTPUT CLOCK TCD CLKIN to CLKOUT Delay 0 20 ns 1, 4 T CLKOUT Period 2 * TC ns 1 TPH CLKOUT High Time (T/2) b 5 (T/2) a 5n s 1 TPL CLKOUT Low Time (T/2) b 5 (T/2) a 5n s 1 TPR CLKOUT Rise Time 1 9 ns 1, 5 TPF CLKOUT Fall Time 1 9 ns 1, 5 OUTPUT DELAYS TCHOV1 S2:0, DT/R , BHE , LOCK 3 2 5 n s 1 ,4 ,6 ,7 TCHOV2 LCS, UCS , DEN , A19:16, RD ,W R , NCS , 3 30 ns 1, 4, 6, 8 WDTOUT, ALE TCHOV3 GCS7:0 3 3 2 n s 1 ,4 ,6 TCLOV1 LOCK, RESOUT, HLDA, T0OUT, T1OUT 3 25 ns 1, 4, 6 TCLOV2 RD,W R , AD15:0 (AD7:0, A15:8), BHE 3 3 0 n s 1 ,4 ,6 (RFSH), NCS , INTA , DEN TCLOV3 GSC7:0, LCS , UCS 3 3 2 n s 1 ,4 ,6 TCLOV4 S2:0, A19:16 3 34 ns 1, 4, 6 TCHOF RD,W R , BHE (RFSH), DT/R , LOCK , 0 28 ns 1 S2:0, A19:16 TCLOF DEN, AD15:0 (AD7:0, A15:8) 0 32 ns 1 INPUT REQUIREMENTS TCHIS TEST, NMI, T1IN, T0IN, READY, 15 ns 1, 9 CTS1:0, BCLK1:0, P3.4, P3.5 TCHIH TEST, NMI, T1IN, T0IN, READY, 3 ns 1, 9 CTS1:0, BCLK1:0, P3.4, P3.5 TCLIS AD15:0 (AD7:0), READY 15 ns 1, 10 TCLIH AD15:0 (AD7:0), READY 3 ns 1, 10 TCLIS HOLD, RESIN , PEREQ, ERROR , DRQ3:0 15 ns 1, 9 TCLIH HOLD, RESIN , PEREQ, ERROR , DRQ3:0 3 ns 1, 9
80C186EC/188EC, 80L186EC/188EC AC CharacteristicsÐ80L186EC16 (Continued) NOTES: 1. See AC Timing Waveforms , for waveforms and definition. 2. Measure at V IH for high time, V IL for low time. 3. Only required to guarantee I CC. Maximum limits are bounded by T C,T CH and T CL. 4. Specified for a 50 pF load, see Figure 14 for capacitive derating information. 5. Specified for a 50 pF load, see Figure 15 for rise and fall times outside 50 pF. 6. See Figure 15 for rise and fall times. 7. T CHOV1 applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release. 8. T CHOV2 applies to RD and WR only after a HOLD release. 9. Setup and Hold are required to guarantee recognition. 10. Setup and Hold are required for proper operation. Relative Timings (80C186EC-25/20/13, 80L186EC-16/13) Symbol Parameter Min Max Unit Notes RELATIVE TIMINGS TLHLL ALE Active Pulse Width T b 15 ns TAVLL AD Valid Setup before ALE Falls (/2T b 10 ns TPLLL Chip Select Valid before ALE Falls (/2T b 10 ns 1 TLLAX AD Hold after ALE Falls (/2T b 10 ns TLLWL ALE Falling to WR Falling (/2T b 15 ns 1 TLLRL ALE Falling to RD Falling (/2T b 15 ns 1 TWHLH WR Rising to Next ALE Rising (/2T b 10 ns 1 TAFRL AD Float to RD Falling 0 ns TRLRH RD Active Pulse Width 2T b 5n s 2 TWLWH WR Active Pulse Width 2T b 5n s 2 TRHAX RD Rising to Next Address Active T b 15 ns TWHDX Output Data Hold after WR Rising T b 15 ns TWHPH WR Rise to Chip Select Rise (/2T b 10 ns 1 TRHPH RD Rise to Chip Select Rise (/2T b 10 ns 1 TPHPL Chip Select Inactive to Next Chip (/2T b 10 ns 1 Select Active TOVRH ONCE Active Setup to RESIN Rising T ns TRHOX ONCE Hold after RESIN Rise T ns TIHIL INTA High to Next INTA Low 4T b 5n s 4 during INTA Cycle TILIH INTA Active Pulse Width 2T b 5n s 2 , 4 TCVIL CAS2:0 Setup before 2nd INTA 8T ns 2, 4 Pulse Low TILCX CAS2:0 Hold after 2nd INTA Pulse Low 4T ns 2, 4 TIRES Interrupt Resolution Time 150 ns 3 TIRLH IR Low Time to Reset Edge Detector 50 ns TIRHIF IR Hold Time after 1st INTA Falling 25 ns 4, 5
80C186EC/188EC, 80L186EC/188EC Relative Timings (80C186EC-25/20/13, 80L186EC-16/13) NOTES: 1. Assumes equal loading on both pins. 2. Can be extended using wait states. 3. Interrupt resolution time is the delay between an unmasked interrupt request going active and the interrupt output of the 8259A module going active. This is not directly measureable by the user. For interrupt pin INT7 the delay from an active signal to an active input to the CPU would actually be twice the T IRES value since the signal must pass through two 8259A modules. 4. See INTA Cycle Waveforms for definition. 5. To guarantee interrupt is not spurious. Serial Port Mode 0 Timings (80C186EC-25/20/13, 80L186EC-16/13) Symbol Parameter Min Max Unit Notes RELATIVE TIMINGS TXLXL TXD Clock Period T (n a 1) ns 1, 2 TXLXH TXD Clock Low to Clock High (N l 1) 2T b 35 2T a 35 ns 1 TXLXH TXD Clock Low to Clock High (N e 1) T b 35 T a 35 ns 1 TXHXL TXD Clock High to Clock Low (N l 1) (n b 1) T b 35 (n b 1) T a 35 ns 1, 2 TXHXL TXD Clock High to Clock Low (N e 1) T b 35 T a 35 ns 1 TQVXH RXD Output Data Setup to TXD (n b 1)T b 35 ns 1, 2 Clock High (N l 1) TQVXH RXD Output Data Setup to TXD T b 35 ns 1 Clock High (N e 1) TXHQX RXD Output Data Hold after TXD 2T b 35 ns 1 Clock High (N l 1) TXHQX RXD Output Data Hold after TXD T b 35 ns 1 Clock High (N e 1) TXHQZ RXD Output Data Float after Last T a 20 ns 1 TXD Clock High TDVXH RXD Input Data Setup to TXD T a 20 ns 1 Clock High TXHDX RXD Input Data Setup after TXD 0 ns 1 Clock High NOTES: 1. See Figure 13 for Waveforms. 2. n is the value in the BxCMP register ignoring the ICLK bit.
Figure 16. Cold RESET Waveforms periods. If RESIN is sampled high while CLKOUT is low (dashed line), then CLKOUT will not be affected. Pin names in parentheses apply to 80C188EC/80L188EC.
Figure 17. Warm RESET Waveforms periods. If RESIN is sampled high while CLKOUT is low (dashed line), then CLKOUT will not be affected. Pin names in parentheses apply to 80C188EC/80L188EC.
needed for a given application. Pin names in parentheses apply to 80C188EC/80L188EC. Figure 18. Memory Read, I/O Read, Instruction Fetch and Refresh Waveforms
Pin names in parentheses apply to 80C188EC/80L188EC. Figure 19. Memory Write and I/O Write Cycle Waveforms
- Address information is invalid. If previous bus cycle was a read, then the AD15:0 (AD7:0) lines will float during T1.
- All address lines drive zeros while in Powerdown or Idle Mode.
Pin names in parentheses apply to 80C188EC/80L188EC. Figure 20. Halt Cycle Waveforms
Pin names in parentheses apply to 80C188EC/80L188EC. Figure 21. Interrupt Acknowledge Cycle Waveforms
Pin names in parentheses apply to 80C188EC/80L188EC. Figure 22. HOLD/HLDA Cycle Waveforms
Pin names in parentheses apply to 80C188EC/80L188EC. Figure 23. Refresh during HLDA Waveforms
- READY must be low by either edge to cause a wait state.
- Lighter lines indicate READ cycles, darker lines indicate WRITE cycles.
Pin names in parentheses apply to 80C188EC/80L188EC. Figure 24. READY Cycle Waveforms
80C186EC/188EC, 80L186EC/188EC 80C186EC/80C188EC EXECUTION TIMINGS A determination of program execution timing must consider the bus cycles necessary to prefetch in- structions as well as the number of execution unit cycles necessary to execute instructions. The fol- lowing instruction timings represent the minimum execution time in clock cycles for each instruction. The timings given are based on the following as- sumptions: # The opcode, along with any data or displacement required for execution of a particular instruction, has been prefetched and resides in the queue at the time it is needed. # No wait states or bus HOLDs occur. # All word-data is located on even-address bound- aries (80C186EC only). All jumps and calls include the time required to fetch the opcode of the next instruction at the destination address. All instructions which involve memory accesses can require one or two additional clocks above the mini- mum timings shown due to the asynchronous hand- shake between the bus interface unit (BIU) and exe- cution unit. With a 16-bit BIU, the 80C186EC has sufficient bus performance to ensure that an adequate number of prefetched bytes will reside in the queue (6 bytes) most of the time. Therefore, actual program execu- tion time will not be substantially greater than that derived from adding the instruction timings shown. The 80C188EC 8-bit BIU is limited in its performance relative to the execution unit. A sufficient number of prefetched bytes may not reside in the prefetch queue (4 bytes) much of the time. Therefore, actual program execution time will be substantially greater than that derived from adding the instruction timings shown.
80C186EC/188EC, 80L186EC/188EC INSTRUCTION SET SUMMARY Function Format 80C186EC 80C188EC CommentsClock Clock Cycles Cycles DATA TRANSFER MOV e Move: Register to Register/Memory 1000100w m o dr e g r / m 2/12 2/12 * Register/memory to register 1000101w m o dr e g r / m 2 / 9 2 / 9 * Immediate to register/memory 1100011w m o d0 0 0 r / m data data if w e1 12/13 12/13 8/16-bit Immediate to register 1011w r e g data data if w e1 3/4 3/4 8/16-bit Memory to accumulator 1010000w addr-low addr-high 8 8 * Accumulator to memory 1010001w addr-low addr-high 9 9 * Register/memory to segment register 10001110 m o d0r e g r / m 2 / 9 2/13 Segment register to register/memory 10001100 m o d0r e g r / m 2/11 2/15 PUSH e Push: Memory 11111111 m o d110 r / m 1 6 2 0 Register 01010 r e g 1 0 1 4 Segment register 000r e g110 9 1 3 Immediate 011010s0 data data if s e01 0 1 4 PUSHA e Push All 01100000 3 6 6 8 POP e Pop: Memory 10001111 m o d000 r / m 2 0 2 4 Register 01011 r e g 1 0 1 4 Segment register 000r e g111 (regi01) 8 12 POPA e P o pA l l 01100001 5 1 8 3 XCHG e Exchange: Register/memory with register 1000011w m o dr e g r / m 4/17 4/17 * Register with accumulator 10010 r e g 3 3 IN e Input from: Fixed port 1110010w port 10 10 * Variable port 1110110w 8 8 * OUT e Output to: Fixed port 1110011w port 9 9 * Variable port 1110111w 7 7 * XLAT e Translate byte to AL 11010111 1 1 1 5 LEA e Load EA to register 10001101 m o dr e g r / m 6 6 LDS e Load pointer to DS 11000101 m o dr e g r / m (modi11) 18 26 LES e Load pointer to ES 11000100 m o dr e g r / m (modi11) 18 26 LAHF e Load AH with flags 10011111 2 2 SAHF e Store AH into flags 10011110 3 3 PUSHF e Push flags 10011100 9 1 3 POPF e Pop flags 10011101 8 1 2 Shaded areas indicate instructions not available in 8086/8088 microsystems. NOTE: *Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for all memory transfers.
80C186EC/188EC, 80L186EC/188EC INSTRUCTION SET SUMMARY (Continued) Function Format 80C186EC 80C188EC CommentsClock Clock Cycles Cycles DATA TRANSFER (Continued) SEGMENT e Segment Override: CS 00101110 2 2 SS 00110110 2 2 DS 00111110 2 2 ES 00100110 2 2 ARITHMETIC ADD e Add: Reg/memory with register to either 000000dw m o dr e g r / m 3/10 3/10 * Immediate to register/memory 100000sw m o d000 r / m data data if s w e01 4/16 4/16 * Immediate to accumulator 0000010w data data if w e1 3/4 3/4 8/16-bit ADC e Add with carry: Reg/memory with register to either 000100dw m o dr e g r / m 3/10 3/10 * Immediate to register/memory 100000sw m o d010 r / m data data if s w e01 4/16 4/16 * Immediate to accumulator 0001010w data data if w e1 3/4 3/4 8/16-bit INC e Increment: Register/memory 1111111w m o d000 r / m 3/15 3/15 * Register 01000 r e g 3 3 SUB e Subtract: Reg/memory and register to either 001010dw m o dr e g r / m 3/10 3/10 * Immediate from register/memory 100000sw m o d101 r / m data data if s w e01 4/16 4/16 * Immediate from accumulator 0010110w data data if w e1 3/4 3/4 * 8/16-bit SBB e Subtract with borrow: Reg/memory and register to either 000110dw m o dr e g r / m 3/10 3/10 * Immediate from register/memory 100000sw m o d011 r / m data data if s w e01 4/16 4/16 * Immediate from accumulator 0001110w data data if w e1 3/4 3/4 * 8/16-bit DEC e Decrement Register/memory 1111111w m o d001 r / m 3/15 3/15 * Register 01001 r e g 3 3 CMP e Compare: Register/memory with register 0011101w m o dr e g r / m 3/10 3/10 * Register with register/memory 0011100w m o dr e g r / m 3/10 3/10 * Immediate with register/memory 100000sw m o d111 r / m data data if s w e01 3/10 3/10 * Immediate with accumulator 0011110w data data if w e1 3/4 3/4 8/16-bit NEG e Change sign register/memory 1111011w m o d011 r / m 3/10 3/10 * AAA e ASCII adjust for add 00110111 8 8 DAA e Decimal adjust for add 00100111 4 4 AAS e ASCII adjust for subtract 00111111 7 7 DAS e Decimal adjust for subtract 00101111 4 4 MUL e Multiply (unsigned): 1111011w m o d1 0 0 r / m Register-Byte 26–28 26–28 Register-Word 35–37 35–37 Memory-Byte 32–34 32–34 Memory-Word 41–43 41–43 * Shaded areas indicate instructions not available in 8086/8088 microsystems. NOTE: *Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for all memory transfers.
80C186EC/188EC, 80L186EC/188EC INSTRUCTION SET SUMMARY (Continued) Function Format 80C186EC 80C188EC CommentsClock Clock Cycles Cycles ARITHMETIC (Continued) IMUL e Integer multiply (signed): 1111011w m o d101 r / m Register-Byte 25–28 25–28 Register-Word 34–37 34–37 Memory-Byte 31–34 32–34 Memory-Word 40–43 40–43 * IMUL e Integer Immediate multiply 011010s1 m o dr e g r / m data data if s e0 22–25/ 22–25/ (signed) 29–32 29–32 DIV e Divide (unsigned): 1111011w m o d110 r / m Register-Byte 29 29 Register-Word 38 38 Memory-Byte 35 35 Memory-Word 44 44 * IDIV e Integer divide (signed): 1111011w m o d111 r / m Register-Byte 44–52 44–52 Register-Word 53–61 53–61 Memory-Byte 50–58 50–58 Memory-Word 59–67 59–67 * AAM e ASCII adjust for multiply 11010100 00001010 1 9 1 9 AAD e ASCII adjust for divide 11010101 00001010 1 5 1 5 CBW e Convert byte to word 10011000 2 2 CWD e Convert word to double word 10011001 4 4 LOGIC Shift/Rotate Instructions: Register/Memory by 1 1101000w m o dT T Tr / m 2/15 2/15 Register/Memory by CL 1101001w m o dT T Tr / m 5 an/17an5 an/17an Register/Memory by Count 1100000w m o dT T Tr / m count 5an/17an5 an/17an TTT Instruction
000 R O L
001 R O R
010 R C L
011 R C R
101 S H R
111 S A R
AND e And: Reg/memory and register to either 001000dw m o dr e g r / m 3/10 3/10 * Immediate to register/memory 1000000w m o d100 r / m data data if w e1 4/16 4/16 * Immediate to accumulator 0010010w data data if w e1 3/4 3/4 * 8/16-bit TESTeAnd function to flags, no result: Register/memory and register 1000010w m o dr e g r / m 3/10 3/10 Immediate data and register/memory 1111011w m o d000 r / m data data if w e1 4/10 4/10 * Immediate data and accumulator 1010100w data data if w e1 3/4 3/4 8/16-bit OReOr: Reg/memory and register to either 000010dw m o dr e g r / m 3/10 3/10 * Immediate to register/memory 1000000w m o d001 r / m data data if w e1 4/16 4/16 * Immediate to accumulator 0000110w data data if w e1 3/4 3/4 * 8/16-bit Shaded areas indicate instructions not available in 8086/8088 microsystems. NOTE: *Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for all memory transfers.
80C186EC/188EC, 80L186EC/188EC INSTRUCTION SET SUMMARY (Continued) Function Format 80C186EC 80C188EC CommentsClock Clock Cycles Cycles LOGIC (Continued) XOR e Exclusive or: Reg/memory and register to either 001100dw m o dr e g r / m 3/10 3/10 * Immediate to register/memory 1000000w m o d110 r / m data data if w e1 4/16 4/16 * Immediate to accumulator 0011010w data data if w e1 3/4 3/4 8/16-bit NOT e Invert register/memory 1111011w m o d010 r / m 3/10 3/10 * STRING MANIPULATION MOVS e Move byte/word 1010010w 1 4 1 4 * CMPS e Compare byte/word 1010011w 2 2 2 2 * SCAS e Scan byte/word 1010111w 1 5 1 5 * LODS e Load byte/wd to AL/AX 1010110w 1 2 1 2 * STOS e Store byte/wd from AL/AX 1010101w 1 0 1 0 * INS e Input byte/wd from DX port 0110110w 1 4 1 4 OUTS e Output byte/wd to DX port 0110111w 1 4 1 4 Repeated by count in CX (REP/REPE/REPZ/REPNE/REPNZ) MOVS e Move string 11110010 1010010w 8 a8n 8 a8n* CMPS e Compare string 1111001z 1010011w 5 a22n 5 a22n* SCAS e Scan string 1111001z 1010111w 5 a15n 5 a15n* LODS e Load string 11110010 1010110w 6 a11n 6 a11n* STOS e Store string 11110010 1010101w 6 a9n 6 a9n* INS e Input string 11110010 0110110w 8 a8n 8 a8n* OUTS e Output string 11110010 0110111w 8 a8n 8 a8n* CONTROL TRANSFER CALL e Call: Direct within segment 11101000 disp-low disp-high 15 19 Register/memory 11111111 m o d010 r / m 13/19 17/27 indirect within segment Direct intersegment 10011010 segment offset 23 31 segment selector Indirect intersegment 11111111 m o d011 r / m (mod i 11) 38 54 JMP e Unconditional jump: Short/long 11101011 disp-low 14 14 Direct within segment 11101001 disp-low disp-high 14 14 Register/memory 11111111 m o d100 r / m 11/17 11/21 indirect within segment Direct intersegment 11101010 segment offset 14 14 segment selector Indirect intersegment 11111111 m o d101 r / m (mod i 11) 26 34 Shaded areas indicate instructions not available in 8086/8088 microsystems. NOTE: *Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for all memory transfers.
80C186EC/188EC, 80L186EC/188EC INSTRUCTION SET SUMMARY (Continued) Function Format 80C186EC 80C188EC CommentsClock Clock Cycles Cycles CONTROL TRANSFER (Continued) RET e Return from CALL: Within segment 11000011 1 6 2 0 Within seg adding immed to SP 11000010 data-low data-high 18 22 Intersegment 11001011 2 2 3 0 Intersegment adding immediate to SP 11001010 data-low data-high 25 33 JE/JZ e Jump on equal/zero 01110100 disp 4/13 4/13 JMP not JL/JNGE e Jump on less/not greater or equal 01111100 disp 4/13 4/13 taken/JMP JLE/JNG e Jump on less or equal/not greater 01111110 disp 4/13 4/13 taken JB/JNAE e Jump on below/not above or equal 01110010 disp 4/13 4/13 JBE/JNA e Jump on below or equal/not above 01110110 disp 4/13 4/13 JP/JPE e Jump on parity/parity even 01111010 disp 4/13 4/13 JO e Jump on overflow 01110 000 disp 4/13 4/13 JS e Jump on sign 01111000 disp 4/13 4/13 JNE/JNZ e Jump on not equal/not zero 01110101 disp 4/13 4/13 JNL/JGE e Jump on not less/greater or equal 01111101 disp 4/13 4/13 JNLE/JG e Jump on not less or equal/greater 01111111 disp 4/13 4/13 JNB/JAE e Jump on not below/above or equal 01110011 disp 4/13 4/13 JNBE/JA e Jump on not below or equal/above 01110111 disp 4/13 4/13 JNP/JPO e Jump on not par/par odd 01111011 disp 4/13 4/13 JNO e Jump on not overflow 01110001 disp 4/13 4/13 JNS e Jump on not sign 01111001 disp 4/13 4/13 JCXZ e Jump on CX zero 11100011 disp 5/15 5/15 LOOP e Loop CX times 11100010 disp 6/16 6/16 LOOP not LOOPZ/LOOPE e Loop while zero/equal 11100001 disp 6/16 6/16 taken/LOOP LOOPNZ/LOOPNE e Loop while not zero/equal 11100000 disp 6/16 6/16 taken ENTER e Enter Procedure 11001000 data-low data-high L L e 0 15 19 L e 1 25 29 L l 1 22a16(nb1) 26 a20(nb1) LEAVE e Leave Procedure 11001001 8 8 INT e Interrupt: Type specified 11001101 type 47 47 Type 3 11001100 4 5 4 5 if INT. taken/ INTO e Interrupt on overflow 11001110 48/4 48/4 if INT. not taken IRET e Interrupt return 11001111 2 8 2 8 BOUND e Detect value out of range 01100010 m o dr e g r / m 3 3 – 3 5 3 3 – 3 5 Shaded areas indicate instructions not available in 8086/8088 microsystems. NOTE: *Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for all memory transfers.
80C186EC/188EC, 80L186EC/188EC INSTRUCTION SET SUMMARY (Continued) 80C186EC 80C188EC Function Format Clock Clock Comments Cycles Cycles PROCESSOR CONTROL CLC e Clear carry 11111000 2 2 CMC e Complement carry 11110101 2 2 STC e Set carry 11111001 2 2 CLD e Clear direction 11111100 2 2 STD e Set direction 11111101 2 2 CLI e Clear interrupt 11111010 2 2 STI e Set interrupt 11111011 2 2 HLT e Halt 11110100 2 2 WAIT e Wait 10011011 6 6 i f TEST e 0 LOCK e Bus lock prefix 11110000 2 2 NOP e No Operation 10010000 3 3 (TTT LLL are opcode to processor extension) Shaded areas indicate instructions not available in 8086/8088 microsystems. NOTE: *Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for all memory transfers. The Effective Address (EA) of the memory operand is computed according to the mod and r/m fields: if mod e 11 then r/m is treated as a REG field if mod e 00 then DISP e 0*, disp-low and disp- high are absent if mod e 01 then DISP e disp-low sign-extended to 16-bits, disp-high is absent if mod e 10 then DISP e disp-high: disp-low if r/m e 000 then EA e (BX) a (SI) a DISP if r/m e 001 then EA e (BX) a (DI) a DISP if r/m e 010 then EA e (BP) a (SI) a DISP if r/m e 011 then EA e (BP) a (DI) a DISP if r/m e 100 then EA e (SI) a DISP if r/m e 101 then EA e (DI) a DISP if r/m e 110 then EA e (BP) a DISP* if r/m e 111 then EA e (BX) a DISP DISP follows 2nd byte of instruction (before data if required) *except if mod e 00 and r/m e 110 then EA e disp-high: disp-low. EA calculation time is 4 clock cycles for all modes, and is included in the execution times given whenev- er appropriate. Segment Override Prefix 0 0 1 reg 1 1 0 reg is assigned according to the following: Segment reg Register 00 ES 01 CS 10 SS 11 DS REG is assigned according to the following table: 16-Bit (w e 1) 8-Bit (w e 0)
000 AX 000 AL
001 CX 001 CL
010 DX 010 DL
011 BX 011 BL
100 SP 100 AH
101 BP 101 CH
110 SI 110 DH
111 DI 111 BH
The physical addresses of all operands addressed by the BP register are computed using the SS seg- ment register. The physical addresses of the desti- nation operands of the string primitive operations (those addressed by the DI register) are computed using the ES segment, which may not be overridden.
80C186EC/188EC, 80L186EC/188EC ERRATA An 80C186EC/80L186EC with a STEPID value of 0002H has no known errata. A device with a STEPID of 0002H can be visually identified by noting the presence of an ‘‘A’’ or ‘‘B’’ alpha character next to the FPO number or the absence of any alpha char- acter. The FPO number location is shown in Figures 4, 5 and 6.
REVISION HISTORY
This data sheet replaces the following data sheets: 272072-003 80C186EC 272076-003 80C188EC 272332-001 80L186EC 272333-001 80L188EC 272373-001 SB80C188EC/SB80L188EC 272372-001 SB80C186EC/SB80L186EC