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Intel® Server Board S5500WB Technical Product Specification Intel order number E53971-008 Revision 1.9 February, 2012 Enterprise Platforms and Services Division

Revision History Intel® Server Board S5500WB TPS Revision 1.9 Intel order number E53971 -008 ii

Revision History

03/30/2009 1.0 Initial Release. 04/29/2009 1.1 Formatting corrections. 05/20/2009 1.2 Updated heatsink installation steps. Corrected processor fault table. Added jumper location figure. 08/03/2009 1.3 Updated memory support. Corrected PCIe slot speed. Removed S4 support. 01/12/2010 1.4 Corrected USB header pin-out. 03/09/2010 1.5 Updated Power Supply communication bus requirements . Increased maximum supported memory to 128GB. Added support for 5600 series processors . 04/21/2010 1.6 Updated12V SKU board picture (Figure 1). 07/18/2010 1.7 Removed Rapid Boot Toolkit section. Updated NIC LEDs. Updated video resolution. 03/21/2010 1.8 Updated typo in board feature set. 02/16/2012 1.9 Updated typo in board feature set.

Intel® Server Board S5500WB TPS Disclaimers Revision 1.9 Intel order number E53971-008 iii Disclaimers Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. This document contains information on products in the design phase of development. Do not finalize a design with this information. Revised information will be published when the product is available. Verify with your local sales office that you have the latest datasheet before finalizing a design. This document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. This document and the software described in it are furnished under license and may only be used or copied in accordance with the terms of the license. The information in this manual is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by Intel Corporation. Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this document or any software that may be provided in association with this document. Except as permitted by such license, no part of this document may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation. Intel and Xeon are trademarks or registered trademarks of Intel Corporation. *Other brands and names may be claimed as the property of others. Copyright © Intel Corporation 2011

Table of Contents Intel® Server Board S5500WB TPS Revision 1.9 Intel order number E53971 -008 iv Table of Contents

Intel® Server Board S5500WB TPS Table of Contents Revision 1.9 Intel order number E53971 -008 v

Table of Contents Intel® Server Board S5500WB TPS Revision 1.9 Intel order number E53971 -008 vi

Intel® Serve r Board S5500WB TPS Table of Contents Revision 1.9 Intel order number E53971 -008 vii

Table of Contents Intel® Server Board S5500WB TPS Revision 1.9 Intel order number E53971 -008 viii

Table 27. 12-V Only Power Control (replaces the 1x5 power control) (J9D1) (FOXCONN Table 28. Peripheral Power (Only for 12-V only SKU) (J8K2) (iPN: C22293-003 MOLEX

Table 50. 8-pin Fan Connector (J2K1 & J8K3) (MOLEX CONNECTOR CORPORATION 53398-

Intel® Server Board S5500WB TPS List of Tables Revision 1.9 Intel order number E53971 -008 xiii <This page is intentionally left blank.>

Intel® Server Board S5500WB TPS Introduction Revision 1.9 Intel order number E53971 -008 1. Introduction The Intel® Server Board S5500WB is a dual socket server using the Intel® Xeon® Processor 5500 series and 5600 series processors, in combination with the IOH and ICH10R to provide a balanced feature set between technology leadership and cost.

1.1 Section Outline

This document is divided into the following chapters:  Section 1 – Introduction  Section 2 – Server Board Overview  Section 3 – Functional Architecture  Section 4 – I/O Expansion Modules  Section 5 – Platform Management Features  Section 6 – Configuration Jumpers  Section 7 – Connector and Header Location and Pin-out  Section 8 – Intel® Light-Guided Diagnostics  Section 9 – Design and Environmental Specifications  Section 10 – Power Subsystem  Section 11 - Regulatory and Certification Information  Appendix A – POST Code LED Decoder  Appendix B – Video POST Code Errors  Glossary  Reference Documents

1.2 Server Board Use Disclaimer

Intel Corporation server boards contain a number of high-density VLSI and power delivery components that need adequate airflow to cool. Intel ensures through its own chassis development and testing that when Intel server building blocks are used together, the fully integrated system will meet the intended thermal requirements of these components. It is the responsibility of the system integrator who chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of air flow required for their specific application and environmental conditions. Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of their published operating or non-operating limits.

high-level product feature list. Table 1. Intel® Server Board S5500WB Feature Set

Intel® Server Board S5500WB TPS Server Board Overview Revision 1.9 Intel order number E53971 -008 Feature Descripti on System Fan Support Two 8-pin fan headers for double rotor memory fans and six 4 -pin fan headers supporting two processor zones and two memory zones in a redundant fashion Add-in Adapter Support One riser slot supporting both full-height and low-profile 1U and 2U MD2 PCI Express* x16 riser cards PCI gen2 Express* x8 w/ x16 connector. One riser slot supporting PCI Express* x8 riser cards PCI gen2 Express* x4 w/ x8 connector. Two Intel® I/O Expansion Module card connectors supporting double - and single- wide I/O modules. Video Onboard ServerEngines* LLC Pilot II Controller  Matrox* G200 2D Video Graphics controller  Uses 8 MB of the BMC 32 MB DDR2 Memory Hard Drive Support for six ICH10R SATA II ports Optional support for SW RAID 5 with activation key LAN Two 10/100/1000 ports provided by Intel® 82576 PHYs with Intel® I/O Acceleration Technology 2 support Server Management Onboard ServerEngines* LLC Pilot II Controller. Integrated Baseboard Management Controller (Integrated BMC), IPMI 2.0 compliant Basic  BMC Controller: ARM 926E-S microcontroller  Super IO: Serial Port logic, legacy interfaces, LPC interface, Port80  Hardware Monitoring: Fan speed control and voltage monitoring Advanced  Video and USB compression and redirection  NC-SI port, a high-speed sideband management interface  Integrated Super I/O on LPC interface

2.1 Intel® Server Board S5500WB Server Board

SKU. The board layouts of the SKUs are shown. Figure 1. Intel® Server Board S5500WB 12V

Figure 2. Intel Server Board S5500WB SSI

2.2 Server Board Connector and Component Layout

Figure 3. Intel® Server Board S5500WB Components (both SKUs are shown)

Table 2. Intel® Server Board S5500WB System Interconnects

2.2.1 Board Rear Connector Placement

Figure 4. Rear Panel Connector Placement:

2.2.2 Server Board Mechanical Drawings

The following figures are mechanical drawings for the Intel® Server Board S5500WB.

Figure 5. Baseboard and Mounting holes

Figure 6. Connector Locations

Figure 7. Primary Side Height Restrictions

Figure 8. Secondary Side Height Restrictions

3.1 High Level Product Features

Table 3. Intel® Server Board S5500WB Features

1 PCI Express* x4 w/ x8 connector

1 PCI Express* x8 w/ x16 connector

*Referenced Chassis: Chenbro RM13204 Chassis and Intel® Server System SR1690WB.

3.2 Functional Block Diagram

Figure 9. Intel® Server Board S5500WB Functional Block Diagram

Intel® Server Board S5500WB TPS Functional Architecture Revision 1.9 Intel order number E53971 -008

3.3 Processor Subsystem

The Intel® 5500 series and the next generation Intel® 5600 series processors support the following key technologies:  Intel® Integrated Memory Controller  Point-to-point link interface based on the Intel® QuickPath Interconnect (Intel® QPI), which was formerly known as the Common System Interface (CSI). The Intel® 5500 series processor is a multi-core processor based on the 45 nm process technology. Processor features vary by SKU and include up to two Intel® QPI point-to-point links capable of up to 6.4 GT/s, up to 8 MB of shared cache, and an integrated memory controller. The Intel® 5600 series processor is the next generation of multi-core processors based on the 32 nm process technology. Processor features vary by SKU and include up to 6 cores and up to 12 MB of shared cache.

3.3.1 Processor Support

The Intel® Server Board S5500WB supports the following processors:  One or two Intel® 5500 series or 5600 series processor(s) in FC-LGA 1366 socket B package with 4.8 GT/s, 5.86 GT/s, or 6.4 GT/s Intel® QPI.  Up to 95 W Thermal Design Power (TDP).  Supports Low Voltage (LV) processors.

3.3.2 Processor Population Rule s

For optimum performance, when two processors are installed, both must be the identical revision and have the same core voltage and Intel® QPI/core speed. When only one processor is installed, it must be in the socket labeled CPU1. The other socket must be empty. You must populate processors in sequential order. Therefore, you must populate processor socket 1 (CPU1) before processor socket 2 (CPU2). When a single processor is installed, no terminator is required in the second processor socket.

3.3.2.1 Mixed Processor Configurations

The following table describes mixed processor conditions and recommended actions for all Intel® server boards and systems that use the Intel® 5500 Chipset. The errors fall into one of the following two categories:  Fatal: If the system can boot, it goes directly to the error manager, regardless of whether the Post Error Pause setup option is enabled or disabled.  Major: If the Post Error Pause setup option is enabled, the system goes directly to the error manager. Otherwise, the system continues to boot and no prompt is given for the error. The error is logged to the error manager.

Table 4. Mixed Processor Configurations  Logs the error into the system event log (SEL).  Does not disable the processor. message in the error manager.  Logs the error into the SEL.  Does not disable the processor.  Continues to boot the system successfully.  Logs the error into the SEL.  Logs the error into the SEL.  Does not disable the processor. update‖ message in the error manager.  Logs the error into the SEL.  Alerts the Integrated BMC about the configuration error.  Does not disable the processor. mismatch‖ message in the Error Manager. system, but can continue to boot if operator directs.

3.3.3 Installing or Replacing t he Processor

3.3.3.1 Installing the Processor

1. Turn off all peripheral devices connected to the server.
2. Disconnect the AC power cord from the server.
3. Remove the server’s cover. See the document that came with your server chassis for

instructions on removing the server’s cover.

1. Locate the processor socket and raise the raise the load lever of the ILM cover

completely. (see letter ―A‖ in the figure below). Figure 10. Lifting the load lever of ILM cover

1. Open the load plate (see letter ―B‖ in Figure 10 and letter ―C‖ in Figure 11).

Figure 11. Removing the socket cover

1. Remove the protective socket cover. (See letter ―D‖ in Figure 11)
2. Align the pins of the processor with the socket and insert the processor into the

Figure 12. Installing processor

1. Lower the load plate and load lever of the ILM cover completely.

Note: Make sure the alignment triangle mark and the alignment triangle cutout align correctly. also provide an initial rough alignment of the package to the socket.

Figure 13. Package Installation/Remove Feature

3.3.3.2 Installing the Processor Heatsink(s)

1. Remove the protective film on the TIM if present.
2. Orient the heatsink over the processor as shown in Figure 14. The heatsink fins must

be positioned as shown to provide correct airflow through the system.

1. Set the heatsink over the processor, lining up the four captive screws with the four

posts surrounding the processor.

1. Loosely screw in the captive screws on the heatsink corners in a diagonal manner

screws are lightly tightened up to a maximum of 8 inch-lbs torque.

Figure 14. Installing/Removing Heatsink

3.3.3.3 Removing the Processor Heatsink

1. Loosen the four captive screws on the heatsink corners in a diagonal manner according
2. Lift the heatsink from the board.

3.3.4 Intel® QuickPath Interconnect (Intel® QPI)

(Accelerated Graphics Port), and so forth, through the appropriate bridges. going to the second processor and one going to the Intel® 5500 chipset IOH. Figure 15. Intel® QPI Link

Intel® Server Board S5500WB TPS Functional Architecture Revision 1.9 Intel order number E53971 -008 In the current implementation, Intel® QPI ports are capable of operating at transfer rates of up to 6.4 GT/s. Intel® QPI ports operate at multiple lane widths (full - 20 lanes, half - 10 lanes, and quarter - 5 lanes) independently in each direction between a pair of devices communicating via the Intel® QPI. The server boards support full-width communication only. For more information see the Intel® QPI Overview Rev 1.04 (Document#: 380531)

3.4 Intel® QuickPath Memory Controller

The Intel® 5500 series and 5600 series processors have an integrated memory controller on its package. Each processor produces up to three channels of DDR3 memory. The Intel® QPI Memory Controller supports DDR3 800, DDR3 1066, and DDR3 1333 memory technologies. The memory controller supports both Registered DIMMs (RDIMMs) and Unbuffered DIMMs (UDIMMs). Mixing of RDIMMs and UDIMMs is not supported.

3.4.1 Supported Memory

The Intel® Server Board S5500WB supports six DDR3 memory channels (three per processor socket) with two DIMMs on the first channel and one DIMM on the second and third channels of each processor. Therefore, the server board supports up to 8 DIMMs with dual-processor sockets with a maximum memory capacity of 128 GB. The server board supports DDR3 800, DDR3 1067, and DDR3 1333 memory technologies. Memory modules of mixed speed are supported by automatic selection of the highest common frequency of all memory modules. The following configurations are not supported, validated or recommended:  Mixing of RDIMMs and UDIMMs is not supported  Mixing of memory type, size, speed and/or rank has not been validated and is not supported  Mixing memory vendors has not been validated and is not recommended  Non-ECC memory has not been validated and is not supported in a server environment Note: Mixed memory is not tested or supported. Non-ECC memory is not tested and is not recommended for use in a server environment The Intel® Server Board S5500WB uses a 2:1:1 memory DIMM layout. A 2:1:1 layout was chosen for its lowest power for a particular bandwidth and because it allows the maximum possible bandwidth when a 1:1:1 memory population is used.

3.4.2 Memory Subsystem Nomenclature

DIMMs are organized into physical slots on DDR3 memory channels that belong to processor sockets.

channels from socket 2 are identified as Channels D, E, and F. Channel A on processor 1; DIMM_D1 is the first DIMM socket on Channel D on processor 2. Table 5. DIMM Nomenclature such as RAS, Error Management, and so forth, are applied commonly across sockets.

3.4.3 ECC Support

If at least one non-ECC DIMM is present in the system, the system reverts to non-ECC mode. validated and not recommended for server use.

3.4.4 Memory Reservation for Memory -mapped Functions

and a variably sized MMIO region for the PCI Express* functions. (PAE) is turned on in the operating system.

3.4.5 High-Memory Reclaim

memory that can be seen by the processor).

support this feature. For details, see the relevant operating system manuals.

3.4.6 Memory Population Rules

You should populate the memory slots of DDR3 channels furthest from the processor first. Therefore, if A1 is empty, you cannot populate/use A2. Figure 16. Memory Channel Population

3.4.7 Installing and Removing Memory

3.4.7.1 Installing DIMMs

1. Disconnect the AC power cord from the server.
2. Remove the server’s cover and locate the DIMM sockets (see ― Installing Memory‖).

Figure 17. Installing Memory

1. Make sure the clips at either end of the DIMM socket(s) are pushed outward to the open

position (see letter ―A‖ in the figure above).

1. Holding the DIMM by the edges, remove it from its anti-static package.
2. Position the DIMM above the socket. Align the two small notches in the bottom edge of

the DIMM with the keys in the socket (letter ―B‖ in Figure 16).

1. Insert the bottom edge of the DIMM into the socket (letter ―C‖ in Figure 16).
2. When the DIMM is inserted, push down on the top edge of the DIMM until the retaining
3. Replace the server’s cover and reconnect the AC power cord.

3.4.7.2 Removing DIMMs

1. Turn off all peripheral devices connected to the server.
2. Remove the AC power cord from the server.
3. Remove the server’s cover.
4. Gently spread the retaining clips at each end of the socket. The DIMM lifts from the
5. Holding the DIMM by the edges, lift it from the socket and store it in an anti-static
6. Reinstall and reconnect any parts you removed or disconnected to reach the DIMM
7. Replace the server’s cover and reconnect the AC power cord.

Intel® Server Board S5500WB TPS Functional Architecture Revision 1.9 Intel order number E53971 -008

3.4.8 Channel-Independent Mode

In the Independent Channel mode, you can populate multiple channels in any order (for example, you can populate channels B and C while channel A is empty). Also, DIMMs on adjacent channels do not need to have identical parameters. Therefore, all DIMMs are enabled and used in the Independent Channel mode. Adjacent slots on channels A and D do not need matching size and organization. However, the speed of the channel is configured to the maximum common speed of the DIMMs. The single channel mode is established using the independent channel mode by populating DIMM slots from channel A only.

3.4.9 Memory RAS

The memory RAS offered by the Intel® 5500 series and 5600 series processors is performed at channel level (for example, during mirroring, channel B mirrors channel A). All DIMM matching requirements are on a slot-to-slot basis on adjacent channels. For example, to enable mirroring, corresponding slots on channels A and B must have DIMMS of identical parameters. If one socket fails, the population requirements for RAS, the BIOS sets all six channels to the Independent Channel mode. One exception to this rule is when all DIMM slots from a socket are empty (for example, when only DIMM slots A1, B1, and C1 are populated, mirroring is possible on the platform).

3.4.9.1 Memory Population for Channel Mirroring Mode

The mirrored configuration is a redundant image of the memory, and can continue to operate despite the presence of sporadic uncorrectable errors. Channel mirroring is a RAS feature in which two identical images of memory data are maintained, thus providing maximum redundancy. On the Intel® 5500 series based Intel server boards, mirroring is achieved across channels. Active channels hold the primary image and the other channels hold the secondary image of the system memory. The integrated memory controller in the processor alternates between both channels for read transactions. Under normal circumstances, write transactions are issued to both channels. Mirroring is only supported between Channels A & B and Channels D & E. The presence of a DIMM on Channel C or F causes the BIOS to disable Mirroring and revert to the Independent Channel mode.

Figure 18. Mirroring Memory Configuration

3.4.10 Memory Error LED

message to the BMC to indicate which DIMM LED needs turn on.

3.5 Intel® 5500 Chipset IOH

can be configured in various combinations of x4, x8, x16 and limited x2 and x1 devices.

3.5.1 IOH24D PCI Express*

usage of the IOH24D PCI Express* bus segments.

**Table 6. IOH24D PCI Express* Bus Segments** x4 PCI Express* Gen1 throughput to an onboard NIC. X4 PCI Express* Gen2 throughput to slot 1. x8 PCI Express* Gen2 throughput to the slot 6 riser . Intel® I/O Expansion Module connectors.

3.5.1.1 Direct Cache Access (DCA)

Direct Cache Access (DCA). You enable or disable DCA in the BIOS processor setup menu.

3.5.1.2 Intel® Virtualization Technology for Directed I/O ( Intel® VT-d)

BIOS setup. The default behavior is disabled. directly assigned to a virtual machine leading to a robust and efficient virtualization.

3.6 Management Engine

Baseboard Management Controller (BMC).

Functional Architecture Intel® Server Board S5500WB TPS Intel order number E53971-008 The functionality provided by the SPS firmware is different from Intel® Active Management Technology (Intel® AMT or AT) provided by the ME on client platforms. Server Platform Services are value-added platform management options that enhance the value of Intel platforms and their component ingredients (CPUs, chipsets, and I/O components). Each service is designed to function independently wherever possible, or grouped together with one or more features in flexible combinations to allow OEMs (Original Equipment Manufacturers) to differentiate platforms. The following is a high-level view of the Intel® Server Board S5500WB SPS functions.  Node Management Features: o NPTM Policy Manager o Power Supply Monitoring Service o Inlet Temperature Monitoring Service o CPU Power Limiting Service  Provide Access to ICH10R Devices: The ME has control of ICH10R platform instrumentation. SPS provides a mechanism for the BMC to access this instrumentation through IPMI OEM commands. Use of this capability on Intel servers is platform-/SKU-specific. o ICH10 temperature monitoring  PECI 2.0 Proxy: SPS offers a means for a BMC without a PECI 2.0 interface to use the ME as a PECI proxy. The BMC on Intel servers already has a PECI 2.0 interface, so this SPS capability is not used.

3.7 Intel® 82801Jx I/O Controller Hub (ICH10 R)

The Intel® 82801Jx I/O Controller Hub (ICH10R) provides extensive I/O support and supports the following features and specifications:  PCI Express* Base Specification, Revision 1.1 support  ACPI Power Management Logic Support, Revision 3.0a  Enhanced DMA controller, interrupt controller, and timer functions  Integrated Serial ATA host controllers with independent DMA operation on up to six ports and AHCI support  USB host interface with support for up to 12 USB ports; six UHCI host controllers; and two EHCI high-speed USB 2.0 host controllers  System Management Bus (SMBus) Specification, Version 2.0 with additional support for I2C devices  Low Pin Count (LPC) interface support  Serial Peripheral Interface (SPI) support

3.7.1 Serial ATA Support

The ICH10R has an integrated Serial ATA (SATA) controller that supports independent DMA operation on six ports and data transfer rates of up to 3.0 Gb/s. The six SATA ports on the

Intel® Server Bo ard S5500WB TPS Functional Architecture Revision 1.9 Intel order number E53971 -008 server board are numbered SATA-1 through SATA-6. You can enable or disable the SATA ports and/or configure them by accessing the BIOS setup utility during POST.

3.7.1.1 Intel® Embedded Server RAID Technology II

The onboard storage capability of these server boards includes support for Intel® Embedded Server RAID Technology II (Intel® ESRTII), which provides three standard software RAID levels: data stripping (RAID Level 0), data mirroring (RAID Level 1), and data stripping with mirroring (RAID Level 10). For higher performance, you can use data stripping to alleviate disk bottlenecks by taking advantage of the dual independent DMA engines that each SATA port offers. Data mirroring is used for data security. If a disk fails, a mirrored copy of the failed disk is brought online. There is no loss of either PCI resources (request/grant pair) or add-in card slots. With the addition of an optional Intel® RAID Activation Key, Intel® ESRTII is also capable of providing fault tolerant data stripping (software RAID Level 5), such that if a SATA hard drive fails, you can restore the lost data on a replacement drive from the other drives that make up the RAID 5 pack. Intel® Embedded Server RAID Technology functionality requires the following items:  ICH10R IO Controller Hub  Software RAID option is selected on BIOS menu for SATA controller  Intel® Embedded Server RAID Technology II Option ROM  Intel® Embedded Server RAID Technology II drivers, most recent revision  At least two SATA hard disk drives

3.7.1.2 Intel® Embedded Server RAID Technology II Option ROM

The Intel® Embedded Server RAID Technology II for SATA Option ROM provides a pre- operating system user interface for the Intel® Embedded Server RAID Technology II implementation and provides the ability to use an Intel® Embedded Server RAID Technology II volume as a boot disk as well as to detect any faults in the Intel® Embedded Server RAID Technology II volume(s). 3.7.2 USB 2.0 Support The USB controller functionality integrated into ICH10R provides the server board with an interface for up to 12 USB 2.0 ports. All ports are high-speed, full-speed, and low-speed capable.  Four external connectors are located on the back edge of the server board.  Two internal 2x5 headers are provided, capable of supporting two optional USB 2.0 ports each, typically, one header supports Front panel USB and one supports an internal third party management card.  One internal low-profile 2x5 header is provided  One Internal Type A USB vertical connector is provided for attaching standard peripherals  The BMC consumes 2 ports, for a total of 12 Ports

3.8 Network Interface Controller (NIC)

Controller Datasheet (Document#: 82576) for full details of the NIC feature set. and receiving data at rates of 1000 Mbps, 100 Mbps, or 10 Mbps. management traffic over the RMII bus to the network during sleep state S5. The NIC supports the normal RJ-45 LINK/Activity speed LEDs as well as the Proset ID function. These LEDs are powered from a Standby voltage rail. 1000-Mbps operation when amber, 100-Mbps operation when green, and 10-Mbps when off. The following table provides an overview of the LEDs. Table 7. NIC 1 Status LED Table 8. NIC 2 Status LED

Intel® Server Board S5500WB TPS Functional Architecture Revision 1.9 Intel order number E53971 -008

3.8.1 MAC Address Definition

The Intel® Server Board S5500WB has the following four MAC addresses assigned to it at the Intel factory.  NIC 1 MAC address  NIC 2 MAC address – Assigned the NIC 1 MAC address +1  Integrated BMC LAN Channel MAC address – Assigned the NIC 1 MAC address +2  Intel® Remote Management Module 3 (Intel® RMM3) MAC address – Assigned the NIC 1 MAC address +3 The Intel® Server Board S5500WB has a white MAC address sticker included with the board. The sticker displays the NIC 1 MAC address in both bar code and alphanumeric formats.

3.8.2 LAN Connector Ordering

The Intel® 82576 NIC is connected to a stacked RJ-45 over USB mag-jack for NIC 1 and a RJ- 45 mag-jack for the second connection (NIC 2).

3.9 Integrated Baseboard Management Controller

The ServerEngines* LLC Pilot II Integrated BMC is provided by an embedded ARM9 controller and associated peripheral functionality that is required for IPMI-based server management. Firmware usage of these hardware features is platform-dependant. The following is a summary of the Integrated BMC management hardware features used by the ServerEngines* LLC Pilot II Integrated BMC:  IPMI 2.0 Compliant  Integrated 250 MHz 32-bit ARM9 processor  Six I2C SMBus modules with Master-Slave support  Two independent 10/100 Ethernet Controllers with RMII support  Six I2C interface  Memory Management Unit (MMU)  DDR2 16-bit up to 667 MHz memory interface  Up to 16 direct and 64 Serial GPIO ports  12 10-bit Analog to Digital Converters  Eight Fan Tachometers Inputs  Four Pulse Width Modulators (PWM)  Chassis Intrusion Logic with battery-backed general purpose register  JTAG Master interface  Watchdog timer Additionally, the ServerEngines* Pilot II part integrates a super I/O module with the following features:  Keyboard Style/BT Interface

Functional Architecture Intel® Server Board S5500WB TPS Intel order number E53971-008  Two 16C550 compatible serial ports  Serial IRQ support  16 GPIO ports (shared with Integrated BMC)  LPC to SPI Bridge for system BIOS support  SMI and PME support  ACPI compliant  Wake-up control The Pilot II contains an integrated KVMS subsystem and graphics controller with the following features:  USB 2.0 for keyboard, mouse, and storage devices  Hardware Video Compression for text and graphics  Hardware encryption  2D Graphics Acceleration  DDR2 graphics memory interface  Matrox 2000 Graphics core with PCI Express* x1 host interface  Up to 1600x1200 pixel resolution

Figure 19. Integrated BMC Hardware

3.9.1 Integrated BMC Embedded LAN Channel

interface for management traffic. The default active interface is the NIC 1 port. For these channels, you can enable support for IPMI-over-LAN and DHCP.

3.9.2 RMM3 Advanced Management Board:

customer the option to add a dedicated management 100-Mbit LAN interface to the product. the board. RMM3 management traffic can use the third NIC or NIC 1. Table 8. RMM3 Features

3.10 Serial Ports

The serial B port is an optional port that is accessed through a 9-pin internal DH-10 header. You can use a standard DH-10 to DB9 cable to direct serial A port to the rear of a chassis. Appendix A defines the serial B interface.

3.11 Wake-up Control

Wake from S1 is supported on LAN, USB, Serial port, and PCI Express* slots.

3.12 Integrated Video Support

The SVGA subsystem supports a variety of modes, up to 1280x1024@24bpp modes under 2D. It also supports both CRT and LCD monitors up to a 200 Hz vertical refresh rate. operation when an add-in video card is configured in the system.

3.12.1 Video Modes

the 2D modes supported for both CRT and LCD. Table 9. Supported Video Modes

3.12.2 Dual Video

when an add-in video card is detected. options to configure the feature as follows. Table 10. Dual Video Options

3.12.3 Front Panel Video

connector, the rear panel video stream is disconnected. rear panel video connector, the video stream to the internal header is cut off.

3.13 I/O Slots

3.13.1 X16 Riser Slot Definition

riser and extending the board over the 1U CPU heatsinks or if CPU2 is unpopulated. Appendix A describes the pin assignments for this connector.

3.13.2 PE WIDTH Strapping

buses used by the riser. For slot 6, the PEWIDTH bit used is 0. Table 11. PEWIDTH Strapping Bits

3.13.3 Slot 1 PCI Express* x8 Connector

would require 2U chassis back panel changes.

3.13.4 I/O Module Connector

Module Bus usage, PEWIDTH bit 1 is to be used for this. Table 12. Intel® I/O Expansion Module Bus PEWIDTH Bits

1. Intel® I/O Expansion Modules

the PCI Express* Gen 1 I/O modules (used on the S5000PAL rack server). interference with some adapters installed in Slot 1. The following table shows the product codes for each module. Table 13. Intel® I/O Expansion Module Product Codes optional host RAID (4 internal ports). optional backup battery AXXRSBBU3 separately. AXXSASIOMOD External 4-port SAS I/O Expansion Module.

Intel® Server Board S5500WB TPS Functional Architecture Revision 1.9 Intel order number E53971 -008 Product Code Description AXX4GBIOMOD2 Quad port Gigabit Ethernet I/O Expansion Module based on the Intel® 82576EB Gigabit Ethernet Controller. AXXIBQDRMOD InfiniBand* I/O Expansion Module Single Port QDR. For more information, refer to the I/O modules in the Intel® I/O Expansion Modules Hardware Specification.

Platform Management Features Intel® Server Board S5500WB TPS Revision 1.9 Intel order number E53971 -008 5. Platform Management Features This section explains BIOS and firmware (FW) requirements that drive specific hardware implementations of the platform. To a large extent, this is background information.

5.1 BIOS Feature Overview

The Intel® Server Board S5500WB product uses the AMI Aptio v3.x code base.

5.1.1 EFI Support

The platform BIOS is compiled to support the 64-bit EFI environment, natively. This allows operating systems that are EFI-aware to take advantage of the EFI-boot process in a native 64- bit environment. It is expected this will reduce the time required to boot the platform to those operating systems. Additionally, any utilities that make use of the EFI environment provided by the platform BIOS need to support either the native 64-bit environment or make use of the EFI byte code (EBC). Of course, to maintain compatibility with legacy operating environments, a legacy boot option is provided.

5.1.2 BIOS Recovery

The platform BIOS supports a BIOS Recovery Mode Jumper. The BIOS samples this jumper during POST through a GPIO and, if set, defaults to a recovery mode of operation that allows restoration of the BIOS Flash to a full operational state. The platform BIOS supports a Reset BIOS Configuration Jumper. The BIOS samples this jumper during POST through a GPIO and, if set, resets its configuration information stored in Flash memory.

5.2 BMC Feature Overview

The server management subsystem consists of multiple components including several interconnected microcontrollers. The subsystem monitors platform sensors (temperatures, voltages, fans, hard drives, and so forth); implements platform acoustics, power, and thermal management policies; provides an intelligent LCD front-panel; and provides facilities for remote and local management. The server management subsystem is available when the system is connected to wall power but not fully operational (S5 state); when the system is in a S1 sleep state or when the system is fully operational (S0 state).

5.2.1 Server Engines Pilot II Controller

The center of the server management subsystem is the Server Engines Pilot II integrated Baseboard Management Controller. This device provides support for many platform functions including system video capabilities, legacy Super I/O functions, and also provides an ARM 926- EJ microcontroller to host the embedded server management firmware stack.

Intel® Server Board S5500WB TPS Platform Management Features Revision 1.9 Intel order number E53971 -008 The Server Engines Pilot II baseboard management controller across Intel’s server product line with two different management feature set configurations: Basic and Advanced. The Intel® Server Board S5500WB supports both. Basic features include IPMI 2.0 support, remote management, hardware monitoring, event management, event alerting, system event log, asset inventory, console redirection, web interface, and SMASH CLP (basic feature set). Advanced features include the Basic features plus KVM redirection, USB Media redirection, SMASH CLP (Advanced feature set), and WS-MAN. To enable the Advanced features, you must install the Remote Management Module 3. Note: The BMC consumes two USB ports; one runs at USB1.1 for keyboard mouse redirection and one runs at USB2.0 for media redirection.

5.2.2 BMC Firmware

The BMC supports a Fast Firmware Update mode in addition to the standard KCS (Keyboard Controller Style) SMS interface. This is a special AMI® proprietary protocol that goes over the USB connection between the host and the BMC. Called ―IPMI over USB‖, it is implemented in the LIBIPMI library on both host and BMC sides to transfer large blocks of data (up to 32 K) much faster than KCS can. IPMI commands are embedded in data written/read to a virtual CD- ROM device. The embedded server management firmware stack is based on a core stack from American Megatrends Incorporated (AMI). The stack runs on an embedded version of the Linux operating system and provides support for current industry standard management interfaces (IPMI 2.0) and emerging industry standard advanced management interfaces (SMASH-CLP and WS- MAN). The stack also includes support for keyboard, video, mouse (KVM), and USB media redirection. The server management subsystem provides remote connectivity through a single GbE NIC with NC-SI support (RMII). NPTM support is required; you must use the ME function in the IOH to accomplish this.

5.2.3 BMC Basic Features

Table 14: BMC Basic Features Feature Description IPMI 2.0 Compliance to IPMI 2.0 specification Remote Management Out-of-band access via either LAN or serial port for numerous features Hardware Monitor Monitor of fans, voltages, temperatures, chassis intrusions, memory errors, power supplies, hard drives, and so forth Event Management System event filtering Event Alerting System events delivered via SNMP traps or email System Event Log Dedicated persistent storage for system events Asset Inventory Field replaceable unit (FRU) information Console Redirection Text-based console redirection via serial-over-LAN

5.2.4 BMC Advanced Fe atures

the local integrated BMC 8 MB SPI flash connected to the PILOT II IBMC down on the board. BMC to offer a dedicated management Ethernet port. Table 15. Advanced Features

5.3 Management Engine (ME)

5.3.1 Overview

AMT or AT) provided by the ME on client platforms.

Intel® Server Board S5 500WB TPS Platform Management Features Revision 1.9 Intel order number E53971 -008 grouped together with one or more features in flexible combinations to allow OEMs to differentiate platforms.

5.3.2 BMC - Management Engine Interaction

Management Engine-Integrated BMC interactions include the following:  Integrated BMC stores sensor data records for ME-owned sensors.  Integrated BMC participates in ME firmware update.  Integrated BMC initializes ME-owned sensors based on SDRs.  Integrated BMC receives platform event messages sent by the ME.  Integrated BMC notifies ME of POST completion.

5.4 Data Center Manageability Interface

The DCMI specifications are derived from Intelligent Platform Management Interface (IPMI) 2.0. The DCMI specifications define a uniform set of monitoring, control features and interfaces that target the common and fundamental hardware management needs of server systems that are used in large deployments within data centers, such as Internet Portal data centers. This includes capabilities such as secure power and reset control, temperature monitoring, event logging, and others. For more information refer to www.intel.com/go/dcmi.

5.5 Other Platform Management

The platform supports the following sleep states, S1 and S5. Within S0, the platform supports additional lower power states, such as C1e and C6, for the CPU.

5.5.1 Wake On LAN (WOL)

 Wake On LAN (WOL) is supported on both LAN ports and IOM LAN modules for all supported Sleep states.  Wake on Ring is supported on the external Serial port only for all supported Sleep states.  Wake on USB is supported on the rear and front panel USB ports for S1 only.  Wake on RTC is supported for all supported Sleep states.  Wake IPMI command is supported (BMC function no additional hardware requirement) for all supported Sleep states.

5.5.2 PCI Express* Power management

L0 and L3 power management states are supported on all PCI Express* slots and embedded end points.

5.5.3 PMBus*

Power supplies that have PMBus* 1.1 are supported and required to support Intel® Dynamic Power Node Manager. Intel® Server Board S5500WB supports the features of Intel® Dynamic Power Node Manager version 1.5 except the inlet temperature sensor.

5.6 I2C\\SMBUS Architecture Block

Figure 20. S5500WB I2C\\SMBUS Block Diagram

5.6.1 I2C\\SMBUS Device Addresses

Table 21 lists the I2C\\SMBus addresses of various devices by bus. Table 16. I2C/SMBus Device Address Assignment

Intel® Server Board S5500WB TPS Platform Management Features Revision 1.9 Intel order number E53971 -008 Main Bus Power Rail Sub Bus Power Rail Device I2C\\SMBus Address Note LAN 3V3SB NA NA IBMC I2C\\SMBus 5 NIC LAN Link 3V3SB NA NA IBMC I2C\\SMBus 4 ICH10R SMLINK 0x88 PWR 5V PS FRU 0xAC PS I2C\\PSMI 0xB0 Spare 3V3SB NA NA IBMC I2C\\SMBus 2 DDC 3V3SB DDC 5V IBMC GFX DDC Video Monitor 0xA0

Configuration Jumpers Intel® Server Board S5500WB TPS Revision 1.9 Intel order number E53971 -008 6. Configuration Jumpers The following table provides a summary and description of configuration, test, and debug jumpers on the Intel® Server Board S5500WB. The server board has several 3-pin jumper blocks that can be used. Pin 1 on each jumper block can be identified by the following symbol on the silkscreen: ▼ Figure 21: Jumper Blocks (J1B5, J1C2, J1C3, J1B4, J6A3, J6A2, J7A2)

1-2 Normal IBMC GPIO[1] is pulled HIGH. Default position. 2-3 Update IBMC GPIO[1] is pulled LOW. 2-3 Clear Password ICH10R INTRUDER# pin is pulled LOW. 2-3 Recovery ICH10R GPIO [55] is pulled LOW. ICH10R RTCRST# pin is pulled LOW.

6.1.1 Force IBMC Update (J1B5)

standard BMC firmware update process fails. Table 18. Force IBMC Update Jumper 1-2 Normal IBMC GPIO[1] is pulled HIGH. Default position. 2-3 Update IBMC GPIO[1] is pulled LOW.

1. Power down and remove the AC power cord.
2. Open the server chassis. See your server chassis documentation for instructions.
3. Move jumper from the default operating position, covering pins1 and 2, to the enabled

position, covering pins 2 and 3.

1. Close the server chassis.
2. Reconnect the AC cord and power up the server.

1. Perform the BMC firmware update procedure as documented in the README.TXT file

BMC is still in update mode.

1. Power down and remove the AC power cord.
2. Move the jumper from the enabled position, covering pins 2 and 3 to the disabled

position, covering pins 1 and 2.

1. Close the server chassis.
2. Reconnect the AC cord and power up the server.

recover specific features of the server board.

6.1.2 Password Clear (J1C2)

The user sets this 3-pin jumper to clear the password. Table 19. Password Clear Jumper 1-2 Normal ICH10R INTRUDER# pin is pulled HIGH. Default position. 2-3 Clear Password ICH10R INTRUDER# pin is pulled LOW.

6.1.2.1 Clearing the Password

1. Power down server. Do not unplug the power cord.
2. Open the chassis. For instructions, see your server chassis documentation.
3. Move jumper (J1B6) from the default operating position, covering pins 1 and 2, to the

password clear position, covering pins 2 and 3.

1. Close the server chassis.
2. Power up the server, wait 10 seconds or POST completes.
3. Open the chassis and move the jumper back to default position, covering pins 1 and 2.
4. Close the server chassis.

The password is now cleared and you can reset it by going into the BIOS setup.

6.1.3 BIOS Recovery Mode (J1C3)

specific BIOS release notes. Table 20. BIOS Recovery Mode Jumper 1-2 Normal ICH10R GPIO [55] is pulled HIGH. Default position. 2-3 Recovery ICH10R GPIO [55] is pulled LOW. You can accomplish a BIOS recovery from the SATA CD and USB Mass Storage device. Please note that this platform does not support recovery from a USB floppy.

1. UEFI iFlash32 2.6 Build 9
2. Startup.nsh (update accordingly to use proper *Rec.CAP file)
3. Switch the recovery jumper. Details regarding the jumper ID and location can be obtained

from the Board EPS for that Platform.

1. The BIOS POST screen will appear displaying the progress, and the system automatically
2. The Startup.nsh file executes, and initiates the flash update (IFlash32.efi) with a new

once the flash update succeeds.

1. Power OFF the system, and revert the recovery jumper position to "normal operation".
2. Do NOT interrupt the BIOS POST during the first boot.

6.1.4 Reset BIOS Configuration (J1B4)

determine if the data in the NVRAM needs to be set to default. Table 21. Reset BIOS Jumper 1-2 Normal ICH10R RTCRST# pin is pulled HIGH. Default position. 2-3 Reset BIOS Configuration ICH10R RTCRST# pin is pulled LOW.

6.1.4.1 Clearing the CMOS

1. Power down server. Do not unplug the power cord.
2. Open the server chassis. For instructions, see your server chassis documentation.
3. Move jumper (J1B4) from the default operating position, covering pins 1 and 2, to the

reset / clear position, covering pins 2 and 3.

1. Move the jumper back to default position, covering pins 1 and 2.
2. Close the server chassis.

The CMOS is now cleared and you can reset it by going into the BIOS setup.

6.1.5 Video Master (J6A3)

Table 22. Video Master Jumper 1-2 Internal Internal connector will override if both connectors are used. 2-3 External External connector will override if both connectors are used. This jumper determines which video is the primary. video connector if you connect to it. video connector if you connect to it.

Intel® Server Board S5500WB TPS Configuration Jumpers Revision 1.9 Intel order number E53971 -008

6.1.6 ME Firmware Force Update (J7A2)

Pins ME Firmware Update Mode 1-2 Disabled (Default) 2-3 Enabled The ME firmware consists of two operational images and a recovery image. During boot, the recovery loader is started first and it tries to load the active firmware image by running the loader of this image. If it fails to boot, it tries to boot the other operational image. If both fail, the recovery loader starts in recovery mode. The recovery mode can also be forced setting the MGPIOx jumper on the board. Boot image verification and boot failure

6.1.7 Serial Interface (J6A2)

1 – 2 DCD to DTR Data Carrier Detect 3 – 4 DSR to DTR Data Set Ready

1. Connector/Header Locations and Pin-out

7.1 Power Connectors

Table 23. SSI SKU 24-pin 2x12 Connector (J9B3)

3 GND 15 GND

5 GND 17 GND

7 GND 19 GND

8 PWR_GD 20 NC

9 SB5V 21 +5V

Table 24. CPU 12V Power 2x4 Connector (J5K1)

1 GND

2 GND

3 GND

4 GND

Table 25. SSI Power Control (J9D1)

1 SMB_PWR_CLK

2 SMB_PWR_DAT

3 SMB_PWR_ALRT

Table 26. 12-V only 2x4 Connector (replaces EPSD12V 2x12 connector) (J9D2) Table 27. 12-V Only Power Control (replaces the 1x5 power control) (J9D1)

4 Remote Sense Return

6 PS_ON

Table 28. Peripheral Power (Only for 12-V only SKU) (J8K2)

4 Powergood

6 GND

7.2 System Management Headers

7.2.1 Intel® Remote Management Module 3 (Intel ® RMM3) Connector

Table 29. Intel® RMM3 Connector Pin-out (J5B1)

7.2.2 BMC Power Cycle Header (12V Only)

effect, it causes a BMC Power on reset to occur. Table 30. BMC Power Cycle Header (J1D2) 1 RST_BMC_PWR_CYC When power is removed from the BMC. is disabled first, then the main 3.3V S/B regulator is disabled, removing power from the BMC.

7.2.3 Hard Drive Activity (Input) LED Header

Table 47. SATA HDD Activity (Input) LED Header (J1D2)

1 LED_HD_ACTIVE_L

7.2.4 IPMB Header

Table 31. IPMB Header 4-pin (J1B2)

1 SMB_IPMB_5VSB_DAT BMC IPMB 5V standby data line

2 GND Ground

3 SMB_IPMB_5VSB_CLK BMC IPMB 5V standby clock line

4 P5V_STBY +5V standby power

7.2.5 SGPIO Header

Table 32. SGPIO Header (J1B1)

1 SCLOCK SGPIO Clock Signal

2 SLOAD SGPIO Load Signal

3 SDOUT0 SGPIO Data Out

4 SDOUT1 SGPIO Data In

7.3 SSI Control Panel Connector

third-party chassis. The following table provides the pin-out for this connector. Table 33. Front Panel SSI Standard 24-pin Connector Pin-out (J1E2)

1 P3V3_STBY (Power LED Anode) 2 P3V3_STBY (Front Panel Power)

3 Key 4 P5V_STBY (ID LED Anode)

7 P3V3 (HDD Activity LED Anode) 8 FP_LED_STATUS_GREEN_N

9 LED_HDD_ACTIVITY_N 10 FP_LED_STATUS_A MBER_N

11 FP_PWR_BTN_N 12 NIC1_ACT_LED_N

13 GND (Power Button GND) 14 NIC1_LINK_LED_N

15 BMC_RST_BTN_N 16 SMB_SENSOR_3V3STB_DATA

17 GND (Reset GND) 18 SMB_SENSOR_3V3STB_CLK

19 FP_ID_BTN_N 20 FP_CHASSIS_INTRU

21 NC 22 NIC2_ACT_LED_N

23 FP_NMI_BTN_N 24 NIC2_LINK_LED_N

Connector/Header Locations a nd Pin-out Intel® Server Board S5500WB TPS Revision 1.9 Intel order number E53971 -008 Combined system BIOS and the Integrated BMC support provide the functionality of the various supported control panel buttons and LEDs. The following sections describe the supported functionality of each control panel feature.

7.3.1 Power Button

The BIOS supports a front control panel power button. Pressing the power button initiates a request that the Integrated BMC forwards to the ACPI power state machines in the chipset. It is monitored by the Integrated BMC and does not directly control power on the power supply.  Power Button — Off to On The Integrated BMC monitors the power button and the wake-up event signals from the chipset. A transition from either source results in the Integrated BMC starting the power- up sequence. Since the processors are not executing, the BIOS does not participate in this sequence. The hardware receives the power good and reset signals from the Integrated BMC and then transitions to an ON state.  Power Button — On to Off (operating system absent) The System Control Interrupt (SCI) is masked. The BIOS sets up the power button event to generate an SMI and checks the power button status bit in the ACPI hardware registers when an SMI occurs. If the status bit is set, the BIOS sets the ACPI power state of the machine in the chipset to the OFF state. The Integrated BMC monitors power state signals from the chipset and de-asserts PS_PWR_ON to the power supply. As a safety mechanism, if the BIOS fails to service the request, the Integrated BMC automatically powers off the system in four to five seconds.  Power Button — On to Off (operating system present) If an ACPI operating system is running, pressing the power button switch generates a request via SCI to the operating system to shut down the system. The operating system retains control of the system and the operating system policy determines the sleep state into which the system transitions, if any. Otherwise, the BIOS turns off the system.

7.3.2 Reset Button

The platform supports a front control panel reset button. Pressing the reset button initiates a request forwarded by the Integrated BMC to the chipset. The BIOS does not affect the behavior of the reset button.

7.3.3 NMI Button

The BIOS supports a front control panel NMI button. The NMI button may not be provided on all front panel designs. Pressing the NMI button initiates a request that causes the Integrated BMC to generate an NMI (non-maskable interrupt). The NMI is captured by the BIOS during boot services time and by the operating system during runtime. During boot services time, the BIOS halts the system upon detection of the NMI.

7.3.4 Chassis Identify Button

The front panel Chassis Identify button toggles the state of the chassis ID LED. If the LED is off, pushing the ID button lights the LED. It remains lit until the button is pushed again or until a Chassis Identify or a Chassis Identify LED command is received to change the state of the LED.

7.3.5 Power LED

Table 34. Power LED Indicator States

7.3.6 System Status LED

source, the system status LED state would be solid on (the critical fault state). with the priority going to the most critical state currently asserted. The following table maps the system state to the LED state.

Table 35. System Status LED

1. Unable to use all of the installed memory (more than one DIMM
2. In a mirrored configuration, when memory mirroring takes place
3. PCI Express* correctable link errors.
4. Redundancy loss such as a power supply or fan. Applies only if

the associated platform subsystem has redundancy capabilities.

1. CPU disabled – if there are two CPUs and one CPU is disabled.
2. Fan alarm – Fan failure. Number of operational fans should be

more than minimum number needed to cool the system.

1. Non-critical threshold crossed – Temperature, voltage, power

nozzle, power gauge, and PROCHOT2 (Therm Ctrl) sensors.

1. Predictive failure when the system has redundant power
2. In non-mirroring mode, if the threshold of ten correctable errors
3. PCI Express* uncorrectable link errors.
4. Critical threshold crossed – Voltage, temperature, power nozzle,

power gauge, and PROCHOT (therm Ctrl) sensors.

1. Minimum number of fans to cool the system is not present or
2. DIMM failure when there is one DIMM present and no good
3. Run-time memory uncorrectable error in non-redundant mode.1
4. CPU configuration error (for instance, processor stepping
5. CPU CATERR signal asserted.
6. No power good – power fault.
7. Power Unit Redundancy sensor – Insufficient resources offset

(indicates not enough power supplies are present ).

1. The BIOS detects these conditions and sends a Set Fault Indication command to the Integrated BMC to provide

the contribution to the system status LED.

7.3.7 Chassis ID LED

Table 36. Chassis ID LED Indicator States pressed again with no intervening commands, the chassis ID LED turns off.

7.4 I/O Connectors

7.4.1 PCI Express* Connectors

shown in the following tables. Table 37. Slot 6 Riser Connector (J4B1)

3 RSVD 12V 3 43 GND PERxP6 43

4 GND GND 4 44 GND PERxN6 44

5 SMCLK JTAG2 5 45 PETxP7 GND 45

6 SMDATA JTAG3 6 46 PETxN7 GND 46

7 GND JTAG4 7 47 GND PERxP7 47

11 WAKE# PERST# 11 51 PETxN8 GND 51

12 RSVD GND 12 54 PETxP9 GND 54

Connector/Header Locations and Pin -out Intel® Server Board S5500WB TPS Revision 1.9 Intel order number E53971 -008 Pin Side B PCI Express* Signal PCI Express* Signal Pin Side A Pin Side B PCI Express* Signal PCI Express* Signal Pin Side A

13 GND REFCLK+ 13 55 PETxN9 GND 55

14 PETxP0 REFCLK- 14 56 GND PERxP9 56

15 PETxN0 GND 15 57 GND PERxN9 57

16 GND PERxP0 16 58 PETxP10 GND 58

17 PRSNT2# PERxN0 17 59 PETxN10 GND 59

18 GND GND 18 60 GND PERxP10 60

19 PETxP1 RSVD 19 61 GND PERxN10 61

20 PETxN1 GND 20 62 PETxP11 GND 62

21 GND PERxP1 21 63 PETxN11 GND 63

22 GND PERxN1 22 64 GND PERxP11 64

23 PETxP2 GND 23 65 GND PERxN11 65

24 PETxN2 GND 24 66 PETxP12 GND 66

25 GND PERxP2 25 67 PETxN12 GND 67

26 GND PERxN2 26 68 GND PERxP12 68

27 PETxP3 GND 27 69 GND PERxN12 69

28 PETxN3 GND 28 70 PETxP13 GND 70

29 GND PERxP3 29 71 PETxN13 GND 71

30 RSVD PERxN3 30 72 GND PERxP13 72

31 PRSNT2# GND 31 73 GND PERxN13 73

32 GND RSVD 32 74 PETxP14 GND 74

33 PETxP4 RSVD 33 75 PETxN14 GND 75

34 PETxN4 GND 34 76 GND PERxP14 76

35 GND PERxP4 35 77 GND PERxN14 77

36 GND PERxN4 36 78 PETxP15 GND 78

37 PETxP5 GND 37 79 PETxN15 GND 79

38 PETxN5 GND 38 80 GND PERxP15 80

39 GND PERxP5 39 81 PRSNT2# PERxN15 81

40 GND PERxN5 40 82 RSVD GND 82

**Table 38. Slot 1 PCI Express* x8 Connector (J1B3)**

Description

3 Reserved 3 12V

4 GND 4 GND

5 SMCLK 5 JTAG-TCK

6 SMDATA 6 JTAG-TDI

7 GND 7 JTAG-TDO

8 3.3V 8 JTAG-TMS 9 JTAG-TRST# 9 3.3V 10 3.3VAux 10 3.3V

11 Wake# 11 PERST#

12 Reserved 12 GND

Intel® Server Board S5500WB TPS Connector/Header Locations and Pin -out Revision 1.9 Intel order number E53971 -008 Pin-Side B PCI Express* Spec Signal Description Pin-Side A PCI Express* Spec Signal

13 GND 13 REFCLK1+

14 PETp(0) 14 REFCLK1+

15 PETn(0) 15 GND

16 GND 16 PERp(0)

17 Reserved 17 PERn(0)

18 GND 1X end 18 GND

19 PETp(1) 19 Reserved

20 PETn(1) 20 GND

21 GND 21 PERp(1)

22 GND 22 PERn(1)

23 PETp(2) 23 GND

24 PETn(2) 24 GND

25 GND 25 PERp(2)

26 GND 26 PERn(2)

27 PETp(3) 27 GND

28 PETn(3) 28 GND

29 GND 29 PERp(3)

30 Reserved 30 PERn(3)

31 PRSNT2# 31 GND

32 GND 4X end 32 Reserved

35 GND 35

36 GND 36

39 GND 39

40 GND 40

43 GND 43

44 GND 44

47 GND 47

48 PRSNT2# 48

49 GND 8X end 49 GND

7.4.2 VGA Connectors

The following table details the pin-out definition of the external VGA connector (J6A1): Table 39. VGA External Video Connector (J6A1)

1 V_IO_R_CONN Red (analog color signal R)

2 V_IO_G_CONN Green (analog color signal G)

3 V_IO_B_CONN Blue (analog color signal B)

4 TP_VID_CONN_B4 No connection

5 GND Ground

6 GND Ground

7 GND Ground

8 GND Ground

9 TP_VID_CONN_B9 No connection

10 GND Ground

11 TP_VID_CONN_B11 No connection

12 V_IO_DDCDAT DDCDAT

13 V_IO_HSYNC_CONN HSYNC (horizontal sync)

14 V_IO_VSYNC_CONN VSYNC (vertical sync)

15 V_IO_DDCCLK DDCCLK

Table 40. VGA Internal Video Connector (J1D1)

1 Red 2 R_RTN(Red Return)

3 Green 4 G_RTN(Green Return)

5 Blue 6 B_RTN(Blue Return)

7 Vsync 8 GND

9 Hsync GND

11 KEY 12 VIDEO_IN_USE signal

13 DDC_SDA 14 GND

15 DDC_SCL 16 +5V

7.4.3 NIC Connectors

Table 41. RJ-45 10/100/1000 NIC Connector Pin-out (J8A2, J9A1)

7.4.4 SATA Connectors

The pin configuration for each connector is identical and defined in the following table. Table 42. SATA Connectors

1 GND Ground

2 SATA_TX_P Positive side of transmit differential pair

3 SATA_TX_N Negative side of transmit differential pair

4 GND Ground

5 SATA_RX_N Negative side of receive differential pair

6 SATA_RX_P Positive side of receive differential pair

7.4.5 Intel® I/O Expansion Module Connector

Expansion Module connectors.

Table 43. 50-pin Intel® I/O Expansion Module Connector Pin-out (J2B1, J3B1)

7.4.6 Serial Port Connectors

B header (J1A2). The following tables define the pin-outs. Table 44. External RJ-45 Serial Port A (COM1) (J7A1)

1 SPA_RTS 5 SPA_RI

2 SPA_DTR 6 SPA_SIN

3 SPA_SOUT_N 7 SPA_DSR

4 GND 8 SPA_CTS

Table 45. Internal 9-pin Serial B (COM2) (J1A2)

1 SPB_DCD 2 SPB_DSR

3 SPB_SIN_N 4 SPB_RTS

5 SPB_SOUT_N 6 SPB_CTS

7 SPB_DTR 8 SPB_RI

9 GND

7.4.7 USB Connectors

Table 46. External USB Connector (J8A1, J9A1))

2 USB_N Differential data line paired with DATAH0

3 USB_P Differential date line paired with DATAL0

ports. The pin-out is the same for both of the connectors and is detailed in the following table. Table 47. Internal USB Connector (J1C1 and J9A2)

3 USB_N 4 USB_N

5 USB_P 6 USB_P

7 GND 8 GND

9 Key Pin 10 NC

Table 48. Low-Profile Internal USB Connector (J1E3)

3 USB_N 4 NC

5 USB_P 6 NC

7 GND 8 NC

9 Key Pin 10 LED#

7.5 Fan Headers

identical and defined in the following tables. Table 49. SSI 4-pin Fan Connector (J2K2, J2K3, J3K1, J7K1, J8K4, J8K5)

3 TACH IN FAN_TACH signal is connected to the BMC to monitor the fan speed

4 PWM OUT FAN_PWM signal to control fan speed

Table 50. 8-pin Fan Connector (J2K1 & J8K3)

3 Tach0

4 PWM0

5 GND

7 Tach1

8 PWM1

Intel® Light-Guided Diagnostics Intel® Ser ver Board S5500WB TPS Revision 1.9 Intel order number E53971 -008 8. Intel® Light-Guided Diagnostics The server boards have several onboard diagnostic LEDs to assist in troubleshooting board- level issues. This section provides a description the location and function of each LED on the server board. 8.1 5-V Standby LED Several server management features of this server board require a 5-V stand-by voltage is supplied from the power supply. Some of the features and components that require this voltage must be present when the system is ―Off‖ include the Integrated BMC, onboard NICs, and optional RMM3 connector with Intel® RMM3 installed. The LED is located in the lower-left corner of the server board and is labeled ―5VSB_LED‖ is illuminated when AC power is applied to the platform and 5-V standby voltage is supplied to the server board by the power supply. Figure 22: 5-V Standby Status LED Location

8.2 Fan Fault LEDs

Fan fault LEDs are present for the six fans and are located near each CPU fan header. Figure 23. Fan Fault LED Locations

8.3 System Status LED

The server board provides LED for system status. The following figure shows the LED location.

Figure 24. System Status LED Location

Table 51. System Status LED

1. Unable to use all of the installed memory (more than one
2. In a mirrored configuration, when memory mirroring takes
3. PCI Express* correctable link errors.
4. Redundancy loss such as a power supply or fan. Applies
5. CPU disabled – if there are two CPUs and one CPU is
6. Fan alarm – Fan failure. Number of operational fans should

be more than minimum number needed to cool the system.

1. Non-critical threshold crossed – Temperature, voltage,
2. Predictive failure when the system has redundant power
3. In non-mirroring mode, if the threshold of ten correctable errors
4. PCI Express* uncorrectable link errors.
5. Critical threshold crossed – Voltage, temperature, power nozzle,

power gauge, and PROCHOT (therm Ctrl) sensors.

1. The minimum number of fans required to cool the system are

Intel® Light-Guided Diagnostics Intel® Server Board S5500WB TPS Revision 1.9 Intel order number E53971 -008 Color State System Status Description Amber Solid on Fatal Fatal alarm – system has failed or shut down: BIOS Detected 1. DIMM failure when there is one DIMM present and no good memory is present.1 2. Run-time memory uncorrectable error in non-redundant mode.1 3. CPU configuration error (for instance, processor stepping mismatch). Integrated BMC Detected 1. CPU IERR signal asserted. 2. CPU 1 is missing. 3. CPU THERMTRIP. 4. No power good – power fault. 5. Power Unit Redundancy sensor – Insufficient resources offset (indicates not enough power supplies are present). Off N/A Not ready AC power off Notes: 1. The BIOS detects these conditions and sends a Set Fault Indication command to the Integrated BMC to provide the contribution to the system status LED. 2. Support for an upper, non-critical threshold limit is not provided in default SDR configuration. However if a user does enable this threshold in the SDR, then the system status LED should behave as described.

8.4 DIMM Fault LEDs

Each DIMM slot has a DIMM Fault LED near the DIMM slot. Figure 25. DIMM Fault LEDs Locations

8.5 POST Code Diagnostic LEDs

the rear I/O area of the server board by the VGA connector. POST process, you can use the Diagnostic LEDs to identify the last POST process executed. Figure 26. Rear Panel Diagnostic LEDs

8.6 Front Panel Support

supports the following diagnostic LEDs. Table 52. Standard Front Panel Functionality failure; or predictive PS failure.

Design and Environmental Specifications Intel® Server Board S5500WB TPS Revision 1.9 Intel order number E53971 -008 9. Design and Environmental Specifications

9.1 Fan Speed Control Thermal Management

Fan speed control supports the following thermal sensors:  Discrete board level digital thermal sensor TMP75  Front panel Temp Sensor (if present)  CPU PECI DTS  DDR3 RDIMM TSOD Eight front system fan headers for four individual thermal zones  Zone 4 (mem2 fans) responds to memory2 and CPU2 temperatures.  Zone 3 (CPU2 and MEM2 fans) responds to CPU2 and IOH temperatures.  Zone 2 (CPU1 and MEM1 fans) responds to CPU1 and IOH temperatures.  Zone 1 (mem1 fans) responds to memory1 and CPU1 temperatures. Figure 27: Thermal Zones

Table 53. Fan Connector Location & Detail

Table 54. Fan Connector Location & Detail Figure 29. Fans and Sensors Block Diagram

9.2 Thermal Sensors

9.2.1 Processor PECI Temperature Sensor

TControl command for the indicated CPU is used.

Intel® Server Board S5500WB TPS Design and Environmental Specifications Revision 1.9 Intel order number E53971 -008  Tcontrol offset Temperature = -2° C  Pos_hyst = 0° C  Neg_hyst = 3° C Those parameters in turn set the following:  Upper = - CPU PECI Tcontrol + Tcontrol offset  Lower = - CPU PECI Tcontrol + Tcontrol offset – 3C

9.2.2 Memory Temperature Sensor

DDR3 cooling requires thermal throttling to protect memory from overheating. The Intel® Server Board S5500WB supports both DDR3 UDIMM and DDR3 RDIMM. SPD temperature sensor on DIMM is anticipated to be available on all DDR3 RDIMM but not for non-ECC UDIMM, so open loop thermal throttling and closed loop thermal throttling are supported.  Static open loop thermal throttling: The system does not change any of the control registers in the processor during runtime. OLTT control registers are configured by BIOS MRC and remain fixed after post.  Static closed loop thermal throttling: The system does not change the control registers for a closed loop in the processor during runtime. CLTT control registers are configured by BIOS MRC. For advanced implementation with dynamic OLTT and CLTT, refer to the VR_Hot Sensor in VR11.1.

9.2.3 Board Temperature Sensor

For rack-based systems or those systems that do not have a front panel temp sensor, the board is enabled to use a board-mounted, industry standard TMP75 type temp sensor. This part is on the IBMC two-wire serial SENSOR bus. The use of digital parts removes calibration and placement location issues imposed by the alternate analog type sensors.

9.2.4 Thermals Sensor Placement

The I2C\\SMBUS based temp sensors are placed such that the ambient air temp can be measured. Placement near hot components and or downstream of hot components (including chassis-based hot spots) is avoided. The following figure shows the sensor placement on the Intel® Server Board S5500WB.

Design and Environmental Sp ecifications Intel® Server Board S5500WB TPS Revision 1.9 Intel order number E53971 -008 Figure 30: Temp Sensor Location Location Description A U4K3 Temp Sensor - TMP75

9.3 Heatsinks

The Intel® Server Board S5500WB system cooling solutions rely on heatsinks for CPU cooling. Chipset and or voltage regulator heatsinks are compatible with the 1U usage.

9.3.1 Unified Retention System Support

Mechanism (ILM) and Unified Backplate at each processor socket. following figure for the stacking order of the URS components. Figure 31. Unified Retention System and Unified Backplate Assembly

Design and Environmental Specifications Intel® Server Board S5500WB TPS Revision 1.9 Intel order number E539 71-008

9.4 Errors

This section outlines how errors are routed in the hardware to ensure appropriate FW action (logging, fan control, system management, and so forth) is taken when an event occurs.

9.4.1 PROCHOT#

PROCHOT# is a bi-directional signal. The CPU toggles PROCHOT# when it goes into throttling mode. The duty cycle of PROCHOT# toggling indicates the amount of throttling initiated by the CPU. FW does not monitor PROCHOT# to determine CPU throttling percentage. Instead, it obtains outbound CPU throttling data via PECI. The path between the CPU’s and IBMC (TTL_CPU_PROCHOT#) is there as a backup. An external source can also toggle PROCHOT# to force the CPU to go into throttling mode. This usually happens when the system reaches a certain thermal threshold. VRHOT is an output of the CPU VR controller, which is capable of throttling the CPU via PROCHOT#. Some simple masking circuitry is required to prevent the VRHOT from asserting the PROCHOT# to the CPUs at the time of CPU_RST#. This keeps the VRHOT from unintentionally causing the CPU to disable. FW monitors VRHOT and creates a SEL event if VRHOT is asserted. There is no fan action as a result of the BMC seeing VRHOT.

9.4.2 THERMTRIP#

THERMTRIP# comes from the CPU. The THERMTRIP# signal is tied to a unique GPI on IBMC for FW to monitor. The combined THERMTRIP#’s from both CPUs is also tied to the ICH10R THERMTRIP input to cause an automatic Power Off condition when activated.

9.4.3 CATERR#

The CATERR# signal from the CPU signals a catastrophic error occurred. CATERR# may signal two types of issues. One type is a warning and is indicated by a pulse on the signal. The other is the static critical error, which is indicated by a continuously asserted level on the signal. The BMC only logs the static Critical Error events and ignores the warnings indicated by the pulse. An error on the CPU is immediately communicated to the ICH10R for notification.

10.1 Server Board Power Distr ibution

Figure 32. Power Distribution Diagram

10.2 Power Supply Compatibility

specifications at the following website http://ssiforum.org.

Power Subsystem Intel® Server Board S5500WB TPS Revision 1.9 Intel order number E53971 -008 The SSI uses the standard 24-pin and 8-pin power headers along with the 5pin Control connector. The 12-V only uses two 8-pin power headers, a 7-pin control header and a 6 pin HDD power connector. For maximum rack server efficiency, a DC 12-V only power supply is recommended. Appendix A shows connector pin outs. PMbus communications between the power supply and server board must comply with both SMBus and I2C Bus timing requirements.

10.3 Power Sequencing and Reset Distribution

The IBMC device is integrated into the power control and reset logic of the system. This design reduces the discrete logic requirements of previous generations and at the same time permits FW to manage certain features related to the power on/off control and the reset logic.

Intel® Server Board S5500WB TPS Regulatory and Certification Information Revision 1.9 Intel order number E53971 -008 11. Regulatory and Certification Information

11.1 Product Regulat ion Requirements

Intended Application – This product was evaluated as Information Technology Equipment (ITE), which may be installed in offices, schools, computer rooms, and similar commercial type locations. The suitability of this product for other product categories and environments (such as: medical, industrial, telecommunications, NEBS, residential, alarm systems, test equipment), other than an ITE application, may require further evaluation. This is an FCC Class A device. Integration of it into a Class B chassis does not result in a Class B device.

11.1.1 Product Safety Compliance

The Intel® Server Board S5520UR complies with the following safety requirements:  UL60950 – CSA 60950(USA / Canada)  EN60950 (Europe)  IEC60950 (International)  CB Certificate & Report, IEC60950 (report to include all country national deviations)  GOST R 50377-92 – Listed on one System Certification (Russia)  Belarus Certification – Listed on System Certification (Belarus)  CE - Low Voltage Directive 73/23/EEE (Europe)  IRAM Certification (Argentina)

11.1.2 Product EMC Compliance – Class A Compliance

 FCC /ICES-003 - Emissions (USA/Canada) Verification  CISPR 22 – Emissions (International)  EN55022 - Emissions (Europe)  EN55024 - Immunity (Europe)  CE – EMC Directive 89/336/EEC (Europe)  AS/NZS 3548 Emissions (Australia / New Zealand)  VCCI Emissions (Japan)  BSMI CNS13438 Emissions (Taiwan)  GOST R 29216-91 Emissions - Listed on one System Certification (Russia)  GOST R 50628-95 Immunity –Listed on one System Certification (Russia)  Belarus Certification – Listed on one System Certification (Belarus)  KCC (EMI) (Korea)

11.1.3 Certifications / Registrations / Declarations

 NRTL Certification (US/Canada)  CE Declaration of Conformity (CENELEC Europe)  FCC/ICES-003 Class A Attestation (USA/Canada)  C-Tick Declaration of Conformity (Australia)  MED Declaration of Conformity (New Zealand)

Regulatory and Certification Information Intel® Server Board S5500WB TPS Revision 1.9 Intel order number E53971 -008  BSMI Certification (Taiwan)  GOST – Listed on one System Certification (Russia)  Belarus – Listed on one System Certification (Belarus)  KCC Certification (Korea)  Ecology Declaration (International)

11.2 Product Regulatory Compliance Markings

This Intel Server Board bears the following regulatory marks: Table 55: Product Regulatory Compliance Markings

11.3 Electromagnetic Compatibility Notices

11.3.1 FCC Verification Statement (USA)

This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Regulatory Compliance Country Marking UL Mark USA/Canada CE Mark Europe FCC Marking (Class A) USA EMC Marking (Class A) Canada CANADA ICES-003 CLASS A CANADA NMB-003 CLASSE A BSMI Marking (Class A) Taiwan KCC Mark Korea

Intel® Server Board S5500WB TPS Regulatory and Certification Information Revision 1.9 Intel order number E53971 -008 For questions related to the EMC performance of this product, contact: Intel Corporation 5200 N.E. Elam Young Parkway Hillsboro, OR 97124-6497 1-800-628-8686 This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:  Reorient or relocate the receiving antenna.  Increase the separation between the equipment and the receiver.  Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.  Consult the dealer or an experienced radio/TV technician for help. Any changes or modifications not expressly approved by the grantee of this device could void the user’s authority to operate the equipment. The customer is responsible for ensuring compliance of the modified product. Only peripherals (computer input/output devices, terminals, printers, etc.) that comply with FCC Class A or B limits may be attached to this computer product. Operation with noncompliant peripherals is likely to result in interference to radio and TV reception. All cables used to connect to peripherals must be shielded and grounded. Operation with cables, connected to peripherals that are not shielded and grounded may result in interference to radio and TV reception.

11.3.2 ICES-003 (Canada)

Cet appareil numérique respecte les limites bruits radioélectriques applicables aux appareils numériques de Classe Aprescrites dans la norme sur le matériel brouilleur: ―Appareils Numériques‖, NMB-003 édictée par le Ministre Canadian des Communications. English translation of the notice above: This digital apparatus does not exceed the Class A limits for radio noise emissions from digital apparatus set out in the interference-causing equipment standard entitled ―Digital Apparatus,‖ ICES-003 of the Canadian Department of Communications.

Regulatory and Certification Information Intel® Server Board S5500WB TPS Revision 1.9 Intel order number E53971 -008

11.3.3 Europe (CE Declaration of Conformity)

This product has been tested in accordance too, and complies with the Low Voltage Directive (73/23/EEC) and EMC Directive (89/336/EEC). The product has been marked with the CE Mark to illustrate its compliance.

11.3.4 BSMI (Taiwan)

The BSMI Certification Marking and EMC warning is located on the outside rear area of the product.

11.3.5 KCC (Korea)

Following is the KCC certification information for Korea. English translation of the notice above: 1. Type of Equipment (Model Name): On Certification and Product 2. Certification No.: On KCC certificate. Obtain certificate from local Intel representative 3. Name of Certification Recipient: Intel Corporation 4. Date of Manufacturer: Refer to date code on product 5. Manufacturer/Nation: Intel Corporation/Refer to country of origin marked on product

process, the diagnostic LEDs can be used to identify the last POST process to be executed. corresponding LED is lit. If the bit is clear, then the corresponding LED is off. labeled as ―LSB‖ (Least Significant Bit). Figure 33. Diagnostic LED Placement Diagram

Table 56. POST Progress Code LED Example

Intel® Server Board S5500WB TPS Appendix A: POST Code LED Decoder Revision 1.9 Intel order number E53971 -008 Table 57. Diagnostic LED POST Code Decoder 1 = On, 0=Off Upper Nibble Lower Nibble MSB LSB 8h 4h 2h 1h 8h 4h 2h 1h Host Processor 0x10h 0 0 0 1 0 0 0 0 Power-on initialization of the host processor (bootstrap processor) 0x11h 0 0 0 1 0 0 0 1 Host processor cache initialization (including AP) 0x12h 0 0 0 1 0 0 1 0 Starting application processor initialization 0x13h 0 0 0 1 0 0 1 1 SMM initialization 0x14h 0 0 0 1 0 1 0 0 Selection of Processor with least features to be used as Boot Strap Processor 0x15h 0 0 0 1 0 1 0 1 Switch an AP processor to become the new Boot Strap Processor Chipset 0x21h 0 0 1 0 0 0 0 1 Initializing a chipset component Memory 0x22h 0 0 1 0 0 0 1 0 Reading configuration data from memory (SPD on FBDIMM) 0x23h 0 0 1 0 0 0 1 1 Detecting presence of memory 0x24h 0 0 1 0 0 1 0 0 Programming timing parameters in the memory controller 0x25h 0 0 1 0 0 1 0 1 Configuring memory parameters in the memory controller 0x26h 0 0 1 0 0 1 1 0 Optimizing memory controller settings 0x27h 0 0 1 0 0 1 1 1 Initializing memory, such as ECC init 0x28h 0 0 1 0 1 0 0 0 Testing memory 0xE4h 1 1 1 0 0 1 0 0 BIOS cannot communicate with DIMM (serial channel hardware failure) 0xE6h 1 1 1 0 0 1 1 0 DIMM(s) failed Memory iBIST or Memory Link Training failure 0xE8h 1 1 1 0 1 0 0 0 No memory available (system halted) 0xE9h 1 1 1 0 1 0 0 1 Unsupported or invalid DIMM configuration (system halted) 0xEAh 1 1 1 0 1 0 1 0 DIMM training sequence failed (system halted) 0xEBh 1 1 1 0 1 0 1 1 Memory test failed (system halted) 0xECh 1 1 1 0 1 1 0 0 Unsupported or invalid DIMM configuration (system halted) 0xEDh 1 1 1 0 1 1 0 1 Unsupported or invalid DIMM configuration (system halted) 0xEBh 1 1 1 0 1 0 1 1 DIMM with corrupted SPD data detected (system halted)

Appendix A: POST Code LED Decoder Intel® Server Board S5500WB TPS Revision 1.9 Intel order number E53 971-008 QuickPath Interconnect (QPI) 0xA0h 1 0 1 0 0 0 0 0 QPI Initialization 0xA1h 1 0 1 0 0 0 0 1 QPI Initialization 0xA2h 1 0 1 0 0 0 1 0 QPI Initialization 0xA3h 1 0 1 0 0 0 1 1 QPI Initialization 0xA4h 1 0 1 0 0 1 0 0 QPI Initialization 0xA5h 1 0 1 0 0 1 0 1 QPI Initialization 0xA6h 1 0 1 0 0 1 1 0 QPI Initialization 0xA7h 1 0 1 0 0 1 1 1 QPI Initialization 0xA8h 1 0 1 0 1 0 0 0 QPI Initialization 0xA9h 1 0 1 0 1 0 0 1 QPI Initialization 0xAAh 1 0 1 0 1 0 1 0 QPI Initialization 0xABh 1 0 1 0 1 0 1 1 QPI Initialization 0xACh 1 0 1 0 1 1 0 0 QPI Initialization 0xADh 1 0 1 0 1 1 0 1 QPI Initialization 0xAEh 1 0 1 0 1 1 1 0 QPI Initialization 0xAFh 1 0 1 0 1 1 1 1 QPI Initialization Integrated Memory Controller (IMC) 0xB0h 1 0 1 1 0 0 0 0 Memory Initialization of Integrated Memory Controller 0xB1h 1 0 1 1 0 0 0 1 Memory Initialization of Integrated Memory Controller 0xB2h 1 0 1 1 0 0 1 0 Memory Initialization of Integrated Memory Controller 0xB3h 1 0 1 1 0 0 1 1 Memory Initialization of Integrated Memory Controller 0xB4h 1 0 1 1 0 1 0 0 Memory Initialization of Integrated Memory Controller 0xB5h 1 0 1 1 0 1 0 1 Memory Initialization of Integrated Memory Controller 0xB6h 1 0 1 1 0 1 1 0 Memory Initialization of Integrated Memory Controller 0xB7h 1 0 1 1 0 1 1 1 Memory Initialization of Integrated Memory Controller 0xB8h 1 0 1 1 1 0 0 0 Memory Initialization of Integrated Memory Controller 0xB9h 1 0 1 1 1 0 0 1 Memory Initialization of Integrated Memory Controller 0xBAh 1 0 1 1 1 0 1 0 Memory Initialization of Integrated Memory Controller 0xBBh 1 0 1 1 1 0 1 1 Memory Initialization of Integrated Memory Controller 0xBCh 1 0 1 1 1 1 0 0 Memory Initialization of Integrated Memory Controller 0xBDh 1 0 1 1 1 1 0 1 Memory Initialization of Integrated Memory Controller 0xBEh 1 0 1 1 1 1 1 0 Memory Initialization of Integrated Memory Controller 0xBFh 1 0 1 1 1 1 1 1 Memory Initialization of Integrated Memory Controller PCI Bus 0x50h 0 1 0 1 0 0 0 0 Enumerating PCI buses 0x51h 0 1 0 1 0 0 0 1 Allocating resources to PCI buses 0x52h 0 1 0 1 0 0 1 0 Hot Plug PCI controller initialization 0x53h 0 1 0 1 0 0 1 1 Reserved for PCI bus 0x54h 0 1 0 1 0 1 0 0 Reserved for PCI bus 0x55h 0 1 0 1 0 1 0 1 Reserved for PCI bus

Intel® Server Board S5500WB TPS Appendix A: POST Code LED Decoder Revision 1.9 Intel order number E53971 -008 USB 0x56h 0 1 0 1 0 1 1 0 Initializing USB host controllers 0x57h 0 1 0 1 0 1 1 1 Detecting USB devices 0x58h 0 1 0 1 1 0 0 0 Resetting USB bus 0x59h 0 1 0 1 1 0 0 1 Reserved for USB devices ATA/ATAPI/SATA 0x5Ah 0 1 0 1 1 0 1 0 Resetting SATA bus and all devices 0x5Bh 0 1 0 1 1 0 1 1 Detecting the presence of ATA device 0x5Ch 0 1 0 1 1 1 0 0 Enable SMART if supported by ATA device 0x5Dh 0 1 0 1 1 1 0 1 Reserved for ATA SMBUS 0x5Eh 0 1 0 1 1 1 1 0 Resetting SMBUS 0x5Fh 0 1 0 1 1 1 1 1 Reserved for SMBUS I/O Controller Hub 0x61h 0 1 1 0 0 0 0 1 Initializing I/O Controller Hub Super I/O 0x63h 0 1 1 0 0 0 1 1 Initializing Super I/O Local Console 0x70h 0 1 1 1 0 0 0 0 Resetting the video controller (VGA) 0x71h 0 1 1 1 0 0 0 1 Disabling the video controller (VGA) 0x72h 0 1 1 1 0 0 1 0 Enabling the video controller (VGA) 0x73h 0 1 1 1 0 0 1 1 Reserved for video controller (VGA) Remote Console 0x78h 0 1 1 1 1 0 0 0 Resetting the console controller 0x79h 0 1 1 1 1 0 0 1 Disabling the console controller 0x7Ah 0 1 1 1 1 0 1 0 Enabling the console controller 0x7Bh 0 1 1 1 1 0 1 1 Reserved for console controller Keyboard (only USB) 0x90h 1 0 0 1 0 0 0 0 Resetting the keyboard 0x91h 1 0 0 1 0 0 0 1 Disabling the keyboard 0x92h 1 0 0 1 0 0 1 0 Detecting the presence of the keyboard 0x93h 1 0 0 1 0 0 1 1 Enabling the keyboard 0x94h 1 0 0 1 0 1 0 0 Clearing keyboard input buffer 0x96h 1 0 0 1 0 1 1 0 Reserved for keyboard Mouse (only USB) 0x98h 1 0 0 1 0 0 1 0 Resetting the mouse 0x99h 1 0 0 1 0 0 1 1 Detecting the mouse 0x9Ah 1 0 0 1 0 1 1 0 Detecting the presence of mouse 0x9Bh 1 0 0 1 0 1 1 1 Enabling the mouse 0x9Ch 1 0 0 1 0 0 1 0 Reserved for mouse Serial Port 0xA8h 1 0 1 0 1 0 0 0 Resetting the serial port 0xA9h 1 0 1 0 1 0 0 1 Disabling the serial port 0xAAh 1 0 1 0 1 0 1 0 Detecting the presence of the serial port 0xABh 1 0 1 0 1 0 1 1 Clearing serial port buffer 0xACh 1 0 1 0 1 1 0 0 Enabling serial port 0xADh 1 0 1 0 1 1 0 1 Reserved for serial port

Appendix A: POST Code LED Decoder Intel® Server Board S5500WB TPS Revision 1 .9 Intel order number E53971 -008 Fixed Media 0xB0h 1 0 1 1 0 0 0 0 Resetting fixed media device 0xB1h 1 0 1 1 0 0 0 1 Disabling fixed media device 0xB2h 1 0 1 1 0 0 1 0 Detecting presence of a fixed media device (SATA hard drive detection, and so forth) 0xB3h 1 0 1 1 0 0 1 1 Enabling / configuring a fixed media device 0xB4h 1 0 1 1 0 1 0 0 Reserved for fixed media Removable Media 0xB8h 1 0 1 1 1 0 0 0 Resetting removable media device 0xB9h 1 0 1 1 1 0 0 1 Disabling removable media device 0xBAh 1 0 1 1 1 0 1 0 Detecting presence of a removable media device ( SATA CDROM detection, and so forth) 0xBCh 1 0 1 1 1 1 0 0 Enabling / configuring a removable media device 0xBDh 1 0 1 1 1 1 0 1 Reserved for removable media device Boot Device Selection (BDS) 0xD0 1 1 0 1 0 0 0 0 Entered the Boot Device Selection phase (BDS) 0xD1 1 1 0 1 0 0 0 1 Return to last good boot device 0xD2 1 1 0 1 0 0 1 0 Setup boot device selection policy 0xD3 1 1 0 1 0 0 1 1 Connect boot device controller 0xD4 1 1 0 1 0 1 0 0 Attempt flash update boot mode 0xD5 1 1 0 1 0 1 0 1 Transfer control to EFI boot 0xD6 1 1 0 1 0 1 1 0 Trying to boot device selection 0xDF 1 1 0 1 1 1 1 1 Reserved for boot device selection Pre-EFI Initialization (PEI) Core 0xE0h 1 1 1 0 0 0 0 0 Entered Pre-EFI Initialization phase (PEI) 0xE1h 1 1 1 0 0 0 0 1 Started dispatching early initialization modules (PEIM) 0xE2h 1 1 1 0 0 0 1 0 Initial memory found, configured, and installed correctly 0xE3h 1 1 1 0 0 0 1 1 Transfer control to the DXE Core PEI Modules 0xF0h 1 1 1 1 0 0 0 0 Install PEIM for Platform Status Codes 0xF1h 1 1 1 1 0 0 0 1 Detecting Platform Type 0xF2h 1 1 1 1 0 0 1 0 Early Platform Initialization 0xF3h 1 1 1 1 0 0 1 1 PEI Modules initialized Driver eXecution Environment (DXE) Core 0xE4h 1 1 1 0 0 1 0 0 Entered EFI driver execution phase (DXE) 0xE5h 1 1 1 0 0 1 0 1 Started dispatching drivers 0xE6h 1 1 1 0 0 1 1 0 Started connecting drivers DXE Drivers 0xE7h 1 1 1 0 1 1 0 1 Waiting for user input 0xE8h 1 1 1 0 1 0 0 0 Checking password 0xE9h 1 1 1 0 1 0 0 1 Entering BIOS setup 0xEAh 1 1 1 0 1 1 0 0 Flash Update 0xEBh 1 1 1 0 1 1 0 1 Legacy Option ROM initialization 0xECh 1 1 1 0 1 0 0 0 DXE Drivers initialized 0xEDh 1 1 1 0 1 0 0 1 Transfer control to Boot Device Selection (BDS) 0xEEh 1 1 1 0 1 1 0 0 Calling Int 19. One beep unless silent boot is enabled. 0xEFh 1 1 1 0 1 1 0 1 Unrecoverable boot failure

Intel® Server Board S5500WB TPS Appendix A: POST Code LED Decoder Revision 1.9 Intel order number E53971 -008 Pre-EFI Initialization Module (PEIM) / Recovery 0x30h 0 0 1 1 0 0 0 0 Crisis recovery initiated because of a user request 0x31h 0 0 1 1 0 0 0 1 Crisis recovery initiated by software (corrupt flash) 0x34h 0 0 1 1 0 1 0 0 Loading crisis recovery capsule 0x35h 0 0 1 1 0 1 0 1 Handing off control to the crisis recovery capsule 0x36h 0 0 1 1 0 1 1 0 Begin crisis recovery 0x3Eh 0 0 1 1 1 1 1 0 No crisis recovery capsule detected 0x3Fh 0 0 1 1 1 1 1 1 Crisis recovery capsule failed integrity check of capsule descriptors

Whenever possible, the BIOS outputs the current boot progress codes on the video screen. progress port. The progress codes may be reported by the system BIOS or option ROMs. action or choose to continue booting. not have any effect with this error. Table 58. POST Error Messages and Handling

0012 CMOS date / time not set Major

0048 Password check failed Major

attempt to reflash the firmware.

0141 PCI resource conflict Major

0146 PCI out of resources error Major

5220 CMOS/NVRAM Configuration Cleared Major

5221 Passwords cleared by jumper Major

Intel® Server Board S5500WB TPS Appendix B: Video POST Code Errors Revision 1.9 Intel order number E53971 -008 Error Code Error Message Response

8160 Processor 01 unable to apply microcode update Major

8161 Processor 02 unable to apply microcode update Major

8180 Processor 0x microcode update not found. Minor

8190 Watchdog timer failed on last boot Major

8198 OS boot watchdog timer failure. Major

8300 Baseboard management controller failed self -test Major

84F2 Baseboard management controller failed to respond Major 84F3 Baseboard management controller in update mode Major 84F4 Sensor data record empty Major 84FF System event log full Minor 8500 Memory component could not be configured in the selected RAS mode. Major 8501 DIMM Population Error. Major 8502 CLTT Configuration Failure Error. Major 8520 DIMM_A1 failed Self Test (BIST). Major 8521 DIMM_A2 failed Self Test (BIST). Major 8522 DIMM_B1 failed Self Test (BIST). Major 8523 DIMM_B2 failed Self Test (BIST). Major 8524 DIMM_C1 failed Self Test (BIST). Major 8525 DIMM_C2 failed Self Test (BIST). Major 8526 DIMM_D1 failed Self Test (BIST). Major 8527 DIMM_D2 failed Self Test (BIST). Major 8528 DIMM_E1 failed Self Test (BIST). Major 8529 DIMM_E2 failed Self Test (BIST). Major 852A DIMM_F1 failed Self Test (BIST). Major 852B DIMM_F2 failed Self Test (BIST). Major 8540 DIMM_A1 Disabled. Major 8541 DIMM_A2 Disabled. Major 8542 DIMM_B1 Disabled. Major 8543 DIMM_B2 Disabled. Major 8544 DIMM_C1 Disabled. Major 8545 DIMM_C2 Disabled. Major 8546 DIMM_D1 Disabled. Major 8547 DIMM_D2 Disabled. Major 8548 DIMM_E1 Disabled. Major 8549 DIMM_E2 Disabled. Major 854A DIMM_F1 Disabled. Major 854B DIMM_F2 Disabled. Major 8560 DIMM_A1 Component encountered a Serial Presence Detection (SPD) fail error. Major 8561 DIMM_A2 Component encountered a Serial Presence Detection (SPD) fail error. Major 8562 DIMM_B1 Component encountered a Serial Presence Detection (SPD) fail error. Major 8563 DIMM_B2 Component encountered a Serial Presence Detection (SPD) fail error. Major 8564 DIMM_C1 Component encountered a Serial Presence Detection (SPD) fail error. Major 8565 DIMM_C2 Component encountered a Serial Presence Detection (SPD) fail error. Major 8566 DIMM_D1 Component encountered a Serial Presence Detection (SPD) fail error. Major 8567 DIMM_D2 Component encountered a Serial Presence Detection (SPD) fail error. Major

Appendix B: Video POST Code Errors Intel® Server Board S5500WB TPS Revision 1.9 Intel order number E53971 -008 Error Code Error Message Response 8568 DIMM_E1 Component encountered a Serial Presence Detection (SPD) fail error. Major 8569 DIMM_E2 Component encountered a Serial Presence Detection (SPD) fail error. Major 856A DIMM_F1 Component encountered a Serial Presence Detection (SPD) fail error. Major 856B DIMM_F2 Component encountered a Serial Presence Detection (SPD) fail error. Major 85A0 DIMM_A1 Uncorrectable ECC error encountered. Major 85A1 DIMM_A2 Uncorrectable ECC error encountered. Major 85A2 DIMM_B1 Uncorrectable ECC error encountered. Major 85A3 DIMM_B2 Uncorrectable ECC error encountered. Major 85A4 DIMM_C1 Uncorrectable ECC error encountered. Major 85A5 DIMM_C2 Uncorrectable ECC error encountered. Major 85A6 DIMM_D1 Uncorrectable ECC error encountered. Major 85A7 DIMM_D2 Uncorrectable ECC error encountered. Major 85A8 DIMM_E1 Uncorrectable ECC error encountered. Major 85A9 DIMM_E2 Uncorrectable ECC error encountered. Major 85AA DIMM_F1 Uncorrectable ECC error encountered. Major 85AB DIMM_F2 Uncorrectable ECC error encountered. Major 8604 Chipset Reclaim of non critical variables complete. Minor 9000 Unspecified processor component has encountered a non specific error. Major 9223 Keyboard component was not detected. Minor 9226 Keyboard component encountered a controller error. Minor 9243 Mouse component was not detected. Minor 9246 Mouse component encountered a controller error. Minor 9266 Local Console component encountered a controller error. Minor 9268 Local Console component encountered an output error. Minor 9269 Local Console component encountered a resource conflict error. Minor 9286 Remote Console component encountered a controller error. Minor 9287 Remote Console component encountered an input error. Minor 9288 Remote Console component encountered an output error. Minor 92A3 Serial port component was not detected Major 92A9 Serial port component encountered a resource conflict error Major 92C6 Serial Port controller error Minor 92C7 Serial Port component encountered an input error. Minor 92C8 Serial Port component encountered an output error. Minor 94C6 LPC component encountered a controller error. Minor 94C9 LPC component encountered a resource conflict error. Major 9506 ATA/ATPI component encountered a controller error. Minor 95A6 PCI component encountered a controller error. Minor 95A7 PCI component encountered a read error. Minor 95A8 PCI component encountered a write error. Minor 9609 Unspecified software component encountered a start error. Minor 9641 PEI Core component encountered a load error. Minor 9667 PEI module component encountered a illegal software state error. Fatal 9687 DXE core component encountered a illegal software state error. Fatal 96A7 DXE boot services driver component encountered a illegal software state error. Fatal 96AB DXE boot services driver component encountered invalid configuration. Minor

Intel® Server Board S5500WB TPS Appendix B: Video POST Code Errors Revision 1.9 Intel order number E53971 -008 Error Code Error Message Response 96E7 SMM driver component encountered a illegal software state error. Fatal 0xA000 TPM device not detected. Minor 0xA001 TPM device missing or not responding. Minor 0xA002 TPM device failure. Minor 0xA003 TPM device failed self test. Minor 0xA022 Processor component encountered a mismatch error. Major 0xA027 Processor component encountered a low voltage error. Minor 0xA028 Processor component encountered a high voltage error. Minor 0xA421 PCI component encountered a SERR error. Fatal 0xA500 ATA/ATPI ATA bus SMART not supported. Minor 0xA501 ATA/ATPI ATA SMART is disabled. Minor 0xA5A0 PCI Express component encountered a PERR error. Minor 0xA5A1 PCI Express component encountered a SERR error. Fatal 0xA5A4 PCI Express IBIST error. Major 0xA6A0 DXE boot services driver Not enough memory available to shadow a legacy option ROM. Minor 0xB6A3 DXE boot services driver Unrecognized. Major

Glossary Intel® Server Board S5500WB TPS Revision 1.9 Intel order number E53971 -008 100 Glossary This appendix contains important terms used in the preceding chapters. For ease of use, numeric entries are listed first (for example, ―82460GX‖) with alpha entries following (for example, ―AGP 4x‖). Acronyms are then entered in their respective place, with non-acronyms following. Table 59: Glossary Term Definition ACPI Advanced Configuration and Power Interface APIC Advanced Programmable Interrupt Control ARP Address Resolution Protocal BIOS Basic Input / Output System BIST Built-In Self Test BMC Baseboard Management Controller Bridge Circuitry connecting one computer bus to another, allowing an agent on one to access the other BSP Bootstrap Processor Byte 8-bit quantity. CATERR On a catastrophic hardware event the core signals CATERR to the uncore. The core enters a halted state that can only be exited by a reset. CBC Chassis Bridge Controller (A microcontroller connected to one or more other CBCs, together they bridge the IPMB buses of multiple chassis.) CEK Common Enabling Kit CHAP Challenge Handshake Authentication Protocol CMOS In terms of this specification, this describes the PC -AT compatible region of battery-backed 128 bytes of memory, which normally resides on the server board. DCMI Data Center Management Interface DHCP Dynamic Host Configuration Protocal DPC Direct Platform Control EEPROM Electrically Erasable Programmable Read-Only Memory EHCI Enhanced Host Controller Interface EMP Emergency Management Port EPS External Product Specification FBD Fully Buffered DIMM F MB Flexible Mother Board FRB Fault Resilient Booting FRU Field Replaceable Unit FSB Front Side Bus GB 1024 MB GPIO General Purpose I/O GTL Gunning Transceiver Logic GPA Guest Physical Address HSC Hot-Swap Controller

Intel® Server Board S5500WB TPS Glossary Revision 1.9 Intel order number E53971 -008 101 Term Definition HPA Host Physical Address Hz Hertz (1 cycle / second) I2C Inter-Integrated Circuit Bus IA Intel® Architecture IBF Input Buffer ICH I/O Controller Hub IC MB Intelligent Chassis Management Bus IFB I/O and Firmware Bridge ILM Independent Loading Mechanism IMC Integrated Memory Controller INTR Interrupt IP Internet Protocol IPMB Intelligent Platform Management Bus IPMI Intelligent Platform Management Interface IR Infrared ITP In-Target Probe KB 1024 bytes KCS Keyboard Controller Style LAN Local Area Network LCD Liquid Crystal Display LED Light Emitting Diode LPC Low Pin Count LUN Logical Unit Number MAC Media Access Control MB 1024KB ME Management Engine MD2 Message Digest 2 – Hashing Algorithm MD5 Message Digest 5 – Hashing Algorithm – Higher Security ms Milliseconds MTTR Memory Type Range Register Mux Multiplexor NIC Network Interface Controller NMI Nonmaskable Interrupt OBF Output Buffer OEM Original Equipment Manufacturer Ohm Unit of electrical resistance PECI Platform Environment Control Interface PEF Platform Event Filtering PEP Platform Event Paging PIA Platform Information Area (This feature configures the firmware for the platform hardware) PLD Programmable Logic Device PMI Platform Management Interrupt POST Power-On Self Test PSMI Power Supply Management Interface PWM Pulse-Width Modulation

Glossary Intel® Server Board S5500WB TPS Revision 1.9 Intel order number E53971 -008 102 Term Definition QPI QuickPath Interconnect RAM Random Access Memory RASUM Reliability, Availability, Serviceability, Usability, and Manageability RISC Reduced Instruction Set Computing ROM Read Only Memory RTC Real-Time Clock (Component of ICH peripheral chip on the server board) RMM3 Remote Management Module 3 SDR Sensor Data Record SECC Single Edge Connector Cartridge SEEPROM Serial Electrically Erasable Programmable Read -Only Memory SEL System Event Log SIO Server Input / Output SMBUS System Management BUS SMI Server Management Interrupt (SMI is the highest priority nonmaskable interrupt) SMM Server Management Mode SMS Server Management Software SNMP Simple Network Management Protocol TBD To Be Determined TDP Thermal Design Power TIM Thermal Interface Material UART Universal Asynchronous Receiver/Transmitter UDP User Datagram Protocol UHCI Universal Host Controller Interface URS Unified Retention System UTC Universal time coordinate UUID Universally Unique Identifier VID Voltage Identification VRD Voltage Regulator Down VT Virtualization Technology Word 16-bit quantity ZIF Zero Insertion Force

Intel® Server Board S5500WB TPS Reference Documents Revision 1.9 Intel orde r number E53971 -008 103 Reference Documents  ACPI 3.0: http://www.acpi.info/spec.htm  IPMI 2.0  Data Center Management Interface Specification v1.0, May 1, 2008: www.intel.com/go/dcmi  PCI Bus Power Management Interface Specification 1.1: http://www.pcisig.com/  PCI Express* Base Specification Rev 2.0 Dec06: http://www.pcisig.com/  PCI Express* Card Electromechanical Specification Rev 2.0: http://www.pcisig.com/  PMBus*: http://pmbus.org  SATA 2.6: http://www.sata-io.org/  SMBIOS 2.4  SSI-EEB 3.0: http://www.ssiforum.org  USB 1.1: http://www.usb.org  USB 2.0: http://www.usb.org  Windows Logo/SDG 3.0  Intel® Dynamic PowerTechnology Node Manager 1.5 External Interface Specification using IPMI, 2007. Intel Corporation. Intel Corporation.  Intel® Server System Integrated Baseboard Management Controller Core External Product Specification, 2007. Intel Corporation.  Intel® Thurley Server Platform Services IPMI Commands Specification, 2007. Intel Corporation.  Intelligent Platform Management Bus Communications Protocol Specification, Version 1.0, 1998. Intel Corporation, Hewlett-Packard Company, NEC Corporation, Dell Computer Corporation.  Platform Environmental Control Interface (PECI) Specification, Version 2.0. Intel Corporation  Platform Management FRU Information Storage Definition, Version 1.0, Revision 1.2, 2002. Intel Corporation, Hewlett-Packard Company, NEC Corporation, Dell Computer Corporation. http://developer.intel.com/design/servers/ipmi/spec.htm