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Intel® Server Products and Solutions Intel® Server Board S2600WF Product Family Technical Product Specification An overview of product features, functions, architecture, and support specifications. Rev 2.4 January 2020

Intel® Server Board S2600WF Product Family Technical Product Specification <Blank Page>

Intel® Server Board S2600WF Product Family Technical Product Specification Document Revision History Date Revision Description of Change July 2017 1.0 • Production release. October 2017 1.1

• Updated all tables from Appendix B and Appendix C.
• Updated Product Architecture Overview.
• Updated S2600WF Architecture Block Diagram. Added Intel® QAT information:
• Server Board Product Family Feature Set
• Architecture Board Diagram
• Added 6.1 section Intel® QuickAssist Technology Support
• Added S2600WFQ(R) Architecture Block Diagram November 2017 1.2
• Updated Trusted Platform Module (China version) iPC AXXTPMCHNE8 on table Intel® Server Board S2600WF product family feature set. Technologies.
• Added TPM definition on Glossary section. August 2018 1.3 • Updated Disclaimers page. Corrected wording and typos. December 2018 2.0 • Added support for 2nd Gen Intel® Xeon® processor Scalable family
• Added support for memory type Intel® Optane™ DC persistent memory module December 2018 2.1 • Updated Table 18 and Table 19 April 2019 2.2 • Removed Table 11
• Updated appropriate support hyperlinks October 2019 2.3
• Added Figure 14. Intel® Server S2600WF Product Family Sensor Position
• Added Table 4. Intel® Server S2600WF Product Family Sensor List
• Corrected section 2.4 Product Architecture Overview to include Intel® Ethernet Con- troller X722
• Corrected Table 70. Intel® Server System R2000WF product family feature set for Riser Card Support January 2020 2.4
• Updated Figures 6 and 74 – added 12V STND-BY Power LED
• Added Appendix F to include Product Regulatory Information, including EU Lot 9 product collateral support links
• Replaced all references of Intel® RSTe to Intel® VROC (SATA RAID)
• Updated on-board RAID support content in chapter 6

Intel® Server Board S2600WF Product Family Technical Product Specification Disclaimers Intel technologies’ features and benefits depend on system configuration and may require enabled hard- ware, software, or service activation. Performance varies depending on system configuration. No computer system can be absolutely secure. Check with your system manufacturer or retailer or learn more at intel.com. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of mer- chantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. Copies of documents which have an order number and are referenced in this document may be obtained by calling 1-800-548-4725 or by visiting www.intel.com/design/literature.htm. Intel, the Intel logo, Xeon, and Xeon Phi are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. *Other names and brands may be claimed as the property of others. © Intel Corporation

Intel® Server Board S2600WF Product Family Technical Product Specification Table of Contents

Intel® Server Board S2600WF Product Family Technical Product Specification

Intel® Server Board S2600WF Product Family Technical Product Specification

Intel® Server Board S2600WF Product Family Technical Product Specification

Table 12. 1st Gen Intel® Xeon® processor Scalable family traditional DDR4 SDRAM DIMM support guidelines Table 13. 2nd Gen Intel® Xeon® processor Scalable family traditional DDR4 SDRAM DIMM support guidelines Table 14. Maximum supported traditional SDRAM DIMM speeds by SKU level in MT/s (Mega Table 17. Traditional DRAM DIMM + Intel® Optane™ DC persistent memory module population configurations

ture and support specifications of the Intel® Server Board S2600WF product family. collectively referred to as the Intel® Server Board S2600WF. your local Intel representative. For more in-depth technical information, refer to the documents in Table 1. Table 1. Reference documents

Intel® Server Board S2600WF Product Family Technical Product Specification

1.1 Intel Server Board Use Disclaimer

Intel Corporation server boards support add-in peripherals and contain several high-density VLSI and power delivery components that need adequate airflow to cool. Intel ensures through its own chassis development and testing that when Intel server building blocks are used together, the fully integrated system will meet the intended thermal requirements of these components. It is the responsibility of the system integrator who chooses not to use Intel developed server building blocks to consult vendor datasheets and operating pa- rameters to determine the amount of airflow required for their specific application and operating environ- ment. Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of its published operating or non-operating limits.

1.2 Product Errata

Shipping product may have features or functionality that may deviate from published specifications. These deviations are generally discovered after the product has gone into formal production. Intel terms these de- viations as product Errata. Known product Errata will be published in the Specification Update for the given product family which can be downloaded from http://www.intel.com/support

1. Server Board Family Overview

Intel® Xeon® processor Scalable family can be identified by a product order code ending in an ‘R’. https://downloadcenter.intel.com. Figure 1. Intel® Server Board S2600WF

Figure 2. Intel® Server Board S2600WF with available onboard options

2.1 Server Board Family Feature Set

Table 2 lists the server board product family feature set. Table 2. Intel® Server Board S2600WF product family feature set

• Supports (1) or (2) processors from the 1st and 2nd Gen Intel® Xeon® processor Scalable family (Platinum, Gold, Silver, and Bronze). Note: Previous generation Intel® Xeon® processors are not supported.
• Maximum supported Thermal Design Power (TDP) of up to 205 W (board only) Note: Intel® Server Systems based on this server board family may support a lower maximum Thermal De- sign Power (TDP). See the appropriate Intel® System TPS for maximum supported TDP. Memory Support • 24 DIMM Slots (12 per CPU)
• DDR4 RDIMM/LRDIMM, Up to 2933 MT/s, 1.2V
• DDR4-compatible Intel® Optane™ DC persistent memory module, Up to 2666 MT/s, 1.2V Note: The maximum memory speed supported is dependent on the installed processor SKU and population configuration. Note: Intel® Optane™ DC persistent memory module memory is only supported in systems configured with 2nd Gen Intel® Xeon® processor Scalable family (Platinum, Gold, and select Silver SKUs) Note: Intel® Optane™ DC persistent memory module memory is only supported with Board and System products that include an ‘R’ at the end of the product order code. Intel® C62x Series Chipset Intel® C624 Chipset Intel® C624 Chipset Intel® C628 Chipset Intel® Quick Assist Technology No No Yes Intel® Omni-Path Fabric Supported Supported Supported Onboard LAN Dual Port RJ45 10 GbE No No OCP Module Support
• Dual Port 10Gb RJ45 – iPC 557T2OCPG1P5
• Dual Port SFP+ – iPC 527DA2OCPG1P5
• Quad Port 1Gb RJ45 – iPC I357T4OCPG1P5
• Quad Port SFP+ – iPC X527DA4OCPG1P5
• Dual Port 10Gb RJ45 – iPC X557T2OCPG1P5
• Dual Port SFP+ – iPC X527DA2OCPG1P5
• Quad Port 1Gb RJ45 – iPC I357T4OCPG1P5
• Quad Port SFP+ – iPC X527DA4OCPG1P5
• Dual Port 10Gb RJ45 – iPC X557T2OCPG1P5
• Dual Port SFP+ – iPC X527DA2OCPG1P5 Intel® Integrated SAS Module Supported Supported Supported Onboard PCIe* NVMe
• (4) – OCuLink connectors
• Intel® VMD support
• Intel® VROC support (acces- sory option)
• (4) – OCuLink connectors
• Intel® VMD support
• Intel® VROC support (acces- sory option)
• (2) – OCuLink connectors
• Intel® VMD support
• Intel® VROC support (accessory op- tion)

Intel® Server Board S2600WF Product Family Technical Product Specification Intel® Server Board Feature iPC - S2600WFT(R) iPC - S2600WF0(R) iPC - S2600WFQ(R) Onboard SATA • 12 x SATA 6 Gbps ports (6 Gb/s, 3 Gb/s and 1.5 Gb/s transfer rates supported) o (2) – single port 7-pin SATA connectors o (2) – M.2 connectors – SATA / PCIe* o (2) – 4-port mini-SAS HD (SFF-8643) connectors

• Embedded SATA Software RAID o Intel® VROC (SATA RAID) o Intel® Embedded Server RAID Technology 2 1.60 with op- tional RAID 5 key support
• 4 x SATA 6 Gbps ports (6 Gb/s, 3 Gb/s and 1.5 Gb/s transfer rates supported) o (2) – single port 7-pin SATA con- nectors o (2) – M.2 connectors – SATA/PCIe*
• Embedded SATA Software RAID o Intel® VROC (SATA RAID) Note: 4-port mini-SAS HD connectors are present on S2600WFQ(R) but are not configured as SATA; these cables are used only for Intel® QAT. Riser Card Concurrent support for up to three riser cards
• Riser #1 – PCIe* 3.0 x24 (CPU1 x16, CPU2 x8) – 2 and 3 slot riser card options available
• Riser #2 – PCIe* 3.0 x24 (CPU2 x24) – 2 and 3 slot riser card options available
• Riser #3 (2U systems only) – PCIe* 3.0 (CPU 2 x12) – 2 slot riser card available Video • Integrated 2D video controller
• 16MB of DDR4 video memory
• (1) – DB-15 external connector
• (1) – 14-pin internal connector for optional front panel video support USB • (3) – external USB 3.0 ports
• (1) – internal type-A USB 2.0 port
• (1) – internal 20-pin connector for optional 2x USB 3.0 port front panel support
• (1) – internal 10-pin connector for optional 2x USB 2.0 port front panel support Serial Port • (1) – external RJ-45 serial-A port connector
• (1) – internal DH-10 serial-B port header for optional front or rear serial port support Server Manage- ment
• Integrated baseboard management controller, IPMI 2.0 compliant
• Support for Intel® Server Management software
• Dedicated onboard RJ45 management port
• Advanced server management via Intel® RMM4 Lite – iPC AXXRMM4LITE2 (accessory option) Security • Trusted platform module 2.0 (Rest of World) – iPC AXXTPMENC8BPP (accessory option)
• Trusted platform module 2.0 (China Version) – iPC AXXTPMCHNE8 (accessory option) System Fan • (6) – system fans supported in two different connector formats: hot swap (2U) and cabled (1U) o (6) – 10-pin managed system fan headers (sys_fan 1-6) – used for 1U system configuration o (6) – 6-pin hot swap capable managed system fan connectors (sys_fan 1-6) – used for 2U system con- figuration

2.2 Server Board Component/Feature Identification

Figure 3. Intel® Server Board S2600WFT(R) component/feature identification Note: Some features may not be present on Intel® Server Boards S2600WF0(R) and/or S2600WFQ(R).

Figure 6. Intel® Light Guided Diagnostic – LED identification Note: See Appendix B for POST Code Diagnostic LED decoder information.

Figure 7. Board configuration and recovery jumpers For more information on reset and recovery jumpers, see Section 11.

2.3 Server Board Mechanical Drawings

Figure 8. Intel® Server Board S2600WF primary side keepout zone

Figure 9. Intel® Server Board S2600WF hole and component positions

Figure 10. Intel® Server Board S2600WF secondary side keepout zone

Figure 11. Intel® Server Board S2600WF primary side height restrictions

2.4 Product Architecture Overview

only), and the ASPEED* AST2500 baseboard management controller (BMC). each of the major sub-system components. Figure 12. Intel® Server Board S2600WF product family architectural block diagram

Figure 13. Intel® Server Board S2600WFQ(R) architectural block diagram

2.5 System Software Stack

data. Together, they configure and manage features and functions of the server system.

• IPMI watchdog timer
• Messaging support, including command bridging and user/session support
• BIOS boot flags support
• Event receiver device – The BMC receives and processes events from the BIOS.
• Serial-over-LAN (SOL)
• ACPI state synchronization – The BMC tracks ACPI state changes that are provided by the BIOS.
• Fault resilient booting (FRB) – Fault resistant boot level 2 (FRB-2) is supported by the watchdog timer functionality.

• Front panel management – The BMC controls the system status LED and chassis ID LED. It supports secure lockout of certain front panel functionality and monitors button presses. The chassis ID LED is turned on using a front panel button or a command.
• DIMM temperature monitoring – New sensors and improved acoustic management using closed-loop fan control algorithm taking into account DIMM temperature readings.
• Integrated KVM
• Integrated remote media redirection
• Intel® Intelligent Power Node Manager support
• Sensor and SEL logging additions/enhancements (e.g., additional thermal monitoring capability)
• Embedded platform debug feature, which allows capture of detailed data for later analysis by Intel A complete system software stack is pre-programmed on the server board during the board assembly pro- cess, making the server board functional at first power on. However, to ensure the most reliable system op- eration, it is highly recommended to check http://downloadcenter.intel.com for the latest available system updates. System updates can be performed in a number of operating environments, including the UEFI shell using the UEFI-only system update package (SUP), or under different operating systems using the Intel® One Boot Flash Update (Intel® OFU) utility. As part of the initial system integration process, system integrators must program system configuration data onto the server board using the FRUSDR utility to ensure the embedded platform management subsystem is able to provide the best performance and cooling for the final system configuration. The FRUSDR utility is included in the SUP and OFU packages. For additional information, see Section 2.5.2. Refer to the following Intel documents for more indepth information about the system software stack and their functions:
• Intel® Server Board S2600 Family BIOS External Product Specification – Intel NDA Required
• Intel® Server System Integrated Baseboard Management Controller (BMC) Firmware External Product Specification for Intel® Servers Systems supporting the Intel® Xeon® processor Scalable family – Intel NDA Required

2.5.1 Hot Keys Supported During POST

most cases, hot keys are recognized even while other processing is in progress. tem, BIOS supported hot keys are no longer recognized. Table 3 provides a list of available POST hot keys along with a description for each. Table 3. POST hot keys

Intel® Server Board S2600WF Product Family Technical Product Specification

2.5.1.1 POST Logo/Diagnostic Screen

If quiet boot is enabled in the BIOS setup utility, a splash screen is displayed with the standard Intel logo screen or a customized original equipment manufacturer (OEM) logo screen if one is present in the desig- nated flash memory location. By default, quiet boot is enabled in the BIOS setup utility and the logo screen is the default POST display. However, the pressing <Esc> hides the logo screen and displays the diagnostic screen instead. If a logo is not present in the BIOS flash memory space, or if quiet boot is disabled in the system configura- tion, the POST diagnostic screen is displayed with a summary of system configuration information. The POST diagnostic screen is purely a text mode screen, as opposed to the graphics mode logo screen. If console redirection is enabled in the BIOS setup utility, the quiet boot setting is disregarded and the text mode diagnostic screen is displayed unconditionally. This is due to the limitations of console redirection, which transfers data in a mode that is not graphics-compatible.

2.5.1.2 BIOS Boot Pop-Up Menu

The BIOS boot specification (BBS) provides a boot pop-up menu that can be invoked by pressing the <F6> key during POST. The BBS pop-up menu displays all available boot devices. The boot order in the pop-up menu is not the same as the boot order in the BIOS setup utility. The pop-up menu simply lists all of the available devices from which the system can be booted, and allows a manual selection of the desired boot device. When an administrator password is installed in the BIOS setup utility, the administrator password is required to access the boot pop-up menu. If a user password is entered, the user is taken directly to the boot manager in the BIOS setup utility only allowing booting in the order previously defined by the administrator.

2.5.1.3 Entering BIOS Setup

To enter the BIOS setup utility using a keyboard (or emulated keyboard), press the <F2> function key during boot time when the OEM or Intel logo screen or the POST diagnostic screen is displayed. The following instructional message is displayed on the diagnostic screen or under the quiet boot logo screen: Press <F2> to enter setup, <F6> Boot Menu, <F12> Network Boot Note: With a USB keyboard, it is important to wait until the BIOS discovers the keyboard and beeps; until the USB controller has been initialized and the keyboard activated, key presses are not read by the system. When the BIOS setup utility is entered, the main screen is displayed initially. However, if a serious error oc- curs during POST, the system enters the BIOS setup utility and displays the error manager screen instead of the main screen. For additional BIOS setup utility information, refer to Intel® Server Board S2600 Family BIOS Setup User Guide.

2.5.1.4 BIOS Update Capability

To bring BIOS fixes or new features into the system, it is necessary to replace the current installed BIOS im- age with an updated one. The BIOS image can be updated using a standalone IFLASH32 utility in the UEFI shell or using the OFU utility program under a supported operating system. Full BIOS update instructions are provided with update packages downloaded from the Intel website.

Intel® Server Board S2600WF Product Family Technical Product Specification

2.5.1.5 BIOS Recovery

If a system is unable to boot successfully to an OS, hangs during POST, or even hangs and fails to start exe- cuting POST, it may be necessary to perform a BIOS recovery procedure to replace a defective copy of the primary BIOS The BIOS provides three mechanisms to start the BIOS recovery process, which is called recovery mode:

• The recovery mode jumper causes the BIOS to boot in recovery mode.
• At power on, if the BIOS boot block detects a partial BIOS update was performed, the BIOS automati- cally boots in recovery mode.
• The BMC asserts the recovery mode general purpose input/output (GPIO) in case of partial BIOS up- date and FRB-2 timeout. The BIOS recovery takes place without any external media or mass storage device as it uses a backup BIOS image inside the BIOS flash in recovery mode. Note: The recovery procedure is included here for general reference. However, if in conflict, the instructions in the BIOS release notes are the definitive version. When the BIOS recovery jumper is set, the BIOS begins by logging a recovery start event to the system event log (SEL). It then loads and boots with a backup BIOS image residing in the BIOS flash device. This process takes place before any video or console is available. The system boots to the embedded UEFI shell, and a recovery complete event is logged to the SEL. From the UEFI shell, the BIOS can then be updated using a standard BIOS update procedure defined in update instructions provided with the system update package downloaded from the Intel website. Once the update has completed, switch the recovery jumper back to its default position and power cycle the system. If the BIOS detects a partial BIOS update or the BMC asserts recovery mode GPIO, the BIOS boots in recovery mode. The difference is that the BIOS boots up to the error manager page in the BIOS setup utility. In the BIOS Setup utility, a boot device, shell or Linux*, for example, could be selected to perform the BIOS update procedure under shell or OS environment. Note: Before attempting a recovery boot, it is highly advisable to reference the BIOS Release Notes to verify the proper recovery procedure.

2.5.2 Field Replaceable Unit (FRU) and Sensor Data Record (SDR) Data

As part of the initial system integration process, the server board/system must have the proper FRU and SDR data loaded. This ensures that the embedded platform management system is able to monitor the appropri- ate sensor data and operate the system with best cooling and performance. Once the system integrator has performed an initial FRU SDR package update, subsequent auto-configuration occurs without the need to perform additional SDR updates or provide other user input to the system when any of the following compo- nents are added or removed:

• Processor
• Memory
• OCP module
• Integrated SAS RAID module
• Power supply
• Fan
• Intel® Xeon Phi™ co-processor PCIe* card
• Hot swap backplane
• Front panel

2.5.2.1 Loading FRU and SDR Data

peripherals as shown in Figure 14 and Table 4. Figure 14. Intel® Server S2600WF Product Family Sensor Position

Table 4. Intel® Server S2600WF Product Family Sensor List

on server boards described in this document. server system product specifications to determine maximum supported processor TDP. Visit http://www.intel.com/support for a complete list of supported processors.

3.1 Processor Socket and Processor Heat Sink Module (PHM) Assembly

processor installation process. Figure 15. Processor heat sink module (PHM) components and processor socket reference diagram onto the server board.as shown in Figure 16.

top side of the processor heat sink. socket assembly. Heat sink screws should be tightened to 12 in-lbs torque. family System Integration and Service Guide. sor socket covers must be removed before processor installation (Figure 18 – B). Figure 18. Processor socket assembly and protective cover

3.2 Processor Thermal Design Power (TDP) Support

processor Scalable families TDP guidelines up to and including 205 W. its published operating or non-operating limits.

3.3 Intel® Xeon® Processor Scalable Family Overview

Figure 19. Intel® Xeon® processor Scalable generation identification Table 5. 1st Gen Intel® Xeon® processor Scalable family feature comparison

1.5 TB (select SKUs)

1.5 TB (select SKUs) 768 GB 768 GB

Table 6. 2nd Gen Intel® Xeon® processor Scalable family feature comparison

2 TB (select SKUs)

4.5 TB (select SKUs)

S2600WFQR with a 2nd Gen Intel® Xeon® Scalable processor.

• Intel® Ultra Path Interconnect (Intel® UPI) – up to 10.4 GT/s
• Intel® Speed Shift Technology
• Intel® 64 Architecture
• Enhanced Intel SpeedStep® Technology
• Intel® Turbo Boost Technology 2.0
• Intel® Hyper-Threading Technology (Intel® HT Technology)
• Intel® Virtualization Technology (Intel® VT-x)
• Intel® Virtualization Technology for Directed I/O (Intel® VT-d)
• Execute Disable Bit
• Intel® Trusted Execution Technology (Intel® TXT)

Intel® Server Board S2600WF Product Family Technical Product Specification

• Intel® Advanced Vector Extensions (Intel® AVX-512)
• Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI) 2nd Gen-only core features:
• Intel® Deep Learning through VNNI
• Intel® Speed Select Technology on select processor SKUs
• Intel® Resource Director Technology The processor uncore features and technologies include:
• Up to 48 PCIe* lanes 3.0 lanes per CPU – 79GB/s bi-directional pipeline
• 6 DDR4 memory channels supported per CPU
• On-package integration of next generation Intel® Omni-Path Fabric Controller – select 1st Gen proces- sor SKUs only.
• DMI3/PCIe* 3.0 interface with a peak transfer rate of 8.0 GT/s
• Non-transparent bridge (NTB) enhancements – 3 full duplex NTBs and 32 MSI-X vectors
• Intel® Volume Management Device (Intel® VMD) – manages CPU attached NVMe* SSDs
• Intel® QuickData Technology
• Support for Intel® Node Manager 4.0 2nd Gen-only uncore features:
• Intel® Optane™ DC persistent memory module support

3.3.1 Supported Technologies

3.3.1.1 Intel® 64 Instruction Set Architecture

64-bit memory extensions to the IA-32 architecture. Further details on Intel 64 architecture and programming model can be found at http://developer.intel.com/technology/intel64/.

3.3.1.2 Intel® Hyper-Threading Technology (Intel® HT Technology)

The processor supports Intel® HT Technology, which allows an execution core to function as two logical pro- cessors. While some execution resources such as caches, execution units, and buses are shared, each logical processor has its own architectural state with its own set of general-purpose registers and control registers. This feature must be enabled via the BIOS and requires operating system support.

3.3.1.3 Enhanced Intel SpeedStep® Technology

Processors in the 1st and 2nd generaton Intel® Xeon® processor Scalable families support Enhanced Intel SpeedStep® Technology. The processors support multiple performance states, which allows the system to dynamically adjust processor voltage and core frequency as needed to enable decreased power consump- tion and decreased heat production. All controls for transitioning between states are centralized within the processor, allowing for an increased frequency of transitions for more effective operation. The Enhanced Intel SpeedStep Technology feature may be enabled/disabled by an option on the Processor Configuration Setup screen. By default Enhanced Intel SpeedStep Technology is enabled. If Enhanced Intel SpeedStep Technology is disabled, then the processor speed is set to the processor’s maximum TDP core frequency (nominal rated frequency). 3.3.1.4 Intel® Turbo Boost Technology 2.0 Intel® Turbo Boost Technology is featured on all processors in the 1st and 2nd Gen Intel® Xeon processor Scalable families. Intel Turbo Boost Technology opportunistically and automatically allows the processor to run faster than the marked frequency if the processor is operating below power, temperature, and current limits. This results in increased performance for both multi-threaded and single-threaded workloads.

Intel® Server Board S2600WF Product Family Technical Product Specification

3.3.1.5 Intel® Virtualization Technology (Intel® VT-x)

Intel® Virtualization Technology (Intel® VT-x) provides hardware support in the core to improve performance and robustness for virtualization. Intel VT-x specifications and functional descriptions are included in the In- tel 64 and IA-32 Architectures Software Developer’s Manual.

3.3.1.6 Intel® Virtualization Technology for Directed I/O (Intel® VT-d)

Intel® Virtualization Technology for Directed I/O (Intel® VT-d) provides hardware support in the core and un- core implementations to improve I/O virtualization performance and robustness.

3.3.1.7 Execute Disable Bit

Execute Disable Bit functionality can help prevent certain classes of malicious buffer overflow attacks when combined with a supporting operating system. This allows the processor to classify areas in memory by where application code can execute and where it cannot. When malicious code attempts to insert code in the buffer, the processor disables code execution, preventing damage and further propagation.

3.3.1.8 Intel® Trusted Execution Technology for servers (Intel® TXT)

Intel® TXT defines platform-level enhancements that provide the building blocks for creating trusted plat- forms. The Intel TXT platform helps to provide the authenticity of the controlling environment such that those wishing to rely on the platform can make an appropriate trust decision. The Intel TXT platform deter- mines the identity of the controlling environment by accurately measuring and verifying the controlling soft- ware.

3.3.1.9 Intel® Advanced Vector Extensions 512 (Intel AVX-512)

The base of the 512-bit single instruction multiple data (SIMD) instruction extensions are referred to as Intel® AVX-512 foundation instructions. They include extensions of the Intel® Advanced Vector Extensions (Intel® AVX) family of SIMD instructions but are encoded using a new scheme with support for 512-bit vector registers, up to 32 vector registers in 64-bit mode, and conditional processing using opmask registers.

3.3.1.10 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)

Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI) is a set of instructions implemented in all processors in the Intel® Xeon® processor Scalable family. This feature adds AES instructions to accelerate encryption and decryption operations used in the Advanced Encryption Standard. The Intel AES-NI feature includes six additional SIMD instructions in the Intel® Streaming SIMD Extensions (Intel® SSE) instruction set. The BIOS is responsible in POST to detect whether the processor has the Intel AES-NI instructions available. Some processors may be manufactured without Intel AES-NI instructions. The Intel AES-NI instructions may be enabled or disabled by the BIOS. Intel AES-NI instructions are enabled unless the BIOS has explicitly disabled them. 3.3.1.11 Intel® Intelligent Power Node Manager 4.0 The Intel® ME on the Intel® C620 series chipset supports Intel® Intelligent Power Node Manager technology. The Intel ME/Intel® Node Manager (Intel® NM) combination is a power and thermal control capability on the platform, which exposes external interfaces that allow IT (through external management software) to query the Intel ME about platform power capability and consumption, thermal characteristics, and specify policy directives (that is, set a platform power budget). Intel ME enforces these policy directives by controlling the power consumption of underlying subsystems using available control mechanisms (such as processor P/T states). The determination of the policy directive is done outside of Intel ME either by intelligent manage- ment software or by the IT operator. Below are the some of the applications of Intel Intelligent Power Node Manager technology:

Intel® Server Board S2600WF Product Family Technical Product Specification

• Platform power monitoring and limiting – The Intel ME/Intel NM monitors platform power con- sumption and holds average power over duration. It can be queried to return actual power at any given instance. The power limiting capability is to allow external management software to address key IT issues by setting a power budget for each server.
• Inlet air temperature monitoring – The Intel ME/Intel NM monitors server inlet air temperatures peri- odically. If there is an alert threshold in effect, then Intel ME/Intel NM issues an alert when the inlet (room) temperature exceeds the specified value. The threshold value can be set by policy.
• Memory subsystem power limiting – The Intel ME/Intel NM monitors memory power consumption. Memory power consumption is estimated using average bandwidth utilization information.
• Processor power monitoring and limiting – The Intel ME/Intel NM monitors processor or socket power consumption and holds average power over duration. It can be queried to return actual power at any given instant. The monitoring process of the Intel ME is used to limit the processor power con- sumption through processor P-states and dynamic core allocation.
• Core allocation at boot time – Restrict the number of cores for OS/VMM use by limiting how many cores are active at boot time. After the cores are turned off, the CPU limits how many working cores are visible to the BIOS and OS/VMM. The cores that are turned off cannot be turned on dynamically after the OS has started. It can be changed only at the next system reboot.
• Core allocation at run-time – This particular use case provides a higher level processor power con- trol mechanism to a user at runtime, after booting. An external agent can dynamically use or not use cores in the processor subsystem by requesting Intel ME/Intel NM to control them, specifying the number of cores to use or not use. For additional information, visit https://www.intel.com/content/www/us/en/data-center/data-center-man- agement/techrefresh-info-nodemanagerfull.html.

3.3.1.12 Trusted Platform Module (TPM)

Trusted Platform Module is bound to the platform and connected to the PCH via the LPC bus or SPI bus. The TPM provides the hardware-based mechanism to store or ‘seal’ keys and other data to the platform. It also provides the hardware mechanism to report platform attestations

3.3.1.13 Intel® Deep Learning Boost

Intel® Deep Learning Boost on the 2 nd Gen Intel® Xeon® processor Scalable family is designed to deliver more efficient Deep Learning (Inference) acceleration by expanding the capabilities of Intel® AVX-512 through In- tel® Vector Neural Network Instructions (VNNI) dedicated to Deep Learning tasks. Consult the Intel® 64 and IA-32 Architectures Software Developer’s Manual for details.

3.3.1.14 Intel® Speed Select Technology

Intel® Speed Select Technology, available on select 2nd Gen Intel® Xeon® processor Scalable family SKUs, of- fers three distinct operating voltage-frequency points for guaranteed base frequency (P1). This frequency is based on the number of active cores within the SKU only when thermal requirements are met. Intel® Speed Select Technology allows either a higher active core count with lower base frequency or a lower active core count with higher base frequency, providing multiple CPU personalities based on workload/VM needs.

Figure 20. Intel® Speed Select Technology comparison

3.3.1.15 Intel® Resource Director Technology

• Cache Monitoring Technology (CMT): monitors LLC (L3 cache) usage by each software thread, through Resource Monitoring ID (RMID).
• Code Data Prioritization (CDP): provides the capability to separate code from data in LLC using masks.
• Memory Bandwidth Monitoring (MBM): gives the OS/VMM the abilities of assigning RMID to software threads and read the memory bandwidth utilization for a given RMID.
• Memory Bandwidth Allocation (MBA): MBA is a new feature introduced in 2nd Gen Intel® Xeon® pro- cessor Scalable family that enables software to control the amount of memory bandwidth a thread or core can consume based on credits.

3.3.1.16 Intel® Optane™ DC Persistent Memory Module

• Volatile memory – Memory Mode
• Persistent memory for select applications – App Direct mode
• Both operation modes simultaneously – Mixed mode See section 4.1.1 Intel® Optane™ DC Persistent Memory Module Overview for additional information.

3.3.2 Intel® Xeon® Processor Scalable Family with Integrated Intel® Omni-Path Fabric

Path Host Fabric Interface (Intel® OP HFI) connector. Table 7. Intel® Xeon® processor Scalable family with integrated Intel® OP HFI features 25 Gbps, providing 100 Gbps of bandwidth in a single direction. Figure 21. Intel® OP HFI connector location

Figure 22. Multi-chip package (MCP) Figure 23. Dual processor configurations with one or two fabric processors

3.3.3 Intel®Omni-Path IFT Carrier Accessory Kits

(AWF1PFABKITM and AWF1PFABKITP).

• Mezannine – Mounted directly to the server board in the designated OCP module mounting location.
• PCIe add-in card – Installed to any available riser slot 2 PCIe add-in slot.

Figure 24. Intel® Omni-Path IFT Carrier Accessory Kit components server board. The sideband connectors are shown in Figure 25.

• The base SKU number of both processor types must be the same. o Example: Intel® Xeon® Platinum 8160F (Intel OP HFI) + Intel Xeon Platinum 8160 (non-fabric) o Example: Intel Xeon Gold 6140F (Intel OP HFI) + Intel Xeon Gold 6140F (Intel OP HFI) There is no restriction on which processor socket is populated with the fabric processor and which processor socket is populated with the matching non-fabric processor.

Table 10. Supported processor mixing – fabric vs non-fabric processors

3.4 Processor Population Rules

tical processors be installed.

• Both processors must have the same number of cores.
• Both processors must have the same cache sizes for all levels of processor cache memory.
• Both processors must support identical DDR4 memory frequencies.
• Both processors must have identical extended family, extended model, processor type, family code and model number.
• Processors with FPGA and processors with Intel® Omni-Path Fabric cannot be mixed. Processors with different core frequencies can be mixed in a system, given that the prior rules are met. If this condition is detected, all processor core frequencies are set to the lowest common denominator (highest common speed) and an error is reported. Processor stepping within a common processor family can be mixed as long as it is listed in the processor specification updates published by Intel. Mixing of steppings is only validated and supported between pro- cessors that are plus or minus one stepping from each other.

3.5 Processor Initialization Error Summary

• Fatal: If the system cannot boot, POST halts and display the following message: Unrecoverable fatal error found. System will not boot until the error is resolved Press <F2> to enter setup When the <F2> key on the keyboard is pressed, the error message is displayed on the error manager screen and an error is logged to the system event log (SEL) with the POST error code. The “POST Error Pause” option setting in the BIOS setup does not have any effect on this error. If the system is not able to boot, the system generates a beep code consisting of three long beeps and one short beep. The system cannot boot unless the error is resolved. The faulty component must be replaced. The system status LED is set to a steady amber color for all fatal errors that are detected during pro- cessor initialization. A steady amber system status LED indicates that an unrecoverable system failure condition has occurred.
• Major: An error message is displayed to the error manager screen and an error is logged to the SEL. If the BIOS setup option “Post Error Pause” is enabled, operator intervention is required to continue booting the system. If the BIOS setup option “POST Error Pause” is disabled, the system continues to boot.
• Minor: An error message may be displayed to the screen or to the BIOS setup error manager and the POST error code is logged to the SEL. The system continues booting in a degraded state. The user may want to replace the erroneous unit. The “POST Error Pause” option setting in the BIOS setup does not have any effect on this error.

Table 11. Mixed processor configurations error summary

• Halts at POST code 0xE6.
• Halts with three long beeps and one short beep.
• Takes fatal error action (see above) and does not boot until the fault condition is remedied. Processor model not identical Fatal
• Logs the POST error code into the SEL.
• Alerts the BMC to set the system status LED to steady amber.
• Displays 0196: Processor model mismatch detected message in the error manager.
• Takes fatal error action (see above) and does not boot until the fault condition is remedied. Processor cores/threads not identical Fatal
• Halts at POST code 0xE5.
• Halts with three long beeps and one short beep.
• Takes fatal error action (see above) and does not boot until the fault condition is remedied. Processor cache or home agent not identical Fatal
• Halts at POST code 0xE5.
• Halts with three long beeps and one short beep.
• Takes fatal error action (see above) and does not boot until the fault condition is remedied.

Intel® Server Board S2600WF Product Family Technical Product Specification Error Sever- ity System Action when BIOS Detects the Error Condition Processor fre- quency (speed) not identical Fatal If the frequencies for all processors can be adjusted to be the same:

• Adjusts all processor frequencies to the highest common frequency.
• Does not generate an error – this is not an error condition.
• Continues to boot the system successfully. If the frequencies for all processors cannot be adjusted to be the same:
• Logs the POST error code into the SEL.
• Alerts the BMC to set the system status LED to steady amber.
• Does not disable the processor.
• Displays 0197: Processor speeds unable to synchronize message in the error manager.
• Takes fatal error action (see above) and does not boot until the fault condition is remedied Processor Intel® UPI link fre- quencies not iden- tical Fatal If the link frequencies for all Intel® Ultra Path Interconnect (Intel® UPI) links can be adjusted to be the same:
• Adjusts all Intel UPI interconnect link frequencies to highest common frequency.
• Does not generate an error – this is not an error condition.
• Continues to boot the system successfully. If the link frequencies for all Intel UPI links cannot be adjusted to be the same:
• Logs the POST error code into the SEL.
• Alerts the BMC to set the system status LED to steady amber.
• Does not disable the processor.
• Displays 0195: Processor Intel(R) UPI link frequencies unable to synchronize message in the error manager.
• Takes fatal error action (see above) and does not boot until the fault condition is remedied. Processor micro- code update failed Major
• Logs the POST error code into the SEL.
• Displays 816x: Processor 0x unable to apply microcode update message in the error manager or on the screen.
• Takes major error action. The system may continue to boot in a degraded state, depending on the “POST Error Pause” setting in setup, or may halt with the POST error code in the error manager waiting for operator intervention. Processor micro- code update miss- ing Minor
• Logs the POST error code into the SEL.
• Displays 818x: Processor 0x microcode update not found message in the error manager or on the screen.
• The system continues to boot in a degraded state, regardless of the “POST Error Pause” set- ting in setup.

memory population rules, and supported memory reliability, accessibility, and serviceability (RAS) features.

4.1 Memory Subsystem Architecture

Figure 27. Memory subsystem architecture

• DDR4 compatible DIMMs only
• Error Correction Code (ECC) enabled Registered DIMMs (RDIMMs), Load-Reduced DIMMs (LRDIMMs), or Non-Volatile Dual Inline Memory Module (NVDIMMs) are supported
• RDIMMs and LRDIMMs with integrated Thermal Sensor On Die (TSOD) only
• Traditional SDRAM DIMMs organized as Single Rank (SR), Dual Rank (DR), Quad Rank (QR), or Oct-Rank (8R) o RDIMMS – Registered DIMMS – SR/DR/QR/8R, ECC only o LRDIMMs – Load Reduced DIMMs – QR/8R, ECC only o Maximum of 8 logical ranks per channel o Maximum of 10 physical ranks loaded on a channel
• Intel® Optane™ DC persistent memory module - Supported with 2nd Gen Intel® Xeon® processor Scalable family (Platinum, Gold, and select Silver processor Scalable SKUs)

Figure 28. Visual differentiation of traditional SDRAM DIMM and Intel® Optane™ DC persistent memory module

Intel® Server Board S2600WF Product Family Technical Product Specification

4.1.1 Intel® Optane™ DC Persistent Memory Module Overview

The 2nd Gen Intel® Xeon® processor Scalable family introduces support for memory type Intel® Optane™ DC persistent memory module. Intel® Optane™ DC persistent memory module enables higher density (capacity per DIMM) DDR4-compatible memory modules with near-DRAM performance and advanced features not found in traditional SDRAM. Note: Use of memory type Intel® Optane™ DC persistent memory module is only supported when the follow- ing are true:

• Server board or System product order codes ends with an ‘R’
• Installed processor(s) are 2nd Gen Intel® Xeon® processor Scalable family Note: Server Boards and Systems that have non-(R) product codes but have had the system software up- dated to support 2nd Gen Intel® Xeon® processor Scalable family, are not equivalent to server boards and systems with product codes ending in (R). Server Boards and Systems with non-(R) product codes do NOT have support for memory type Intel® Optane™ DC persistent memory module DIMMs. Intel® Optane™ DC persistent memory module supports the following features:
• Always-enabled AES-256 encryption
• Cache coherent: like DRAM, contains evicted information from the LLC
• Byte-addressable memory
• Higher endurance than enterprise class SSDs Intel® Optane™ DC persistent memory module supports the following operating modes:
• Memory Mode
• App Direct mode
• Mixed mode App Direct and Mixed modes require both driver and explicit software support. For more information con- cerning OS compatibility, visit support.intel.com.

4.1.1.1 Intel® Optane™ DC Persistent Memory Module - Memory Mode (MM)

In Memory Mode (MM), Intel® Optane™ DC Persistent Memory works as the main large volatile (non-persis- tent) system memory. While in Memory Mode, all available traditional DRAM within the same memory con- troller functions as the write-back L4 cache for Intel® Optane™ DC persistent memory module. This lowers the cost of total system memory capacity versus only traditional DRAM while maintaining near-DRAM perfor- mance.

4.1.1.2 Intel® Optane™ DC Persistent Memory Module - App Direct (AD) Mode

App Direct (AD) mode allows Intel® Optane™ DC persistent memory module to work as persistent memory, maintaining data integrity while power is lost for applications while sustaining near-DRAM performance. While in App Direct mode, DRAM operates as normal system memory and Intel® Optane™ DC persistent memory module functions as application storage.

4.1.1.3 Intel® Optane™ DC Persistent Memory Module - Mixed Mode

Mixed mode allows partial use of Intel® Optane™ DC persistent memory module’s capacity to work as a large pool of volatile system memory, and for the remaining capacity to work as persistent memory for applica- tions with near-DRAM performance. The capacity dedicated to volatile system memory must meet the Memory Mode population criteria, and any remaining capacity will be available as persistent memory for ap- plication storage and must be supported by the OS, driver, and application.

4.2 Supported Memory

Table 12. 1st Gen Intel® Xeon® processor Scalable family traditional DDR4 SDRAM DIMM support guide-

2 Slots per Channel

Table 14. Maximum supported traditional SDRAM DIMM speeds by SKU level in MT/s (Mega transfers/second)

2 Only in 1DPC configuration

Table 15. Intel® Optane™ DC persistent memory module support guidelines

3 Supported on select Silver processor SKUs

4.3 General Support Rules for Memory

tems that are configured with identical DIMMs installed. nels/CPU, 2 DIMMs/Channel. Figure 29 identifies all DIMM slots on the server board. Figure 29. Intel® Server Board S2600WF memory slot layout

• Each installed processor provides six channels of memory. Memory channels from each processor are identified as Channels A – F.
• Each memory channel supports two DIMM slots, identified as slots 1 and 2. o On the server board, each DIMM slot is labeled by CPU #, memory channel, and slot # such as CPU1_DIMM_A2 and CPU2_DIMM_A2.

Intel® Server Board S2600WF Product Family Technical Product Specification

• DIMM population rules require that DIMMs within a channel be populated starting with the blue DIMM slot or DIMM farthest from the processor in a “fill-farthest” approach.
• When only one DIMM is used for a given memory channel, it must be populated in the blue DIMM slot (furthest from the CPU).
• Mixing of DDR4 DIMM types (RDIMM, LRDIMM, 3DS RDIMM, 3DS LRDIMM) within or across processor sockets produces a Fatal Error Halt during memory initialization.
• Mixing DIMMs of different frequencies and latencies is not supported within or across processor sock- ets. If a mixed configuration is encountered, the BIOS attempts to operate at the highest common fre- quency and the lowest latency possible.
• When populating a quad-rank DIMM with a single- or dual-rank DIMM in the same channel, the quad- rank DIMM must be populated farthest from the processor. Incorrect DIMM placement results in an MRC error code. A maximum of 8 logical ranks can be used on any one channel, as well as a maximum of 10 physical ranks loaded on a channel.
• The memory slots associated with a given processor are unavailable if the corresponding processor socket is not populated.
• A processor may be installed without populating the associated memory slots, provided a second processor is installed with associated memory. In this case, the memory is shared by the processors. However, the platform suffers performance degradation and latency due to the remote memory.
• Processor sockets are self-contained and autonomous. However, all memory subsystem support (such as memory RAS and error management) in the BIOS setup are applied commonly across pro- cessor sockets.
• For multiple DIMMs per channel: o For RDIMM, LRDIMM, 3DS RDIMM, 3DS LRDIMM; always populate DIMMs with higher electrical loading in slot1, followed by slot 2.
• For best system performance in dual processor configurations, installed DIMM type and population for DIMMs configured to CPU2 must match DIMM type and population configured to CPU1. See sec- tion 4.3.1 for additional information. Intel® Optane™ DC persistent memory module-specific rules – All operating modes:
• Support for Intel® Optane™ DC persistent memory module is only available with 2nd Gen Intel® Xeon® processor Scalable family installed
• Support for Intel® Optane™ DC persistent memory module is only available on server boards and sys- tems with product codes ending in “R”.
• Only one Intel® Optane™ DC persistent memory module is supported per memory channel.
• Intel® Optane™ DC persistent memory modules of different capacities can’t be mixed within or across processor sockets.
• Memory slots supported by integrated memory controller IMC0 (memory channels A-C) of a given processor must be populated before memory slots supported by integrated memory channel IMC1 (memory channels D-F)
• When both DIMM slots within a channel are populated, Intel® Optane™ DC persistent memory mod- ules are only supported in the black DIMM slots.
• System configurations with Intel® Optane™ DC persistent memory modules installed only to memory channels A-C of a given processor, is supported
• No traditional SDRAM SRx8 DIMM is supported in conjunction with Intel® Optane™ DC persistent memory module in any operating mode. Intel® Optane™ DC persistent memory module-specific rules – Memory mode:
• Minimum one DRAM DIMM and one Intel® Optane™ DC persistent memory module per integrated memory controller (IMC0 & IMC1) of a given processor
• Populate DRAM across all available memory channels to maximize bandwidth

• Minimum one DRAM DIMM per integrated memory controller (IMC0 & IMC1) for each installed pro- cessor
• Minimum one Intel® Optane™ DC persistent memory module installed to any supported DIMM slot (per defined rules)

4.3.1 DIMM Population Guidelines

DIMMs configured to CPU2 must match DIMM type and population configured to CPU1. Figure 30. Intel® Server Board S2600WF product family memory channel assignment Table 16. Traditional DRAM DIMM-only population configurations

12 DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM

1 Configuration not recommended. This is an unbalanced configuration which will yield less than optimal performance.

Table 18. Supported DRAM types

DRAM1 and DRAM2 types in Table 18 must meet the specifications listed in Table 19. Table 19. Traditional DRAM DIMMs compatible with Intel® Optane™ persistent memory module

• For MM, general DRAM/DC persistent memory module ratio is between 1:4 and 1:16. Excess capacity for DC persistent memory module can be used for AD.
• For each individual population, rearrangements between channels are allowed as long as the result- ing population is consistent to defined memory population rules.
• For each individual population, the same DDR4 DIMM has to be used in all slots as specified by the defined memory ppulation rules.
• For each individual population, sockets are normally symmetric with exceptions for 1 DC persistent memory module per socket and 1 DC persistent memory module per node case.

4.4 Memory RAS Features

features as defined in Table 20. Table 20. Memory RAS features

Intel® Server Board S2600WF Product Family Technical Product Specification DDR4 Command/Address Parity Check and Retry DDR4 Command/Address Parity Check and Retry: Is a DDR4 technology based CMD/ADDR parity check and retry with following attributes:

• CMD/ADDR Parity error “address“ logging
• CMD/ADDR Retry √ √ DDR4 Write Data CRC Protec- tion DDR4 Write Data CRC Protection detects DDR4 data bus faults dur- ing write operation. √ √ Memory Demand and Patrol Scrubbing Demand scrubbing is the ability to write corrected data back to the memory once a correctable error is detected on a read transaction. Patrol scrubbing proactively searches the system memory, repairing correctable errors. Prevents accumulation of singlebit errors. √ √ Memory Mirroring Full Memory Mirroring: An intra IMC method of keeping a duplicate (secondary or mirrored) copy of the contents of memory as a redun- dant backup for use if the primary memory fails. The mirrored copy of the memory is stored in memory of the same processor socket's IMC. Dynamic (without reboot) failover to the mirrored DIMMs is transparent to the OS and applications. √ √ Address Range/Partial Memory Mirroring: Provides further intra socket granularity to mirroring of memory by allowing the firmware or OS to determine a range of memory addresses to be mirrored, leaving the rest of the memory in the socket in non-mirror mode. Sparing
• Rank Level Memory Spar- ing
• Multi-rank Level Memory Sparing Dynamic fail-over of failing Ranks to spare Ranks behind the same memory controller DDR ranks. √ √ With Multi Rank up to two ranks out of a maximum of eight ranks can be assigned as spare ranks. √ √ iMC’s Corrupt Data Contain- ment Corrupt Data Containment is a process of signaling error along with the detected UC data. iMC's patrol scrubber and sparing engine have the ability to poison the UC data. √ √ Failed DIMM Isolation Ability to identify a specific failing DIMM thereby enabling the user to replace only the failed DIMM(s). In case of uncorrected error and lockstep mode, only DIMM-pair level isolation granularity is sup- ported. √ √ Memory Disable and Map Out for FRB Allows memory initialization and booting to OS even when memory fault occurs. √ √ Post Package Repair Starting with DDR4 technology there is an additional capability available known as PPR (Post Package Repair). PPR offers additional spare capacity within the DDR4 DRAM that can be used to replace faulty cell areas detected during system boot time. √ √ Note: RAS features may not be supported on all SKUs of a processor type.

4.4.1 DIMM Populations Rules and BIOS Setup for Memory RAS

• Memory sparing and memory mirroring options are enabled in BIOS setup.
• Memory sparing and memory mirroring options are mutually exclusive. Only one operating mode may be selected in BIOS setup.
• If a RAS mode has been enabled, and the memory configuration is not able to support it during boot, the system will fall back to independent channel mode and log and display errors.
• Rank sparing mode is only possible when all channels that are populated with memory that meet the reaquirement of having at least two single-rank or double-rank DIMMs installed, or at least one quad- rank DIMM installed, on each populated channel.
• Memory mirroring mode requires that for any channel pair that is populated with memory, the memory population on both channels of the pair must be identically sized.

**Table 21. CPU - PCIe* port routing**

5.1.1 PCIe* Enumeration and Allocation

tion, Revision 3.0. The bus number is incremented when the BIOS encounters a PCI-PCI bridge device. Scanning continues on the secondary side of the bridge until all subordinate buses are assigned numbers. never change during the pre-boot phase. manually configure the IRQs for devices.

5.1.2 Non-Transparent Bridge

Intel® Server Board S2600WF Product Family Technical Product Specification 6. System I/O The server board input/output features are provided via the embedded features and functions of several onboard components including: the Integrated I/O Module (IIO) of the Intel® Xeon® processor, the Intel® C620 series chipset (PCH), and the I/O controllers embedded within the Aspeed* AST2500 management controller. See Figure 12 for an overview of the features and interconnects of each of the major sub-system components. Server board I/O features include:

• Intel® QuickAssist Technology (Intel® QAT) support (S2600WFQ(R) only)
• PCIe* riser card and add-in card support
• Intel® Ethernet Network Adapter for OCP* support
• Intel® Integrated RAID Module support
• Onboard storage subsystem
• External I/O port support

6.1 Intel® QuickAssist Technology (Intel® QAT) Support

This section provides a high level overview for Intel QAT and its support on the Intel® Server Board S2600WF product family. For more information about this technology, visit http://www.intel.com/con- tent/www/us/en/embedded/technology/quickassist/overview.html. Note: For the Intel Server Board S2600WF product family, only the S2600WFQ(R) SKU supports Intel QAT. Intel QAT provides security and compression acceleration capabilities used to improve performance and effi- ciency across the data center. Intel QAT supports the following:

• Cryptographic capabilities: 100 Gb/s IPSec & SSL o Symmetric ciphers: (AES, AES-XTS, 3DES/DES, RC4, Kasumi, Snow3G, ZUC) o Message digest/hash (MD5, SHA1, SHA2, SHA3) o Authentication (HMAC, AES-XCBC) o Authenticated encryption (AES-GCM, AES-CCM)
• Asymmetric (public key) cryptographic capabilities o Modular exponentiation for Diffie-Hellman (DH) o RSA key generation, encryption/decryption and digital signature generation/verification. RSA(2K Keys) up to 100K Ops/sec o DSA parameter generation and digital signature generation/verification o Elliptic curve cryptography: ECDSA, ECDH
• Compression/decompression (deflate) up to 100Gb/s On the Intel Server Board S2600WFQ(R), there are three Intel QAT engines incorporated into the Intel C628 chipset with a dedicated x16 PCIe* 3.0 link that allows for up to 100 Gbps aggregated bandwidth. Intel QAT bandwidth can be increased to 150 Gbps with the addition of an optional Intel QAT bridge cable connected between the onboard mini-SAS HD connectors for SATA Ports 0-3 and 4-7, and two of the onboard PCIe x4 OCuLink connectors as shown in Figure 32.

Figure 32. Intel® QAT cable loadcenter.intel.com to download the latest available drivers.

6.2 PCIe* Add-in Card Support

The server board provides three riser card slots identified as: Riser Slot #1, Riser Slot #2, and Riser Slot #3. provide the PCIe* bus routing for all supported risers cards. bottom add-in card slot for 2U riser cards installed in Riser Slot #1.

**Figure 33. PCIe* add-in card support** **Table 22. Riser slot #1 PCIe* root port mapping** **Table 23. Riser slot #2 PCIe* root port mapping** **Table 24. Riser slot #3 PCIe* root port mapping** Top CPU #2 – DMI x4 (x4 elec, x8 mech) Low profile cards only. Bottom CPU #2 – Ports 3C and 3D (x8 elec, x8 mech) Low profile cards only.

6.2.1 Riser Slot #1 and Riser Slot #2 Riser Card Options

riser slots #1 and #2 are common between the two slots.

½ length add-in card (bottom slot). **Figure 36. 2U two-slot PCIe* riser card (iPC – A2UL16RISER2)** **Table 27. Two-slot PCIe* riser card slot description**

6.2.2 Riser Slot #3 Riser Card Option (iPC – A2UX8X4RISER)

Riser slot #3 is provided to support up to two additional PCIe add-in card slots for 2U server configurations. The available riser card option is designed to support low profile add-in cards only. Figure 37. Low profile riser card (iPC – A2UX8X4RISER) Table 28. Low profile riser card slot description

6.2.3 Intel® Ethernet Network Adapter for OCP* Support

server board, as shown in Figure 38. **Figure 38. Intel® Ethernet Network Adapter for OCP* connector** Table 29. Supported Intel® Ethernet Network Adapters for OCP*

6.2.4 Intel® Integrated RAID Module Support

nector labeled “SAS Module” on the server board. Figure 39. Intel® Integrated RAID module https://serverconfigurator.intel.com.

6.3 Onboard Storage Subsystem

• (2) – M.2 PCIe*/SATA
• (4) – PCIe* OCuLink
• Intel® Volume Management Device (Intel® VMD) for NVMe*
• Intel® VROC (VMD NVMe RAID) 6.0
• (2) – 7-pin single port SATA
• (2) – Mini-SAS HD (SFF-8643) 4-port SATA (S2600WFT(R) and S2600WF0(R) boards only)
• Onboard SATA RAID aptions o Intel® VROC (SATA RAID) 6.0 o Intel® Embedded Server RAID Technology 2 (Intel® ESRT2) v1.60 for SATA The following sections provide an overview of each option. 6.3.1 M.2 SSD Support The Intel Server Board S2600WF product family includes two M.2 SSD connectors labeled “M2_x4PCIE/sSATA_1” and “M2_x2PCIE/sSATA_2” on the server board as shown in Figure 40. Intel® Integrated SAS RAID Module

Figure 40. M.2 storage device connectors Each M.2 connector can support PCIe or SATA modules that conform to a 2280 (80 mm) form factor. lanes and sSATA-2 from the chipset embedded sSATA controller.

6.3.1.1 Embedded RAID Support

• Neither Intel® ESRT2 nor Intel® VROC (SATA RAID) have RAID support for PCIe M.2 SSDs when in- stalled to the M.2 connectors on the server board. Note: NVMe RAID support using Intel® VROC (SATA RAID) and Intel VROC requires that the PCIe bus lanes be routed directly from the CPU. On this server board, the PCIe bus lanes routed to the on-board M.2 connect- ors are routed from the Intel chipset (PCH). Note: The Intel ESRT2 option does not support PCIe devices.
• Both Intel ESRT2 and Intel® VROC (SATA RAID) provide RAID support for SATA devices (see Section 6.3.6).
• Neither embedded RAID option supports mixing of M.2 SATA SSDs and SATA hard drives within a sin- gle RAID volume. Note: Storage devices used to create a single RAID volume created using either Intel® VROC (SATA RAID) or Intel ESRT2 cannot span across the two embedded SATA controllers nor is mixing both SATA and NVMe de- vices within a single RAID volume supported.
• The binary driver includes partial source files. The driver is fully open source using an MDRAID layer in Linux*.

6.3.2 Onboard PCIe* OCuLink Connectors

directly routed from CPU_2. See Chapter 7 for OCuLink connector pin-out definition. Figure 41. Onboard OCuLink connectors

6.3.3 Intel® Volume Management Device (Intel® VMD) for NVMe*

NVMe SSD devices on the PCIe bus. **Figure 42. NVMe* storage bus event/error handling**

Intel® Server Board S2600WF Product Family Technical Product Specification Intel VMD handles the physical management of NVMe storage devices as a standalone function but can be enhanced when Intel® VROC (VMD NVMe RAID) support options are enabled to implement RAID based stor- age systems. The following is a list of features of the Intel® VMD technology:

• Hardware is integrated inside the processor PCIe root complex.
• Entire PCIe trees are mapped into their own address spaces (domains).
• Each domain manages x16 PCIe lanes.
• Can be enabled/disabled in BIOS setup at x4 lane granularity.
• Driver sets up/manages the domain (enumerate, event/error handling)
• May load an additional child device driver that is Intel VMD aware.
• Hot plug support - hot insert array of PCIe SSDs.
• Support for PCIe SSDs and switches only (no network interface controllers (NICs), graphics cards, etc.)
• Maximum of 128 PCIe bus numbers per domain.
• Support for MCTP over SMBus* only.
• Support for MMIO only (no port-mapped I/O).
• Does not support NTB, Quick Data Tech, Intel® Omni-Path Architecture, or SR-IOV.
• Correctable errors do not bring down the system.
• Intel VMD only manages devices on PCIe lanes routed directly from the processor. Intel VMD cannot provide device management on PCI lanes routed from the chipset (PCH)
• When Intel VMD is enabled, the BIOS does not enumerate devices that are behind Intel VMD. The In- tel VMD-enabled driver is responsible for enumerating these devices and exposing them to the host.
• Intel VMD supports hot-plug PCIe SSDs connected to switch downstream ports. Intel VMD does not support hot-plug of the switch itself.

6.3.3.1 Enabling Intel® VMD support

For installed NVMe devices to utilize the Intel VMD features of the server board, Intel VMD must be enabled on the appropriate CPU PCIe root ports in BIOS setup. By default, Intel VMD support is disabled on all CPU PCIe root ports in BIOS setup. See Table 21 to determine which specific CPU PCIe root ports are used to supply the PCIe bus lanes for onboard OCuLink connectors. For NVMe devices attached to a riser card via a PCIe switch or plugged directly into a PCIe add-in card slot, see Table 22, Table 23, and Table 24 to determine CPU PCIe root ports supporting each add-in card slot. In BIOS setup, the Intel VMD support menu can be found Advanced > PCI Configuration > Volume Manage- ment Device.

Table 30. Intel® VROC (VMD NVMe RAID) upgrade key options

6.3.5 Onboard SATA Support

providing for up to twelve 6 Gb/sec SATA ports.

• Two ports accessed via two white single port 7-pin connectors labeled “sSATA-4” and “sSATA-5” on the server board.
• Two ports (sSATA 1 and sSATA 2) via two M.2 SSD connectors The AHCI SATA controller provides support for up to eight SATA ports on the server board (Intel Server Boards S2600WFT(R) and S2600W0 only):
• Four ports from the mini-SAS HD (SFF-8643) connector labeled “SATA Ports 0-3” on the server board.
• Four ports from the mini-SAS HD (SFF-8643) connector labeled “SATA Ports 4-7” on the server board. Note: The onboard SATA controllers are not compatible with and cannot be used with SAS expander cards.

Figure 47. Onboard SATA port connector identification Table 31. SATA and sSATA controller feature support

6 Gb/s Transfer Rate Capable of data transfers up to 6 Gb/s Supported Supported Supported

table identifies supported setup options.

Table 32. SATA and sSATA controller BIOS setup utility options

6.3.5.1 Staggered Disk Spin-Up

startup than for normal operations. means that the drives are started up separately, with a certain delay between disk drives starting. Mass Storage Controller Configuration screen found in the BIOS setup utility.

6.3.6 Onboard SATA RAID Options

• Intel® VROC (SATA RAID) 6.0
• Intel® Embedded Server RAID Technology 2 (Intel® ESRT2) 1.60 By default, onboard RAID options are disabled in BIOS setup. To enable onboard RAID support, access the BIOS setup utility during POST. The onboard RAID options can be found under the sSATA Controller or SATA Controller options under the following BIOS setup menu: Advanced > Mass Storage Controller Con- figuration.

Figure 48. BIOS setup Mass Storage Controller Configuration screen engines that each SATA port offers in the chipset. Supported RAID levels include 0, 1, 5, and 10.

• RAID 0 – Uses striping to provide high data throughput, especially for large files in an environment that does not require fault tolerance.
• RAID 1 – Uses mirroring so that data written to one disk drive simultaneously writes to another disk drive. This is good for small databases or other applications that require small capacity but complete data redundancy.
• RAID 5 – Uses disk striping and parity data across all drives (distributed parity) to provide high data throughput, especially for small random access.
• RAID 10 – A combination of RAID 0 and RAID 1, consists of striped data across mirrored spans. It pro- vides high data throughput and complete data redundancy but uses a larger number of spans. By using Intel® VROC (SATA RAID), there is no loss of PCI resources (request/grant pair) or add-in card slot. Intel® VROC (SATA RAID) functionality requires the following:
• The embedded RAID option must be enabled in BIOS setup.
• Intel® VROC (SATA RAID) option must be selected in BIOS setup.
• Intel® VROC (SATA RAID) drivers must be loaded for the installed operating system.
• At least two SATA drives needed to support RAID levels 0 or 1.
• At least three SATA drives needed to support RAID level 5.
• At least four SATA drives needed to support RAID level 10.
• NVMe SSDs and SATA drives must not be mixed within a single RAID volume With Intel® VROC (SATA RAID) software RAID enabled, the following features are made available:
• A boot-time, pre-operating-system environment, text-mode user interface that allows the user to manage the RAID configuration on the system. Its feature set is kept simple to keep size to a mini- mum, but allows the user to create and delete RAID volumes and select recovery options when prob- lems occur. The user interface can be accessed by pressing <CTRL-I> during system POST.

• Boot support when using a RAID volume as a boot disk. It does this by providing Int13 services when a RAID volume needs to be accessed by MS-DOS applications (such as NT loader (NTLDR)) and by ex- porting the RAID volumes to the system BIOS for selection in the boot order.
• At each boot-up, a status of the RAID volumes provided to the user. 6.3.6.2 Intel® Embedded Server RAID Technology 2 (Intel® ESRT2) 1.60 for SATA Intel ESRT2 (powered by LSI*) is a driver-based RAID solution for SATA that is compatible with previous gen- eration Intel® server RAID solutions. Intel ESRT2 provides RAID levels 0, 1, and 10, with an optional RAID 5 capability depending on whether a RAID upgrade key is installed. Note: The embedded Intel ESRT2 option has no RAID support for PCIe NVMe SSDs. Intel ESRT2 is based on LSI MegaRAID software stack and utilizes the system memory and CPU. Supported RAID levels include.
• RAID 0 – Uses striping to provide high data throughput, especially for large files in an environment that does not require fault tolerance.
• RAID 1 – Uses mirroring so that data written to one disk drive simultaneously writes to another disk drive. This is good for small databases or other applications that require small capacity but complete data redundancy
• RAID 10 – A combination of RAID 0 and RAID 1, consists of striped data across mirrored spans. It pro- vides high data throughput and complete data redundancy but uses a larger number of spans. Optional support for RAID level 5 can be enabled with the addition of a RAID 5 upgrade key (iPN – RKSATA4R5).
• RAID 5 – Uses disk striping and parity data across all drives (distributed parity) to provide high data throughput, especially for small random access.

Figure 49. Intel® ESRT2 SATA RAID-5 upgrade key (iPN – RKSATA4R5) also used to support the Intel® VROC (VMD NVMe RAID) upgrade key options.

6.4 Rear External RJ45 Connector Overview

• Dedicated server management port
• Network interface connectors (S2600WFT(R) only)
• Serial-A port (see Section 6.5)

Figure 50. Rear external RJ45 connectors link speed. Table 33 provides a full definition for the LED states. Figure 51. RJ45 connector LEDs Table 33. External RJ45 NIC port LED definition

6.4.1 RJ45 Dedicated Management Port

additional information about onboard server management support.

6.4.2 RJ45 Network Interface Connectors (Intel® Server Board S2600WFT(R) only)

• Intel® Ethernet Controller X557-AT2 10 GbE Refer to the respective product data sheet for a complete list of supported Intel Ethernet Controller features.

6.5 Serial Port Support

The server board has support for two serial ports: Serial-A and Serial-B.

1. The pin orientation is shown in Figure 52 and the pinout is given in Table 34.

Figure 52. RJ45 Serial-A pin orientation pins 1–2 (default) to pins 2–3 as shown in Figure 53.

6.6 USB Support

The server board includes three (1x3 stacked) USB 3.0 ports on the back edge of the server board. Figure 55. External USB 3.0 ports The server board includes one internal Type-A USB 2.0 connector. Figure 56. Internal USB 2.0 type-A connector tion of routing two USB 3.0 ports to the front of a given chassis. Table 36 provides the connector pin-out.

Figure 57. Front panel USB 3.0 connector Note: The following USB ports are routed to this connector: USB 3.0 ports 1 and 2; USB 2.0 ports 11 and 13.

1 P5V_USB_FP

near the I/O module connector. Table 37 provides the connector pin-out.

Figure 58. Front panel USB 2.0 connector Table 37. Front panel USB 2.0 connector pinout ("FP_USB_2.0_5-6 ")

10 TP_USB2_FP_10

6.7 Video Support

resloutions specified in Table 38. Table 38. Supported video resolutions

6.7.1 Onboard Video Connectors

• A standard 15-pin video connector located on the back edge of the server board.

Figure 59. Rear external video connector

• On the server board near the front right edge, is A connector near the front right edge of the server board labeled “FP_VIDEO” that, when cabled, can provide video from the front of the server system. When a monitor is attached to the front of the system, the video out the back is disabled. Table 39 provides the pinout for this connector.

Figure 60. Front panel video connector Table 39. Front panel video connector pinout ("FP VIDEO")

Intel® Server Board S2600WF Product Family Technical Product Specification

6.7.2 Onboard Video and Add-In Video Adapter Support

Add-in video cards can be used to either replace or complement the onboard video option of the server board. BIOS setup includes options to support the desired video operation when an add-in video card is in- stalled.

• When both the Onboard Video and Add-in Video Adapter options are set to Enabled, both video displays can be active. The onboard video is still the primary console and active during BIOS POST; the add-in video adapter is only be active under an OS environment with video driver support.
• When Onboard Video is Enabled and Add-in Video Adapter is Disabled, only the onboard video is active.
• When Onboard Video is Disabled and Add-in Video Adapter is Enabled, only the add-in video adapter is active. Configurations with add-in video cards can get more complicated with a dual CPU socket board. Some multi- socket boards have PCIe slots capable of hosting an add-in video card which are attached to the IIOs of CPU sockets other than CPU Socket 1. However, only one CPU socket can be designated as legacy VGA socket as required in POST. To provide for this, there is the PCI Configuration option Legacy VGA Socket. The rules for this option are:
• The Legacy VGA Socket option is grayed out and unavailable unless an add-in video card is installed in a PCIe slot supported by CPU 2.
• Because the onboard video is hardwired to CPU socket 1, when Legacy VGA Socket is set to CPU Socket 2, the onboard video is disabled.

6.7.3 Dual Monitor Support

The BIOS supports single and dual video when add-in video adapters are installed. Although there is no ena- ble/disable option in BIOS setup for dual video, it works when both the Onboard Video and Add-in Video Adapter options are enabled. In the single video mode, the onboard video controller or the add-in video adapter is detected during POST. In dual video mode, the onboard video controller is enabled and is the primary video device while the add-in video adapter is allocated resources and is considered as the secondary video device during POST. The add- in video adapter will not be active until the operating system environment is loaded.

1. Onboard Connector/Header Pinout Definition

This section identifies the location and pinout for most onboard connectors and headers of the server board. matics directly from Intel (NDA required).

• All riser slots
• OCP* module connector
• SAS module connector
• M.2 SSD connectors
• DIMM slots
• Processor sockets

7.1 Power Connectors

The server board includes several power connectors that are used to provide DC power to various devices.

7.1.1 Main Power

pin-out mapping for the “MAIN PWR 2” connector. Figure 61. “MAIN PWR 1” and “MAIN PWR 2” connectors

Table 40. Main power (slot 1) connector pinout (“MAIN PWR 1”) Table 41. Main power (slot 2) connector pinout (“MAIN PWR 2”)

7.1.2 Hot Swap Backplane Power Connector

swap backplanes, as shown in Figure 62. On the server board, this connector is labeled as “HSBP PWR”. Figure 62. Hot swap backplane power connector Table 42. Hot swap backplane power connector pinout (“HSBP PWR”)

7.1.3 Riser Card Supplemental 12-V Power Connectors

sor) that have power requirements that exceed the 75 W maximum power supplied by the riser card slot. available to support any high-power add-in cards. Figure 63. Riser slot auxiliary power connectors Table 43 provides the pinout values for the 12-V power connectors. Table 43. Riser slot auxiliary power connector pinout ("OPT_12V_PWR”) arate orderable accessory kit (iPC – AXXGPGPUCABLE).

Figure 64. High power add-in card 12-V auxiliary power cable option

7.1.4 Peripheral Power Connector

as “Peripheral_ PWR”. Table 44 provides the pinout for this connector. Figure 65. Peripheral power connector Table 44. Peripheral drive power connector pinout ("Peripheral_PWR")

7.2 Front Control Panel Headers and Connectors

provides a functional description and pinout for each connector. connector, labeled “STORAGE _FP”. Figure 66. Front control panel connectors Supported control buttons and LEDs are identified in Table 45. Table 45. Front panel control button and LED support Figure 67. Example front control panel view (for reference purposes only)

The pinout for both connector types, shown in Table 46, is identical. Table 46. 30-pin front panel connector pinouts

7.2.1 Front Panel LED and Control Button Features Overview

7.2.1.1 Power/Sleep Button and LED Support

ferent indicator states as defined in Table 47. Table 47. Power/sleep LED functional states Off Power-off System power is off and the BIOS has not initialized the chipset. Off S5 Mechanical is off and the operating system has not saved any context to the hard disk. On S0 System and the operating system are up and running.

7.2.1.2 System ID Button and LED Support

“Chassis Identify” command which causes the LED to blink for 15 seconds.

7.2.1.3 System Reset Button Support

When pressed, this button reboots and re-initializes the system.

7.2.1.4 NMI Button Support

cause an event to be logged in the SEL.  Watchdog timer pre-timeout expiration with NMI/diagnostic interrupt pre-timeout action enabled. Table 48 describes behavior regarding NMI signal generation and event logging by the BMC. Table 48. NMI signal generation and event logging

7.2.1.5 NIC Activity LED Support

consistent with the amount of network activity that is occurring.

7.2.1.6 Storage Device Activity LED Support

cess to this LED for add-in controllers.

7.2.1.7 System Status LED Support

7.3 System Fan Connectors

configurations. Concurrent use of both fan connector types for any given system fan pair is not supported. Figure 68. Dual-rotor fixed mount fan pin connector orientation Table 49. Dual-rotor fixed mount fan connector pinout Figure 69. Hot swap fan connector pin orientation Table 50. Hot swap fan connector pinout each system fan connector on the server board.

Figure 70. Fan connector locations

7.4 Management Connectors

vide the pinout definition for each. Table 51. Hot swap backplane I2C connector – SMBUS 3-pin (J5C3)

1 SDA

2 Ground

3 SCL

Table 52. Hot swap backplane I2C connector – SMBUS 4-pin (J1K1)

4 RST_PCIE_SSD_PERST

Table 53. IPMB – SMBUS 4-pin (J1C3)

1 CMOS_SDA

3 CMOS_SCL

4 P5V_AUX

1. Basic and Advanced Server Management Features

tionally installed Intel® Remote Management Module 4 Lite (Intel® RMM4 Lite) key. Table 54. Intel® Remote Management Module 4 (Intel® RMM4) options On the server board, the Intel RMM4 Lite key is installed at the location shown in Figure 72. Figure 72. Intel® RMM4 Lite activation key installation tel RMM4 Lite is successful, then the BMC activates the advanced features. Table 55 identifies both basic and advanced server management features. Table 55. Basic and advanced server management features overview

8.1 Dedicated Management Port

without the Intel RMM4 Lite key installed. Figure 73. Dedicated managment port

8.2 Embedded Web Server

• Microsoft Internet Explorer*
• Mozilla Firefox*
• Google Chrome*
• Safari* The embedded web user interface supports strong security – authentication, encryption, and firewall support – since it enables remote server configuration and control. Encryption using 128-bit SSL is supported. User authentication is based on user ID and password. The user interface presented by the embedded web server authenticates the user before allowing a web ses- sion to be initiated. It presents all functions to all users but grays out those functions that the user does not

Intel® Server Board S2600WF Product Family Technical Product Specification have privilege to execute. For example, if a user does not have privilege to power control, then the item is disabled and displayed in grey font in that user’s display. The web interface also provides a launch point for some of the advanced features, such as keyboard, video, and mouse (KVM) and media redirection. These fea- tures are grayed out in the GUI unless the system has been updated to support these advanced features. The embedded web server only displays US English or Chinese language output. Additionally, the web interface can:

• Present all the basic features to the users.
• Power on, power off, and reset the server and view current power state.
• Display BIOS, BMC, ME and SDR version information
• Display overall system health.
• Display configuration of various IPMI over LAN parameters for both IPV4 and IPV6.
• Display configuration of alerts (SNMP and SMTP).
• Display system asset information for the product, board, and chassis.
• Display BMC-owned sensors (name, status, current reading, enabled thresholds), including color-code status of sensors.
• Provide ability to filter sensors based on sensor type (voltage, temperature, fan, and power supply related).
• Automatically refresh sensor data with a configurable refresh rate.
• Provide online help
• Display/clear SEL (display is in easily understandable human readable format).
• Support major industry-standard browsers (Microsoft Internet Explorer* and Mozilla Firefox*).
• Automatically time out GUI session after a user-configurable inactivity period. By default, this inactiv- ity period is 30 minutes.
• Provide embedded platform debug feature, allowing the user to initiate a “debug dump” to a file that can be sent to Intel for debug purposes.
• Provide a virtual front panel with the same functionality as the local front panel. The displayed LEDs match the current state of the local panel LEDs. The displayed buttons (for example, power button) can be used in the same manner as the local buttons.
• Display Intel ME sensor data. Only sensors that have associated SDRs loaded are displayed.
• Save the SEL to a file.
• Force HTTPS connectivity for greater security. This is provided through a configuration option in the user interface.
• Display processor and memory information that is available over IPMI over LAN.
• Get and set Intel® Node Manager (Intel® NM) power policies
• Display the power consumed by the server.
• View and configure VLAN settings.
• Warn user that the reconfiguration of IP address causes disconnect.
• Block logins for a period of time after several consecutive failed login attempts. The lock-out period and the number of failed logins that initiates the lock-out period are configurable by the user.
• Force into BIOS setup on a reset (server power control).
• Provide the system’s Power-On Self Test (POST) sequence for the previous two boot cycles, including timestamps. The timestamps may be displayed as a time relative to the start of POST or the previous POST code.
• Provide the ability to customize the port numbers used for SMASH, http, https, KVM, secure KVM, re- mote media, and secure remote media. For additional information, refer to the Intel® Remote Management Module 4 and Integrated BMC Web Con- sole User Guide.

Intel® Server Board S2600WF Product Family Technical Product Specification

8.3 Advanced Management Feature Support

The integrated baseboard management controller has support for advanced management features which are enabled when an optional Intel RMM4 Lite is installed. The Intel RMM4 Lite add-on offers convenient, remote KVM access and control through LAN and internet. It captures, digitizes, and compresses video and transmits it with keyboard and mouse signals to and from a remote computer. Remote access and control software runs in the integrated baseboard management controller, utilizing expanded capabilities enabled by the Intel RMM4 Lite hardware. Key features of the Intel RMM4 Lite add-on include:

• KVM redirection from either the dedicated management NIC or the server board NICs used for man- agement traffic and up to two KVM sessions. KVM automatically senses video resolution for best pos- sible screen capture, high performance mouse tracking, and synchronization. It allows remote viewing and configuration in pre-boot POST and BIOS setup.
• Media redirection intended to allow system administrators or users to mount a remote IDE or USB CDROM, floppy drive, or a USB flash disk as a remote device to the server. Once mounted, the remote device appears to the server just like a local device, allowing system administrators or users to install software (including operating systems), copy files, update BIOS, or boot the server from this device.

8.3.1 Keyboard, Video, Mouse (KVM) Redirection

The BMC firmware supports keyboard, video, and mouse redirection (KVM) over LAN. This feature is available remotely from the embedded web server as a Java* applet. This feature is only enabled when the Intel® RMM4 Lite is present. The client system must have a Java Runtime Environment (JRE) version 6.0 or later to run the KVM or media redirection applets. The BMC supports an embedded KVM application (Remote Console) that can be launched from the embed- ded web server from a remote console. USB1.1 or USB 2.0 based mouse and keyboard redirection are sup- ported. It is also possible to use the KVM redirection (KVM-r) session concurrently with media redirection (media-r). This feature allows a user to interactively use the keyboard, video, and mouse functions of the re- mote server as if the user were physically at the managed server. KVM redirection console supports the fol- lowing keyboard layouts: English, Dutch, French, German, Italian, Russian, and Spanish. KVM redirection includes a soft keyboard function. The soft keyboard is used to simulate an entire keyboard that is connected to the remote system. The soft keyboard functionality supports the following layouts: Eng- lish, Dutch, French, German, Italian, Russian, and Spanish. The KVM redirection feature automatically senses video resolution for best possible screen capture and pro- vides high-performance mouse tracking and synchronization. It allows remote viewing and configuration in pre-boot POST and BIOS setup, once BIOS has initialized video. Other attributes of this feature include:

• Encryption of the redirected screen, keyboard, and mouse
• Compression of the redirected screen.
• Ability to select a mouse configuration based on the OS type.
• Support for user definable keyboard macros. KVM redirection feature supports the following resolutions and refresh rates:
• 640x480 at 60 Hz, 72 Hz, 75 Hz, 85 Hz
• 800x600 at 60 Hz, 72 Hz, 75 Hz, 85 Hz
• 1024x768 at 60 Hz, 72 Hz, 75 Hz, 85 Hz
• 1152x864 at 75 Hz
• 1280x800 at 60 Hz

Intel® Server Board S2600WF Product Family Technical Product Specification

• 1280x1024 at 60 Hz
• 1440x900 at 60 Hz
• 1600x1200 at 60 Hz

8.3.1.1 Availability

The remote KVM session is available even when the server is powered off (in stand-by mode). No restart of the remote KVM session is required during a server reset or power on/off. A BMC reset – for example, due to a BMC watchdog initiated reset or BMC reset after BMC firmware update – does require the session to be re- established. KVM sessions persist across system reset, but not across an AC power loss.

8.3.1.2 Security

The KVM redirection feature supports multiple encryption algorithms, including RC4 and AES. The actual al- gorithm that is used is negotiated with the client based on the client’s capabilities.

8.3.1.3 Usage

As the server is powered up, the remote KVM session displays the complete BIOS boot process. The user is able to interact with BIOS setup, change and save settings, and enter and interact with option ROM configu- ration screens.

8.3.1.4 Force-enter BIOS Setup

KVM redirection can present an option to force-enter BIOS etup. This enables the system to enter BIOS setup while booting which is often missed by the time the remote console redirects the video.

8.3.2 Media Redirection

The embedded web server provides a Java applet to enable remote media redirection. This may be used in conjunction with the remote KVM feature or as a standalone applet. The media redirection feature is intended to allow system administrators or users to mount a remote IDE or USB CD-ROM, floppy drive, or a USB flash disk as a remote device to the server. Once mounted, the remote device appears to the server just like a local device, allowing system administrators or users to install soft- ware (including operating systems), copy files, update BIOS, or boot the server from this device. The following list describes additional media redirection capabilities and features.

• The operation of remotely mounted devices is independent of the local devices on the server. Both remote and local devices are usable in parallel.
• Either IDE (CD-ROM, floppy) or USB devices can be mounted as a remote device to the server.
• It is possible to boot all supported operating systems from the remotely mounted device and to boot from disk IMAGE (*.IMG) and CD-ROM or DVD-ROM ISO files. See the tested/supported operating sys- tem list for more information.
• Media redirection supports redirection for both a virtual CD device and a virtual floppy/USB device concurrently. The CD device may be either a local CD drive or else an ISO image file; the Floppy/USB device may be either a local Floppy drive, a local USB device, or else a disk image file.
• The media redirection feature supports multiple encryption algorithms, including RC4 and AES. The actual algorithm that is used is negotiated with the client based on the client’s capabilities.
• A remote media session is maintained even when the server is powered off (in standby mode). No re- start of the remote media session is required during a server reset or power on/off. A BMC reset (for example, due to an BMC reset after BMC FW update) requires the session to be re-established
• The mounted device is visible to (and usable by) managed system’s OS and BIOS in both pre-boot and post-boot states.

Intel® Server Board S2600WF Product Family Technical Product Specification 100

• The mounted device shows up in the BIOS boot order and it is possible to change the BIOS boot or- der to boot from this remote device.
• It is possible to install an operating system on a bare metal server (no OS present) using the remotely mounted device. This may also require the use of KVM-r to configure the OS during install. USB storage devices appear as floppy disks over media redirection. This allows for the installation of device drivers during OS installation. If either a virtual IDE or virtual floppy device is remotely attached during system boot, both the virtual IDE and virtual floppy are presented as bootable devices. It is not possible to present only a single-mounted de- vice type to the system BIOS.

8.3.2.1 Availability

The default inactivity timeout is 30 minutes and is not user-configurable. Media redirection sessions persist across system reset but not across an AC power loss or BMC reset.

8.3.3 Remote Console

The remote console is the redirected screen, keyboard, and mouse of the remote host system. To use the remote console window of the managed host system, the browser must include a Java* Runtime Environ- ment (JRE) plug-in. If the browser has no Java support, such as with a small handheld device, the user can maintain the remote host system using the administration forms displayed by the browser. The remote console window is a Java applet that establishes TCP connections to the BMC. The protocol that is run over these connections is a unique KVM protocol and not HTTP or HTTPS. This protocol uses ports #7578 for KVM, #5120 for CD-ROM media redirection, and #5123 for floppy and USB media redirection. When encryption is enabled, the protocol uses ports #7582 for KVM, #5124 for CD-ROM media redirection, and #5127 for floppy and USB media redirection. The local network environment must permit these connec- tions to be made; that is the firewall and, in case of a private internal network, the Network Address Transla- tion (NAT) settings have to be configured accordingly. For additional information, reference the Intel® Remote Management Module 4 and Integrated BMC Web Console User Guide.

8.3.4 Performance

The remote display accurately represents the local display. The feature adapts to changes in the video reso- lution of the local display and continues to work smoothly when the system transitions from graphics to text or vice-versa. The responsiveness may be slightly delayed depending on the bandwidth and latency of the network. Enabling KVM and/or media encryption does degrade performance. Enabling video compression provides the fastest response while disabling compression provides better video quality. For the best possible KVM performance, a 2 Mbps link or higher is recommended. The redirection of KVM over IP is performed in paral- lel with the local KVM without affecting the local KVM operation.

Intel® Server Board S2600WF Product Family Technical Product Specification 102 Figure 75.DIMM fault LED placement

9.1 System ID LED

The server board includes a blue system ID LED which is used to visually identify a specific server installed among many other similar servers. There are two options available for illuminating the System ID LED.

• The front panel ID LED button is pushed, which causes the LED to illuminate to a solid on state until the button is pushed again.
• An IPMI Chassis Identify command is remotely entered, which causes the LED to blink The system ID LED on the server board is tied directly to the system ID LED on system front panel, if present.

9.2 System Status LED

The server board includes a bi-color system status LED. The system status LED on the server board is tied directly to the system status LED on the front panel (if present). This LED indicates the current health of the server. Possible LED states include solid green, blinking green, solid amber, and blinking amber. When the server is powered down (transitions to the DC-off state or S5), the BMC is still on standby power and retains the sensor and front panel status LED state established before the power-down event. When AC power is first applied to the system, the status LED turns solid amber and then immediately changes to blinking green to indicate that the BMC is booting. If the BMC boot process completes with no errors, the status LED changes to solid green. Table 56 lists and describes the states of the system status LEDs.

Table 56. System status LED states power is present and BMC has booted and manageability functionality is up and running.

1. After a BMC reset, and in conjunction with the Chassis ID solid ON, the BMC is

will be in this state for 10-20 seconds.

1 Hz blinking

1. Redundancy loss such as power-supply or fan. Applies only if the associated plat-

form sub-system has redundancy capabilities.

1. Fan warning or failure when the number of fully operational fans is more than

minimum number needed to cool the system.

1. Non-critical threshold crossed – Temperature (including HSBP temp), voltage, in-

and Processor Thermal Control (Therm Ctrl) sensors.

1. Power supply predictive failure occurred while redundant power supply configu-
2. Unable to use all of the installed memory (more than 1 DIMM installed) 1.
3. Correctable Errors over a threshold and migrating to a spare DIMM (memory spar-

dancy lost condition. Corresponding DIMM LED lit.

1. In mirrored configuration, when memory mirroring takes place and system loses
2. BMC executing in uBoot. (Indicated by Chassis ID blinking at 3Hz). System in de-

while it pulls the Linux* image into flash.

1. BMC Watchdog has reset the BMC.
2. Power Unit sensor offset for configuration error is asserted.
3. HDD HSC is off-line or degraded.
4. Critical threshold crossed – Voltage, temperature (including HSBP temp), input

PROCHOT (Therm Ctrl) sensors.

1. Minimum number of fans to cool the system not present or failed
2. Power Unit Redundancy sensor – Insufficient resources offset (indicates not

9.3 BMC Boot/Reset Status LED Indicators

Table 57. BMC boot/reset status LED indicators formation on replacing this motherboard.

Intel® Server Board S2600WF Product Family Technical Product Specification 104 Both universal bootloader (u-Boot) images bad

6 Hz blinking

blue Solid amber Non-recoverable condition. Contact an Intel representative for in- formation on replacing this motherboard. BMC in u-Boot 3 Hz blinking blue Blinking green indicates degraded state (no manageability), blinking blue indicates u-Boot is running but has not transferred control to BMC Linux*. Server will be in this state 6-8 seconds after BMC reset while it pulls the Linux image into flash. BMC booting Linux* Solid blue Solid green After an AC cycle/BMC reset, indicates that the control has been passed from u-Boot to BMC Linux* itself. It will be in this state for 10-20 seconds. End of BMC boot/reset process. Normal system operation Off Solid green Indicates BMC Linux* has booted and manageability functionality is up and running. Fault/status LEDs operate as per usual.

9.4 Post Code Diagnostic LEDs

A bank of eight POST code diagnostic LEDs are located on the back edge of the server next to the stacked USB connectors (see Figure 74). During the system boot process, the BIOS executes a number of platform configuration processes, each of which is assigned a specific hex POST code number. As each configuration routine is started, the BIOS displays the given POST code to the POST code diagnostic LEDs. The purpose of these LEDs is to assist in troubleshooting a system hang condition during the POST process. The diagnostic LEDs can be used to identify the last POST process to be executed. See Appendix B for a complete descrip- tion of how these LEDs are read, and for a list of all supported POST codes

9.5 Fan Fault LEDs

The server board includes a fan fault LED next to each of the six system fans (see Figure 74). The LED has two states: on and off. The BMC lights a fan fault LED if the associated fan-tach sensor has a lower critical thresh- old event status asserted. Fan-tach sensors are manual re-arm sensors. Once the lower critical threshold is crossed, the LED remains lit until the sensor is rearmed. These sensors are rearmed at system DC power-on and system reset.

9.6 Memory Fault LEDs

The server board includes a memory fault LED for each DIMM slot (see Figure 75). When the BIOS detects a memory fault condition, it sends an IPMI OEM command (Set Fault Indication) to the BMC to instruct the BMC to turn on the associated memory slot fault LED. These LEDs are only active when the system is in the on state. The BMC does not activate or change the state of the LEDs unless instructed by the BIOS.

9.7 CPU Fault LEDs

The server board includes a CPU fault LED for each CPU socket. The CPU fault LED is lit if there is an MSID mismatch error is detected (that is, CPU power rating is incompatible with the board).

• Password protection
• Front panel lockout
• Trusted Platform Module (TPM) support
• Intel® Trusted Execution Technology (Intel® TXT)

10.1 Password Protection

front panel lockout, and TPM settings, can be found. Figure 76. BIOS setup Security tab

10.1.1 Password Setup

Intel® Server Board S2600WF Product Family Technical Product Specification 106 re-ordering, and prevent unauthorized system power on. It is strongly recommended that an administrator password be set. A system with no administrator password set allows anyone who has access to the server to change BIOS settings. An administrator password must be set in order to set the user password. The maximum length of a password is 14 characters and can be made up of a combination of alphanumeric (a-z, A-Z, 0-9) characters and any of the following special characters: Passwords are case sensitive. The administrator and user passwords must be different from each other. An error message is displayed and a different password must be entered if there is an attempt to enter the same password for both. The use of strong passwords is encouraged, but not required. In order to meet the criteria for a strong password, the password entered must be at least eight characters in length, and must include at least one each of alpha- betic, numeric, and special characters. If a weak password is entered, a warning message is displayed, and the weak password is accepted. Once set, a password can be cleared by changing it to a null string. This requires the administrator password, and must be done through BIOS setup. Clearing the administrator password also clears the user password. Passwords can also be cleared by using the password clear jumper on the server board. For more information on the password clear jumper, see Section 11.2. Resetting the BIOS configuration settings to default values (by any method) has no effect on the administra- tor and user passwords. As a security measure, if a user or administrator enters an incorrect password three times in a row during the boot sequence, the system is placed into a halt state. A system reset is required to exit out of the halt state. This feature makes it more difficult to guess or break a password. In addition, on the next successful reboot, the Error Manager displays a Major Error code 0048, which also logs a SEL event to alert the authorized user or administrator that a password access failure has occurred.

10.1.2 System Administrator Password Rights

When the correct administrator password is entered when prompted, the user has the ability to perform the following actions:

• Access the BIOS setup utility.
• Configure all BIOS setup options in the BIOS setup utility.
• Clear both the administrator and user passwords.
• Access the Boot Menu during POST. If the Power On Password function is enabled in BIOS setup, the BIOS halts early in POST to request a pass- word (administrator or user) before continuing POST.

10.1.3 Authorized System User Password Rights and Restrictions

When the correct user password is entered, the user has the ability to perform the following actions:

• Access the BIOS setup utility.
• View, but not change, any BIOS setup options in the BIOS setup utility.
• Modify system time and date in the BIOS setup utility. If the Power On Password function is enabled in BIOS setup, the BIOS halts early in POST to request a pass- word (administrator or user) before continuing POST. Configuring an administrator password imposes restrictions on booting the system, and configures most setup fields to read-only if the administrator password is not provided. The boot popup menu requires the

Intel® Server Board S2600WF Product Family Technical Product Specification 107 administrator password to function, and the USB reordering is suppressed as long as the administrator pass- word is enabled. Users are restricted from booting in anything other than the boot order defined in setup by an administrator.

10.2 Front Panel Lockout

If enabled in BIOS setup from the Security screen, this option disables the following front panel features:

• The off function of the power button.
• System reset button. If front panel lockout is enabled, system power off and reset must be controlled via a system management interface.

10.3 Trusted Platform Module (TPM) Support

The Trusted Platform Module (TPM) option is a hardware-based security device that addresses the growing concern about boot process integrity and offers better data protection. TPM protects the system startup pro- cess by ensuring it is tamper-free before releasing system control to the operating system. A TPM device provides secured storage to store data, such as security keys and passwords. In addition, a TPM device has encryption and hash functions. The server board implements TPM as per TPM PC Client Specifications revi- sion 1.2, published by the Trusted Computing Group (TCG). A TPM device is optionally installed on a high-density 14-pin connector labeled “TPM” on the server board, and is secured from external software attacks and physical theft. A pre-boot environment, such as the BIOS and operating system loader, uses the TPM to collect and store unique measurements from multiple factors within the boot process to create a system fingerprint. This unique fingerprint remains the same unless the pre-boot environment is tampered with. Therefore, it is used to compare to future measurements to verify the integrity of the boot process. After the system BIOS completes the measurement of its boot process, it hands off control to the operating system loader and, in turn, to the operating system. If the operating system is TPM-enabled, it compares the BIOS TPM measurements to those of previous boots to make sure the system was not tampered with before continuing the operating system boot process. Once the operating system is in operation, it optionally uses TPM to provide additional system and data security (for example, Microsoft Windows 10* supports Bitlocker* drive encryption).

10.3.1 TPM Security BIOS

The BIOS TPM support conforms to the TPM PC Client Implementation Specification for Conventional BIOS the TPM Interface Specification, and the Microsoft Windows BitLocker Requirements. The role of the BIOS for TPM security includes the following:

• Measures and stores the boot process in the TPM microcontroller to allow a TPM-enabled operating system to verify system boot integrity.
• Produces extensible firmware interface (EFI) and legacy interfaces to a TPM-enabled operating sys- tem for using TPM.
• Produces Advanced Configuration and Power Interface (ACPI) TPM device and methods to allow a TPM-enabled operating system to send TPM administrative command requests to the BIOS.
• Verifies operator physical presence. Confirms and executes operating system TPM administrative command requests.
• Provides BIOS setup options to change TPM security states and to clear TPM ownership.

Intel® Server Board S2600WF Product Family Technical Product Specification 108 For additional details, refer to the TCG PC Client Specific Implementation Specification, the TCG PC Client Specific Physical Presence Interface Specification, and the Microsoft Windows* BitLocker* Requirements documents.

10.3.2 Physical Presence

Administrative operations to the TPM require TPM ownership or physical presence indication by the opera- tor to confirm the execution of administrative operations. The BIOS implements the operator presence indi- cation by verifying the setup administrator password. A TPM administrative sequence invoked from the operating system proceeds as follows: 1. A user makes a TPM administrative request through the operating system’s security software. 2. The operating system requests the BIOS to execute the TPM administrative command through TPM ACPI methods and then resets the system. 3. The BIOS verifies the physical presence and confirms the command with the operator. 4. The BIOS executes TPM administrative command, inhibits BIOS setup entry, and boots directly to the operating system which requested the TPM command.

10.3.3 TPM Security Setup Options

The BIOS TPM setup allows the operator to view the current TPM state and to carry out rudimentary TPM administrative operations. Performing TPM administrative options through the BIOS setup requires TPM physical presence verification. Using the BIOS TPM setup, the operator can turn TPM functionality on or off and clear the TPM ownership contents. After the requested TPM BIOS setup operation is carried out, the option reverts to No Operation. The BIOS TPM setup also displays the current state of the TPM, whether TPM is enabled or disabled and acti- vated or deactivated. Note that while using TPM, a TPM-enabled operating system or application may change the TPM state independently of the BIOS setup. When an operating system modifies the TPM state, the BIOS Setup displays the updated TPM state. The BIOS setup TPM Clear option allows the operator to clear the TPM ownership key and allows the opera- tor to take control of the system with TPM. You use this option to clear security settings for a newly initial- ized system or to clear a system for which the TPM ownership security key was lost.

10.4 Intel® Trusted Execution Technology

The 1st and 2nd Gen Intel® Xeon® processor Scalable families support Intel® Trusted Execution Technology (Intel® TXT), which is a robust security environment. Designed to help protect against software-based attacks, Intel TXT integrates new security features and capabilities into the processor, chipset, and other platform components. When used in conjunction with Intel® Virtualization Technology (Intel® VT), Intel TXT provides hardware-rooted trust for virtual applications. This hardware-rooted security provides a general-purpose, safer computing environment capable of running a wide variety of operating systems and applications to increase the confidentiality and integrity of sensitive information without compromising the usability of the platform. Intel TXT requires a computer system with Intel Virtualization Technology enabled (both VT-x and VT-d), an Intel TXT -enabled processor, chipset, and BIOS, Authenticated Code Modules, and an Intel TXT compatible measured launched environment (MLE). The MLE could consist of a virtual machine monitor, an OS, or an application. In addition, Intel TXT requires the system to include a TPM v1.2, as defined by the Trusted Com- puting Group TPM PC Client Specifications, Revision 1.2. When available, Intel TXT can be enabled or disabled in the processor by a BIOS setup option. For general information about Intel TXT, visit http://www.intel.com/technology/security/.

1. Reset and Recovery Jumpers

Figure 77. Reset and recovery jumper block location The following sections describe how each jumper block is used.

11.1 BIOS Default Jumper Block

1. Power down the server and unplug the power cord(s).
2. Remove the system top cover and move the “BIOS DFLT” jumper from pins 1-2 (normal operation) to

pins 2-3 (set BIOS defaults).

1. Wait five seconds then move the jumper back to pins 1-2.
2. Re-install the system top cover.
3. Re-Install system power cords.

Note: The system automatically powers on after AC is applied to the system.

1. During POST, press <F2> to access the BIOS setup utility to configure and save desired BIOS options.

Intel® Server Board S2600WF Product Family Technical Product Specification 110 After resetting BIOS options using the BIOS default jumper, the Error Manager Screen in the BIOS setup util- ity displays two errors:

• 0012 System RTC date/time not set
• 5220 BIOS Settings reset to default settings Also, the system time and date may need to be reset.

11.2 Password Clear Jumper Block

This jumper causes both the user password and the administrator password to be cleared if they were set. The operator should be aware that this creates a security gap until passwords have been installed again through the BIOS setup utility. This is the only method by which the administrator and user passwords can be cleared unconditionally. Other than this jumper, passwords can only be set or cleared by changing them explicitly in BIOS setup or by similar means. No method of resetting BIOS configuration settings to default values affects either the administrator or user passwords. To use the password clear jumper, perform the following steps: 1. Power down the server. For safety, unplug the power cord(s). 2. Remove the system top cover. 3. Move the password clear jumper from pins 1-2 (default) to pins 2-3 (password clear position). 4. Re-install the system top cover and re-attach the power cords. 5. Power up the server and press <F2> to access the BIOS setup utility. 6. Verify the password clear operation was successful by viewing the Error Manager screen. Two errors should be logged: o 5221 Passwords cleared by jumper o 5224 Password clear jumper is set 7. Exit the BIOS setup utility and power down the server. For safety, remove the AC power cords 8. Remove the system top cover and move the password clear jumper back to pins 1-2 (default). 9. Re-install the system top cover and reattach the AC power cords. 10. Power up the server. 11. It is strongly recommended to boot into BIOS setup immediately, navigate to the Security tab, and set the administrator and user passwords if intending to use BIOS password protection.

11.3 Intel® Management Engine (Intel® ME) Firmware Force Update Jumper Block

When the Intel ME firmware force update jumper is moved from its default position, the Intel ME is forced to operate in a reduced minimal operating capacity. This jumper should only be used if the Intel ME firmware has gotten corrupted and requires re-installation. Note: System update files are included in the system update packages (SUP) posted to Intel’s download cen- ter website at http://downloadcenter.intel.com. To use the Intel ME firmware force update jumper, perform the following steps: 1. Turn off the system and remove the AC power cords. Note: If the Intel ME force update jumper is moved with AC power applied to the system, the Intel ME will not operate properly. 2. Remove the system top cover. 3. Move the “ME FRC UPD” jumper from pins 1-2 (default) to pins 2-3 (force update position). 4. Re-install the system top cover and re-attach the AC power cords.

Intel® Server Board S2600WF Product Family Technical Product Specification 111 5. Power on the system. 6. Boot to the EFI shell. 7. Change directories to the folder containing the update files. 8. Update the Intel ME firmware using the following command: iflash32 /u /ni <version#>_ME.cap 9. When the update has successfully completed, power off the system. 10. Remove the AC power cords. 11. Remove the system top cover. 12. Move the “ME FRC UPD” jumper back to pins 1-2 (default). 13. Re-attach the AC power cords and power on the system.

11.4 BMC Force Update Jumper Block

The BMC force update jumper is used to put the BMC in boot recovery mode for a low-level update. It causes the BMC to abort its normal boot process and stay in the boot loader without executing any Linux* code. This jumper should only be used if the BMC firmware has become corrupted and requires re-installation. Note: System update files are included in the SUP posted to Intel’s download center website at http://down- loadcenter.intel.com. To use the BMC force update jumper, perform the following steps: 1. Turn off the system and remove the AC power cords. Note: If the BMC FRC UPD jumper is moved with AC power applied to the system, the BMC will not operate properly. 2. Remove the system top cover. 3. Move the “BMC FRC UPD” jumper from pins 1 - 2 (default) to pins 2 - 3 (force update position). 4. Re-install the system top cover and re-attach the AC power cords. 5. Power on the system. 6. Boot to the EFI shell. 7. Change directories to the folder containing the update files. 8. Update the BMC firmware using the following command: FWPIAUPD -u -bin -ni -b -o -pia -if=usb <file name.BIN> 9. When the update has successfully completed, power off the system. 10. Remove the AC power cords. 11. Remove the system top cover. 12. Move the “BMC FRC UPD” jumper back to pins 1-2 (default). 13. Re-attach the AC power cords and power on the system. 14. Boot to the EFI shell. 15. Change directories to the folder containing the update files. 16. Re-install the board/system SDR data by running the FRUSDR utility. 17. After the SDRs have been loaded, reboot the server.

11.5 BIOS Recovery Jumper

When the BIOS recovery jumper block is moved from its default pin position (pins 1–2), the system boots using a backup BIOS image to the UEFI shell, where a standard BIOS update can be performed. See the BIOS update instructions that are included with the SUP downloaded from Intel’s download center website. This

Intel® Server Board S2600WF Product Family Technical Product Specification 112 jumper is used when the system BIOS has become corrupted and is non-functional, requiring a new BIOS image to be loaded on to the server board. Note: The BIOS Recovery jumper is only used to re-install a BIOS image in the event the BIOS has become corrupted. This jumper is not used when the BIOS is operating normally to update the BIOS from one version to another. Note: System update files are included in the SUP posted to Intel’s download center website at http://down- loadcenter.intel.com. To use the BIOS recovery jumper, perform the following steps: 1. Turn off the system and remove the AC power cords. 2. Remove the system top cover. 3. Move the “BIOS Recovery” jumper from pins 1 – 2 (default) to pins 2 – 3 (BIOS recovery position). 4. Re-install the system top cover and re-attach the AC power cords. 5. Power on the system. The system automaticallys boot to the EFI shell. 6. Update the BIOS using the standard BIOS update instructions provided with the system update pack- age. 7. After the BIOS update has successfully completed, power off the system. For safety, remove the AC power cords from the system. 8. Remove the system top cover. 9. Move the BIOS recovery jumper back to pins 1 – 2 (default). 10. Re-install the system top cover and re-attach the AC power cords. 11. During POST, press <F2> to access the BIOS setup utility to configure and save desired BIOS options.

Intel® Server Board S2600WF Product Family Technical Product Specification 113 12. Platform Management Platform management is supported by several hardware and software components integrated on the server board that work together to:

• Control system functions – power system, ACPI, system reset control, system initialization, front panel interface, system event log.
• Monitor various board and system sensors and regulate platform thermals and performance to main- tain (when possible) server functionality in the event of component failure and/or environmentally stressed conditions.
• Monitor and report system health.
• Provide an interface for Intel® Server Management software applications. This chapter provides a high level overview of the platform management features and functionality imple- mented on the server board. The Intel® Server System BMC Firmware External Product Specification (EPS) and the Intel® Server System BIOS External Product Specification (EPS) for Intel® Server Products based on the 1st and 2nd Gen Intel® Xeon® processor Scalable-2600 v5 product families should be referenced for more in-depth and design level platform management information.

12.1 Management Feature Set Overview

The following sections outline features that the integrated BMC firmware can support. Support and utiliza- tion for some features is dependent on the server platform in which the server board is integrated and any additional system level components and options that may be installed. 12.1.1 IPMI 2.0 Features Overview The baseboard management controller (BMC) supports the following IPMI 2.0 features:

• IPMI watchdog timer.
• Messaging support, including command bridging and user/session support.
• Chassis device functionality, including power/reset control and BIOS boot flags support.
• Event receiver device to receive and process events from other platform subsystems.
• Access to system Field Replaceable Unit (FRU) devices using IPMI FRU commands.
• System Event Log (SEL) device functionality including SEL Severity Tracking and Extended SEL.
• Storage of and access to system Sensor Data Records (SDRs).
• Sensor device management and polling to monitor and report system health.
• IPMI interfaces o Host interfaces including system management software (SMS) with receive message queue support and server management mode (SMM) o Intelligent platform management bus (IPMB) interface o LAN interface that supports the IPMI-over-LAN protocol (RMCP, RMCP+)
• Serial-over-LAN (SOL)
• ACPI state synchronization to state changes provided by the BIOS.
• Initialization and runtime self-tests including making results available to external entities. See also the Intelligent Platform Management Interface Specification Second Generation v2.0.

12.1.2 Non-IPMI Features Overview

The BMC supports the following non-IPMI features.

• In-circuit BMC firmware update.

Intel® Server Board S2600WF Product Family Technical Product Specification 114

• Fault resilient booting (FRB) including FRB-2 supported by the watchdog timer functionality.
• Chassis intrusion detection (dependent on platform support).
• Fan speed control with SDR, fan redundancy monitoring, and support.
• Enhancements to fan speed control.
• Power supply redundancy monitoring and support.
• Hot-swap fan support.
• Acoustic management and support for multiple fan profiles.
• Test commands for setting and getting platform signal states.
• Diagnostic beep codes for fault conditions.
• System globally unique identifier (GUID) storage and retrieval.
• Front panel management including system status LED and chassis ID LED (turned on using a front panel button or command), secure lockout of certain front panel functionality, and button press monitoring.
• Power state retention.
• Power fault analysis.
• Intel® Light-Guided Diagnostics.
• Power unit management including support for power unit sensor and handling of power-good drop- out conditions.
• DIMM temperature monitoring facilitating new sensors and improved acoustic management using closed-loop fan control algorithm taking into account DIMM temperature readings.
• Sending and responding to Address Resolution Protocols (ARPs) (supported on embedded NICs).
• Dynamic Host Configuration Protocol (DHCP) (supported on embedded NICs).
• Platform environment control interface (PECI) thermal management support.
• Email alerting.
• Support for embedded web server UI in Basic Manageability feature set.
• Enhancements to embedded web server. o Human-readable SEL. o Additional system configurability. o Additional system monitoring capability. o Enhanced online help.
• Integrated keyboard, video, and mouse (KVM).
• Enhancements to KVM redirection. o Support for higher resolution.
• Integrated remote media redirection.
• Lightweight Directory Access Protocol (LDAP) support.
• Intel® Intelligent Power Node Manager support.
• Embedded platform debug feature which allows capture of detailed data for later analysis. o Creation of password protected files accessible by Intel only.
• Provisioning and inventory enhancements. o Inventory data/system information export (partial SMBIOS table).
• DCMI 1.5 compliance.
• Management support for Power Management Bus (PMBus*) 1.2 compliant power supplies.
• BMC data repository (managed data region feature).
• Support for an Intel® Local Control Panel display.
• System airflow monitoring.
• Exit air temperature monitoring.
• Ethernet controller thermal monitoring.
• Global aggregate temperature margin sensor.
• Memory thermal management.
• Power supply fan sensors.

• ENERGY STAR* server support.
• Smart ride through (SmaRT) / closed-loop system throttling (CLST).
• Power supply cold redundancy.
• Power supply firmware update.
• Power supply compatibility check.
• BMC firmware reliability enhancements: o Redundant BMC boot blocks to avoid possibility of a corrupted boot block resulting in a sce- nario that prevents a user from updating the BMC. o BMC system management health monitoring.

12.2 Platform Management Features and Functions

12.2.1 Power Subsystem

Table 58. Power control sources

12.2.2 Advanced Configuration and Power Interface (ACPI)

Table 59. ACPI power states

• Front panel power LED is on (not controlled by the BMC).
• Fans spin at the normal speed, as determined by sensor inputs.
• Front panel buttons work normally. S1 No Not supported. S2 No Not supported. S3 No Supported only on workstation platforms. See appropriate platform specific Information for more information. S4 No Not supported. S5 Yes Soft off.
• Front panel buttons are not locked.
• Fans are stopped.
• Power-up process goes through the normal boot process.
• Power, reset, front panel non-maskable interrupt (NMI), and ID buttons are unlocked.

Intel® Server Board S2600WF Product Family Technical Product Specification 116

12.2.3 System Initialization

During system initialization, both the BIOS and the BMC initialize the items described in the following sec- tions.

12.2.3.1 Processor Tcontrol Setting

Processors used with this chipset implement a feature called Tcontrol, which provides a processor-specific value that can be used to adjust the fan-control behavior to achieve optimum cooling and acoustics. The BMC reads these from the CPU through PECI Proxy mechanism provided by Intel® ME. The BMC uses these values as part of the fan-speed-control algorithm.

12.2.3.2 Fault Resilient Booting (FRB)

Fault resilient booting (FRB) is a set of BIOS and BMC algorithms and hardware support that allow a multipro- cessor system to boot even if the bootstrap processor (BSP) fails. Only FRB-2 is supported using watchdog timer commands. FRB-2 refers to the FRB algorithm that detects system failures during POST. The BIOS uses the BMC watch- dog timer to back up its operation during POST. The BIOS configures the watchdog timer to indicate that the BIOS is using the timer for the FRB2 phase of the boot operation. After the BIOS has identified and saved the BSP information, it sets the FRB-2 timer use bit and loads the watchdog timer with the new timeout interval. If the watchdog timer expires while the watchdog use bit is set to FRB-2, the BMC (if so configured) logs a watchdog expiration event showing the FRB-2 timeout in the event data bytes. The BMC then hard resets the system, assuming the BIOS-selected reset as the watchdog timeout action. The BIOS is responsible for disabling the FRB-2 timeout before initiating the option ROM scan and before displaying a request for a boot password. If the processor fails and causes an FRB-2 timeout, the BMC resets the system. The BIOS gets the watchdog expiration status from the BMC. If the status shows an expired FRB-2 timer, the BIOS enters the failure in the system event log (SEL). In the OEM bytes entry in the SEL, the last POST code generated during the previous boot attempt is written. FRB-2 failure is not reflected in the processor status sensor value. The FRB-2 failure does not affect the front panel LEDs.

12.2.3.3 Post Code Display

The BMC, upon receiving standby power, initializes internal hardware to monitor port 80h (POST code) writes. Data written to port 80h is output to the system POST LEDs. The BMC deactivates POST LEDs after POST completes. Refer to Appendix B for a complete list of supported POST code diagnostic LEDs.

12.2.4 Watchdog Timer

The BMC implements a fully IPMI 2.0 compatible watchdog timer. For details, see the Intelligent Platform Management Interface Specification Second Generation v2.0. The NMI/diagnostic interrupt for an IPMI 2.0 watchdog timer is associated with an NMI. A watchdog pre-timeout SMI or equivalent signal assertion is not supported.

12.2.5 System Event Log (SEL)

The BMC implements the system event log as specified in the Intelligent Platform Management Interface Specification v2.0. The SEL is accessible regardless of the system power state through the BMC's in-band and out-of-band interfaces.

Intel® Server Board S2600WF Product Family Technical Product Specification 117 The BMC allocates 95,231 bytes (approx. 93 KB) of non-volatile storage space to store system events. The SEL timestamps may not be in order. Up to 3,639 SEL records can be stored at a time. Because the SEL is cir- cular, any command that results in an overflow of the SEL beyond the allocated space will overwrite the old- est entries in the SEL, while setting the overflow flag.

12.3 Sensor Monitoring

The BMC monitors system hardware and reports system health. The information gathered from physical sen- sors is translated into IPMI sensors as part of the IPMI sensor model. The BMC also reports various system state changes by maintaining virtual sensors that are not specifically tied to physical hardware. This section describes general aspects of BMC sensor management as well as describing how specific sensor types are modeled. Unless otherwise specified, the term “sensor” refers to the IPMI sensor-model definition of a sen- sor.

• Sensor scanning
• BIOS event-only sensors
• Margin sensors
• IPMI watchdog sensor
• BMC watchdog sensor
• BMC system management health monitoring
• VR watchdog timer
• System airflow monitoring sensors - valid for Intel® server chassis only
• Fan monitoring sensors
• Thermal monitoring sensors
• Voltage monitoring sensors
• CATERR sensor
• LAN leash event monitoring
• CMOS battery monitoring
• NMI (diagnostic interrupt) sensor

12.3.1 Sensor Re-arm Behavior

12.3.1.1 Manual versus Automatic Re-arm Sensors

Sensors can be re-armed either manually or automatically. An automatic re-arm sensor re-arms (clears) the assertion event state for a threshold or offset if that threshold or offset is de-asserted after having been as- serted. This allows a subsequent assertion of the threshold or an offset to generate a new event and associ- ated side-effect. An example side-effect is boosting fans due to an upper critical threshold crossing of a tem- perature sensor. The event state and the input state (value) of the sensor track each other. Most sensors are of the auto-rearm type. A manual re-arm sensor does not clear the assertion state even when the threshold or offset becomes de- asserted. In this case, the event state and the input state (value) of the sensor do not track each other. The event assertion state is "sticky". The following methods can be used to re-arm a sensor:

• Automatic re-arm – Only applies to sensors that are designated as auto re-arm.
• IPMI command – Re-arm sensor event.
• BMC internal method – The BMC may re-arm certain sensors due to a trigger condition. For example, some sensors may be re-armed due to a system reset. A BMC reset re-arms all sensors.
• System reset or DC power cycle – Re-arms all system fan sensors.

Intel® Server Board S2600WF Product Family Technical Product Specification 118

12.3.2 Thermal Monitoring

The BMC provides monitoring of component and board temperature sensing devices. This monitoring capa- bility is instantiated in the form of IPMI analog/threshold or discrete sensors, depending on the nature of the measurement. For analog/threshold sensors, with the exception of processor temperature sensors, critical and non-critical thresholds (upper and lower) are set through SDRs and event generation enabled for both assertion and de- assertion events. For discrete sensors, both assertion and de-assertion event generation are enabled. Mandatory monitoring of platform thermal sensors includes:

• Inlet temperature (physical sensor is typically on system front panel or HDD back plane),
• Board ambient thermal sensors,
• Processor temperature,
• Memory (DIMM) temperature,
• CPU voltage regulator down (VRD) hot monitoring, and
• Power supply unit (PSU) inlet temperature (only supported for PMBus*-compliant PSUs). Additionally, the BMC firmware may create virtual sensors that are based on a combination or aggregation of multiple physical thermal sensors and the application of a mathematical formula to thermal or power sensor readings.

12.3.3 Standard Fan Management

The BMC controls and monitors the system fans. Each fan is associated with a fan speed sensor that detects fan failure and may also be associated with a fan presence sensor for hot-swap support. For redundant fan configurations, the fan failure and presence status determines the fan redundancy sensor state. The system fans are divided into fan domains, each of which has a separate fan speed control signal and a separate configurable fan control policy. A fan domain can have a set of temperature and fan sensors associ- ated with it. These are used to determine the current fan domain state. A fan domain has three states: sleep, boost, and nominal. The sleep and boost states have fixed (but configu- rable through OEM SDRs) fan speeds associated with them. The nominal state has a variable speed deter- mined by the fan domain policy. An OEM SDR record is used to configure the fan domain policy. The fan domain state is controlled by several factors. The factors for the boost state are listed below in order of precedence, high to low. If any of these conditions apply, the fans are set to a fixed boost state speed.

• An associated fan is in a critical state or missing. The SDR describes which fan domains are boosted in response to a fan failure or removal in each domain. If a fan is removed when the system is in fans-off mode, it is not detected and there is not any fan boost until the system comes out of fans-off mode.
• Any associated temperature sensor is in a critical state. The SDR describes which temperature-thresh- old violations cause fan boost for each fan domain.
• The BMC is in firmware update mode, or the operational firmware is corrupted. A fan domain’s nominal fan speed can be configured as static (fixed value) or controlled by the state of one or more associated temperature sensors.

12.3.3.1 Hot-Swappable Fans

Hot-swappable fans, which can be removed and replaced while the system is powered on and operating, are supported. The BMC implements fan presence sensors for each hot-swappable fan.

Intel® Server Board S2600WF Product Family Technical Product Specification 119 When a fan is not present, the associated fan speed sensor is put into the reading/unavailable state, and any associated fan domains are put into the boost state. The fans may already be boosted due to a previous fan failure or fan removal. When a removed fan is inserted, the associated fan speed sensor is re-armed. If there are no other critical conditions causing a fan boost condition, the fan speed returns to the nominal state. Power cycling or reset- ting the system re-arms the fan speed sensors and clears fan failure conditions. If the failure condition is still present, the boost state returns once the sensor has re-initialized and the threshold violation is detected again.

12.3.3.2 Fan Redundancy Detection

The BMC supports redundant fan monitoring and implements a fan redundancy sensor. A fan redundancy sensor generates events when its associated set of fans transitions between redundant and non-redundant states, as determined by the number and health of the fans. The definition of fan redundancy is configura- tion dependent. The BMC allows redundancy to be configured on a per fan redundancy sensor basis through OEM SDR records. A fan failure or removal of hot-swap fans up to the number of redundant fans specified in the SDR in a fan configuration is a non-critical failure and is reflected in the front panel status. A fan failure or removal that exceeds the number of redundant fans is a non-fatal, insufficient-resources condition and is reflected in the front panel status as a non-fatal error. Redundancy is checked only when the system is in the DC-on state. Fan redundancy changes that occur when the system is DC-off or when AC is removed will not be logged until the system is turned on.

12.3.3.3 Fan Domains

System fan speeds are controlled through pulse width modulation (PWM) signals, which are driven sepa- rately for each domain by integrated PWM hardware. Fan speed is changed by adjusting the duty cycle, which is the percentage of time the signal is driven high in each pulse. The BMC controls the average duty cycle of each PWM signal through direct manipulation of the integrated PWM control registers. The same device may drive multiple PWM signals.

12.3.3.4 Thermal and Acoustic Management

This feature refers to enhanced fan management to keep the system optimally cooled while reducing the amount of noise generated by the system fans. Aggressive acoustics standards might require a trade-off be- tween fan speed and system performance parameters that contribute to the cooling requirements, primarily memory bandwidth. The BIOS, BMC, and SDRs work together to provide control over how this trade-off is determined. This capability requires the BMC to access temperature sensors on the individual memory DIMMs. Addition- ally, closed-loop thermal throttling is only supported with DIMMs with temperature sensors.

12.3.3.5 Thermal Sensor Input to Fan Speed Control

The BMC uses various IPMI sensors as inputs to the fan speed control. Some of the sensors are IPMI models of actual physical sensors whereas some are virtual sensors whose values are derived from physical sensors using calculations and/or tabular information. The following IPMI thermal sensors are used as the input to the fan speed control:

• Front panel temperature sensor
• CPU margin sensors 2, 4, 5
• DIMM thermal margin sensors 2, 4

• Exit air temperature sensor 1, 7, 9
• PCH temperature sensor 3, 5
• Onboard Ethernet controller temperature sensors 3, 5
• Add-in SAS module temperature sensors 3, 5
• PSU thermal sensor 3, 8
• CPU VR temperature sensors 3, 6
• DIMM VR temperature sensors 3, 6
• BMC temperature sensor 3, 6
• Global aggregate thermal margin sensors 7
• Hot swap backplane temperature sensors
• Intel® OCP module temperature sensor (with option installed)
• Intel® SAS module (with option installed)
• Riser card temperature sensors (2U systems only)
• Intel® Xeon Phi™ coprocessor (2U system only with option installed) Notes:

1 For fan speed control in Intel chassis

2 Temperature margin to max junction temp

3 Absolute temperature

4 PECI value or margin value

5 On-die sensor

6 Onboard sensor

7 Virtual sensor

8 Available only when PSU has PMBus

9 Calculated estimate

Figure 78 shows a high-level illustration of the fan speed control structure that determines fan speed. Figure 78. High-level fan speed control process

12.3.3.6 Fan Boosting Due to Fan Failures

• Intrusion
• Fan failure
• Power supply failure Memory throttle settings Sensors:
• Front panel
• Processor margin
• Other sensors (chipset, temp, etc.) Policy:
• CLTT
• Acoustic/ performance
• Auto-profile configuration System behaviors

Intel® Server Board S2600WF Product Family Technical Product Specification 121 (for PMBus*-compliant power supplies only). This means that if a system has six fans, there are six different fan fail reactions.

12.3.4 Memory Thermal Management

The system memory is the most complex subsystem to manage thermally, as it requires substantial interac- tions between the BMC, BIOS, and the embedded memory controller hardware. This section provides an overview of this management capability from a BMC perspective.

12.3.4.1 Memory Thermal Throttling

The system supports thermal management through closed loop throttling (CLTT) only. Throttling levels are changed dynamically to cap throttling based on memory and system thermal conditions as determined by the system and DIMM power and thermal parameters. The BMC fan speed control functionality is related to the memory throttling mechanism used. The following terminology is used for the various memory throttling options:

• Static Closed-Loop Thermal Throttling (Static-CLTT): CLTT control registers are configured by the BIOS Memory Reference Code (MRC) during POST. The memory throttling is run as a closed-loop sys- tem with the DIMM temperature sensors as the control input. Otherwise, the system does not change any of the throttling control registers in the embedded memory controller during runtime.
• Dynamic Closed-Loop Thermal Throttling (Dynamic-CLTT): CLTT control registers are configured by BIOS MRC during POST. The memory throttling is run as a closed-loop system with the DIMM tem- perature sensors as the control input. Adjustments are made to the throttling during runtime based on changes in system cooling (fan speed). Intel® Server Systems supporting the 1st and 2nd Gen Intel® Xeon® processor Scalable families support a type of CLTT, called a hybrid CLTT, for which the integrated memory controller estimates the DRAM temper- ature in between actual reads of the TSODs. Hybrid CLTT is used on all Intel Server Systems supporting the Intel Xeon processor Scalable family that have DIMMs with thermal sensors. Therefore, the terms Dynamic- CLTT and Static-CLTT are really referring to this “hybrid” mode. Note that if the IMC’s polling of the TSODs is interrupted, the temperature readings that the BMC gets from the IMC are these estimated values.

12.3.4.2 Dynamic (Hybrid) CLTT

The system supports dynamic (memory) CLTT for which the BMC firmware dynamically modifies thermal off- set registers in the IMC during runtime based on changes in system cooling (fan speed). For static CLTT, a fixed offset value is applied to the TSOD reading to get the die temperature; however this is does not provide results as accurate when the offset takes into account the current airflow over the DIMM, as is done with dy- namic CLTT. To support this feature, the BMC firmware derives the air velocity for each fan domain based on the PWM value being driven for the domain. Since this relationship is dependent on the chassis configuration, a method must be used which supports this dependency (for example, through OEM SDR) that establishes a lookup table providing this relationship. BIOS has an embedded lookup table that provides thermal offset values for each DIMM type and air velocity range (three ranges of air velocity are supported). During system boot, BIOS provides three offset values (corresponding to the three air velocity ranges) to the BMC for each enabled DIMM. Using this data the BMC firmware constructs a table that maps the offset value corresponding to a given air velocity range for each DIMM. During runtime the BMC applies an averaging algorithm to determine the target offset value corre- sponding to the current air velocity and then the BMC writes this new offset value into the IMC thermal offset register for the DIMM.

12.3.5 Power Management Bus (PMBus*)

Intel ME to monitor them for status and/or power metering purposes.

12.3.6 Component Fault LED Control

LEDs are owned by the BMC and some by the BIOS. A description of these LEDs is below and in Table 60.

• DIMM fault LEDs – The BMC owns the hardware control for these LEDs. The LEDs reflect the state of BIOS-owned event-only sensors. When the BIOS detects a DIMM fault condition, it sends an IPMI OEM command (Set Fault Indication) to the BMC to instruct the BMC to turn on the associated DIMM Fault LED. These LEDs are only active when the system is in the ‘on’ state. The BMC does not activate or change the state of the LEDs unless instructed by the BIOS.
• HDD status LEDs – The HSBP PSoC* of supported Intel and non-Intel chassis owns the hardware con- trol for these LEDs and detection of the fault/status conditions that the LEDs reflect.
• CPU fault LEDs – The BMC owns control for these LEDs. An LED is lit if there is an MSID mismatch where the CPU power rating is incompatible with the board.

Table 60. Component fault LEDs

Intel® Server Board S2600WF Product Family Technical Product Specification 123 Appendix A. Integration and Usage Tips

• When adding or removing components or peripherals from the server board, power cords must be disconnected from the server. With power applied to the server, standby voltages are still present even though the server board is powered off.
• This server board supports the 1st and 2nd Gen Intel® Xeon® processor Scalable families with a Thermal Design Power (TDP) of up to and including 205 Watts. Previous generations of the Intel® Xeon® processors are not supported. Server systems using this server board may or may not meet the TDP design limits of the server board. Validate the TDP limits of the server system before selecting a processor.
• Processors must be installed in order. CPU 1 must be populated for the server board to operate.
• The 2U 3-slot riser card and Riser Card Slots #2 and #3 on the server board can only be used in dual processor configurations.
• The riser card slots are specifically designed to support riser cards only. Attempting to install a PCIe* add-in card directly into a riser card slot on the server board may damage the server board, the add- in card, or both.
• For the best performance, the number of DDR4 DIMMs installed should be balanced across both processor sockets and memory channels.
• On the back edge of the server board are eight diagnostic LEDs that display a sequence of amber POST codes during the boot process. If the server board hangs during POST, the LEDs display the last POST event run before the hang.
• The system status LED is set to a steady amber color for all fatal errors that are detected during processor initialization. A steady amber system status LED indicates that an unrecoverable system failure condition has occurred.
• RAID partitions created using either Intel® VROC (SATA RAID) or Intel® ESRT2 cannot span across the two embedded SATA controllers. Only drives attached to a common SATA controller can be included in a RAID partition.

cludes a bank of eight POST code diagnostic LEDs on the back edge of the server board. the back edge of the server board. run prior to the error occurring, helping to isolate the possible cause of the hang condition. bits, LED 0 represents the least significant bit (LSB) and LED 3 represents the most significant bit (MSB). Figure 79. Onboard POST diagnostic LED location and definition Note: Diagnostic LEDs are best read and decoded when viewing the LEDs from the back of the system. lower nibble bits represented by the green LEDs equal 1100b or Ch. The two are concatenated as ACh. Table 61. POST progress code LED example

settings, and initialization of applicable RAS configurations. erational path at each step. Table 62. MRC progress codes get logged as SEL events. Table 63 lists all MRC fatal errors that are displayed to the diagnostic LEDs. codes by the accompanying memory failure beep code of three long beeps as identified in Table 66.

Table 63. MRC fatal error codes 03h = No memory installed. All channels are disabled. 01h = Software memtest failure. 02h = Hardware memtest failed. 02h = Violation of DIMM population rules. 04h = UDIMMs are not supported. 05h = Unsupported DIMM Voltage.

Table 64 provides a list of all POST progress codes. Table 64. POST progress codes 05 0 0 0 0 0 1 0 1 SEC Core At Power On Begin. 06 0 0 0 0 0 1 1 0 Early CPU initialization during SEC Phase. A1 1 0 1 0 0 0 0 1 Collect info such as SBSP, boot mode, reset type, etc.

Intel® Server Board S2600WF Product Family Technical Product Specification 128 Post Code (Hex) Upper Nibble Lower Nibble Description 8h 4h 2h 1h 8h 4h 2h 1h 7D 0 1 1 1 1 1 0 1 DXE Removable Media Detect 7E 0 1 1 1 1 1 1 0 DXE Removable Media Detected 90 1 0 0 1 0 0 0 0 DXE BDS started 91 1 0 0 1 0 0 0 1 DXE BDS connect drivers 92 1 0 0 1 0 0 1 0 DXE PCI bus begin 93 1 0 0 1 0 0 1 1 DXE PCI Bus HPC Init 94 1 0 0 1 0 1 0 0 DXE PCI Bus enumeration 95 1 0 0 1 0 1 0 1 DXE PCI Bus resource requested 96 1 0 0 1 0 1 1 0 DXE PCI Bus assign resource 97 1 0 0 1 0 1 1 1 DXE CON_OUT connect 98 1 0 0 1 1 0 0 0 DXE CON_IN connect 99 1 0 0 1 1 0 0 1 DXE SIO Init 9A 1 0 0 1 1 0 1 0 DXE USB start 9B 1 0 0 1 1 0 1 1 DXE USB reset 9C 1 0 0 1 1 1 0 0 DXE USB detect 9D 1 0 0 1 1 1 0 1 DXE USB enable A1 1 0 1 0 0 0 0 1 DXE IDE begin A2 1 0 1 0 0 0 1 0 DXE IDE reset A3 1 0 1 0 0 0 1 1 DXE IDE detect A4 1 0 1 0 0 1 0 0 DXE IDE enable A5 1 0 1 0 0 1 0 1 DXE SCSI begin A6 1 0 1 0 0 1 1 0 DXE SCSI reset A7 1 0 1 0 0 1 1 1 DXE SCSI detect A8 1 0 1 0 1 0 0 0 DXE SCSI enable AB 1 0 1 0 1 0 1 1 DXE SETUP start AC 1 0 1 0 1 1 0 0 DXE SETUP input wait AD 1 0 1 0 1 1 0 1 DXE Ready to Boot AE 1 0 1 0 1 1 1 0 DXE Legacy Boot AF 1 0 1 0 1 1 1 1 DXE Exit Boot Services B0 1 0 1 1 0 0 0 0 RT Set Virtual Address Map Begin B1 1 0 1 1 0 0 0 1 RT Set Virtual Address Map End B2 1 0 1 1 0 0 1 0 DXE Legacy Option ROM init B3 1 0 1 1 0 0 1 1 DXE Reset system B4 1 0 1 1 0 1 0 0 DXE USB Hot plug B5 1 0 1 1 0 1 0 1 DXE PCI BUS Hot plug B8 1 0 1 1 1 0 0 0 PWRBTN Shutdown B9 1 0 1 1 1 0 0 1 SLEEP Shutdown C0 1 1 0 0 0 0 0 0 End of DXE C7 1 1 0 0 0 1 1 1 DXE ACPI Enable 0 0 0 0 0 0 0 0 0 Clear POST Code

Intel® Server Board S2600WF Product Family Technical Product Specification 129 Post Code (Hex) Upper Nibble Lower Nibble Description 8h 4h 2h 1h 8h 4h 2h 1h S3 Resume E0 1 1 1 0 0 0 0 0 S3 Resume PEIM (S3 started) E1 1 1 1 0 0 0 0 1 S3 Resume PEIM (S3 boot script) E2 1 1 1 0 0 0 1 0 S3 Resume PEIM (S3 Video Repost) E3 1 1 1 0 0 0 1 1 S3 Resume PEIM (S3 OS wake) BIOS Recovery F0 1 1 1 1 0 0 0 0 PEIM which detected forced Recovery condition F1 1 1 1 1 0 0 0 1 PEIM which detected User Recovery condition F2 1 1 1 1 0 0 1 0 Recovery PEIM (Recovery started) F3 1 1 1 1 0 0 1 1 Recovery PEIM (Capsule found) F4 1 1 1 1 0 1 0 0 Recovery PEIM (Capsule loaded)

Intel® Server Board S2600WF Product Family Technical Product Specification 130 Appendix C. POST Code Errors Most error conditions encountered during POST are reported using POST error codes. These codes repre- sent specific failures, warnings, or information. POST error codes may be displayed in the error manager dis- play screen and are always logged to the System Event Log (SEL). Logged events are available to system management applications, including remote and Out of Band (OOB) management. There are exception cases in early initialization where system resources are not adequately initialized for handling POST Error Code reporting. These cases are primarily fatal error conditions resulting from initializa- tion of processors and memory, and they are handed by a diagnostic LED display with a system halt. Table 65 lists the supported POST error codes. Each error code is assigned an error type which determines the action the BIOS takes when the error is encountered. Error types include minor, major, and fatal. The BIOS action for each is defined as follows:

• Minor: An error message may be displayed to the screen or to the BIOS setup error manager and the POST error code is logged to the SEL. The system continues booting in a degraded state. The user may want to replace the erroneous unit. The “POST Error Pause” option setting in the BIOS setup does not have any effect on this error.
• Major: An error message is displayed to the error manager screen and an error is logged to the SEL. If the BIOS setup option “Post Error Pause” is enabled, operator intervention is required to continue booting the system. If the BIOS setup option “POST Error Pause” is disabled, the system continues to boot. Note: For 0048 “Password check failed”, the system halts and then, after the next reset/reboot, displays the error code on the error manager screen.
• Fatal: If the system cannot boot, POST halts and display the following message: Unrecoverable fatal error found. System will not boot until the error is resolved Press <F2> to enter setup When the <F2> key on the keyboard is pressed, the error message is displayed on the error manager screen and an error is logged to the system event log (SEL) with the POST error code. The system cannot boot unless the errror is resolved. The faulty component must be replaced. The “POST Error Pause” option setting in the BIOS setup does not have any effect on this error. Note: The POST error codes in the following table are common to all current generation Intel® server plat- forms. Features present on a given server board/system determine which of the listed error codes are sup- ported.

Table 65. POST error messages and handling

0012 System RTC date/time not set Major

0140 PCI component encountered a PERR error Major

0141 PCI resource conflict Major

0146 PCI out of resources error

0195 Processor Intel(R) UPI link frequencies unable to synchro-

5220 BIOS Settings reset to default settings Major

5221 Passwords cleared by jumper Major

5224 Password clear jumper is Set

8130 Processor 01 disabled Major

8131 Processor 02 disabled Major

8160 Processor 01 unable to apply microcode update Major

8161 Processor 02 unable to apply microcode update Major

8170 Processor 01 failed Self Test (BIST) Major

8171 Processor 02 failed Self Test (BIST) Major

8180 Processor 01 microcode update not found Minor

8181 Processor 02 microcode update not found Minor

8305 Hot Swap Controller failure Major

Intel® Server Board S2600WF Product Family Technical Product Specification 132 Error Code Error Message Action message Response 85FC Memory component could not be configured in the se- lected RAS mode Major 8501 Memory Population Error Please plug DIMM at right population. Major 8520 Memory failed test/initialization CPU1_DIMM_A1 please remove the disabled DIMM. Major 8521 Memory failed test/initialization CPU1_DIMM_A2 please remove the disabled DIMM. Major 8522 Memory failed test/initialization CPU1_DIMM_A3 please remove the disabled DIMM. Major 8523 Memory failed test/initialization CPU1_DIMM_B1 please remove the disabled DIMM. Major 8524 Memory failed test/initialization CPU1_DIMM_B2 please remove the disabled DIMM. Major 8525 Memory failed test/initialization CPU1_DIMM_B3 please remove the disabled DIMM. Major 8526 Memory failed test/initialization CPU1_DIMM_C1 please remove the disabled DIMM. Major 8527 Memory failed test/initialization CPU1_DIMM_C2 please remove the disabled DIMM. Major 8528 Memory failed test/initialization CPU1_DIMM_C3 please remove the disabled DIMM. Major 8529 Memory failed test/initialization CPU1_DIMM_D1 please remove the disabled DIMM. Major 852A Memory failed test/initialization CPU1_DIMM_D2 please remove the disabled DIMM. Major 852B Memory failed test/initialization CPU1_DIMM_D3 please remove the disabled DIMM. Major 852C Memory failed test/initialization CPU1_DIMM_E1 please remove the disabled DIMM. Major 852D Memory failed test/initialization CPU1_DIMM_E2 please remove the disabled DIMM. Major 852E Memory failed test/initialization CPU1_DIMM_E3 please remove the disabled DIMM. Major 852F Memory failed test/initialization CPU1_DIMM_F1 please remove the disabled DIMM. Major 8530 Memory failed test/initialization CPU1_DIMM_F2 please remove the disabled DIMM. Major 8531 Memory failed test/initialization CPU1_DIMM_F3 please remove the disabled DIMM. Major 8532 Memory failed test/initialization CPU1_DIMM_G1 please remove the disabled DIMM. Major 8533 Memory failed test/initialization CPU1_DIMM_G2 please remove the disabled DIMM. Major 8534 Memory failed test/initialization CPU1_DIMM_G3 please remove the disabled DIMM. Major 8535 Memory failed test/initialization CPU1_DIMM_H1 please remove the disabled DIMM. Major 8536 Memory failed test/initialization CPU1_DIMM_H2 please remove the disabled DIMM. Major 8537 Memory failed test/initialization CPU1_DIMM_H3 please remove the disabled DIMM. Major 8538 Memory failed test/initialization CPU2_DIMM_A1 please remove the disabled DIMM. Major 8539 Memory failed test/initialization CPU2_DIMM_A2 please remove the disabled DIMM. Major 853A Memory failed test/initialization CPU2_DIMM_A3 please remove the disabled DIMM. Major 853B Memory failed test/initialization CPU2_DIMM_B1 please remove the disabled DIMM. Major 853C Memory failed test/initialization CPU2_DIMM_B2 please remove the disabled DIMM. Major 853D Memory failed test/initialization CPU2_DIMM_B3 please remove the disabled DIMM. Major 853E Memory failed test/initialization CPU2_DIMM_C1 please remove the disabled DIMM. Major 853F (Go to 85C0) Memory failed test/initialization CPU2_DIMM_C2 please remove the disabled DIMM. Major 8540 Memory disabled.CPU1_DIMM_A1 please remove the disabled DIMM. Major 8541 Memory disabled.CPU1_DIMM_A2 please remove the disabled DIMM. Major 8542 Memory disabled.CPU1_DIMM_A3 please remove the disabled DIMM. Major 8543 Memory disabled.CPU1_DIMM_B1 please remove the disabled DIMM. Major

Intel® Server Board S2600WF Product Family Technical Product Specification 133 Error Code Error Message Action message Response 8544 Memory disabled.CPU1_DIMM_B2 please remove the disabled DIMM. Major 8545 Memory disabled.CPU1_DIMM_B3 please remove the disabled DIMM. Major 8546 Memory disabled.CPU1_DIMM_C1 please remove the disabled DIMM. Major 8547 Memory disabled.CPU1_DIMM_C2 please remove the disabled DIMM. Major 8548 Memory disabled.CPU1_DIMM_C3 please remove the disabled DIMM. Major 8549 Memory disabled.CPU1_DIMM_D1 please remove the disabled DIMM. Major 854A Memory disabled.CPU1_DIMM_D2 please remove the disabled DIMM. Major 854B Memory disabled.CPU1_DIMM_D3 please remove the disabled DIMM. Major 854C Memory disabled.CPU1_DIMM_E1 please remove the disabled DIMM. Major 854D Memory disabled.CPU1_DIMM_E2 please remove the disabled DIMM. Major 854E Memory disabled.CPU1_DIMM_E3 please remove the disabled DIMM. Major 854F Memory disabled.CPU1_DIMM_F1 please remove the disabled DIMM. Major 8550 Memory disabled.CPU1_DIMM_F2 please remove the disabled DIMM. Major 8551 Memory disabled.CPU1_DIMM_F3 please remove the disabled DIMM. Major 8552 Memory disabled.CPU1_DIMM_G1 please remove the disabled DIMM. Major 8553 Memory disabled.CPU1_DIMM_G2 please remove the disabled DIMM. Major 8554 Memory disabled.CPU1_DIMM_G3 please remove the disabled DIMM. Major 8555 Memory disabled.CPU1_DIMM_H1 please remove the disabled DIMM. Major 8556 Memory disabled.CPU1_DIMM_H2 please remove the disabled DIMM. Major 8557 Memory disabled.CPU1_DIMM_H3 please remove the disabled DIMM. Major 8558 Memory disabled.CPU2_DIMM_A1 please remove the disabled DIMM. Major 8559 Memory disabled.CPU2_DIMM_A2 please remove the disabled DIMM. Major 855A Memory disabled.CPU2_DIMM_A3 please remove the disabled DIMM. Major 855B Memory disabled.CPU2_DIMM_B1 please remove the disabled DIMM. Major 855C Memory disabled.CPU2_DIMM_B2 please remove the disabled DIMM. Major 855D Memory disabled.CPU2_DIMM_B3 please remove the disabled DIMM. Major 855E Memory disabled.CPU2_DIMM_C1 please remove the disabled DIMM. Major 855F (Go to 85D0) Memory disabled.CPU2_DIMM_C2 please remove the disabled DIMM. Major

8560 Memory encountered a Serial Presence Detection(SPD) fail-

ure.CPU1_DIMM_A1 Major

8561 Memory encountered a Serial Presence Detection(SPD) fail-

ure.CPU1_DIMM_A2 Major

8562 Memory encountered a Serial Presence Detection(SPD) fail-

ure.CPU1_DIMM_A3 Major

8563 Memory encountered a Serial Presence Detection(SPD) fail-

ure.CPU1_DIMM_B1 Major

8564 Memory encountered a Serial Presence Detection(SPD) fail-

ure.CPU1_DIMM_B2 Major

8565 Memory encountered a Serial Presence Detection(SPD) fail-

ure.CPU1_DIMM_B3 Major

Intel® Server Board S2600WF Product Family Technical Product Specification 134 Error Code Error Message Action message Response

8566 Memory encountered a Serial Presence Detection(SPD) fail-

ure.CPU1_DIMM_C1 Major

8567 Memory encountered a Serial Presence Detection (SPD)

failure.CPU1_DIMM_C2 Major

8568 Memory encountered a Serial Presence Detection (SPD)

failure.CPU1_DIMM_C3 Major

8569 Memory encountered a Serial Presence Detection(SPD) fail-

ure.CPU1_DIMM_D1 Major 856A Memory encountered a Serial Presence Detection(SPD) fail- ure.CPU1_DIMM_D2 Major 856B Memoryencountered a Serial Presence Detection(SPD) fail- ure.CPU1_DIMM_D3 Major 856C Memory encountered a Serial Presence Detection(SPD) fail- ure.CPU1_DIMM_E1 Major 856D Memory encountered a Serial Presence Detection(SPD) fail- ure.CPU1_DIMM_E2 Major 856E Memory encountered a Serial Presence Detection(SPD) fail- ure.CPU1_DIMM_E3 Major 856F Memory encountered a Serial Presence Detection(SPD) fail- ure.CPU1_DIMM_F1 Major

8570 Memory encountered a Serial Presence Detection(SPD) fail-

ure.CPU1_DIMM_F2 Major

8571 Memory encountered a Serial Presence Detection(SPD) fail-

ure.CPU1_DIMM_F3 Major

8572 Memory encountered a Serial Presence Detection(SPD) fail-

ure.CPU1_DIMM_G1 Major

8573 Memory encountered a Serial Presence Detection(SPD) fail-

ure.CPU1_DIMM_G2 Major

8574 Memory encountered a Serial Presence Detection(SPD) fail-

ure.CPU1_DIMM_G3 Major

8575 Memory encountered a Serial Presence Detection(SPD) fail-

ure.CPU1_DIMM_H1 Major

8576 Memory encountered a Serial Presence Detection(SPD) fail-

ure.CPU1_DIMM_H2 Major

8577 Memory encountered a Serial Presence Detection(SPD) fail-

ure.CPU1_DIMM_H3 Major

8578 Memory encountered a Serial Presence Detection(SPD) fail-

ure.CPU2_DIMM_A1 Major

8579 Memory encountered a Serial Presence Detection(SPD) fail-

ure.CPU2_DIMM_A2 Major 857A Memory encountered a Serial Presence Detection(SPD) fail- ure.CPU2_DIMM_A3 Major 857B Memory encountered a Serial Presence Detection(SPD) fail- ure.CPU2_DIMM_B1 Major 857C Memory encountered a Serial Presence Detection(SPD) fail- ure.CPU2_DIMM_B2 Major 857D Memory encountered a Serial Presence Detection(SPD) fail- ure.CPU2_DIMM_B3 Major 857E Memory encountered a Serial Presence Detection(SPD) fail- ure.CPU2_DIMM_C1 Major 857F (Go to 85E0) Memory encountered a Serial Presence Detection(SPD) fail- ure.CPU2_DIMM_C2 Major

Intel® Server Board S2600WF Product Family Technical Product Specification 135 Error Code Error Message Action message Response 85C0 Memory failed test/initialization CPU2_DIMM_C3 please remove the disabled DIMM. Major 85C1 Memory failed test/initialization CPU2_DIMM_D1 please remove the disabled DIMM. Major 85C2 Memory failed test/initialization CPU2_DIMM_D2 please remove the disabled DIMM. Major 85C3 Memory failed test/initialization CPU2_DIMM_D3 please remove the disabled DIMM. Major 85C4 Memory failed test/initialization CPU2_DIMM_E1 please remove the disabled DIMM. Major 85C5 Memory failed test/initialization CPU2_DIMM_E2 please remove the disabled DIMM. Major 85C6 Memory failed test/initialization CPU2_DIMM_E3 please remove the disabled DIMM. Major 85C7 Memory failed test/initialization CPU2_DIMM_F1 please remove the disabled DIMM. Major 85C8 Memory failed test/initialization CPU2_DIMM_F2 please remove the disabled DIMM. Major 85C9 Memory failed test/initialization CPU2_DIMM_F3 please remove the disabled DIMM. Major 85CA Memory failed test/initialization CPU2_DIMM_G1 please remove the disabled DIMM. Major 85CB Memory failed test/initialization CPU2_DIMM_G2 please remove the disabled DIMM. Major 85CC Memory failed test/initialization CPU2_DIMM_G3 please remove the disabled DIMM. Major 85CD Memory failed test/initialization CPU2_DIMM_H1 please remove the disabled DIMM. Major 85CE Memory failed test/initialization CPU2_DIMM_H2 please remove the disabled DIMM. Major 85CF Memory failed test/initialization CPU2_DIMM_H3 please remove the disabled DIMM. Major 85D0 Memory disabled.CPU2_DIMM_C3 please remove the disabled DIMM. Major 85D1 Memory disabled.CPU2_DIMM_D1 please remove the disabled DIMM. Major 85D2 Memory disabled.CPU2_DIMM_D2 please remove the disabled DIMM. Major 85D3 Memory disabled.CPU2_DIMM_D3 please remove the disabled DIMM. Major 85D4 Memory disabled.CPU2_DIMM_E1 please remove the disabled DIMM. Major 85D5 Memory disabled.CPU2_DIMM_E2 please remove the disabled DIMM. Major 85D6 Memory disabled.CPU2_DIMM_E3 please remove the disabled DIMM. Major 85D7 Memory disabled.CPU2_DIMM_F1 please remove the disabled DIMM. Major 85D8 Memory disabled.CPU2_DIMM_F2 please remove the disabled DIMM. Major 85D9 Memory disabled.CPU2_DIMM_F3 please remove the disabled DIMM. Major 85DA Memory disabled.CPU2_DIMM_G1 please remove the disabled DIMM. Major 85DB Memory disabled.CPU2_DIMM_G2 please remove the disabled DIMM. Major 85DC Memory disabled.CPU2_DIMM_G3 please remove the disabled DIMM. Major 85DD Memory disabled.CPU2_DIMM_H1 please remove the disabled DIMM. Major 85DE Memory disabled.CPU2_DIMM_H2 please remove the disabled DIMM. Major 85DF Memory disabled.CPU2_DIMM_H3 please remove the disabled DIMM. Major 85E0 Memory encountered a Serial Presence Detection(SPD) fail- ure.CPU2_DIMM_C3 Major 85E1 Memory encountered a Serial Presence Detection (SPD) failure. CPU2_DIMM_D1 Major 85E2 Memory encountered a Serial Presence Detection (SPD) failure.CPU2_DIMM_D2 Major 85E3 Memory encountered a Serial Presence Detection(SPD) fail- ure.CPU2_DIMM_D3 Major

Intel® Server Board S2600WF Product Family Technical Product Specification 136 Error Code Error Message Action message Response 85E4 Memory encountered a Serial Presence Detection(SPD) fail- ure.CPU2_DIMM_E1 Major 85E5 Memory encountered a Serial Presence Detection(SPD) fail- ure.CPU2_DIMM_E2 Major 85E6 Memory encountered a Serial Presence Detection(SPD) fail- ure.CPU2_DIMM_E3 Major 85E7 Memory encountered a Serial Presence Detection (SPD) failure.CPU2_DIMM_F1 Major 85E8 Memory encountered a Serial Presence Detection(SPD) fail- ure.CPU2_DIMM_F2 Major 85E9 Memory encountered a Serial Presence Detection(SPD) fail- ure.CPU2_DIMM_F3 Major 85EA Memory encountered a Serial Presence Detection(SPD) fail- ure.CPU2_DIMM_G1 Major 85EB Memory encountered a Serial Presence Detection(SPD) fail- ure. CPU2_DIMM_G2 Major 85EC Memory encountered a Serial Presence Detection(SPD) fail- ure.CPU2_DIMM_G3 Major 85ED Memory encountered a Serial Presence Detection(SPD) fail- ure.CPU2_DIMM_H1 Major 85EE Memory encountered a Serial Presence Detection(SPD) fail- ure.CPU2_DIMM_H2 Major 85EF Memory encountered a Serial Presence Detection(SPD) fail- ure.CPU2_DIMM_H3 Major

8604 POST Reclaim of non-critical NVRAM variables Minor

8605 BIOS Settings are corrupted Major

8606 NVRAM variable space was corrupted and has been rei-

8607 Recovery boot has been initiated. Note: The Primary BIOS image may be corrupted or the system may hang during POST. A BIOS update is required. Fatal A100 BIOS ACM Error Major A421 PCI component encountered a SERR error Fatal A5A0 PCI Express component encountered a PERR error Minor A5A1 PCI Express component encountered an SERR error Fatal A6A0 DXE Boot Services driver: Not enough memory available to shadow a Legacy Option ROM. Please disable OpRom at SETUP to save runtime memory. Minor

Table 66. POST error beep codes or inserted or removed during runtime. tected a potential violation of system security. ily/core/cache mismatch was detected. started N/A BIOS recovery boot has been initiated. recovery is initiated that it sounds like a 2-4 beep code. each time the problem is discovered, such as on each power-up attempt, but are not sounded continuously. Table 67. Integrated BMC beep codes

Intel® Server Board S2600WF Product Family Technical Product Specification 138 Appendix D. Statement of Volatile Memory Components This section is used to identify the volatile and non-volatile memory components of the Intel® Server Board S2600WF product family. Table 68 provides the following data for each identified component.

• Component Type: Three types of components are on the server board assembly: o Non-volatile: Non-volatile memory is persistent, and is not cleared when power is removed from the system. Non-volatile memory must be erased to clear data. The exact method of clearing these areas varies by the specific component. Some areas are required for normal op- eration of the server, and clearing these areas may render the server board inoperable o Volatile: Volatile memory is cleared automatically when power is removed from the system. o Battery powered RAM: Battery powered RAM is similar to volatile memory, but is powered by a battery on the server board. Data in battery powered RAM is persistent until the battery is removed from the server board.
• Size: Size of each component in bits, Kbits, Mbits, bytes, kilobytes (KB), or megabytes (MB).
• Board Location: Board location is the physical location of each component corresponding to infor- mation on the server board silkscreen.
• User Data: The flash components on the server boards do not store user data from the operating sys- tem. No operating system level data is retained in any listed components after AC power is removed. The persistence of information written to each component is determined by its type as described in the table. Each component stores data specific to its function. Some components may contain passwords that provide access to that device’s configuration or functionality. These passwords are specific to the de- vice and are unique and unrelated to operating system passwords. The specific components that may contain password data are: o BIOS: The server board BIOS provides the capability to prevent unauthorized users from con- figuring BIOS settings when a BIOS password is set. This password is stored in BIOS flash, and is only used to set BIOS configuration access restrictions. o BMC: The server boards support an Intelligent Platform Management Interface (IPMI) 2.0 con- formant baseboard management controller (BMC). The BMC provides health monitoring, alert- ing and remote power control capabilities for the Intel® Server Board. The BMC does not have access to operating system level data. The BMC supports the capability for remote software to connect over the network and per- form health monitoring and power control. This access can be configured to require authenti- cation by a password. If configured, the BMC maintains user passwords to control this access. These passwords are stored in the BMC flash.

Table 68. Volatile and non-volatile components system, processors, memory, storage devices, or add-in cards.

downloaded from the Intel website. Figure 80. Intel® Server System R1000WF product family

Table 69. Intel® Server System R1000WF product family feature set

• RJ-45 serial port A connector on back panel
• Dual RJ-45 network interface connectors (S2600WFT(R)-based systems only)
• Dedicated RJ-45 server management port on back panel
• (3) – USB 3.0 connectors on back panel
• (2) – USB 3.0 connectors on front panel (non-storage system configurations only) Internal I/O Connectors/Head- ers
• (1) – Type-A USB 2.0 connector
• (1) – DH-10 serial port B connector System Fans • (6) – managed 40 mm dual rotor system fans
• One power supply fan for each installed power supply module Riser Card Support Support for two riser cards:
• Riser #1 – PCIe* 3.0 x24
• Riser #2 – PCIe* 3.0 x24 With two riser cards installed, up to two possible add-in cards can be supported (one x16 PCIe* 3.0 add-in card slot per riser card):
• (2) full height/half-length add-in cards via Risers #1 and #2 Power Supply Options The server system can have up to two power supply modules installed, providing support for the following power configurations: 1+0, 1+1 redundant power, and 2+0 combined power. (2) power supply options:
• AC 1300W Titanium
• AC 1100W Platinum
• DC 750W Gold Drive Support • R1304WFxxx – 4 x 3.5” hot swap drive bays + SAS/SATA backplane
• R1208WFxxx – 8 x 2.5” hot swap drive bays + SAS/SATA/NVMe* combo backplane Supported Rack Mount Kit Ac- cessory Options
• AXXELVRAIL – Enhanced value rack mount rail kit – 424 mm max travel length
• A1UFULLRAIL – Tool-less rack mount rail kit with CMA support – 780 mm max travel length
• A1USHRTRAIL – Tool-less rack mount rail kit – 780 mm max travel length (no CMA support)
• AXX2POSTBRCKT – Two post fixed mount bracket kit
• AXX1U2UCMA2– Cable management arm (supported with AXXFULLRAIL only)

Figure 81. Intel® Server System R2000WF product family Table 70. Intel® Server System R2000WF product family feature set

• RJ-45 serial port A connector
• Dual RJ-45 network interface connectors (S2600WFT(R)-based systems only)
• Dedicated RJ-45 server management NIC
• (3) – USB 3.0 connectors on back panel
• (2) – USB 3.0 connectors on front panel (non-storage system configurations only)
• (1) – USB 2.0 connector on rack handle (storage configurations only) Internal I/O Connectors/Head- ers
• (1) – Type-A USB 2.0 connector
• (1) – DH-10 serial port B connector System Fans • (6) – managed 60 mm hot swap capable system fans
• Integrated fans included with each installed power supply module

Intel® Server Board S2600WF Product Family Technical Product Specification 143 Feature Description Riser Card Support Support for three riser cards:

• Riser #1 – PCIe* 3.0 x24 - up to 3 PCIe slots
• Riser #2 – PCIe* 3.0 x24 - up to 3 PCIe slots
• Riser #3 – PCIe* 3.0 x16 – up to 2 PCIe slots – Low profile cards only (optional) With three riser cards installed, up to eight possible add-in cards can be supported:
• (4) full height/full-length + (2) full height/half-length add-in cards via Risers #1 and #2
• (2) low profile add in cards via riser #3 (option) Power Supply Options The server system can have up to two power supply modules installed, providing support for the following power configurations: 1+0, 1+1 redundant power, and 2+0 combined power. (3) power supply options:
• AC 1100W Platinum
• AC 1300W Titanium
• DC 750W Gold Drive Bay Options Hot Swap Backplane Options:
• 8 x 3.5” SAS/ SATA
• 8 x 2.5” combo backplane – SAS/SATA/NVMe
• 8 x 2.5” Dual Port SAS
• 12 x 3.5” SAS/ SATA (supports up to 2 NVMe drives) Note: All available backplane options have support for SAS 3.0 (12 Gb/sec). Storage Bay Options:
• 8 x 3.5” SAS/SATA hot swap drive bays
• 12 x 3.5” SAS/SATA hot swap drive bays (supports up to 2 NVMe drives)
• 8 x 2.5” SAS/SATA/NVMe hot swap drive bays
• 16 x 2.5” SAS/SATA/NVMe hot swap drive bays
• 24 x 2.5” SAS/SATA/NVMe swap drive bays
• 2 x 2.5” SATA SSD Back of Chassis Hot Swap Drive Bays (accessory Option)
• 2 x internal fixed mount 2.5” SSDs (all SYSTEM MODELs) Supported Rack Mount Kit Ac- cessory Options
• AXXELVRAIL – Enhanced value rack mount rail kit – 424 mm max travel length, 59kgs (130lbs.) max supported weight
• AXXFULLRAIL – 2U premium rail with CMA support – 800 mm max travel length, 45kgs (99lbs.) max supported weight
• AXXSHRTRAIL – 2U premium rail without CMA support – 788 mm max travel length, 45kgs (99lbs.) max supported weight
• AXX2POSTBRCKT – Two post fixed mount bracket kit
• AXXCMA2– Cable management arm (supported with AXXFULLRAIL only)

Intel® Server Board S2600WF Product Family Technical Product Specification 144 Appendix F. Product Regulatory Information This product has been evaluated and certified as Information Technology Equipment (ITE), which may be in- stalled in offices, schools, computer rooms, and similar commercial type locations. The suitability of this product for other product certification categories and/or environments (such as: medical, industrial, telecom- munications, NEBS, residential, alarm systems, test equipment, etc.), other than an ITE application, will re- quire further evaluation and may require additional regulatory approvals. Intel has verified that all L3, L6, and L9 server products4 as configured and sold by Intel to its customers comply with the requirements for all regulatory certifications defined in the following table. It is the Intel cus- tomer’s responsibility to ensure their final server system configurations are tested and certified to meet the regulatory requirements for the countries to which they plan to ship and or deploy server systems into. Intel® Server S2600WF Family NOTES “Wolf Pass” Intel Project Code Name L3 Board L6 / L9 System Product Integration Level S2600WF R1000WF Intel® Server System R1000WF Family R2000WF Intel® Server System R2000WF Family Regulatory Certification RCM DoC Australia & New Zealand   CB Certification & Report (International - report to in- clude all CB country national deviations)   China CCC Certification   Only applicable to select OEM defined SKUs CU Certification (Russia/Belarus/Kazakhstan)   Europe CE Declaration of Conformity   FCC Part 15 Emissions Verification (USA & Canada)   Germany GS Certification   India BIS Certification   Only applicable to select OEM defined SKUs International Compliance – CISPR32 & CISPR24   Japan VCCI Certification   Korea KC Certification   Mexico Certification   NRTL Certification (USA & Canada)   South Africa Certification   Taiwan BSMI Certification  (DOC)  Ukraine Certification   Table Key Not Tested / Not Certified  Tested / Certified – Limited OEM SKUs only  Testing / Certification (Planned) (Date) Tested / Certified  4 An L9 system configuration is a power-on ready server system with NO operating system installed. An L6 system configuration requires additional components to be installed in order to make it power -on ready. L3 are component building block options that require integration into a chassis to create a functional server system.

Intel® Server Board S2600WF Product Family Technical Product Specification 145 EU Directive 2019/424 (Lot 9) Beginning on March 1, 2020, an additional component of the European Union (EU) regulatory CE marking scheme, identified as EU Directive 2019/424 (Lot 9), will go into effect. After this date, all new server systems shipped into or deployed within the EU must meet the full CE marking requirements including those defined by the additional EU Lot 9 regulations. Intel has verified that all L3, L6, and L9 server products 5 as configured and sold by Intel to its customers comply with the full CE regulatory requirements for the given product type, including those defined by EU Lot 9. It is the Intel customer’s responsibility to ensure their final server system configurations are SPEC® SERT™ tested and meet the new CE regulatory requirements. Visit the following website for additional EU Directive 2019/424 (Lot9) information: https://eur-lex.europa.eu/legal-content/EN/TXT/?uri=CELEX:32019R0424 In compliance with the EU Directive 2019/424 (Lot 9) materials efficiency requirements, Intel makes available all necessary product collaterals as identified below:

• Product Serviceability Instructions o Intel® Server System R1000WF Product Family System Integration and Service Guide o https://www.intel.com/content/www/us/en/support/articles/000024289/server-prod- ucts.html o Intel® Server System R2000WF Product Family System Integration and Service Guide o https://www.intel.com/content/www/us/en/support/articles/000024479/server-prod- ucts.html
• Product Specifications o Intel® Server Board S2600WF Product Family Technical Product Specification (This document) o Intel® Server System R1000WF Product Family Technical Product Specification o Intel® Server System R2000WF Product Family Technical Product Specification o https://www.intel.com/content/www/us/en/support/articles/000023750/server-prod- ucts/server-boards.html
• System BIOS/Firmware and Security Updates – Intel® Server Board S2600WF family o System Update Package (SUP) – uEFI only o Intel® One Boot Flash Update (OFU) – Various OS Support o https://www.intel.com/content/www/us/en/support/topics/server-bios-firmware.html
• Intel Solid State Drive (SSD) Secure Data Deletion and Firmware Updates o Note: for system configurations that may be configured with an Intel SSD o Intel® Solid State Drive Toolbox o https://downloadcenter.intel.com/download/29205?v=t
• Intel® RAID Controller Firmware Updates and other support collaterals o Note: for system configurations that may be configured with an Intel® RAID Controller o https://www.intel.com/content/www/us/en/support/products/43732/server-products/raid- products.html 5 An L9 system configuration is a power-on ready server system with NO operating system installed. An L6 system configuration requires additional components to be installed in order to make it power -on ready. L3 are component building block options that require integration into a chassis to create a functional server system

Intel® Server Board S2600WF Product Family Technical Product Specification 146 Appendix G. Glossary Term Definition BMC Baseboard Management Controller BIOS Basic Input/Output System CMOS Complementary Metal-oxide-semiconductor CPU Central Processing Unit DDR4 Double Data Rate 4th edition DIMM Dual In-line Memory Module DPC DIMMs per Channel EDS External Design Specification EPS External Product Specification FP Front Panel FRB Fault Resilient Boot FRU Field Replaceable Unit GPGPU General Purpose Graphic Processing Unit I2C Inter-integrated Circuit bus iPC Intel Product Code LED Light Emitting Diode LRDIMM Load Reduced DIMM LSB Least Significant Bit MSB Most Significant Bit NIC Network Interface Card NMI Non-maskable Interrupt OCuLink Optical Copper Link PCI Peripheral Component Interconnect PCIe* Peripheral Component Interconnect Express* PMM Persistent Memory Module POST Power-on Self-Test PSU Power Supply Unit RAID Redundant Array of Independent Disks RAM Random Access Memory RDIMM Registered DIMM ROC RAID On Chip SAS Serial Attached SCSI SATA Serial Advanced Technology Attachment SCA Single Connector Attachment SCSI Small Computer System Interface SDR Sensor Data Record SSD Solid State Device TPM Trusted Platform Module TPS Technical Product Specification Intel® TXT Intel® Trusted Execution Technology for servers VLSI Very Large Scale Integration Intel® VROC Intel® Virtual RAID on CPU VSB Voltage Standby