S10-TXOVERVIEW

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Intel® Stratix® 10 TX Device Overview Online Version Send Feedback S10-TX- OVERVIEW ID: 683717 Version: 2022.08.18

1. Intel® Stratix® 10 TX Device Overview Intel® Stratix® 10 TX FPGAs feature power-efficient, dual-mode transceivers, capable of both 57.8 Gbps PAM4 (Pulse Amplitude Modulation) and 28.9 Gbps NRZ (Non Return to Zero) operation. Supported by hardened PCI Express Gen 3 and 10/25/100 Gbps Ethernet MAC IP blocks, these devices can deliver over 8 Tbps of aggregate bandwidth, meeting the demanding transceiver bandwidth and power budget specifications of next generation designs. In addition to the 57.8 Gbps PAM4 / 28.9 Gbps NRZ dual-mode transceivers, Intel Stratix 10 TX devices feature several other breakthrough innovations. These include all new HyperFlex® core architecture, hardened floating point DSP blocks, hardened external memory controllers and advanced packaging technology based on Intel's Embedded Multi-die Interconnect Bridge (EMIB). With an embedded quad-core 64-bit Arm* Cortex*-A53 hard processor system (HPS) available in select devices, Intel Stratix 10 TX FPGAs deliver power efficient, application-class processing, and allow designers to extend hardware virtualization into the FPGA fabric. Intel Stratix 10 TX FPGAs integrate a monolithic 14 nm FPGA fabric die with multiple high-speed transceiver tiles, all inside a single flip-chip BGA package. This implementation, combined with the unmatched transceiver bandwidth and core fabric performance, demonstrates Intel's commitment to deliver high-performance programmable solutions to your most challenging system design problems. Important innovations in Intel Stratix 10 TX devices include:

• All new Intel Hyperflex ™ core architecture delivering 2X the core performance compared to previous generation high-performance FPGAs
• Intel 14 nm tri-gate (FinFET) technology
• Heterogeneous 3D System-in-Package (SiP) technology
• Monolithic core fabric with up to 2.8 million logic elements (LEs)
• Up to 144 full duplex transceiver channels on heterogeneous 3D SiP transceiver tiles
• Transceiver data rates up to 57.8 Gbps PAM4 and 28.9 Gbps NRZ for chip-to-chip, chip-to-module, and backplane applications
• Embedded eSRAM (47.25 Mbit) in select devices, and M20K (20 Kb) internal SRAM memory blocks
• Fractional synthesis and ultra-low jitter LC tank based transmit phase locked loops (PLLs)
• Hard PCI Express ® Gen3 x16 intellectual property (IP) blocks
• Hard 10/25/100 Gbps Ethernet MAC with dedicated Reed-Solomon FEC for NRZ signals (528, 514) and PAM4 signals (544, 514) 683717 | 2022.08.18 Send Feedback Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2015 Registered

• Hard memory controllers and PHY supporting DDR4 rates up to 2666 Mbps per pin
• Hard fixed-point and IEEE 754 compliant hard floating-point variable precision digital signal processing (DSP) blocks with over 9 TFLOP compute performance with a power efficiency of 80 GFLOP per Watt
• Quad-core 64 bit Arm Cortex-A53 embedded processor in select devices, running up to 1.5 GHz
• Programmable clock tree synthesis for flexible, low power, low skew clock trees
• Dedicated secure device manager (SDM) for: — Enhanced device configuration and security — AES-256, SHA-256/384 and ECDSA-256/384 encrypt/decrypt accelerators and authentication — Multi-factor authentication — Physically Unclonable Function (PUF) service and software programmable device configuration capability
• Advanced power saving features delivering up to 70% lower core power compared to previous generation high-performance FPGAs With these capabilities, Intel Stratix 10 TX devices are ideally suited for the highest transceiver bandwidth applications in diverse markets such as:
• Compute and Storage—for custom servers, cloud computing and datacenter acceleration
• Networking—for Terabit, 400G and multi-100G bridging, aggregation, packet processing and traffic management
• Optical Transport Networks—for OTU4, 2xOTU4, 4xOTU4
• Broadcast—for high-end studio distribution, headend encoding/decoding, edge QAM
• Military—for radar, electronic warfare, and secure communications
• Medical—for diagnostic scanners and diagnostic imaging
• Test and Measurement—for protocol analyzers and application testers
• Wireless—for next-generation 5G networks 1.1. Intel Stratix 10 TX Devices In addition to delivering over 8 Tbps of transceiver bandwidth in a single package, Intel Stratix 10 TX devices offer up to 1 GHz core fabric performance and contain up to 2.8 million LEs in a monolithic fabric. They also feature up to 144 general purpose transceivers on separate transceiver tiles, and 2666 Mbps DDR4 external memory interface performance. The dual mode transceivers are capable of data rates up to 57.8 Gbps PAM4 / 28.9 Gbps NRZ for both short reach and backplane driving applications. Select devices contain an embedded hard processor system (HPS) based on an application-class quad-core 64 bit Arm Cortex-A53, running at clock rates up to 1.5 GHz. These devices are optimized for FPGA applications that require the highest transceiver bandwidth, and the highest core fabric performance, with the power efficiency of Intel’s 14 nm tri-gate process technology. 1. Intel® Stratix® 10 TX Device Overview 683717 | 2022.08.18 Intel® Stratix® 10 TX Device Overview Send Feedback

The high-performance monolithic FPGA fabric is based on the new Intel Hyperflex core architecture that includes additional Hyper-Registers everywhere throughout the interconnect routing and at the inputs of all functional blocks. The core fabric also contains an enhanced logic array utilizing Intel’s adaptive logic module (ALM) and a rich set of high performance building blocks including:

• eSRAM (47.25 Mbit) embedded memory blocks (available in select devices)
• M20K (20 Kb) embedded memory blocks
• Variable precision DSP blocks with IEEE 754 compliant hard floating-point
• Fractional synthesis and integer PLLs
• Hard memory controllers and PHY for external memory interfaces
• General purpose IO cells To clock these building blocks, Intel Stratix 10 TX devices use programmable clock tree synthesis, which uses dedicated clock tree routing to synthesize only those branches of the clock trees required for the application. All devices support in-system, fine-grained partial reconfiguration of the logic array, allowing logic to be added and subtracted from the system while it is operating. The high speed serial transceivers contain both the physical medium attachment (PMA) and the physical coding sublayer (PCS), which can be used to implement a variety of industry standard and proprietary protocols. In addition to the hard PCS, Intel Stratix 10 TX devices contain hard PCI Express IP that supports Gen1/Gen2/Gen3 rates in x1/x2/x4/x8/x16 lane configurations, and 10/25/100 Gbps Ethernet MAC with dedicated Reed-Solomon FEC for NRZ signals (528, 514) and PAM4 signals (544, 514). The hard PCS, PCI Express IP and 10/25/100 Gbps Ethernet MAC and FEC IP free up valuable core logic resources, save power, and increase your productivity. 1. Intel® Stratix® 10 TX Device Overview 683717 | 2022.08.18 Send Feedback Intel® Stratix® 10 TX Device Overview

Figure 1. Sample Ordering Code and Available Options for Intel Stratix 10 TX Devices

28.9 Gbps NRZ transceivers

generation high-performance Stratix V FPGAs. Table 1. Key Features of Intel Stratix 10 TX Devices Compared to Stratix V Devices

1. Intel® Stratix® 10 TX Device Overview

Feature Stratix V FPGAs Intel Stratix 10 TX Devices Power dissipation 1x As low as 0.3x Logic density 952 KLE (monolithic) 2,800 KLE (monolithic) Embedded memory (eSRAM) None 94.5 Mbits (select devices) Embedded memory (M20K) 52 Mbits 229 Mbits 18x19 multipliers 3,926 Note: Multiplier is 18x18 in Stratix V devices. 11,520 Note: Multiplier is 18x19 in Intel Stratix 10 TX devices. Floating point DSP capability Up to 1 TFLOP, requires soft floating point adder and multiplier Over 9 TFLOP, hard IEEE 754 compliant single precision floating point adder and multiplier Maximum transceivers 66 144 Maximum transceiver data rate (chip-to- chip) 28.05 Gbps Dual mode 57.8 Gbps PAM4 / 28.9 Gbps NRZ Maximum transceiver data rate (backplane) 12.5 Gbps Dual mode 57.8 Gbps PAM4 / 28.9 Gbps NRZ up to 30 dB insertion loss Hard memory controller None DDR4 @ 1333 MHz/2666 Mbps DDR3 @ 1067 MHz/2133 Mbps Hard protocol IP PCIe* Gen3 x8 PCIeGen3 x16 with SR-IOV 10/25/100 Gbps Ethernet MAC with dedicated Reed-Solomon FEC for NRZ signals (528, 514) and PAM4 signals (544, 514) Core clocking and PLLs Global, quadrant and regional clocks supported by fractional- synthesis fPLLs Programmable clock tree synthesis supported by fractional synthesis fPLLs and integer IO PLLs These innovations result in the following improvements:

• Improved Core Logic Performance: The Intel Hyperflex core architecture combined with Intel’s 14 nm tri-gate technology allows Intel Stratix 10 TX devices to achieve 2X the core performance compared to the previous generation
• Lower Power: Intel Stratix 10 TX devices use up to 70% lower core power compared to the previous generation, enabled by 14 nm Intel tri-gate technology, the Intel Hyperflex core architecture, and optional power savings features built into the architecture
• Higher Density: Intel Stratix 10 TX devices offer over two times the level of integration, with up to 2,800K logic elements (LEs) in a monolithic fabric, 94.5 Mbits of embedded eSRAM blocks in select devices, over 229 Mbits of embedded M20K memory blocks, and 11,520 18x19 multipliers
• Embedded Processing: Select Intel Stratix 10 TX devices feature a Quad-Core 64-bit Arm Cortex-A53 processor optimized for power efficiency and software compatible with previous generation Intel SoCs
• Improved Transceiver Performance: With up to 144 transceiver channels implemented in heterogeneous 3D SiP transceiver tiles, Intel Stratix 10 TX devices support data rates up to 57.8 Gbps PAM4 and 28.9 Gbps NRZ for chip-to-chip and backplane driving with signal conditioning circuits capable of equalizing over 30 dB of system loss 1. Intel® Stratix® 10 TX Device Overview 683717 | 2022.08.18 Send Feedback Intel® Stratix® 10 TX Device Overview

• Improved DSP Performance: The variable precision DSP block in Intel Stratix

10 TX devices features hard fixed and floating point capability, with over 9 TFLOP

• Additional Hard IP: Intel Stratix 10 TX devices include many more hard IP blocks than previous generation devices, with a hard memory controller included in each bank of 48 general purpose IOs, hard PCS, PCIe Gen3x16 full protocol stack and 10/25/100 Gbps Ethernet MAC with dedicated Reed-Solomon FEC for NRZ signals (528, 514) and PAM4 signals (544, 514) to support the transceivers
• Enhanced Core Clocking: Intel Stratix 10 TX devices feature programmable clock tree synthesis; clock trees are only synthesized where needed, increasing the flexibility and reducing the power dissipation of the clocking solution
• Additional Core PLLs: The core fabric in Intel Stratix 10 TX devices is supported by both integer IO PLLs and fractional synthesis fPLLs, resulting in a greater total number of PLLs than the previous generation 1.3. Intel Stratix 10 TX Features Summary

Table 2. Intel Stratix 10 TX Device Features

• SmartVID controlled core voltage, standard power devices Low power serial transceivers
• Up to 144 total transceivers available
• Continuous operating range of 1 Gbps to 28.9 Gbps in NRZ mode and 2 Gbps to 57.8 Gbps in PAM4 mode
• Backplane support up to 57.8 Gbps PAM4 / 28.9 Gbps NRZ
• Extended range down to 125 Mbps with oversampling
• ATX transmit PLLs with user-configurable fractional synthesis capability
• XFP, SFP+, QSFP/QSFP28, CFP/CFP2/CFP4, QSFPDD optical module support
• Adaptive linear and decision feedback equalization
• Transmit pre-emphasis and de-emphasis
• Dynamic partial reconfiguration of individual transceiver channels
• On-chip instrumentation (Eye Viewer non-intrusive data eye monitoring) General purpose I/Os • Up to 440 total GPIO available
• 1.6 Gbps LVDS—every pair can be configured as an input or output
• 1333 MHz/2666 Mbps DDR4 external memory interface
• 1067 MHz/2133 Mbps DDR3 external memory interface
• 1.2 V to 3.0 V single-ended LVCMOS/LVTTL interfacing
• On-chip termination (OCT) Embedded hard IP • Quad-core 64 bit Arm Cortex-A53 processor, select devices
• PCIe Gen1/Gen2/Gen3 complete protocol stack, x1/x2/x4/x8/x16 end point and root port
• 10/25/100 Gbps Ethernet MAC with dedicated Reed-Solomon FEC for NRZ signals (528, 514) and PAM4 signals (544, 514)
• DDR4/DDR3 hard memory controller (RLDRAM3/QDR II+/QDR IV using soft memory controller) Transceiver hard IP • 10GBASE-KR/40GBASE-KR4, 100GBASE-CR2/KR2/LR2 Forward Error Correction (FEC)
• 10G Ethernet PCS
• PCI Express PIPE interface
• Interlaken PCS
• Gigabit Ethernet PCS
• Deterministic latency support for Common Public Radio Interface (CPRI) PCS continued... 1. Intel® Stratix® 10 TX Device Overview 683717 | 2022.08.18 Intel® Stratix® 10 TX Device Overview Send Feedback

• Fast lock-time support for Gigabit Passive Optical Networking (GPON) PCS
• 8B/10B, 64B/66B, 64B/67B encoders and decoders
• Custom mode support for proprietary protocols Power management • SmartVID controlled core voltage, standard power devices High performance monolithic core fabric
• Intel Hyperflex core architecture with Hyper-Registers everywhere throughout the interconnect routing and at the inputs of all functional blocks
• Monolithic fabric minimizes compile times and increases logic utilization
• Enhanced adaptive logic module (ALM)
• Improved multi-track routing architecture reduces congestion and improves compile times
• Hierarchical core clocking architecture with programmable clock tree synthesis
• Fine-grained partial reconfiguration Internal memory blocks • eSRAM - 47.25 Mbit blocks with hard ECC support, select devices
• M20K—20 Kb with hard ECC support
• MLAB—640 bit distributed LUTRAM Variable precision DSP blocks
• IEEE 754-compliant hard single-precision floating point capability
• Supports signal processing with precision ranging from 18x19 up to 54x54
• Native 27x27 and 18x19 multiply modes
• 64 bit accumulator and cascade for systolic FIRs
• Internal coefficient memory banks
• Pre-adder/subtractor improves efficiency
• Additional pipeline register increases performance and reduces power Phase locked loops (PLL) • Fractional synthesis PLLs (fPLL) support both fractional and integer modes
• Fractional mode with third-order delta-sigma modulation
• Precision frequency synthesis
• Integer PLLs adjacent to general purpose I/Os, support external memory, and LVDS interfaces, clock delay compensation, zero delay buffering Core clock networks • 1 GHz fabric clocking
• 667 MHz external memory interface clocking, supports 2666 Mbps DDR4 interface
• 800 MHz LVDS interface clocking, supports 1600 Mbps LVDS interface
• Programmable clock tree synthesis, backwards compatible with global, regional and peripheral clock networks
• Clocks only synthesized where needed, to minimize dynamic power continued... 1. Intel® Stratix® 10 TX Device Overview 683717 | 2022.08.18 Send Feedback Intel® Stratix® 10 TX Device Overview

• Software programmable device configuration
• Serial and parallel flash interface
• Configuration via protocol (CvP) using PCI Express Gen1/Gen2/Gen3
• Fine-grained partial reconfiguration of core fabric
• Dynamic reconfiguration of transceivers and PLLs
• Comprehensive set of security features including AES-256, SHA-256/384, and ECDSA-256/384 accelerators, and multi-factor authentication
• Physically Unclonable Function (PUF) service Packaging • Intel Embedded Multi-die Interconnect Bridge (EMIB) packaging technology
• Multiple devices with identical package footprints allows seamless migration across different device densities
• 1.0 mm ball-pitch FBGA packaging
• Lead and lead-free package options Software and tools • Intel Quartus ® Prime Pro Edition design suite with Hyper-Aware design flow
• Fast Forward compiler to allow HyperFlex architecture performance exploration
• Transceiver toolkit
• Platform Designer system integration tool
• DSP Builder advanced blockset
• OpenCL ™ support
• SoC Embedded Design Suite (EDS)

Table 3. Intel Stratix 10 TX HPS Features (Available in Select Devices)

• Scalar floating-point unit supporting single and double precision
• Arm Neon* media processing engine for each processor System Controllers • System Memory Management Unit (SMMU)
• Cache Coherency Unit (CCU) Layer 1 Cache • 32 KB L1 instruction cache with parity
• 32 KB L1 data cache with ECC Layer 2 Cache • 1 MB Shared L2 Cache with ECC On-Chip Memory • 256 KB On-Chip RAM Direct memory access (DMA) controller • 8-Channel DMA Ethernet media access controller (EMAC)
• Three 10/100/1000 EMAC with integrated DMA USB On-The-Go controller (OTG) • 2 USB OTG with integrated DMA UART controller • 2 UART 16550 compatible Serial Peripheral Interface (SPI) controller
• 4 SPI I2C controller • 5 I 2C controllers SD/SDIO/MMC controller • 1 eMMC 4.5 with DMA and CE-ATA support NAND flash controller • 1 ONFI 1.0 or later 8 and 16 bit support General-purpose I/O (GPIO) • Maximum of 48 software programmable GPIO continued... 1. Intel® Stratix® 10 TX Device Overview 683717 | 2022.08.18 Intel® Stratix® 10 TX Device Overview Send Feedback

• 4 watchdog timers Security • Secure boot
• Advanced Encryption Standard (AES) and authentication (SHA/ECDSA) External Memory Interface External Memory Interface • Hard Memory Controller with DDR4 and DDR3 1.4. Intel Stratix 10 TX Block Diagram

Figure 2. Intel Stratix 10 TX Architecture Block Diagram

57.8 Gbps PAM4

1. Intel® Stratix® 10 TX Device Overview

Table 4. Intel Stratix 10 TX Family Plan—FPGA Core (part 1) Table 5. Intel Stratix 10 TX Family Plan - Interconnects, PLLs and Hard IP (part 2) (1) The number of 27x27 multipliers is one-half the number of 18x19 multipliers.

1. Intel® Stratix® 10 TX Device Overview

Table 6. Intel Stratix 10 TX Package Plan

10 TX Device

Figure 3. Tile Configuration 1: HF35 Package (2) All packages are ball grid arrays with 1.0 mm pitch. (3) High-Voltage I/O pins are used for 3 V and 2.5 V interfacing. (4) Each LVDS pair can be configured as either a differential input or a differential output. (5) High-Voltage I/O pins and LVDS pairs are included in the General Purpose I/O count. Transceivers are counted separately.

1. Intel® Stratix® 10 TX Device Overview

Figure 7. Tile Configuration 5: YF55 Package

• Higher Throughput—Capitalizes on 2X core clock frequency performance to obtain throughput breakthroughs
• Improved Power Efficiency—Uses reduced IP size, enabled by Intel Hyperflex, to consolidate designs which previously spanned multiple devices into a single device, thereby reducing power by up to 70% versus previous generation devices
• Greater Design Functionality—Uses faster clock frequency to reduce bus widths and reduce IP size, freeing up additional FPGA resources to add greater functionality
• Increased Designer Productivity—Boosts performance with less routing congestion and fewer design iterations using Hyper-Aware design tools, obtaining greater timing margin for more rapid timing closure In addition to the traditional user registers found in the Adaptive Logic Modules (ALM), the Intel Hyperflex core architecture introduces additional bypassable registers everywhere throughout the fabric of the FPGA. These additional registers, called Hyper-Registers are available on every interconnect routing segment and at the inputs of all functional blocks. 1. Intel® Stratix® 10 TX Device Overview 683717 | 2022.08.18 Send Feedback Intel® Stratix® 10 TX Device Overview

modulation schemes, and protocol IPs evolve. Figure 10. Monolithic Core Fabric, Heterogeneous 3D SiP Transceiver Tiles

• 24 full-duplex transceiver channels (PMA and PCS)
• Reference clock distribution network
• Transmit PLLs
• High-speed clocking and bonding networks
• PCI Express and 100G Ethernet MAC hard IP, or 100G Ethernet MAC with dedicated Reed-Solomon FEC for NRZ signals (528, 514) and PAM4 signals (544, 514) 1. Intel® Stratix® 10 TX Device Overview 683717 | 2022.08.18 Send Feedback Intel® Stratix® 10 TX Device Overview

Figure 11. Heterogeneous 3D SiP Transceiver Tile Architecture Intel Stratix 10 TX devices offer up to 144 total full-duplex transceiver channels. adaptive equalization circuits can equalize over 30 dB of system loss. All transceiver channels feature a dedicated PMA and a hardened PCS.

• The PMA provides primary interfacing capabilities to physical channels.
• The PCS typically handles encoding/decoding, word alignment, and other pre- processing functions before transferring data to the FPGA core fabric. Within each transceiver tile, the transceivers arrange in four banks of six PMA-PCS groups. A wide variety of bonded and non-bonded data rate configurations are possible within each bank, and within each tile, using a highly configurable clock distribution network. 1.8.1. PMA Features PMA channels are comprised of transmitter (TX), receiver (RX), and high speed clocking resources. The transmit features deliver exceptional signal integrity at data rates up to 57.8 Gbps PAM4 / 28.9 Gbps NRZ. Clocking options include ultra-low jitter LC tank-based (ATX) PLLs with optional fractional synthesis capability, channel PLLs operating as clock multiplier units (CMUs), and fractional synthesis PLLs (fPLLs). 1. Intel® Stratix® 10 TX Device Overview 683717 | 2022.08.18 Intel® Stratix® 10 TX Device Overview Send Feedback

• ATX PLL—can be configured in integer mode, or optionally, in a new fractional synthesis mode. Each ATX PLL spans the full frequency range of the supported data rate range providing a stable, flexible clock source with the lowest jitter.
• CMU PLL—when not being used as a transceiver, select PMA channels can be configured as channel PLLs operating as CMUs to provide an additional master clock source within the transceiver bank.
• fPLL—In addition, dedicated fPLLs are available with precision frequency synthesis capabilities. fPLLs can be used to synthesize multiple clock frequencies from a single reference clock source and replace multiple reference oscillators for multi- protocol and multi-rate applications. On the receiver side, each PMA has an independent channel PLL that allows analog tracking for clock-data recovery. Each PMA also has advanced equalization circuits that compensate for transmission losses across a wide frequency spectrum.
• Variable Gain Amplifier (VGA)—to optimize the receiver's dynamic range
• Continuous Time Linear Equalizer (CTLE)—to compensate for channel losses with lowest power dissipation
• Decision Feedback Equalizer (DFE)—to provide additional equalization capability on backplanes even in the presence of crosstalk and reflections
• On-Die Instrumentation (ODI)—to provide on-chip eye monitoring capabilities (Eye Viewer). This capability helps to optimize link equalization parameters during board bring-up and supports in-system link diagnostics and equalization margin testing

Figure 12. Intel Stratix 10 TX Receiver Block Features and ensures robust, reliable, and error-free operation.

1. Intel® Stratix® 10 TX Device Overview

Table 7. Transceiver PMA Features monitoring (Eye Viewer). Also inject jitter from transmitter to test link margin in system. interface for the most transceiver flexibility. bypassable PCS interface layers. transceiver and the core logic. (7) Intel Stratix 10 transceivers can support data rates down to 125 Mbps with over sampling.

1. Intel® Stratix® 10 TX Device Overview

and support for data rates up to 28.9 Gbps. Stratix 10 E-Tile Transceiver PHY User Guide. Table 8. Transceiver PCS Features

8.0 Phase compensation FIFO, byte

performance, ease-of-use, increased functionality, and designer productivity.

1. Intel® Stratix® 10 TX Device Overview

from the core logic (autonomous mode). This feature allows the PCI Express link to power up and complete link training in less than 100 ms, while the rest of the device is still in the process of being configured. The hard IP also provides added functionality, which makes it easier to support emerging features such as Single Root I/O Virtualization (SR-IOV) and optional protocol extensions. The PCI Express hard IP has improved end-to-end data path protection using Error Checking and Correction (ECC). In addition, the hard IP supports configuration of the device via protocol (CvP) across the PCI Express bus at Gen1/Gen2/Gen3 rates. 1.10. Ethernet MAC, Reed-Solomon FEC for NRZ signals (528, 514) and PAM4 signals (544, 514) Intel Stratix 10 TX devices contain a single instance of 50/100 Gbps Ethernet MAC hard IP, and multiple instances of 10/25/100 Gbps Ethernet MAC hard IP along with the associated Reed-Solomon FEC for NRZ signals (528, 514) and PAM4 signals (544, 514), simplifying the design of complex multi-port Ethernet systems. 1.11. 10G Ethernet Hard IP Intel Stratix 10 TX devices include IEEE 802.3 10-Gbps Ethernet (10GbE) compliant 10GBASE-R PCS and PMA hard IP. The scalable 10GbE hard IP supports multiple independent 10GbE ports while using a single PLL for all the 10GBASE-R PCS instantiations, which saves on core logic resources and clock networks. The integrated serial transceivers simplify multi-port 10GbE systems compared to 10 GbE Attachment Unit Interface (XAUI) interfaces that require an external XAUI-to-10G PHY. Furthermore, the integrated transceivers incorporate signal conditioning circuits, which enable direct connection to standard 10G XFP and SFP+ pluggable optical modules. The transceivers also support backplane Ethernet applications and include a hard 10GBASE-KR/40GBASE-KR4 Forward Error Correction (FEC) circuit that can be used for both 10G and 40G applications. The integrated 10G Ethernet hard IP and 10G transceivers save external PHY cost, board space and system power. The 10G Ethernet PCS hard IP and 10GBASE-KR FEC are present in every transceiver channel. 1.12. Interlaken PCS Hard IP Intel Stratix 10 TX devices have integrated Interlaken PCS hard IP supporting rates up to 17.4 Gbps per lane. The Interlaken PCS hard IP is based on the proven functionality of the PCS developed for Intel’s previous generation FPGAs, which has demonstrated interoperability with Interlaken ASSP vendors and third-party IP suppliers. The Interlaken PCS hard IP is present in every transceiver channel in Intel Stratix 10 TX devices. 1.13. External Memory and General Purpose I/O Intel Stratix 10 TX devices offer substantial external memory bandwidth, supporting DDR4 memory interfaces running at up to 2666 Mbps. For external memory interface and LVDS restrictions, see AN 906: Intel Stratix 10 GX 400, SX 400, and TX 400 Routing and Designing Floorplan Guidelines. 1. Intel® Stratix® 10 TX Device Overview 683717 | 2022.08.18 Intel® Stratix® 10 TX Device Overview Send Feedback

hard or soft memory controllers. Figure 13. Hard Memory Controller

• Read/write leveling
• FIFO buffering to lower latency and improve margin
• Timing calibration
• On-chip termination The timing calibration is aided by the inclusion of hard microcontrollers based on Intel’s Nios® II technology, specifically tailored to control the calibration of multiple memory interfaces. This calibration allows the Intel Stratix 10 TX device to compensate for any changes in process, voltage, or temperature either within the device itself, or within the external memory device. The advanced calibration algorithms ensure maximum bandwidth and robust timing margin across all operating conditions. 1. Intel® Stratix® 10 TX Device Overview 683717 | 2022.08.18 Send Feedback Intel® Stratix® 10 TX Device Overview

Table 9. External Memory Interface Performance The listed speeds are for the 1-rank case. link running at data rates of 15 Gbps (HMC short reach specification). input buffer. This enables configurable direction for each LVDS pair. of logic functions and easy conversion of IP between the devices.

1. Intel® Stratix® 10 TX Device Overview

Figure 14. ALM Block Diagram

4 Registers per ALM

• High register count with 4 registers per 8-input fracturable LUT, operating in conjunction with the new Intel Hyperflex architecture, enables Intel Stratix 10 TX devices to maximize core performance at very high core logic utilization
• Implements select 7-input logic functions, all 6-input logic functions, and two independent functions consisting of smaller LUT sizes (such as two independent 4- input LUTs) to optimize core logic utilization The Intel Quartus Prime software takes advantage of the ALM logic structure to deliver the highest performance, optimal logic utilization, and lowest compile times. The Intel Quartus Prime software simplifies design reuse as it automatically maps legacy designs into the Intel Stratix 10 TX ALM architecture. 1.15. Core Clocking Core clocking in Intel Stratix 10 TX devices makes use of programmable clock tree synthesis. This technique uses dedicated clock tree routing and switching circuits, and allows the Intel Quartus Prime software to create the exact clock trees required for your design. Clock tree synthesis minimizes clock tree insertion delay, reduces dynamic power dissipation in the clock tree and allows greater clocking flexibility in the core while still maintaining backwards compatibility with legacy global and regional clocking schemes. 1. Intel® Stratix® 10 TX Device Overview 683717 | 2022.08.18 Send Feedback Intel® Stratix® 10 TX Device Overview

The core clock network in Intel Stratix 10 TX devices supports the new Intel Hyperflex core architecture at clock rates up to 1 GHz. It also supports the hard memory controllers up to 2666 Mbps with a quarter rate transfer to the core. The core clock network is supported by dedicated clock input pins, fractional clock synthesis PLLs, and integer I/O PLLs. 1.16. Fractional Synthesis PLLs and I/O PLLs Intel Stratix 10 TX devices contain fractional synthesis PLLs (fPLL) available for use with transceivers or in the core fabric. The fPLLs are located in the 3D SiP transceiver L-tiles and H-tiles, eight per tile, adjacent to the transceiver channels. The fPLLs can be used to reduce both the number of oscillators required on the board and the number of clock pins required, by synthesizing multiple clock frequencies from a single reference clock source. In addition to synthesizing reference clock frequencies for the transceiver transmit PLLs, the fPLLs can also be used directly for transmit clocking. Each fPLL can be independently configured for conventional integer mode, or enhanced fractional synthesis mode with third-order delta-sigma modulation. In addition to the fPLLs, Intel Stratix 10 TX devices contain up to 24 integer I/O PLLs (IOPLLs) available for general purpose use in the core fabric and for simplifying the design of external memory interfaces and high-speed LVDS interfaces. The IOPLLs are located in each bank of 48 general purpose I/O, one per I/O bank, adjacent to the hard memory controllers and LVDS SerDes in each I/O bank. This makes it easier to close timing because the IOPLLs are tightly coupled with the I/Os that need to use them. The IOPLLs can be used for general purpose applications in the core such as clock network delay compensation and zero-delay clock buffering. 1.17. Internal Embedded Memory Intel Stratix 10 TX devices contain three types of embedded memory blocks: eSRAM (47.25 Mbit) in select devices, M20K (20 Kb), and MLAB (640 bit). This variety of on- chip memory provides fast access times and low latency for applications such as wide and deep FIFOs and variable buffers. The eSRAM blocks are a new innovation in Intel Stratix 10 TX devices. These large embedded SRAM blocks are tightly coupled to the core fabric and are directly accessible with no need for a separate memory controller. Each eSRAM block is arranged as 8 channels, 40 banks per channel, with a total capacity of 47.25 Mbits running at clock rates up to 750 MHz. Within the eSRAM block, each channel has a bus width of 72 bit read and 72 bit write, and has one READ and one WRITE per channel. This allows each eSRAM block to support a total aggregate bandwidth (read + write) of up to 864 Gbps. The eSRAM block is implemented as a simple dual port memory with concurrent read and write access per channel, and includes integrated hard ECC generation and checking. Compared to an off-chip SRAM solution, the eSRAM block allows you to reduce system power and save board space and cost. The M20K and MLAB blocks are familiar block sizes carried over from previous Intel device families. The MLAB blocks are ideal for wide and shallow memories, while the M20K blocks are intended to support larger memory configurations and include hard ECC. Both M20K and MLAB embedded memory blocks can be configured as a single- 1. Intel® Stratix® 10 TX Device Overview 683717 | 2022.08.18 Intel® Stratix® 10 TX Device Overview Send Feedback

Table 10. Internal Embedded Memory Block Configurations and IEEE 754 compliant floating point capability. operating frequency of the DSP block and reduce power consumption. Figure 15. DSP Block: Standard Precision Fixed Point Mode

1. Intel® Stratix® 10 TX Device Overview

block, or by utilizing multiple blocks. Table 11. Variable Precision DSP Block Configurations

1 Single Precision floating point adder, 1 Single

characteristic of increasing precision requirements on only one side of the multiplier. in DSP resources as the precision grows. Table 12. Complex Multiplication With Variable Precision DSP Block and performance similar to high precision fixed point implementations.

• Hard 18 bit and 25 bit pre-adders
• Hard floating point multipliers and adders
• 64 bit dual accumulator (for separate I, Q product accumulations)
• Cascaded output adder chains for 18 and 27 bit FIR filters
• Embedded coefficient registers for 18 and 27 bit coefficients
• Fully independent multiplier outputs
• Inferability using HDL templates supplied by the Intel Quartus Prime software for most modes The Variable Precision DSP block is ideal to support the growing trend towards higher bit precision in high performance DSP applications. At the same time, it can efficiently support the many existing 18 bit DSP applications, such as high definition video processing and remote radio heads. With the Variable Precision DSP block architecture and hard floating point multipliers and adders, Intel Stratix 10 TX devices can efficiently support many different precision levels up to and including floating point 1. Intel® Stratix® 10 TX Device Overview 683717 | 2022.08.18 Send Feedback Intel® Stratix® 10 TX Device Overview

implementations. This flexibility can result in increased system performance, reduced power consumption, and reduce architecture constraints on system algorithm designers. 1.19. Hard Processor System (HPS) The Hard Processor System (HPS) in select Intel Stratix 10 TX devices is Intel’s third generation HPS. Leveraging the performance of Intel 14 nm tri-gate technology, the HPS provides more than double the performance of previous generation devices with an integrated quad-core 64-bit Arm Cortex-A53. The HPS also enables system-wide hardware virtualization capabilities by adding a system memory management unit. These architecture improvements ensure that Intel Stratix 10 TX devices meet the requirements of current and future embedded markets, including wireless and wireline communications, datacenter acceleration, and numerous military applications. 1. Intel® Stratix® 10 TX Device Overview 683717 | 2022.08.18 Intel® Stratix® 10 TX Device Overview Send Feedback

Figure 18. HPS Block Diagram

1 MB L2 Cache with ECC

1. Integrated direct memory access (DMA)
2. Integrated error correction code (ECC)
3. Multiport front-end interface to hard memory controller

32 KB I-Cache

32 KB D-Cache

32 KB D -Cache

Table 13. Key Features of the Intel Stratix 10 HPS

• 2.3 MIPS/MHz instruction efficiency
• CPU frequency up to 1.5 GHz
• At 1.5 GHz total performance of 13,800 MIPS
• Armv8-A architecture
• Runs 64-bit and 32-bit Arm instructions
• 16-bit and 32-bit Thumb instructions for 30% reduction in memory footprint
• Jazelle ® RCT execution architecture with 8 bit Java bytecodes continued... 1. Intel® Stratix® 10 TX Device Overview 683717 | 2022.08.18 Send Feedback Intel® Stratix® 10 TX Device Overview

• Superscalar, variable length, out-of-order pipeline with dynamic branch prediction
• Improved Arm NEON ™ media processing engine
• Single- and double-precision floating-point unit
• CoreSight ™ debug and trace technology System Memory Management Unit
• Enables a unified memory model and extends hardware virtualization into peripherals implemented in the FPGA fabric Cache Coherency unit • Changes in shared data stored in cache are propagated throughout the system providing bi-directional coherency for co-processing elements. Cache • L1 Cache — 32 KB of instruction cache w/ parity check — 32 KB of L1 data cache w /ECC — Parity checking
• L2 Cache — 1MB shared — 8-way set associative — SEU Protection with parity on TAG ram and ECC on data RAM — Cache lockdown support On-Chip Memory • 256 KB of scratch on-chip RAM External SDRAM and Flash Memory Interfaces for HPS
• Hard memory controller with support for DDR4, DDR3 — 40 bit (32 bit + 8 bit ECC) with select packages supporting 72 bit (64 bit + 8 bit ECC) — Support for up to 2666 Mbps DDR4 and 2166 Mbps DDR3 frequencies — Error correction code (ECC) support including calculation, error correction, write- back correction, and error counters — Software Configurable Priority Scheduling on individual SDRAM bursts — Fully programmable timing parameter support for all JEDEC-specified timing parameters — Multiport front-end (MPFE) scheduler interface to the hard memory controller, which supports the AXI® Quality of Service (QoS) for interface to the FPGA fabric
• NAND flash controller — ONFI 1.0 — Integrated descriptor based with DMA — Programmable hardware ECC support — Support for 8 and 16 bit Flash devices
• Secure Digital SD/SDIO/MMC controller — eMMC 4.5 — Integrated descriptor based DMA — CE-ATA digital commands supported — 50 MHz operating frequency
• Direct memory access (DMA) controller — 8-channel — Supports up to 32 peripheral handshake interface continued... 1. Intel® Stratix® 10 TX Device Overview 683717 | 2022.08.18 Intel® Stratix® 10 TX Device Overview Send Feedback

• Three 10/100/1000 Ethernet media access controls (MAC) with integrated DMA — Supports RGMII and RMII external PHY Interfaces — Option to support other PHY interfaces through FPGA logic
• GMII
• MII
• RMII (requires MII to RMII adapter)
• RGMII (requires GMII to RGMII adapter)
• SGMII (requires GMII to SGMII adapter) — Supports IEEE 1588-2002 and IEEE 1588-2008 standards for precision networked clock synchronization — Supports IEEE 802.1Q VLAN tag detection for reception frames — Supports Ethernet AVB standard
• Two USB On-the-Go (OTG) controllers with DMA — Dual-Role Device (device and host functions)
• High-speed (480 Mbps)
• Full-speed (12 Mbps)
• Low-speed (1.5 Mbps)
• Supports USB 1.1 (full-speed and low-speed) — Integrated descriptor-based scatter-gather DMA — Support for external ULPI PHY — Up to 16 bidirectional endpoints, including control endpoint — Up to 16 host channels — Supports generic root hub — Configurable to OTG 1.3 and OTG 2.0 modes
• Five I 2C controllers (three can be used by EMAC for MIO to external PHY) — Support both 100 Kbps and 400 Kbps modes — Support both 7 bit and 10 bit addressing modes — Support Master and Slave operating mode
• Two UART 16550 compatible — Programmable baud rate up to 115.2 Kbaud
• Four serial peripheral interfaces (SPI) (2 Masters, 2 Slaves) — Full and Half duplex Timers and I/O • Timers — 4 general-purpose timers — 4 watchdog timers
• 48 HPS direct I/O allow HPS peripherals to connect directly to I/O
• Up to three IO48 banks may be assigned to HPS for HPS DDR access Interconnect to Logic Core • FPGA-to-HPS Bridge — Allows IP bus masters in the FPGA fabric to access to HPS bus slaves — Configurable 32, 64, or 128 bit AMBA AXI interface
• HPS-to-FPGA Bridge — Allows HPS bus masters to access bus slaves in FPGA fabric — Configurable 32, 64, or 128 bit AMBA AXI interface allows high-bandwidth HPS master transactions to FPGA fabric
• HPS-to-SDM and SDM-to-HPS Bridges — Allows the HPS to reach the SDM block and the SDM to bootstrap the HPS
• Light Weight HPS-to-FPGA Bridge — Light weight 32 bit AXI interface suitable for low-latency register accesses from HPS to soft peripherals in FPGA fabric
• FPGA-to-HPS SDRAM Bridge — Up to three AMBA AXI interfaces supporting 32, 64, or 128 bit data paths 1. Intel® Stratix® 10 TX Device Overview 683717 | 2022.08.18 Send Feedback Intel® Stratix® 10 TX Device Overview

1.20. Power Management Intel Stratix 10 TX devices use the advanced Intel 14 nm tri-gate process technology, the all new Intel Hyperflex core architecture to enable Hyper-Folding, power gating, and optional power reduction techniques to reduce total power consumption by as much as 70% compared to previous generation high-performance Stratix V devices. Intel Stratix 10 standard power devices (-V) are SmartVID devices. The core voltage supplies (VCC and VCCP) for each SmartVID device must be driven by a PMBus voltage regulator dedicated to that Intel Stratix 10 device. Use of a PMBus voltage regulator for each SmartVID (-V) device is mandatory; it is not an option. A code is programmed into each SmartVID device during manufacturing that allows the PMBus voltage regulator to operate at the optimum core voltage to meet the device performance specifications. With the new Intel Hyperflex core architecture, designs can run 2X faster than previous generation FPGAs. With 2X performance and same required throughput, architects can cut the data path width in half to save power. This optimization is called Hyper-Folding. Additionally, power gating reduces static power of unused resources in the FPGA by powering them down. The Intel Quartus Prime software automatically powers down specific unused resource blocks such as DSP and M20K blocks, at configuration time. Furthermore, Intel Stratix 10 TX devices feature Intel’s low power transceivers and include a number of hard IP blocks that not only reduce logic resources but also deliver substantial power savings compared to soft implementations. In general, hard IP blocks consume up to 50% less power than the equivalent soft logic implementations. 1.21. Device Configuration and Secure Device Manager (SDM) All Intel Stratix 10 TX devices contain a Secure Device Manager (SDM), which is a dedicated triple-redundant processor that serves as the point of entry into the device for all JTAG and configuration commands. The SDM also bootstraps the HPS, ensuring that the HPS can boot using the same security features as the rest of the FPGA. 1. Intel® Stratix® 10 TX Device Overview 683717 | 2022.08.18 Intel® Stratix® 10 TX Device Overview Send Feedback

Figure 19. SDM Block Diagram used to respond to single-event upsets and security attacks. reconfiguration, they overlay the normal rows and columns of FPGA logic and routing. and no impact to the timing of logic signals that cross the sector boundaries.

1. Intel® Stratix® 10 TX Device Overview

• Dedicated secure configuration manager
• Reduced device configuration time, because sectors are configured in parallel
• Updateable configuration process
• Reconfiguration of one or more sectors independent of all other sectors
• Zeroization of individual sectors or the complete device 1.22. Device Security Building on top of the robust security features present in the previous generation devices, Intel Stratix 10 TX devices include a number of new and innovative security enhancements. These features are also managed by the SDM, tightly coupling device configuration and reconfiguration with encryption, authentication, key storage and anti-tamper services. Security services provided by the SDM include:
• Bitstream encryption
• Multi-factor authentication
• Hard encryption and authentication acceleration; AES-256, SHA-256/384, ECDSA-256/384
• Volatile and non-volatile encryption key storage and management
• Boot code authentication for the HPS
• Physically Unclonable Function (PUF) service
• Updateable configuration process
• Secure device maintenance and upgrade functions
• Side channel attack protection
• Scripted response to sensor inputs and security attacks, including selective sector zeroization
• Readback, JTAG and test mode disable
• Enhanced response to single-event upsets (SEU)
• Black key provisioning
• Physical anti-tamper See the Intel Stratix 10 Device Security User Guide for a complete list of all security features. The SDM and associated security services provide a robust, multi-layered security solution for your Intel Stratix 10 TX design.

Table 14. Device Security

1. Intel® Stratix® 10 TX Device Overview

• My Intel Support
• Intel Stratix 10 Device Security User Guide 1.23. Configuration via Protocol Using PCI Express Configuration via protocol using PCI Express allows the FPGA to be configured across the PCI Express bus, simplifying the board layout and increasing system integration. Making use of the embedded PCI Express hard IP operating in autonomous mode before the FPGA is configured, this technique allows the PCI Express bus to be powered up and active within the 100 ms time allowed by the PCI Express specification. Intel Stratix 10 TX devices also support partial reconfiguration across the PCI Express bus which reduces system down time by keeping the PCI Express link active while the device is being reconfigured. 1.24. Partial and Dynamic Reconfiguration Partial reconfiguration allows you to reconfigure part of the FPGA while other sections continue running. This capability is required in systems where uptime is critical, because it allows you to make updates or adjust functionality without disrupting services. In addition to lowering power and cost, partial reconfiguration also increases the effective logic density by removing the necessity to place in the FPGA those functions that do not operate simultaneously. Instead, these functions can be stored in external memory and loaded as needed. This reduces the size of the required FPGA by allowing multiple applications on a single FPGA, saving board space and reducing power. The partial reconfiguration process is built on top of the proven incremental compile design flow in the Intel Quartus Prime design software Dynamic reconfiguration in Intel Stratix 10 TX devices allows transceiver data rates, protocols and analog settings to be changed dynamically on a channel-by-channel basis while maintaining data transfer on adjacent transceiver channels. Dynamic reconfiguration is ideal for applications that require on-the-fly multiprotocol or multi- rate support. Both the PMA and PCS blocks within the transceiver can be reconfigured using this technique. Dynamic reconfiguration of the transceivers can be used in conjunction with partial reconfiguration of the FPGA to enable partial reconfiguration of both core and transceivers simultaneously. 1.25. Fast Forward Compile The innovative Fast Forward Compile feature in the Intel Quartus Prime software identifies performance bottlenecks in your design and provides detailed, step-by-step performance improvement recommendations that you can then implement. The Compiler reports estimates of the maximum operating frequency that can be achieved by applying the recommendations. As part of the new Hyper-Aware design flow, Fast Forward Compile maximizes the performance of your Intel Stratix 10 TX design and achieves rapid timing closure. (8) Contact My Intel Support for additional information. 1. Intel® Stratix® 10 TX Device Overview 683717 | 2022.08.18 Send Feedback Intel® Stratix® 10 TX Device Overview

Previously, this type of optimization required multiple time-consuming design iterations, including full design re-compilation to determine the effectiveness of the changes. Fast Forward Compile enables you to make better decisions about where to focus your optimization efforts, and how to increase your design performance and throughput. This technique removes much of the guesswork of performance exploration, resulting in fewer design iterations and as much as 2X core performance gains for Intel Stratix 10 designs. 1.26. Single Event Upset (SEU) Error Detection and Correction Intel Stratix 10 TX devices offer robust SEU error detection and correction circuitry. The detection and correction circuitry includes protection for Configuration RAM (CRAM) programming bits and user memories. The CRAM is protected by a continuously running parity checker circuit with integrated ECC that automatically corrects one or two bit errors and detects higher order multibit errors. The physical layout of the CRAM array is optimized to make the majority of multi-bit upsets appear as independent single-bit or double-bit errors which are automatically corrected by the integrated CRAM ECC circuitry. In addition to the CRAM protection, user memories also include integrated ECC circuitry and are layout optimized for error detection and correction. The SEU error detection and correction hardware is supported by both soft IP and the Intel Quartus Prime software to provide a complete SEU mitigation solution. The components of the complete solution include:

• Hard error detection and correction for CRAM and user eSRAM and M20K memory blocks
• Optimized physical layout of memory cells to minimize probability of SEU
• Sensitivity processing soft IP that reports if CRAM upset affects a used or unused bit
• Fault injection soft IP with the Intel Quartus Prime software support that changes state of CRAM bits for testing purposes
• Hierarchy tagging in the Intel Quartus Prime software
• Triple Mode Redundancy (TMR) used for the Secure Device Manager and critical on-chip state machines In addition to the SEU mitigation features listed above, the Intel 14 nm tri-gate process technology used for Intel Stratix 10 TX devices is based on FinFET transistors which have reduced SEU susceptibility versus conventional planar transistors. 1.27. Document Revision History for the Intel Stratix 10 TX Device Overview Version Changes

2022.08.18 Made the following change:

• Removed the details of Register state readback and writeback feature from Key Features of Intel Stratix 10 TX Devices Compared to Stratix V Devices table.
• Removed readback and writeback feature from advatnages in Device Configuration and Secure Device Manager (SDM) section.

2020.09.28 Made the following change:

continued... 1. Intel® Stratix® 10 TX Device Overview 683717 | 2022.08.18 Intel® Stratix® 10 TX Device Overview Send Feedback

• Added black key provisioning (-BK) devices. See the "Sample Ordering Code" figure in Available Options.

2020.03.24 Made the following change:

• Added advanced security (-AS) devices.

2019.08.19 Made the following changes:

• Added composition details for the leaded and lead-free contact device options.
• Updated family plan device options and added a tile layout variant.

2019.03.11 Made the following changes:

• Updated maximum transceiver data rate from 30 Gbps to 28.9 Gbps.

2019.02.15 Made the following changes:

• Added "Figure 1: Sample Ordering Code and Available Options for Intel Stratix 10 Devices" in the "Intel Stratix 10 TX Devices" section.
• Changed the number of eSRAM memory block to 47.25 Mb and the number of embedded memory to 94.5 Mb.
• Changed the number of maximum transceiver data rate to 57.8 Gbps.
• Added the resource availabilities for the TX 400, TX 650, TX 850, and TX 1100 devices in the "Intel Stratix 10 TX Family Plan—FPGA Core (part 1)" table.
• Added the resource availabilities for the TX 400, TX 650, TX 850, and TX 1100 devices in the "Intel Stratix 10 TX Family Plan - Interconnects, PLLs and Hard IP (part 1)" table.
• Added the resource availabilities for the TX 400, TX 650, TX 850, and TX 1100 devices in the "Intel Stratix 10 TX Package Plan" table.
• Updated Tile Layout diagrams for NF43 (F1760) and SF50 (F2397) packages.

2018.08.10 Made the following changes:

• Changed the direction arrow from the coefficient registers block in the "DSP Block: High Precision Fixed Point Mode" figure.
• Changed the descriptions for the core process technology and power management features in the "Intel Stratix 10 TX Device Features" table.
• Changed the description of the SmartVID in the "Power Management" section.

2018.02.21 Made the following changes:

• Updated the fPLL counts in the "Intel Stratix 10 TX Family Plan - Interconnects, PLLs and Hard IP (part 2)" table.
• Changed the fPLL counts in the "Fractional Synthesis and I/O PLLs" section.

2017.10.30 Made the following changes:

• Changed the resource availabilities for the TX 1650 and TX 2100 devices in the "Intel Stratix 10 TX Family Plan—FPGA Core (part 1)" table.

2017.08.02 Made the following changes:

• Only some of the devices have eSRAM. Mentioned this in the appropriate places in the app note
• 100Gbe Hard IP included in the bottom left H-tile of the Intel Stratix 10 TX Architecture Block Diagram
• Added a new column "HPS" in the Intel Stratix 10 TX Family Plan - FPGA Core (part 1) table
• Updated table "Intel Stratix 10 TX Family Plan - Interconnects, PLLs and Hard IP (part 2)"
• Added Tile Layout diagrams 2016.10.31 Initial release. 1. Intel® Stratix® 10 TX Device Overview 683717 | 2022.08.18 Send Feedback Intel® Stratix® 10 TX Device Overview