RD48F3000L0ZBQ0

28F640L30 INTEL | Alldatasheet

Document overview

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• PDF pages: 100

Technical content

Datasheet sections

• 1.0 Introduction
• 1.1 Nomenclature
• 1.2 Acronyms
• 1.3 Conventions
• 2.0 Device Description
• 2.1 Product Overview
• 2.2 Ballout DiagramsforVFBGAPackage
• 2.3 Ballout DiagramsforIntel®StackedChipScalePackage
• 2.4 Signal DescriptionsforVFBGAPackage
• 2.4.1 SignalDescriptionsfor128/0and256/0Stacked-CSP
• 2.5 Memory Map
• 3.0 Device Operations
• 3.1 Bus Operations
• 3.1.1 Reads
• 3.1.2 Writes
• 3.1.3 OutputDisable
• 3.1.4 Standby
• 3.1.5 Reset
• 3.2 Device Commands
• 3.3 Command Definitions
• 4.0 Read Operations
• 4.1 Asynchronous Page-ModeRead
• 4.2 Synchronous Burst-ModeRead
• 4.2.1 BurstSuspend
• 4.3 Read ConfigurationRegister(RCR)
• 4.3.1 ReadMode
• 4.3.2 LatencyCount
• 4.3.3 WAITPolarity
• 4.3.3.1 WAITSignalFunction
• 4.3.4 DataHold
• 4.3.5 WAITDelay
• 4.3.6 BurstSequence
• 4.3.7 ClockEdge
• 4.3.8 BurstWrap
• 4.3.9 BurstLength
• 5.0 Programming Operations
• 5.1 Word Programming
• 5.1.1 FactoryWordProgramming
• 5.2 Buffered Programming
• 5.3 Buffered EnhancedFactoryProgramming
• 5.3.1 BufferedEFPRequirementsandConsiderations
• 5.3.2 BufferedEFPSetupPhase
• 5.3.3 BufferedEFPProgram/VerifyPhase

1.8VoltIntelStrataFlash®Wireless Memorywith3.0-VoltI/O(L30) 28F640L30,28F128L30,28F256L30 Datasheet ProductFeatures The1.8VoltIntelStrataFlash®wirelessmemorywith3-VoltI/Oproductisthelatestgenerationof IntelStrataFlash®memorydevicesfeaturingflexible,multiple-partition,dualoperation.Itprovideshigh performancesynchronous-burstreadmodeandasynchronousreadmodeusing1.8voltlow-voltage,multi- levelcell(MLC)technology. Themultiple-partitionarchitectureenablesbackgroundprogrammingorerasingtooccurinonepartition whilecodeexecutionordatareadstakeplaceinanotherpartition.Thisdual-operationarchitecturealso allowstwoprocessorstointerleavecodeoperationswhileprogramanderaseoperationstakeplaceinthe background. The1.8VoltIntelStrataFlash®wirelessmemorywith3-VoltI/OdeviceismanufacturedusingIntel 0.13µmETOX™VIIIprocesstechnology.Itisavailableinindustry-standardchipscalepackaging. ■ HighperformanceRead-While-Write/Erase —85nsinitialaccess —52MHzwithzerowaitstate,17nsclock-to-data outputsynchronous-burstmode —25nsasynchronous-pagemode —4-,8-,16-,andcontinuous-wordburstmode —Burstsuspend —ProgrammableWAITconfiguration —BufferedEnhancedFactoryProgramming (BufferedEFP):3.5µs/byte(Typ) —1.8Vlow-powerbufferedandnon-buffered programming@10µs/byte(Typ) ■ Architecture —Asymmetrically-blockedarchitecture —Multiple8-Mbitpartitions:64Mband128Mb devices —Multiple16-Mbitpartitions:256Mbdevices —Four16-KWordparameterblocks:topor bottomconfigurations —64K-Wordmainblocks —Dual-operation:Read-While-Write(RWW)or Read-While-Erase(RWE) —Statusregisterforpartitionanddevicestatus ■ Power —1.7V-2.0VVCCoperation —I/Ovoltage:2.2V-3.3V —Standbycurrent:30µA(Typ) —4-Wordsynchronousreadcurrent:17mA(Typ) @54MHz —AutomaticPowerSavings(APS)mode ■ Software —20µs(Typ)programsuspend —20µs(Typ)erasesuspend —Intel®FlashDataIntegrator(FDI)optimized —BasicCommandSet(BCS)andExtended CommandSet(ECS)compatible —CommonFlashInterface(CFI)capable ■ Security —OTPspace: — 64uniquedeviceidentifierbits — 64user-programmableOTPbits — Additional2048user-programmableOTP bits —Absolutewriteprotection:VPP=GND —Power-transitionerase/programlockout —Individualzero-latencyblocklocking —Individualblocklock-down ■ QualityandReliability —Expandedtemperature:–25°Cto+85°C —Minimum100,000erasecyclesperblock —ETOX™ VIIIprocesstechnology(0.13µm) ■ DensityandPackaging —64-,128-and256-MbitdensityinVFBGA packages —128/0,and256/0DensityinStacked-CSP —16-bitwidedatabus OrderNumber:251903-003 April2003 Notice:Thisdocumentcontainsinformationonproductsinthedesignphaseof development.Theinformationhereissubjecttochangewithoutnotice.Donotfinalize adesignwiththisinformation.

INFORMATIONINTHISDOCUMENTISPROVIDEDINCONNECTIONWITHINTELPRODUCTS.NOLICENSE,EXPRESSORIMPLIED,BY ESTOPPELOROTHERWISE,TOANYINTELLECTUALPROPERTYRIGHTSISGRANTEDBYTHISDOCUMENT.EXCEPTASPROVIDEDIN INTEL'STERMSANDCONDITIONSOFSALEFORSUCHPRODUCTS,INTELASSUMESNOLIABILITYWHATSOEVER,ANDINTELDISCLAIMS ANYEXPRESSORIMPLIEDWARRANTY,RELATINGTOSALEAND/ORUSEOFINTELPRODUCTSINCLUDINGLIABILITYORWARRANTIES RELATINGTOFITNESSFORAPARTICULARPURPOSE,MERCHANTABILITY,ORINFRINGEMENTOFANYPATENT,COPYRIGHTOROTHER INTELLECTUALPROPERTYRIGHT.Intelproductsarenotintendedforuseinmedical,lifesaving,orlifesustainingapplications. Intelmaymakechangestospecificationsandproductdescriptionsatanytime,withoutnotice. Thisdocumentcontainsinformationonproductsinthedesignphaseofdevelopment.Theinformationhereissubjecttochangewithoutnotice.Donot finalizeadesignwiththisinformation. The1.8VoltIntelStrataFlash®WirelessMemorywith3.0VoltI/Odatasheetmaycontaindesigndefectsorerrorsknownaserratawhichmaycause theproducttodeviatefrompublishedspecifications.Currentcharacterizederrataareavailableonrequest. ContactyourlocalIntelsalesofficeoryourdistributortoobtainthelatestspecificationsandbeforeplacingyourproductorder. Copiesofdocumentswhichhaveanorderingnumberandarereferencedinthisdocument,orotherIntelliteraturemaybeobtainedbycalling1-800- 548-4725orbyvisitingIntel'swebsiteathttp://www.intel.com. Copyright©2003,IntelCorporation *Othernamesandbrandsmaybeclaimedasthepropertyofothers.

28F640L30,28F128L30,28F256L30

8.2.2 SynchronousandAsynchronousRead-While-Write

28F640L30,28F128L30,28F256L30

28F640L30,28F128L30,28F256L30 RevisionHistory Revision Date Revision Description 10/14/02 -001 Initial Release 02/08/03 -002 Revised 256MbPartitionSize Revised256MbMemoryMap ChangedWAITfunctiontode-assertduringAsynchronousOperations(Asyn- chronousReadsandallWrites) ChangedWAITfunctiontoactiveduringSynchronousNon-ArrayRead UpdatedallWaveformstoreflectnewWAITfunction RevisedSection8.2.2 AddedSynchronousReadtoWritetransitionSection AddednewACspecs:R15,R16,R17,R111,R311,R312,W21,andW22 Varioustextedits 04/11/03 -003 Improved Bin1to85nsfrom90ns ImprovedFrequencyto52MHzfrom50MHz AddedStacked-CSPfor128/0and256/0Ball-outandMechanicalDrawing

28F640L30,28F128L30,28F256L30 Datasheet 7

1.0 Introduction

Thisdocumentprovidesinformationaboutthe1.8VoltIntelStrataFlash®wirelessmemorywith 3-VoltI/O(L30)device.ThisdocumentdescribestheL30flashmemorydevicefeatures,operation, andspecifications.

1.1 Nomenclature

1.8V:VCCvoltagerangeof1.7V–2.0V(exceptwherenoted) 3.0VRange:VCCQvoltagerangeof2.2V–3.3V VPP=9.0V :VPPvoltagerangeof8.5V–9.5V Block:Agroupofbits,bytesorwordswithintheflashmemoryarraythaterasesimultaneously whentheErasecommandisissuedtothedevice.TheL30flashmemorydevicehastwoblock sizes:16K-Word,and64K-Word. Mainblock:Anarrayblockthatisusuallyusedtostorecodeand/ordata.Mainblocksarelarger thanparameterblocks. Parameterblock:Anarrayblockthatisusuallyusedtostorefrequentlychangingdataorsmall systemparametersthattraditionallywouldbestoredinEEPROM. Topparameterdevice:Previouslyreferredtoasatop-bootdevice,adevicewithitsparameter partitionlocatedatthehighestphysicaladdressofitsmemorymap.Parameterblockswithina parameterpartitionarelocatedatthehighestphysicaladdressoftheparameterpartition. Bottomparameterdevice:Previouslyreferredtoasabottom-bootdevice,adevicewithits parameterpartitionlocatedatthelowestphysicaladdressofitsmemorymap.Parameterblocks withinaparameterpartitionarelocatedatthelowestphysicaladdressoftheparameterpartition. Partition:Agroupofblocksthatsharecommonprogram/erasecircuitry.Blockswithinapartition alsoshareacommonstatusregister.Ifanyblockwithinapartitionisbeingprogrammedorerased, onlystatusregisterdata(ratherthanarraydata)isavailablewhenanyaddresswithinthatpartition isread. Mainpartition:Apartitioncontainingonlymainblocks. Parameterpartition:Apartitioncontainingparameterblocksandmainblocks.

1.2 Acronyms

CUI:CommandUserInterface MLC:Multi-LevelCell OTP:One-TimeProgrammable PLR:ProtectionLockRegister PR:ProtectionRegister RCR:ReadConfigurationRegister RFU:ReservedforFutureUse SR:StatusRegister WSM:WriteStateMachine

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1.3 Conventions

VCC:signalorvoltageconnection VCC:signalorvoltagelevel 0x:hexadecimalnumberprefix 0b:binarynumberprefix SR[4]:Denotesanindividualregisterbit. A[15:0]:Denotesagroupofsimilarlynamedsignals,suchasaddressordatabus. A5:Denotesoneelementofasignalgroupmembership,suchasanaddress. bit:binaryunit byte:eightbits word:twobytes,orsixteenbits Kbit:1024bits KByte:1024bytes KWord:1024words Mbit:1,048,576bits MByte:1,048,576bytes MWord:1,048,576words

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2.0 Device Description

Thissectionprovidesanoverviewofthefeaturesandcapabilitiesofthe1.8VoltIntelStrataFlash® wirelessmemorywith3-VoltI/O(L30)device.

2.1 Product Overview

The1.8VoltIntelStrataFlash®wirelessmemorywith3-VoltI/O(L30)deviceprovidesread-while- writeandread-while-erasecapabilitywithdensityupgradesthrough256-Mbit.Thisfamilyof devicesprovideshighperformanceatlowvoltageona16-bitdatabus.Individuallyerasable memoryblocksaresizedforoptimumcodeanddatastorage. Eachdevicedensitycontainsoneparameterpartitionandseveralmainpartitions.Theflash memoryarrayisgroupedintomultiple8-Mbitpartitions.Bydividingtheflashmemoryinto partitions,programoreraseoperationscantakeplaceatthesametimeasreadoperations. Althougheachpartitionhaswrite,eraseandburstreadcapabilities,simultaneousoperationis limitedtowriteoreraseinonepartitionwhileotherpartitionsareinreadmode.TheL30flash memorydeviceallowsburstreadsthatcrosspartitionboundaries.Userapplicationcodeis responsibleforensuringthatburstreadsdon’tcrossintoapartitionthatisprogrammingorerasing. Uponinitialpoweruporreturnfromreset,thedevicedefaultstoasynchronouspage-moderead. ConfiguringtheReadConfigurationRegisterenablessynchronousburst-modereads.In synchronousburstmode,outputdataissynchronizedwithauser-suppliedclocksignal.AWAIT signalprovideseasyCPU-to-flashmemorysynchronization. Inadditiontotheenhancedarchitectureandinterface,thedeviceincorporatestechnologythat enablesfastfactoryprogramanderaseoperations.Designedforlow-voltagesystems,theL30flash memorydevicesupportsreadoperationswithVCCat1.8V,anderaseandprogramoperationswith VPPat1.8Vor9.0V.BufferedEnhancedFactoryProgramming(BufferedEFP)providesthe fastestflasharrayprogrammingperformancewithVPPat9.0Volt,whichincreasesfactory throughput.WithVPPat1.8V,VCCandVPPcanbetiedtogetherforasimple,ultralowpower design.Inadditiontovoltageflexibility,adedicatedVPPconnectionprovidescompletedata protectionwhenVPPislessthanVPPLK. ACommandUserInterface(CUI)istheinterfacebetweenthesystemprocessorandallinternal operationsofthedevice.AninternalWriteStateMachine(WSM)automaticallyexecutesthe algorithmsandtimingsnecessaryforblockeraseandprogram.AStatusRegisterindicateseraseor programcompletionandanyerrorsthatmayhaveoccurred. Anindustry-standardcommandsequenceinvokesprogramanderaseautomation.Eacherase operationerasesoneblock.TheEraseSuspendfeatureallowssystemsoftwaretopauseanerase cycletoreadorprogramdatainanotherblock.ProgramSuspendallowssystemsoftwaretopause programmingtoreadotherlocations.Dataisprogrammedinwordincrements(x16). TheL30flashmemorydeviceofferspowersavingsthroughAutomaticPowerSavings(APS) modeandstandbymode.ThedeviceautomaticallyentersAPSfollowingread-cyclecompletion. StandbyisinitiatedwhenthesystemdeselectsthedevicebydeassertingCE#orbyassertingRST#. Combined,thesefeaturescansignificantlyreducepowerconsumption. TheL30flashmemorydevice’sprotectionregisterallowsuniqueflashdeviceidentificationthat canbeusedtoincreasesystemsecurity.Also,theindividualBlockLockfeatureprovideszero- latencyblocklockingandunlocking.

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2.2 Ballout DiagramsforVFBGAPackage

TheL30flashmemorydeviceisavailableinaVFBGApackagewith0.75mmball-pitch.Figure1 showstheballoutforthe64-Mbitand128-Mbitdevicesinthe56-ballVFBGApackagewitha7x 8active-ballmatrix.Figure2showsthedeviceballoutforthe256-Mbitdeviceinthe63-ballVF BGApackagewitha7x9active-ballmatrix.Bothpackagedensitiesareidealforspace- constrainedboardapplications NOTE: Onlower-densitydevices,upper-addressballscanbetreatedasNC.(e.g.,for64-Mbitdensity,A22willbeNC) NOTE: OnlowerdensitydevicesupperaddressballscanbetreatedasRFUs.(A24isfor512MbandA25isfor1Gbdensities.)All balllocationsarepopulated. Figure1.7x8Active-BallMatrixfor64-,and128-MbitDensitiesinVFBGAPackages Figure2.7x9Active-BallMatrixfor256-MbitDensityinVFBGAPackage VFBGA7x8 BottomView-BallSideUp VFBGA7x8 TopView-BallSideDown 23456781 A8 VSS VCC VPP A18 A6 A4 A9 A20 CLK RST# A17 A5 A3 A10 A21 WE# A19 A7 A2 A14 WAIT A16 D12 WP# A22 D15 D6 D4 D2 D1 CE# A0 D14 D13 D11 D10 D9 D0 OE# ADV# VSSQ VCC D3 VCCQ D8 VSSQ A11 A12 A13 A15 VCCQ VSS D7 D5 A B C D E F G 23456781 A8VSSVCCVPPA18A6A4 A9A20CLKRST#A17A5A3 A10A21WE#A19A7A2 A14WAITA16D12WP#A22 D15D6D4D2D1CE#A0 D14D13D11D10D9D0OE# ADV# VSSQVCCD3VCCQD8VSSQ A11 A12 A13 A15 VCCQ VSS D7D5 A B C D E F G RFU VCCA4 A6 A18 VPP VSS A8 A11 RFU CLKA3 A5 A17 RST# A20 A9 A12 A25 ADV#A2 A7 A19 WE# A21 A10 A13 A24 A16A1 A22 WP# D12 WAIT A14 A15 A23 D4A0 CE# D1 D2 D6 D15 VCCQ RFU D11OE# D0 D9 D10 D13 D14 VSS RFU VCCVSSQ D8 VCCQ D3 D5 VSSQ D7 BottomView - BallSideUp A B C D E F G DU DU DU DU DU DU DU DU DU DU DU DU DU DU DU DU 11 101213 7 5 4 3 2 1896 RFUVCC A4 A6A18VPPVSSA8A11 RFUCLK A3 A5A17RST#A20A9A12 A25ADV# A2A7A19WE#A21A10A13 A24A16 A1 A22WP#D12WAITA14A15 A23D4 A0CE#D1D2D6D15VCCQ RFUD11 OE# D0D9D10D13D14VSS RFUVCC VSSQ D8VCCQD3D5VSSQD7 TopView-BallSideDown A B C D E F G DU DUDU DU DU DUDU DUDU DUDU DU DU DUDU DU 1110 12 13754321 896

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2.3 Ballout DiagramsforIntel®StackedChipScalePackage

The1.8VoltIntelStrataFlash®wirelessmemoryinQuad+balloutdeviceisavailableinan88-ball (80-activeball)Intel®StackedChipScalePackageforthe128-Mbitdeviceandinan88-ball(80- activeball)Intel®Ultra-ThinStackedChipScalePackageforthe256-Mbitdevice.Figure3shows thesignalballout.RefertoSection5.0forMechanicalPackageInformation. Figure3.88-Ball(80-ActiveBall)Stacked-CSPPackageBallout Flashspecific SRAM/PSRAM specific Global Legend: TopView-BallSideDown 87654321 A B C D E F G H J K L M DU DU DU DU DUDUDU DU A2 A7 A1 A6 A18 A19 VSS VSSA23 A24 A25 A17 F2-VCC CLK A21 A22 A12 A11 A13A9P1-CS#F-VPP, F-VPEN A20 A10 A15 F-WE# A8 D8 D2 D10 D5 D13 WAIT A14 A16 F1-CE# P-Mode VSS VSS VSS P2-CS# F1-VCC F2-VCC VCCQF3-CE# D0 D1 D4 D6 D15D11 D12 D14 F1-OE# F2-OE# P-VCC S-CS2 R-WE# R-UB# R-LB# R-OE# S-VCC S-CS1# F1-VCC F-WP# ADV# F-RST# F2-CE# VCCQ VSS VSSVCCQ VSS

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2.4 Signal DescriptionsforVFBGAPackage

Table1describestheactivesignalsusedontheL30flashmemorydevice. Table1.SignalDescriptions Symbol Type Name andFunction A[MAX:0] In ADDRESS:Deviceaddressinputs.64-Mbit:A[21:0];128-Mbit:A[22:0];256-Mbit:A[23:0]. D[15:0] In/Out DATAINPUT/OUTPUTS:Inputsdataandcommandsduringwritecycles;outputsdataduringmemory, StatusRegister,ProtectionRegister,andReadConfigurationRegisterreads.Databallsfloatwhenthe CE#orOE#arede-asserted.Dataisinternallylatchedduringwrites. ADV# In ADDRESSVALID:Active-lowinput.Duringsynchronousreadoperations,addressesarelatchedon therisingedgeofADV#,oronthenextvalidCLKedgewithADV#low,whicheveroccursfirst. Inasynchronousmode,theaddressislatchedwhenADV#goinghighorcontinuouslyflowsthroughif ADV#isheldlow. CE# In CHIPENABLE:Active-lowinput.CE#-lowselectsthedevice.CE#-highdeselectsthedevice,placingit instandby,withD[15:0]andWAITinHigh-Z. CLK In CLOCK:Synchronizesthedevicewiththesystem’sbusfrequencyinsynchronous-readmodeand incrementstheinternaladdressgenerator.Duringsynchronousreadoperations,addressesare latchedontherisingedgeofADV#,oronthenextvalidCLKedgewithADV#low,whicheveroccurs first. OE# In OUTPUTENABLE:Active-lowinput.OE#-lowenablesthedevice’soutputdatabuffersduringread cycles.OE#-highplacesthedataoutputsinHigh-ZandWAITinHigh-Z. RST# In RESET:Active-lowinput.RST#resetsinternalautomationandinhibitswriteoperations.Thisprovides dataprotectionduringpowertransitions.RST#-highenablesnormaloperation.Exitfromresetplaces thedeviceinasynchronousreadarraymode. WAIT Out WAIT:Indicatesdatavalidinsynchronousarrayornon-arrayburstreads.ConfigurationRegisterbit10 (CR.10,WT)determinesitspolaritywhenasserted.WithCE#andOE#atVIL,WAIT’sactiveoutputis VOLorVOHwhenCE#andOE#areasserted.WAITishigh-ZifCE#orOE#isVIH.

• I n synchronousarrayornon-arrayreadmodes,WAITindicatesinvaliddatawhenassertedand validdatawhende-asserted.
• I n asynchronouspagemode,andallwritemodes,WAITisde-asserted. WE# In WRITEENABLE:Active-lowinput.WE#controlswritestothedevice.Addressanddataarelatchedon therisingedgeofWE#. WP# In WRITEPROTECT:Active-lowinput.WP#-lowenablesthelock-downmechanism.Blocksinlock-down cannotbeunlockedwiththeUnlockcommand.WP#-highoverridesthelock-downfunctionenabling blockstobeerasedorprogrammedusingsoftwarecommands. VPP Pwr/l ERASEANDPROGRAMPOWER:Avalidvoltageonthispinallowserasingorprogramming.Memory contentscannotbealteredwhenVPP≤VPPLK.BlockeraseandprogramatinvalidVPPvoltagesshould notbeattempted. SetVPP=VCCforin-systemprogramanderaseoperations.Toaccommodateresistorordiodedrops fromthesystemsupply,theVIHlevelofVPPcanbeaslowasVPP1min.VPPmustremainaboveVPP1 mintoperformin-systemflashmodification.VPPmaybe0Vduringreadoperations. VPP2canbeappliedtomainblocksfor1000cyclesmaximumandtoparameterblocksfor2500cycles. VPPcanbeconnectedto12Vforacumulativetotalnottoexceed80hours.Extendeduseofthispin at12Vmayreduceblockcyclingcapability. VCC Pwr DEVICECOREPOWERSUPPLY:Core(logic)sourcevoltage.Writestotheflasharrayareinhibited whenVCC≤VLKO.OperationsatinvalidVCCvoltagesshouldnotbeattempted. VCCQ Pwr OUTPUTPOWERSUPPLY:Output-driversourcevoltage. VSS Pwr GROUND:Groundreferencefordevicelogicvoltages.Connecttosystemground. VSSQ Pwr GROUND:Groundreferencefordeviceoutputvoltages.Connecttosystemground. DU - DON’TUSE:Donotusethisball.Thisballshouldnotbeconnectedtoanypowersupplies,signalsor otherballs,andmustbeleftfloating. NC - NOCONNECT:Nointernalconnection;canbedrivenorfloated. RFU - RESERVEDforFUTUREUSE:ReservedbyIntelforfuturedevicefunctionalityandenhancement.

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2.4.1 Signal Descriptionsfor128/0and256/0Stacked-CSP

Table2describestheactivesignalsusedonthe128/0and256/0-MbitS-CSP. Table2.DeviceSignalDescriptionsforS-CSP(Sheet1of2) Symbol Type Description A[Max:0] Input ADDRESSINPUTS:Inputsforalldieaddressesduringreadandwriteoperations.

• 128-MbitDie:A[Max]=A22
• 256-MbitDie:A[Max]=A23 D[15:0] Input/ Output DATAINPUTS/OUTPUTS:Inputsdataandcommandsduringwritecycles,outputs dataduringreadcycles.Datasignalsfloatwhenthedeviceoritsoutputsare deselected.Dataisinternallylatchedduringwrites. CE#1 CE#2 Input FLASHCHIPENABLE:Low-true:CE#-lowselectstheassociatedflashmemory die.Whenasserted,flashinternalcontrollogic,inputbuffers,decoders,andsense amplifiersareactive.Whendeasserted,theassociatedflashdieisdeselected, powerisreducedtostandbylevels,dataandWAIToutputsareplacedinhigh-Z state. CE#1selectsflashdie#1;CE#2selectsflashdie#2.CE#2isavailableonstacked combinationswithtwoflashdieandisRFU(ReservedForFutureUse)onstacked combinationswithonlyoneflashdie. S-CS1# S-CS2 Input SRAMCHIPSELECTS:WhenbothSRAMchipselectsareasserted,SRAMinternal controllogic,inputbuffers,decoders,andsenseamplifiersareactive.Wheneither/ bothSRAMchipselectsaredeasserted(S-CS1#=VIHorS-CS2=VIL),theSRAM isdeselectedanditspowerisreducedtostandbylevels. TreatthissignalasNC(NoConnect)forthisdevice. P-CS# Input PSRAMCHIPSELECT:Low-true;Whenasserted,PSRAMinternalcontrollogic, inputbuffers,decoders,andsenseamplifiersareactive.Whendeasserted,the PSRAMisdeselectedanditspowerisreducedtostandbylevels. TreatthissignalasNC(NoConnect)forthisdevice. OE#1 OE#2 Input FLASHOUTPUTENABLE:Low-true;OE#-lowenablestheflashoutputbuffers. OE#-highdisablestheflashoutputbuffers,andplacestheflashoutputsinHigh-Z. OE#1controlstheoutputsofflashdie#1;OE#2controlstheoutputsofflashdie#2. OE#2isavailableonstackedcombinationswithtwoflashdieandisRFUonstacked combinationswithonlyoneflashdie. R-OE# Input RAMOUTPUTENABLE:Low-true;R-OE#-lowenablestheselectedRAMoutput buffers.R-OE#-highdisablestheRAMoutputbuffers,andplacestheselectedRAM outputsinHigh-Z. TreatthissignalasNC(NoConnect)forthisdevice. WE# Input FLASHWRITEENABLE:Low-true;WE#controlswritestotheselectedflashdie. AddressanddataarelatchedontherisingedgeofWE#. R-WE# Input RAMWRITEENABLE:Low-true;R-WE#controlswritestotheselectedRAMdie. TreatthissignalasNC(NoConnect)forthisdevice. CLK Input FLASHCLOCK:Synchronizesthedevicewiththesystem’sbusfrequencyin synchronous-readmodeandincrementstheinternaladdressgenerator.During synchronousreadoperations,addressesarelatchedontherisingedgeofADV#,or onthenextvalidCLKedgewithADV#low,whicheveroccursfirst. WAIT Output FLASHWAIT:Indicatesdatavalidinsynchronousarrayornon-arrayburstreads. ConfigurationRegisterbit10(CR.10,WT)determinesitspolaritywhenasserted. WithCE#andOE#atVIL,WAIT’sactiveoutputisVOLorVOHwhenCE#andOE# areasserted.WAITishigh-ZifCE#orOE#isVIH.
• I n synchronousarrayornon-arrayreadmodes,WAITindicatesinvaliddata whenassertedandvaliddatawhende-asserted.
• I n asynchronouspagemode,andallwritemodes,WAITisde-asserted.

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WP# Input FLASHWRITEPROTECT:Low-true;WP#enables/disablesthelock-down protectionmechanismoftheselectedflashdie.WP#-lowenablesthelock-down mechanism-lockeddownblockscannotbeunlockedwithsoftwarecommands. WP#-highdisablesthelock-downmechanism,allowinglockeddownblockstobe unlockedwithsoftwarecommands. ADV# Input FLASHADDRESSVALID:Active-lowinput.Duringsynchronousreadoperations, addressesarelatchedontherisingedgeofADV#,oronthenextvalidCLKedge withADV#low,whicheveroccursfirst. Inasynchronousmode,theaddressislatchedwhenADV#goinghighor continuouslyflowsthroughifADV#isheldlow. R-UB# R-LB# Input RAMUPPER/LOWERBYTEENABLES:Low-true;DuringRAMreads,R-UB#-low enablestheRAMhighorderbytesonD[15:8],andR-LB#-lowenablestheRAMlow- orderbytesonD[7:0]. TreatthissignalasNC(NoConnect)forthisdevice. RST# Input FLASHRESET:Low-true;RST#-lowinitializesflashinternalcircuitryanddisables flashoperations.RST#-highenablesflashoperation.Exitfromresetplacestheflash inasynchronousreadarraymode. P-Mode Input PSRAMMODE:Low-true;P-MODEisusedtoprogramtheconfigurationregister, andenter/exitlowpowermode. TreatthissignalasNC(NoConnect)forthisdevice. VPP, VPEN Power FLASHPROGRAM/ERASEPOWER:Avalidvoltageonthispinallowserasingor programming.MemorycontentscannotbealteredwhenVPP≤VPPLK.Blockerase andprogramatinvalidVPPvoltagesshouldnotbeattempted. SetVPP=VCCforin-systemprogramanderaseoperations.Toaccommodate resistorordiodedropsfromthesystemsupply,theVIHlevelofVPPcanbeaslowas VPP1min.VPPmustremainaboveVPP1mintoperformin-systemflashmodification. VPPmaybe0Vduringreadoperations. VPP2canbeappliedtomainblocksfor1000cyclesmaximumandtoparameter blocksfor2500cycles.VPPcanbeconnectedto12Vforacumulativetotalnotto exceed80hours.Extendeduseofthispinat12Vmayreduceblockcycling capability VPEN((Erase/Program/BlockLockEnables)isnotavailableforL18/L30 products. VCC1 VCC2 Power FLASHLOGICPOWER:VCC1suppliespowertothecorelogicofflashdie#1; VCC2suppliespowertothecorelogicofflashdie#2.Writeoperationsareinhibited whenVCC<VLKO.DeviceoperationsatinvalidVCCvoltagesshouldnotbe attempted. S-VCC Power SRAMPOWERSUPPLY:SuppliespowerforSRAMoperations. TreatthissignalasNC(NoConnect)forthisdevice. P-VCC Power PSRAMPOWERSUPPLY:SuppliespowerforPSRAMoperations. TreatthissignalasNC(NoConnect)forthisdevice. VCCQ Power FLASHI/OPOWER:Supplypowerfortheinputandoutputbuffers. VSS Power GROUND:Connecttosystemground.DonotfloatanyVSSconnection. RFU RESERVEDforFUTUREUSE:Reserveforfuturedevicefunctionality/ enhancements.ContactIntelregardingtheirfutureuse. DU DON’TUSE:Donotconnecttoanyothersignal,orpowersupply;mustbeleft floating. NC NOCONNECT:Nointernalconnection;canbedrivenorfloated. Table2.DeviceSignalDescriptionsforS-CSP(Sheet2of2)

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2.5 Memory Map

The64Mband128Mbmemoryarrayisdividedintomultiple8-Mbitpartitions.Eachdevice densitycontainsoneparameterpartitionandseveralmainpartitions.The8-Mbittoporbottom parameterpartitioncontainsfour16K-Wordblocksandseven64K-Wordblocks.Thereare multiple8-Mbitmainpartitions.The8-Mbitmainpartitionseachcontainseight64K-Wordblocks. Thedevicemulti-partitionarchitectureisdividedasfollow:

• The64-Mbitdevicecontainseightpartitions:one8-Mbitparameterpartition,seven8-Mbit mainpartitions.
• The128-Mbitdevicecontainssixteenpartitions:one8-Mbitparameterpartition,fifteen8- Mbitmainpartitions.
• The256Mbmemoryarrayisdividedintomultiple16-Mbitpartitions.Eachdevicecontains oneparameterpartitionandfifteenmainpartitions.The16-Mbittoporbottomparameter partitioncontainsfour16K-Wordblocksandfifteen64K-Wordblocks.Therearefifteen16- Mbitmainpartitions.The16-Mbitmainpartitionseachcontainssixteen64K-Wordblocks. Table3andTable4showthetopandbottomparametermemorymaps. Table3.TopParameterMemoryMap Size(KW) Blk 64-Mbit Size (KW) Blk 128-Mbit 8-MbitParameter Partition OnePartition 16 66 3FC000-3FFFFF 8-MbitParameter Partition OnePartition 16 130 7FC000-7FFFFF 16 65 3F8000-3FBFFF 16 129 7F8000-7FBFFF 16 64 3F4000-3F7FFF 16 128 7F4000-7F7FFF 16 63 3F0000-3F3FFF 16 127 7F0000-7F3FFF 64 62 3E0000-3EFFFF 64 126 7E0000-7EFFFF… 64 56 380000-38FFFF 64 120 780000-78FFFF 8-MbitMain Partition Seven Partitions 64 55 370000-37FFFF 8-MbitMain Partitions Fifteen Partitions 64 119 770000-77FFFF 64 0 000000-00FFFF 64 0 000000-00FFFF Size(KW) Blk 256-Mbit 16-MbitParameter Partition OnePartition 16 258 FFC000-FFFFFF 16 257 FF8000-FFBFFF 16 256 FF4000-FF7FFF 16 255 FF0000-FF3FFF 64 254 FE0000-FEFFFF … 64 240 F00000-FFFFFF 16-MbitMainPartitions Seven Partitions 64 239 EF0000-EFFFFF… 64 128 800000-80FFFF Eight Partitions 64 127 7F0000-7FFFFF… 64 0 000000-00FFFF

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Table4.BottomParameterMemoryMap Size(KW) Blk 64-Mbit Size(KW) Blk 128-Mbit 8-MbitMain Partitions Seven Partitions 64 66 3F0000-3FFFFF 8-MbitMain Partitions Fifteen Partitions 64 130 7F0000-7FFFFF 64 11 080000-08FFFF 64 11 080000-08FFFF 8-MbitParameter Partition OnePartition 64 10 070000-07FFFF 8-MbitParameter Partition OnePartition 64 10 070000-07FFFF 64 4 010000-01FFFF 64 4 010000-01FFFF 16 3 00C000-00FFFF 16 3 00C000-00FFFF 16 2 008000-00BFFF 16 2 008000-00BFFF 16 1 004000-007FFF 16 1 004000-007FFF 16 0 000000-003FFF 16 0 000000-003FFF Size(KW) Blk 256-Mbit 16-MbitMainPartitions Eight Partitions 64 258 FF0000-FFFFFF… 64 131 100000-10FFFF Seven Partitions 64 130 7F0000-7FFFFF… 64 19 100000-10FFFF 16-MbitParameter Partition OnePartition 64 18 0F0000-0FFFFF… 64 4 010000-01FFFF 16 3 00C000-00FFFF 16 2 008000-00BFFF 16 1 004000-007FFF 16 0 000000-003FFF

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3.0 Device Operations

Thissectionprovidesanoverviewofdeviceoperations.ThesystemCPUprovidescontrolofallin- systemread,write,anderaseoperationsofthedeviceviathesystembus.Theon-chipWriteState Machine(WSM)managesallblock-eraseandword-programalgorithms. DevicecommandsarewrittentotheCommandUserInterface(CUI)tocontrolallflashmemory deviceoperations.TheCUIdoesnotoccupyanaddressablememorylocation;itisthemechanism throughwhichtheflashdeviceiscontrolled.

3.1 Bus Operations

CE#-lowandRST#highenabledevicereadoperations.Thedeviceinternallydecodesupper addressinputstodeterminetheaccessedpartition.ADV#-lowopenstheinternaladdresslatches. OE#-lowactivatestheoutputsandgatesselecteddataontotheI/Obus. Inasynchronousmode,theaddressislatchedwhenADV#goeshighorcontinuouslyflowsthrough ifADV#isheldlow.Insynchronousmode,theaddressislatchedbythefirstofeithertherising ADV#edgeorthenextvalidCLKedgewithADV#low(WE#andRST#mustbeVIH;CE#must beVIL).

3.1.1 Reads

Toperformareadoperation,RST#andWE#mustbedeassertedwhileCE#andOE#areasserted. CE#isthedevice-selectcontrol.Whenasserted,itenablestheflashmemorydevice.OE#isthe data-outputcontrol.Whenasserted,theaddressedflashmemorydataisdrivenontotheI/Obus. SeeSection4.0,“ReadOperations”onpage22fordetailsontheavailablereadmodes,andsee Section9.0,“SpecialReadStates”onpage47fordetailsregardingtheavailablereadstates. TheAutomaticPowerSavings(APS)featureprovideslowpoweroperationfollowingreadsduring activemode.Afterdataisreadfromthememoryarrayandtheaddresslinesarequiescent,APS automaticallyplacesthedeviceintostandby.InAPS,devicecurrentisreducedtoICCAPS(see Section11.3,“DCCurrentCharacteristics”onpage53).

3.1.2 Writes

Toperformawriteoperation,bothCE#andWE#areassertedwhileRST#andOE#aredeasserted. Duringawriteoperation,addressanddataarelatchedontherisingedgeofWE#orCE#, whicheveroccursfirst.Table5,“CommandBusCycles”onpage19showsthebuscyclesequence foreachofthesupporteddevicecommands,whileTable6,“CommandCodesandDefinitions”on page20describeseachcommand.SeeSection12.0,“ACCharacteristics”onpage55forsignal- timingdetails. Note: WriteoperationswithinvalidVCCand/orVPPvoltagescanproducespuriousresultsandshouldnot beattempted.

3.1.3 Output Disable

WhenOE#isdeasserted,deviceoutputsD[15:0]aredisabledandplacedinahigh-impedance (High-Z)state,WAITisalsoplacedinHigh-Z.

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3.1.4 Standby

WhenCE#isdeassertedthedeviceisdeselectedandplacedinstandby,substantiallyreducing powerconsumption.Instandby,thedataoutputsareplacedinHigh-Z,independentofthelevel placedonOE#.Standbycurrent,ICCS,istheaveragecurrentmeasuredoverany5mstimeinterval, 5µsafterCE#isdeasserted.Duringstandby,averagecurrentismeasuredoverthesametime interval5µsafterCE#isdeasserted. Whenthedeviceisdeselected(whileCE#isdeasserted)duringaprogramoreraseoperation,it continuestoconsumeactivepoweruntiltheprogramoreraseoperationiscompleted.

3.1.5 Reset

Aswithanyautomateddevice,itisimportanttoassertRST#whenthesystemisreset.Whenthe systemcomesoutofreset,thesystemprocessorattemptstoreadfromtheflashmemoryifitisthe systembootdevice.IfaCPUresetoccurswithnoflashmemoryreset,improperCPUinitialization mayoccurbecausetheflashmemorymaybeprovidingstatusinformationratherthanarraydata. Intel®flashmemorydevicesallowproperCPUinitializationfollowingasystemresetthroughthe useoftheRST#input.RST#shouldbecontrolledbythesamelow-trueresetsignalthatresetsthe systemCPU. Afterinitialpower-uporreset,thedevicedefaultstoasynchronousReadArray,andtheStatus Registerissetto0x80.AssertingRST#de-energizesallinternalcircuits,andplacestheoutput driversinHigh-Z.WhenRST#isasserted,thedeviceshutsdowntheoperationinprogress,a processwhichtakesaminimumamountoftimetocomplete.WhenRST#hasbeendeasserted,the deviceisresettoasynchronousReadArraystate. Note: IfRST#isassertedduringaprogramoreraseoperation,theoperationisterminatedandthe memorycontentsattheabortedlocation(foraprogram)orblock(foranerase)arenolongervalid, becausethedatamayhavebeenonlypartiallywrittenorerased. Whenreturningfromareset(RST#deasserted),aminimumwaitisrequiredbeforetheinitialread accessoutputsvaliddata.Also,aminimumdelayisrequiredafteraresetbeforeawritecyclecan beinitiated.Afterthiswake-upintervalpasses,normaloperationisrestored.SeeSection12.0,“AC Characteristics”onpage55fordetailsaboutsignal-timing.

3.2 Device Commands

DeviceoperationsareinitiatedbywritingspecificdevicecommandstotheCommandUser Interface(CUI).SeeTable5,“CommandBusCycles”onpage19. SeveralcommandsareusedtomodifyarraydataincludingWordProgramandBlockErase commands.WritingeithercommandtotheCUIinitiatesasequenceofinternally-timedfunctions thatculminateinthecompletionoftherequestedtask.However,theoperationcanbeabortedby eitherassertingRST#orbyissuinganappropriatesuspendcommand.

28F640L30,28F128L30,28F256L30 Datasheet 19 Table5.CommandBusCycles Mode Command Bus Cycles FirstBusCycle Second BusCycle Oper Addr 1 Data2 Oper Addr 1 Data2 Read ReadArray 1 Write PnA 0xFF ReadDeviceIdentifier ≥2 Write PnA 0x90 Read PBA+IA ID CFIQuery ≥2 Write PnA 0x98 Read PnA+QA QD ReadStatusRegister 2 Write PnA 0x70 Read PnA SRD ClearStatusRegister 1 Write X 0x50 Program WordProgram 2 Write WA 0x40/ 0x10 Write WA WD BufferedProgram3 ≥2W r i t eW A0 x E 8 W r i t e W A N -1 BufferedEnhancedFactoryProgram (BufferedEFP)4 > 2 Write WA 0x80 Write WA 0xD0 Erase BlockErase 2 Write BA 0x20 Write BA 0xD0 Suspend Program/EraseSuspend 1 Write X 0xB0 Program/EraseResume 1 Write X 0xD0 Block Locking/ Unlocking LockBlock 2 Write BA 0x60 Write BA 0x01 UnlockBlock 2 Write BA 0x60 Write BA 0xD0 Lock-downBlock 2 Write BA 0x60 Write BA 0x2F Protection ProgramProtectionRegister 2 Write PRA 0xC0 Write PRA PD ProgramLockRegister 2 Write LRA 0xC0 Write LRA LRD Configuration ProgramReadConfigurationRegister 2 Write RCD 0x60 Write RCD 0x03 NOTES: 1.Firstcommandcycleaddressshouldbethesameastheoperation’stargetaddress. PnA=Addresswithinthepartition. PBA=Partitionbaseaddress. IA=Identificationcodeaddressoffset. QA=CFIQueryaddressoffset. BA=Addresswithintheblock. WA=Wordaddressofmemorylocationtobewritten. PRA=ProtectionRegisteraddress. LRA=LockRegisteraddress. X=Anyvalidaddresswithinthedevice. 2.ID=Identifierdata. QD=QuerydataonD[15:0]. SRD=StatusRegisterdata. WD=Worddata. N=Wordcountofdatatobeloadedintothewritebuffer. PD=ProtectionRegisterdata. PD=ProtectionRegisterdata. LRD=LockRegisterdata. RCD=ReadConfigurationRegisterdataonA[15:0].A[MAX:16]canselectanypartition. 3.ThesecondcycleoftheBufferedProgramCommandisthewordcountofthedatatobeloadedintothewritebuffer.Thisis followedbyupto32wordsofdata.Thentheconfirmcommand(0xD0)isissued,triggeringthearrayprogrammingoperation. 4.Theconfirmcommand(0xD0)isfollowedbythebufferdata.

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3.3 Command Definitions

ValiddevicecommandcodesanddescriptionsareshowninTable6. Table6.CommandCodesandDefinitions(Sheet1of2) Mode Code Device Mode Description Read 0xFF ReadArray Places theaddressedpartitioninReadArraymode.ArraydataisoutputonD[15:0]. 0x70 ReadStatus Register PlacestheaddressedpartitioninReadStatusRegistermode.Thepartitionentersthismode afteraprogramorerasecommandisissued.StatusRegisterdataisoutputonD[7:0]. 0x90 ReadDevice IDor Configuration Register PlacestheaddressedpartitioninReadDeviceIdentifiermode.Subsequentreadsfrom addresseswithinthepartitionoutputsmanufacturer/devicecodes,ConfigurationRegisterdata, BlockLockstatus,orProtectionRegisterdataonD[15:0]. 0x98 ReadQuery PlacestheaddressedpartitioninReadQuerymode.Subsequentreadsfromthepartition addressesoutputCommonFlashInterfaceinformationonD[7:0]. 0x50 ClearStatus Register TheWSMcanonlysetStatusRegistererrorbits.TheClearStatusRegistercommandisused tocleartheSRerrorbits. Write 0x40 WordProgram Setup Firstcycleofa2-cycleprogrammingcommand;preparestheCUIforawriteoperation.Onthe nextwritecycle,theaddressanddataarelatchedandtheWSMexecutestheprogramming algorithmattheaddressedlocation.Duringprogramoperations,thepartitionrespondsonlyto ReadStatusRegisterandProgramSuspendcommands.CE#orOE#mustbetoggledto updatetheStatusRegisterinasynchronousread.CE#orADV#mustbetoggledtoupdatethe StatusRegisterDataforsynchronousNon-arrayread.TheReadArraycommandmustbe issuedtoreadarraydataafterprogramminghasfinished. 0x10 AlternateWord Program Setup EquivalenttotheWordProgramSetupcommand,0x40. 0xE8 Buffered Program Thiscommandloadsavariablenumberofbytesuptothebuffersizeof32wordsontothe programbuffer. 0xD0 Buffered Program Confirm TheconfirmcommandisIssuedafterthedatastreamingforwritingintothebufferisdone.This instructstheWSMtoperformtheBufferedProgramalgorithm,writingthedatafromthebuffer totheflashmemoryarray. 0x80 Buffered Enhanced Factory Programming Setup Firstcycleofa2-cyclecommand;initiatesBufferedEnhancedFactoryProgrammode (BufferedEFP).TheCUIthenwaitsfortheBufferedEFPConfirmcommand,0xD0,that initiatestheBufferedEFPalgorithm.AllothercommandsareignoredwhenBufferedEFPmode begins. 0xD0 BufferedEFP Confirm IfthepreviouscommandwasBufferedEFPSetup(0x80),theCUIlatchestheaddressand data,andpreparesthedeviceforBufferedEFPmode. Erase 0x20 BlockErase Setup Firstcycleofa2-cyclecommand;preparestheCUIforablock-eraseoperation.TheWSM performstheerasealgorithmontheblockaddressedbytheEraseConfirmcommand.Ifthe nextcommandisnottheEraseConfirm(0xD0)command,theCUIsetsStatusRegisterbits SR[4]andSR[5],andplacestheaddressedpartitioninreadstatusregistermode. 0xD0 BlockErase Confirm IfthefirstcommandwasBlockEraseSetup(0x20),theCUIlatchestheaddressanddata,and theWSMerasestheaddressedblock.Duringblock-eraseoperations,thepartitionresponds onlytoReadStatusRegisterandEraseSuspendcommands.CE#orOE#mustbetoggledto updatetheStatusRegisterinasynchronousread.CE#orADV#mustbetoggledtoupdatethe StatusRegisterDataforsynchronousNon-arrayread. Suspend 0xB0 Programor Erase Suspend Thiscommandissuedtoanydeviceaddressinitiatesasuspendofthecurrently-executing programorblockeraseoperation.TheStatusRegisterindicatessuccessfulsuspendoperation bysettingeitherSR2orSR6,alongwithSR[7] (ready).TheWriteStateMachineremainsinthesuspendmoderegardlessofcontrolsignal states(exceptforRST#asserted). 0xD0 Suspend Resume Thiscommandissuedtoanydeviceaddressresumesthesuspendedprogramorblock-erase operation.

28F640L30,28F128L30,28F256L30 Datasheet 21 Block Locking/ Unlocking 0x60 LockBlock Setup Firstcycleofa2-cyclecommand;preparestheCUIforblocklockconfigurationchanges.Ifthe nextcommandisnotBlockLock(0x01),BlockUnlock(0xD0),orBlockLock-Down(0x2F),the CUIsetsStatusRegisterbitsSR[4]andSR[5],indicatingacommandsequenceerror. 0x01 LockBlock If thepreviouscommandwasBlockLockSetup(0x60),theaddressedblockislocked. 0xD0 UnlockBlock IfthepreviouscommandwasBlockLockSetup(0x60),theaddressedblockisunlocked.Ifthe addressedblockisinalock-downstate,theoperationhasnoeffect. 0x2F Lock-Down Block IfthepreviouscommandwasBlockLockSetup(0x60),theaddressedblockislockeddown. Protection 0xC0 Program Protection Register Setup Firstcycleofa2-cyclecommand;preparesthedeviceforaProtectionRegisterorLock Registerprogramoperation.Thesecondcyclelatchestheregisteraddressanddata,andstarts theprogrammingalgorithm Configu- ration 0x60 Read Configuration Register Setup Firstcycleofa2-cyclecommand;preparestheCUIfordevicereadconfiguration.IftheSet ReadConfigurationRegistercommand(0x03)isnotthenextcommand,theCUIsetsStatus RegisterbitsSR[4]andSR[5],indicatingacommandsequenceerror. 0x03 Read Configuration Register IfthepreviouscommandwasReadConfigurationRegisterSetup(0x60),theCUIlatchesthe addressandwritesA[15:0]totheReadConfigurationRegister.FollowingaConfigureRead ConfigurationRegistercommand,subsequentreadoperationsaccessarraydata. Table6.CommandCodesandDefinitions(Sheet2of2) Mode Code Device Mode Description

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4.0 Read Operations

Thedevicesupportstworeadmodes:asynchronouspagemodeandsynchronousburstmode. Asynchronouspagemodeisthedefaultreadmodeafterdevicepower-uporareset.TheRead ConfigurationRegistermustbeconfiguredtoenablesynchronousburstreadsoftheflashmemory array(seeSection4.3,“ReadConfigurationRegister(RCR)”onpage23). Eachpartitionofthedevicecanbeinanyoffourreadstates:ReadArray,ReadIdentifier,Read StatusorReadQuery.Uponpower-up,orafterareset,allpartitionsofthedevicedefaulttoRead Array.Tochangeapartition’sreadstate,theappropriatereadcommandmustbewrittentothe device(seeSection3.2,“DeviceCommands”onpage18).SeeSection9.0,“SpecialReadStates” onpage47fordetailsregardingReadStatus,ReadID,andCFIQuerymodes. Thefollowingsectionsdescriberead-modeoperationsindetail.

4.1 Asynchronous Page-ModeRead

Followingadevicepower-uporreset,asynchronouspagemodeisthedefaultreadmodeandall partitionsaresettoReadArray.However,toperformarrayreadsafteranyotherdeviceoperation (e.g.writeoperation),theReadArraycommandmustbeissuedinordertoreadfromtheflash memoryarray. Note: Asynchronouspage-modereadscanonlybeperformedwhenReadConfigurationRegisterbit RCR[15]isset(seeSection4.3,“ReadConfigurationRegister(RCR)”onpage23). Toperformanasynchronouspage-moderead,anaddressisdrivenontoA[MAX:0],andCE#and ADV#areasserted.WE#andRST#mustalreadyhavebeendeasserted.WAITisde-asserted duringasynchronouspagemode.ADV#canbedrivenhightolatchtheaddress,oritmustbeheld lowthroughoutthereadcycle.CLKisnotusedforasynchronouspage-modereads,andisignored. Ifonlyasynchronousreadsaretobeperformed,CLKshouldbetiedtoavalidVIHlevel,WAIT signalcanbefloatedandADV#mustbetiedtoground.ArraydataisdrivenontoD[15:0]afteran initialaccesstimetAVQVdelay.(seeSection12.0,“ACCharacteristics”onpage55). Inasynchronouspagemode,fourdatawordsare“sensed”simultaneouslyfromtheflashmemory arrayandloadedintoaninternalpagebuffer.Thebufferwordcorrespondingtotheinitialaddress onA[MAX:0]isdrivenontoD[15:0]aftertheinitialaccessdelay.AddressbitsA[MAX:2]select the4-wordpage.AddressbitsA[1:0]determinewhichwordofthe4-wordpageisoutputfromthe databufferatanygiventime.

4.2 Synchronous Burst-ModeRead

ReadConfigurationregisterbitsCR[15:0]mustbesetbeforesynchronousburstoperationcanbe performed.Synchronousburstmodecanbeperformedforbotharrayandnon-arrayreadssuchas ReadID,ReadStatusorReadQuery.(SeeSection4.3,“ReadConfigurationRegister(RCR)”on page23fordetails).Synchronousburstmodeoutputs4-,8-,16-,orcontinuous-words.Toperform asynchronousburst-read,aninitialaddressisdrivenontoA[MAX:0],andCE#andADV#are asserted.WE#andRST#mustalreadyhavebeendeasserted.ADV#isasserted,andthen deassertedtolatchtheaddress.Alternately,ADV#canremainassertedthroughouttheburstaccess, inwhichcasetheaddressislatchedonthenextvalidCLKedgewhileADV#isasserted.

28F640L30,28F128L30,28F256L30 Datasheet 23 Duringsynchronousarrayandnon-arrayreadmodes,thefirstwordisoutputfromthedatabuffer onthenextvalidCLKedgeaftertheinitialaccesslatencydelay(seeSection4.3.2,“Latency Count”onpage24).SubsequentdataisoutputonvalidCLKedgesfollowingaminimumdelay. However,forasynchronousnon-arrayread,thesamewordofdatawillbeoutputonsuccessive clockedgesuntiltheburstlengthrequirementsaresatisfied. Duringsynchronousreadoperations,WAITisdrivenwithrespecttoOE#assertion.WAIT indicatesinvaliddatawhenasserted,andvaliddatawhende-assertedwithrespecttoavalidclock edge.SeeFigure16throughFigure18foradditionaldetails.

4.2.1 Burst Suspend

TheBurstSuspendfeatureofthedevicecanreduceoreliminatetheinitialaccesslatencyincurred whensystemsoftwareneedstosuspendaburstsequencethatisinprogressinordertoretrievedata fromanotherdeviceonthesamesystembus.Thesystemprocessorcanresumetheburstsequence later.Burstsuspendprovidesmaximumbenefitinnon-cachesystems. Burstaccessescanbesuspendedduringtheinitialaccesslatency(beforedataisreceived)orafter thedevicehasoutputdata.Whenaburstaccessissuspended,internalarraysensingcontinuesand anypreviouslylatchedinternaldataisretained.Aburstsequencecanbesuspendedandresumed withoutlimitaslongasdeviceoperationconditionsaremet. BurstSuspendoccurswhenCE#isasserted,thecurrentaddresshasbeenlatched(eitherADV# risingedgeorvalidCLKedge),CLKishalted,andOE#isdeasserted.CLKcanbehaltedwhenit isatVIHorVIL.WAITisinHigh-ZduringOE#de-assertion. Toresumetheburstaccess,OE#isreasserted,andCLKisrestarted.SubsequentCLKedges resumetheburstsequence. Withinthedevice,CE#andOE#gateWAIT.Therefore,duringBurstSuspendWAITisplacedin high-impedancestatewhenOE#isde-assertedandresumedactivewhenOE#isre-asserted.See Figure19,“BurstSuspendTiming”onpage59.

4.3 Read ConfigurationRegister(RCR)

TheRCRisusedtoselectthereadmode(synchronousorasynchronous),anditdefinesthe synchronousburstcharacteristicsofthedevice.TomodifyRCRsettings,usetheConfigureRead ConfigurationRegistercommand(seeSection3.2,“DeviceCommands”onpage18). RCRcontentscanbeexaminedusingtheReadDeviceIdentifiercommand,andthenreadingfrom <partitionbaseaddress>+0x05(seeSection9.2,“ReadDeviceIdentifier”onpage48). TheRCRisshowninTable7.ThefollowingsectionsdescribeeachRCRbit. Table7.ReadConfigurationRegisterDescription(Sheet1of2) ReadConfigurationRegister(RCR) Read Mode RES LatencyCount WAIT Polarity Data Hold WAIT Delay Burst Seq CLK Edge RES RES Burst Wrap BurstLength RM R LC[2:0] WP DH WD BS CE R R BW BL[2:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name Description

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4.3.1 Read Mode

TheReadMode(RM)bitselectssynchronousburst-modeorasynchronouspage-modeoperation forthedevice.WhentheRMbitisset,asynchronouspagemodeisselected(default).WhenRMis cleared,synchronousburstmodeisselected.

4.3.2 Latency Count

TheLatencyCountbits,LC[2:0],tellthedevicehowmanyclockcyclesmustelapsefromthe risingedgeofADV#(orfromthefirstvalidclockedgeafterADV#isasserted)untilthefirstdata wordistobedrivenontoD[15:0].Theinputclockfrequencyisusedtodeterminethisvalue. Figure4showsthedataoutputlatencyforthedifferentsettingsofLC[2:0]. SynchronousburstwithaLatencyCountsettingofCode4willresultinzeroWAITstate;however, aLatencyCountsettingofCode5willcause1WAITstate(Code6willcause2WAITstates,and Code7willcause3WAITstates)aftereveryfourwords,regardlessofwhethera16-word boundaryiscrossed.IfCR.9bitisset(dataholdoftwoclocks)thisWAITcondition willnotoccurbecauseenoughclockselapseduringeachburstcycletoeliminatesubsequentWAIT states.

15 ReadMode(RM) 0=Synchronousburst-moderead

1=Asynchronouspage-moderead(default)

14 Reserved (R) Reserved bitsshouldbecleared(0)

13:11 LatencyCount(LC[2:0]) 010 =Code2 011=Code3 100=Code4 101=Code5 110=Code6 111=Code7(default) (Otherbitsettingsarereserved)

10 Wait Polarity(WP) 0 =WAITsignalisactivelow

1=WAITsignalisactivehigh(default)

9 Data Hold(DH) 0 =Dataheldfora1-clockdatacycle

1=Dataheldfora2-clockdatacycle(default) 8W a i t Delay(WD) 0 =WAITde-assertedwithvaliddata 1=WAITde-assertedonedatacyclebeforevaliddata(default) 7B u r s t Sequence(BS) 0 =Reserved 1=Linear(default)

6 Clock Edge(CE) 0 =Fallingedge

1=Risingedge(default) 5:4 Reserved (R) Reserved bitsshouldbecleared(0) 3B u r s t Wrap(BW) 0 =Wrap;BurstaccesseswrapwithinburstlengthsetbyBL[2:0] 1=NoWrap;Burstaccessesdonotwrapwithinburstlength(default) 2:0 Burst Length(BL[2:0]) 001 =4-wordburst 010=8-wordburst 011=16-wordburst 111=Continuous-wordburst(default) (Otherbitsettingsarereserved) NOTE: LatencyCode2,DataHoldfora2-clockdatacycle(DH=1)Waitmustbede-assertedwithvaliddata(WD= 0).LatencyCode2,DataHoldfora2-cockdatacycle(DH=1)Waitde-assertedonedatacyclebeforevalid data(WD=1)combinationisnotsupported. Table7.ReadConfigurationRegisterDescription(Sheet2of2)

28F640L30,28F128L30,28F256L30 Datasheet 25 RefertoTable8,“LCandFrequencySupportforBin1tAVQV/tCHQV(85ns/17ns)”onpage25 andTable9,“LCandFrequencySupportforBin2tAVQV/tCHQV(110ns/20ns)”onpage26for LatencyCodeSettings. Figure4.First-AccessLatencyCount Code1 (Reserved Code6 Code5 Code4 Code3 Code2 Code0(Reserved) Code7 Valid Address Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Address[A] ADV#[V] DQ15-0[D/Q] CLK[C] DQ15-0[D/Q] DQ15-0[D/Q] DQ15-0[D/Q] DQ15-0[D/Q] DQ15-0[D/Q] DQ15-0[D/Q] DQ15-0[D/Q] Table8.LCandFrequencySupportforBin1tAVQV/tCHQV(85ns/17ns) LatencyCountSettings Frequency Support(MHz) 2 ≤ 27 3 ≤ 40 4,5,6,or7 ≤ 52

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SeeFigure5,“ExampleLatencyCountSettingusingCode3.

4.3.3 WAIT Polarity

TheWAITPolaritybit(WP),RCR[10]determinestheassertedlevel(VOHorVOL)ofWAIT. WhenWPisset,WAITisasserted-high(default).WhenWPiscleared,WAITisasserted-low. WAITchangesstateonvalidclockedgesduringactivebuscycles(CE#asserted,OE#asserted, RST#deasserted).

4.3.3.1 WAIT SignalFunction

TheWAITsignalindicatesdatavalidwhenthedeviceisoperatinginsynchronousmode (CR[15]=0).TheWAITsignalisonly“de-asserted”whendataisvalidonthebus. Whenthedeviceisoperatinginsynchronousnon-arrayreadmode,suchasreadstatus,readID,or readquery.TheWAITsignalisalso“de-asserted”whendataisvalidonthebus. Whenthedeviceisoperatinginasynchronouspagemode,asynchronoussinglewordreadmode, andallwriteoperations,WAITissettoade-assertedstateasdeterminedbyCR[10].SeeFigure14, “AsynchronousSingle-WordRead(ADV#Latch)”onpage57,andFigure15,“Asynchronous Page-ModeReadTiming”onpage57. Table9.LCandFrequencySupportforBin2tAVQV/tCHQV(110ns/20ns) LatencyCountSettings Frequency Support(MHz) 2 ≤ 22 3 ≤ 33 4,5,6,or7 ≤40 Figure5.ExampleLatencyCountSettingusingCode3 CLK CE# ADV# A[MAX:0] D[15:0] tData Code3 Address Data 01 2 34 R103 High-Z

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4.3.4 Data Hold

Forburstreadoperations,theDataHold(DH)bitdetermineswhetherthedataoutputremainsvalid onD[15:0]foroneortwoclockcycles.Thisperiodoftimeiscalledthe“datacycle”.WhenDHis set,outputdataisheldfortwoclocks(default).WhenDHiscleared,outputdataisheldforone clock(seeFigure6).Theprocessor’sdatasetuptimeandtheflashmemory’sclock-to-dataoutput delayshouldbeconsideredwhendeterminingwhethertoholdoutputdataforoneortwoclocks. AmethodfordeterminingtheDataHoldconfigurationisshownbelow: Tosetthedeviceatoneclockdataholdforsubsequentreads,thefollowingconditionmustbe satisfied: tCHQV(ns)+tDATA(ns)≤ OneCLKPeriod(ns) tDATA=DatasetuptoClock(definedbyCPU) Forexample,withaclockfrequencyof40MHz,theclockperiodis25ns.Assuming tCHQV=20nsandtDATA=4ns.Applyingthesevaluestotheformulaabove: 20ns+4ns≤ 25ns Theequationissatisfiedanddatawillbeavailableateveryclockperiodwithdataholdsettingat oneclock. IftCHQV(ns)+tDATA(ns)> OneCLKPeriod(ns),dataholdsettingof2clockperiodsmustbe used. Table10.WAITSummaryTable CONDITION WAIT CE#=VIH CE#=VIL High-Z Active OE#=VIH OE#=VIL High-Z Active SynchronousArrayReads Active SynchronousNon-ArrayReads Active AllAsynchronousReadsandallWrites De-asserted NOTE: Active:WAITisasserteduntildatabecomesvalid,thende-asserts Figure6.DataHoldTiming Valid Output Valid Output Valid Output Valid Output Valid Output CLK[C] D[15:0][Q] D[15:0][Q]2CLK DataHold 1CLK DataHold

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4.3.5 WAIT Delay

TheWAITDelay(WD)bitcontrolstheWAITassertion-delaybehaviorduringsynchronousburst reads.WAITcanbeassertedeitherduringoronedatacyclebeforevaliddataisoutputon DQ[15:0].WhenWDisset,WAITisde-assertedonedatacyclebeforevaliddata(default).When WDiscleared,WAITisde-assertedduringvaliddata.

4.3.6 Burst Sequence

TheBurstSequence(BS)bitselectslinear-burstsequence(default).Onlylinear-burstsequenceis supported.Table11showsthesynchronousburstsequenceforallburstlengths,aswellasthe effectoftheBurstWrap(BW)setting.

4.3.7 Clock Edge

TheClockEdge(CE)bitselectseitherarising(default)orfallingclockedgeforCLK.Thisclock edgeisusedatthestartofaburstcycle,tooutputsynchronousdata,andtoassert/deassertWAIT.

4.3.8 Burst Wrap

TheBurstWrap(BW)bitdetermineswhether4-word,8-word,or16-wordburstlengthaccesses wrapwithintheselectedword-lengthboundariesorcrossword-lengthboundaries.WhenBWis set,burstwrappingdoesnotoccur(default).WhenBWiscleared,burstwrappingoccurs. WhenperformingsynchronousburstreadswithBWset(nowrap),anoutputdelaymayoccur whentheburstsequencecrossesitsfirstdevice-row(16-word)boundary.Iftheburstsequence’s startaddressis4-wordaligned,thennodelayoccurs.Ifthestartaddressisattheendofa4-word Table11.BurstSequenceWordOrdering Start Addr. (DEC) BurstWrap (RCR[3]) BurstAddressingSequence(DEC) 4-WordBurst (BL[2:0]=0b001) 8-WordBurst (BL[2:0]=0b010) 16-WordBurst (BL[2:0]=0b011) ContinuousBurst (BL[2:0]=0b111)

28F640L30,28F128L30,28F256L30 Datasheet 29 boundary,theworstcaseoutputdelayisoneclockcyclelessthanthefirstaccessLatencyCount. Thisdelaycantakeplaceonlyonce,anddoesn’toccuriftheburstsequencedoesnotcrossa device-rowboundary.WAITinformsthesystemofthisdelaywhenitoccurs.

4.3.9 Burst Length

TheBurstLengthbit(BL[2:0])selectsthelinearburstlengthforallsynchronousburstreadsofthe flashmemoryarray.Theburstlengthsare4-word,8-word,16-word,andcontinuousword. Continuous-burstaccessesarelinearonly,anddonotwrapwithinanywordlengthboundaries(see Table11,“BurstSequenceWordOrdering”onpage28).Whenaburstcyclebegins,thedevice outputssynchronousburstdatauntilitreachestheendofthe“burstable”addressspace.

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5.0 Programming Operations

Thedevicesupportsthreeprogrammingmethods:WordProgramming(40h/10h),Buffered Programming(E8h,D0h),andBufferedEnhancedFactoryProgramming(BufferedEFP)(80h, D0h).SeeSection3.0,“DeviceOperations”onpage17fordetailsonthevariousprogramming commandsissuedtothedevice. Successfulprogrammingrequirestheaddressedblocktobeunlocked.Iftheblockislockeddown, WP#mustbedeassertedandtheblockmustbeunlockedbeforeattemptingtoprogramtheblock. Attemptingtoprogramalockedblockcausesaprogramerror(SR[4]andSR[1]set)and terminationoftheoperation.SeeSection7.0,“SecurityModes”onpage38fordetailsonlocking andunlockingblocks. Thefollowingsectionsdescribedeviceprogrammingindetail.

5.1 Word Programming

WordprogrammingoperationsareinitiatedbywritingtheWordProgramSetupcommandtothe device(seeSection3.0,“DeviceOperations”onpage17).Thisisfollowedbyasecondwritetothe devicewiththeaddressanddatatobeprogrammed.Thepartitionaccessedduringbothwrite cyclesoutputsStatusRegisterdatawhenread.Thepartitionaccessedduringthesecondcycle(the datacycle)oftheprogramcommandsequenceisthelocationwherethedataiswritten.SeeFigure 30,“WordProgramFlowchart”onpage74. Programmingcanoccurinonlyonepartitionatatime;allotherpartitionsmustbeinareadstateor inerasesuspend.VPPmustbeaboveVPPLK,andwithinthespecifiedVPPLmin/maxvalues (nominally1.8V). Duringprogramming,theWriteStateMachine(WSM)executesasequenceofinternally-timed eventsthatprogramthedesireddatabitsattheaddressedlocation,andverifiesthatthebitsare sufficientlyprogrammed.Programmingtheflashmemoryarraychanges“ones”to“zeros.” Memoryarraybitsthatarezeroscanbechangedtoonesonlybyerasingtheblock(seeSection6.0, “EraseOperations”onpage36). TheStatusRegistercanbeexaminedforprogrammingprogressanderrorsbyreadinganyaddress withinthepartitionthatisbeingprogrammed.ThepartitionremainsintheReadStatusRegister stateuntilanothercommandiswrittentothatpartition.IssuingtheReadStatusRegistercommand toanotherpartitionaddresssetsthatpartitiontotheReadStatusRegisterstate,allowing programmingprogresstobemonitoredatthatpartition’saddress. StatusRegisterbitSR[7]indicatestheprogrammingstatuswhilethesequenceexecutes. CommandsthatcanbeissuedtotheprogrammingpartitionduringprogrammingareProgram Suspend,ReadStatusRegister,ReadDeviceIdentifier,CFIQuery,andReadArray(thisreturns unknowndata). Whenprogramminghasfinished,StatusRegisterbitSR4indicatesaprogramming failure.IfSR[3]isset,theWSMcouldnotperformthewordprogrammingoperationbecauseVPP wasoutsideofitsacceptablelimits.IfSR[1]isset,thewordprogrammingoperationattemptedto programalockedblock,causingtheoperationtoabort. Beforeissuinganewcommand,theStatusRegistercontentsshouldbeexaminedandthencleared usingtheClearStatusRegistercommand.Anyvalidcommandcanfollow,whenword programminghascompleted.

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5.1.1 Factory WordProgramming

Factorywordprogrammingissimilartowordprogramminginthatitusesthesamecommandsand programmingalgorithms.However,factorywordprogrammingenhancestheprogramming performancewithVPP=VPPH.ThiscanenablefasterprogrammingtimesduringOEM manufacturingprocesses.Factorywordprogrammingisnotintendedforextendeduse.SeeSection 11.2,“OperatingConditions”onpage52forlimitationswhenVPP=VPPH. Note: WhenVPP=VPPL,thedevicedrawsprogrammingcurrentfromtheVCCsupply.IfVPPisdriven byalogicsignal,VPPLmustremainaboveVPPLMINtoprogramthedevice.WhenVPP=VPPH, thedevicedrawsprogrammingcurrentfromtheVPPsupply.Figure7,“ExampleVPPSupply Connections”onpage35showsexamplesofdevicepowersupplyconfigurations.

5.2 Buffered Programming

Thedevicefeaturesa32-wordbuffertoenableoptimumprogrammingperformance.ForBuffered Programming,dataisfirstwrittentoanon-chipwritebuffer.Thenthebufferdataisprogrammed intotheflashmemoryarrayinbuffer-sizeincrements.Thiscanimprovesystemprogramming performancesignificantlyovernon-bufferedprogramming. WhentheBufferedProgrammingSetupcommandisissued(seeSection3.2,“DeviceCommands” onpage18),StatusRegisterinformationisupdatedandreflectstheavailabilityofthebuffer.SR[7] indicatesbufferavailability:ifset,thebufferisavailable;ifcleared,thebufferisnotavailable.To retry,issuetheBufferedProgrammingSetupcommandagain,andre-checkSR[7].WhenSR[7]is set,thebufferisreadyforloading.(seeFigure32,“BufferedProgramFlowchart”onpage76). Onthenextwrite,awordcountiswrittentothedeviceatthebufferaddress.Thistellsthedevice howmanydatawordswillbewrittentothebuffer,uptothemaximumsizeofthebuffer. Onthenextwrite,adevicestartaddressisgivenalongwiththefirstdatatobewrittentotheflash memoryarray.Subsequentwritesprovideadditionaldeviceaddressesanddata.Alldataaddresses mustliewithinthestartaddressplusthewordcount.Optimumprogrammingperformanceand lowerpowerusageareobtainedbyaligningthestartingaddressatthebeginningofa32-word boundary(A[4:0]=0x00).Amisalignedstartingaddressdoublesthetotalprogramtime. Afterthelastdataiswrittentothebuffer,theBufferedProgrammingConfirmcommandmustbe issuedtotheoriginalblockaddress.TheWSMbeginstoprogrambuffercontentstotheflash memoryarray.IfacommandotherthantheBufferedProgrammingConfirmcommandiswrittento thedevice,acommandsequenceerroroccursandStatusRegisterbitsSR[7,5,4]areset.Ifanerror occurswhilewritingtothearray,thedevicestopsprogramming,andStatusRegisterbitsSR[7,4] areset,indicatingaprogrammingfailure. Readingfromanotherpartitionisallowedwhiledataisbeingprogrammedintothearrayfromthe writebuffer(seeFigure38,“ReadWhileBufferedProgrammingFlowchart”onpage82). WhenBufferedProgramminghascompleted,anadditionalbufferwritescanbeinitiatedbyissuing anotherBufferedProgrammingSetupcommandandrepeatingthebufferedprogramsequence. BufferedprogrammingmaybeperformedwithVPP=VPPLorVPPH(seeSection11.2,“Operating Conditions”onpage52forlimitationswhenoperatingthedevicewithVPP=VPPH). WhenStatusRegisterbitsSR[5,4]areset,thedevicedoesnotacceptBufferedProgram commands.Ifanattemptismadetoprogrampastanerase-blockboundaryusingtheBuffered Programcommand,thedeviceabortstheoperation.Thisgeneratesacommandsequenceerror,and StatusRegisterbitsSR[5,4]areset.

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IfBufferedprogrammingisattemptedwhileVPPisbelowVPPLK,StatusRegisterbitsSR[4,3]are set.IfanyerrorsaredetectedthathavesetStatusRegisterbits,theStatusRegistershouldbe clearedusingtheClearStatusRegistercommand.

5.3 Buffered EnhancedFactoryProgramming

BufferedEnhancedFactoryPrograming(BufferedEFP)speedsupMulti-LevelCell(MLC)flash programmingfortoday'sbeat-rate-sensitivemanufacturingenvironments.Theenhanced programmingalgorithmusedinBufferedEFPeliminatestraditionalprogrammingelementsthat driveupoverheadindeviceprogrammersystems. BufferedEFPconsistsofthreephases:Setup,Program/Verify,andExit(seeFigure33,“Buffered EFPFlowchart”onpage77).ItusesawritebuffertospreadMLCprogramperformanceacross32 datawords.Verificationoccursinthesamephaseasprogrammingtoaccuratelyprogramtheflash memorycelltothecorrectbitstate. Asingletwo-cyclecommandsequenceprogramstheentireblockofdata.Thisenhancement eliminatesthreewritecyclesperbuffer:twocommandsandthewordcountforeachsetof32data words.Hostprogrammerbuscyclesfillthedevice’swritebufferfollowedbyastatuscheck.SR[0] indicateswhendatafromthebufferhasbeenprogrammedintosequentialflashmemoryarray locations. Followingthebuffer-to-flasharrayprogrammingsequence,theWriteStateMachine(WSM) incrementsinternaladdressingtoautomaticallyselectthenext32-wordarrayboundary.This aspectofBufferedEFPsaveshostprogrammingequipmenttheaddress-bussetupoverhead. Withadequatecontinuitytesting,programmingequipmentcanrelyontheWSM’sinternal verificationtoensurethatthedevicehasprogrammedproperly.Thiseliminatestheexternalpost- programverificationanditsassociatedoverhead.

5.3.1 Buffered EFPRequirementsandConsiderations

BufferedEFPrequirements:

• Ambienttemperature:TA=25°C,±5°C
• VCCwithinspecifiedoperatingrange.
• VPPdriventoVPPH.
• TargetblockunlockedbeforeissuingtheBufferedEFPSetupandConfirmcommands.
• Thefirst-wordaddress(WA0)fortheblocktobeprogrammedmustbeheldconstantfromthe setupphasethroughalldatastreamingintothetargetblock,untiltransitiontotheexitphaseis desired.
• WA0mustalignwiththestartofanarraybufferboundary1. BufferedEFPconsiderations:
• Foroptimumperformance,cyclingmustbelimitedbelow100erasecyclesperblock2.
• BufferedEFPprogramsoneblockatatime;allbufferdatamustfallwithinasingleblock3.
• BufferedEFPcannotbesuspended.
• Programmingtotheflashmemoryarraycanoccuronlywhenthebufferisfull4.

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• ReadoperationwhileperformingBufferedEFPisnotsupported. NOTES: 1.WordbufferboundariesinthearrayaredeterminedbyA4:0.Thealignmentstartpoint isA[4:0]=0x00. 2.Somedegradationinperformancemayoccurifthislimitisexceeded,buttheinternalalgorithmcontinuesto workproperly. 3.Iftheinternaladdresscounterincrementsbeyondtheblock'smaximumaddress,addressingwrapsaroundto thebeginningoftheblock. 4.Ifthenumberofwordsislessthan32,remaininglocationsmustbefilledwith0xFFFF.

5.3.2 Buffered EFPSetupPhase

AfterreceivingtheBufferedEFPSetupandConfirmcommandsequence,StatusRegisterbitSR[7] (Ready)iscleared,indicatingthattheWSMisbusywithBufferedEFPalgorithmstartup.Adelay beforecheckingSR[7]isrequiredtoallowtheWSMenoughtimetoperformallofitssetupsand checks(Block-Lockstatus,VPPlevel,etc.).Ifanerrorisdetected,SR[4]issetandBufferedEFP operationterminates.Iftheblockwasfoundtobelocked,SR[1]isalsoset.SR[3]issetiftheerror occurredduetoanincorrectVPPlevel. Note: ReadingfromthedeviceaftertheBufferedEFPSetupandConfirmcommandsequenceoutputs StatusRegisterdata.DonotissuetheReadStatusRegistercommand;itwillbeinterpretedasdata tobeloadedintothebuffer.

5.3.3 Buffered EFPProgram/VerifyPhase

AftertheBufferedEFPSetupPhasehascompleted,thehostprogrammingsystemmustcheck SR[7,0]todeterminetheavailabilityofthewritebufferfordatastreaming.SR[7]clearedindicates thedeviceisbusyandtheBufferedEFPprogram/verifyphaseisactivated.SR[0]indicatesthe writebufferisavailable. Twobasicsequencesrepeatinthisphase:loadingofthewritebuffer,followedbybufferdata programmingtothearray.ForBufferedEFP,thecountvalueforbufferloadingisalwaysthe maximumbuffersizeof32words.Duringthebuffer-loadingsequence,dataisstoredtosequential bufferlocationsstartingataddress0x00.Programmingofthebuffercontentstotheflashmemory arraystartsassoonasthebufferisfull.Ifthenumberofwordsislessthan32,theremainingbuffer locationsmustbefilledwith0xFFFF. Caution: Thebuffermustbecompletelyfilledforprogrammingtooccur.Supplyinganaddressoutsideofthe currentblock'srangeduringabuffer-fillsequencecausesthealgorithmtoexitimmediately.Any datapreviouslyloadedintothebufferduringthefillcycleisnotprogrammedintothearray. Thestartingaddressfordataentrymustbebuffersizealigned,ifnottheBufferedEFPalgorithm willbeabortedandtheprogramfail(SR[4])flagwillbeset. Datawordsfromthewritebufferaredirectedtosequentialmemorylocationsintheflashmemory array;programmingcontinuesfromwherethepreviousbuffersequenceended.Thehost programmingsystemmustpollSR[0]todeterminewhenthebufferprogramsequencecompletes. SR[0]clearedindicatesthatallbufferdatahasbeentransferredtotheflasharray;SR[0]set indicatesthatthebufferisnotavailableyetforthenextfillcycle.Thehostsystemmaycheckfull statusforerrorsatanytime,butitisonlynecessaryonablockbasisafterBufferedEFPexit.After thebufferfillcycle,nowritecyclesshouldbeissuedtothedeviceuntilSR.0=0andthedeviceis readyforthenextbufferfill.

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Note: Anyspuriouswritesareignoredafterabufferfilloperationandwheninternalprogramis proceeding. ThehostprogrammingsystemcontinuestheBufferedEFPalgorithmbyprovidingthenextgroup ofdatawordstobewrittentothebuffer.Alternatively,itcanterminatethisphasebychangingthe blockaddresstooneoutsideofthecurrentblock’srange. TheProgram/Verifyphaseconcludeswhentheprogrammerwritestoadifferentblockaddress; datasuppliedmustbe0xFFFF.UponProgram/Verifyphasecompletion,thedeviceentersthe BufferedEFPExitphase.

5.3.4 Buffered EFPExitPhase

WhenSR[7]isset,thedevicehasreturnedtonormaloperatingconditions.Afullstatuscheck shouldbeperformedonthepartitionbeingprogrammedatthistimetoensuretheentireblock programmedsuccessfully.WhenexitingtheBufferedEFPalgorithmwithablockaddresschange, thereadmodeofboththeprogrammedandtheaddressedpartitionwillnotchange.AfterBuffered EFPexit,anyvalidcommandcanbeissuedtothedevice.

5.4 Program Suspend

IssuingtheProgramSuspendcommandwhileprogrammingsuspendstheprogrammingoperation. Thisallowsdatatobeaccessedfrommemorylocationsotherthantheonebeingprogrammed.The ProgramSuspendcommandcanbeissuedtoanydeviceaddress;thecorrespondingpartitionisnot affected.Aprogramoperationcanbesuspendedtoperformreadsonly.Additionally,aprogram operationthatisrunningduringanerasesuspendcanbesuspendedtoperformareadoperation (seeFigure31,“ProgramSuspend/ResumeFlowchart”onpage75). Whenaprogrammingoperationisexecuting,issuingtheProgramSuspendcommandrequeststhe WSMtosuspendtheprogrammingalgorithmatpredeterminedpoints.Thepartitionthatis suspendedcontinuestooutputStatusRegisterdataaftertheProgramSuspendcommandisissued. ProgrammingissuspendedwhenStatusRegisterbitsSR[7,2]areset.Suspendlatencyisspecified inSection12.3,“ProgramandEraseCharacteristics”onpage64. Toreaddatafromblockswithinthesuspendedpartition,theReadArraycommandmustbeissued tothatpartition.ReadArray,ReadStatusRegister,ReadDeviceIdentifier,CFIQuery,and ProgramResumearevalidcommandsduringaprogramsuspend. Aprogramoperationdoesnotneedtobesuspendedinordertoreaddatafromablockinanother partitionthatisnotprogramming.IftheotherpartitionisalreadyinaReadArray,ReadDevice Identifier,orCFIQuerystate,issuingavalidaddressreturnscorrespondingreaddata.Iftheother partitionisnotinareadmode,oneofthereadcommandsmustbeissuedtothepartitionbefore datacanberead. Duringaprogramsuspend,deassertingCE#placesthedeviceinstandby,reducingactivecurrent. VPPmustremainatitsprogramminglevel,andWP#mustremainunchangedwhileinprogram suspend.IfRST#isasserted,thedeviceisreset.

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5.5 Program Resume

TheResumecommandinstructsthedevicetocontinueprogramming,andautomaticallyclears StatusRegisterbitsSR[7,2].Thiscommandcanbewrittentoanypartition.Whenreadatthe partitionthat’sprogramming,thedeviceoutputsdatacorrespondingtothepartition’slaststate.If errorbitsareset,theStatusRegistershouldbeclearedbeforeissuingthenextinstruction.RST# mustremaindeasserted(seeFigure31,“ProgramSuspend/ResumeFlowchart”onpage75).

5.6 Program Protection

WhenVPP=VIL,absolutehardwarewriteprotectionisprovidedforalldeviceblocks.IfVPPis belowVPPLK,programmingoperationshaltandSR[3]issetindicatingaVPP-levelerror.Block lockregistersarenotaffectedbythevoltagelevelonVPP;theymaystillbeprogrammedandread, evenifVPPislessthanVPPLK. Figure7.ExampleVPPSupplyConnections FactoryWordProgrammingwithVPP=VPPH CompleteWrite/EraseProtectionwhenVPP<VPPLK LowVoltageandFactoryWordProgramming LowVoltageProgrammingOnly FullDeviceProtectionUnavailable LowVoltageProgrammingOnly LogicControlofDeviceProtection VCC VPP PROT# VCC VPP VCC VPP KΩ VCC VPP VCC VPP VCC VPP=VPPH VCC VCC

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6.0 Erase Operations

Flasherasingisperformedonablockbasis.Anentireblockiserasedeachtimeanerasecommand sequenceisissued,andonlyoneblockiserasedatatime.Whenablockiserased,allbitswithin thatblockreadaslogicalones.Thefollowingsectionsdescribeblockeraseoperationsindetail.

6.1 Block Erase

BlockeraseoperationsareinitiatedbywritingtheBlockEraseSetupcommandtotheaddressof theblocktobeerased(seeSection3.2,“DeviceCommands”onpage18).Next,theBlockErase Confirmcommandiswrittentotheaddressoftheblocktobeerased.Erasingcanoccurinonlyone partitionatatime;allotherpartitionsmustbeinareadstate.Ifthedeviceisplacedinstandby (CE#deasserted)duringaneraseoperation,thedevicecompletestheeraseoperationbefore enteringstandby.VPPmustbeaboveVPPLKandtheblockmustbeunlocked(seeFigure34,“Block EraseFlowchart”onpage78). Duringablockerase,theWriteStateMachine(WSM)executesasequenceofinternally-timed eventsthatconditions,erases,andverifiesallbitswithintheblock.Erasingtheflashmemoryarray changes“zeros”to“ones.”Memoryarraybitsthatareonescanbechangedtozerosonlyby programmingtheblock(seeSection5.0,“ProgrammingOperations”onpage30). TheStatusRegistercanbeexaminedforblockeraseprogressanderrorsbyreadinganyaddress withinthepartitionthatisbeingerased.ThepartitionremainsintheReadStatusRegisterstate untilanothercommandiswrittentothatpartition.IssuingtheReadStatusRegistercommandto anotherpartitionaddresssetsthatpartitiontotheReadStatusRegisterstate,allowingerase progresstobemonitoredatthatpartition’saddress.SR[0]indicateswhethertheaddressedpartition oranotherpartitioniserasing.Thepartition’sStatusRegisterbitSR[7]issetuponerase completion. StatusRegisterbitSR[7]indicatesblockerasestatuswhilethesequenceexecutes.Whentheerase operationhasfinished,StatusRegisterbitSR[5]indicatesanerasefailureifset.SR[3]setwould indicatethattheWSMcouldnotperformtheeraseoperationbecauseVPPwasoutsideofits acceptablelimits.SR[1]setindicatesthattheeraseoperationattemptedtoerasealockedblock, causingtheoperationtoabort. Beforeissuinganewcommand,theStatusRegistercontentsshouldbeexaminedandthencleared usingtheClearStatusRegistercommand.Anyvalidcommandcanfollowoncetheblockerase operationhascompleted.

6.2 Erase Suspend

IssuingtheEraseSuspendcommandwhileerasingsuspendstheblockeraseoperation.Thisallows datatobeaccessedfrommemorylocationsotherthantheonebeingerased.TheEraseSuspend commandcanbeissuedtoanydeviceaddress;thecorrespondingpartitionisnotaffected.Ablock eraseoperationcanbesuspendedtoperformawordorbufferprogramoperation,oraread operationwithinanyblockexcepttheblockthatiserasesuspended(seeFigure31,“Program Suspend/ResumeFlowchart”onpage75).

28F640L30,28F128L30,28F256L30 Datasheet 37 Whenablockeraseoperationisexecuting,issuingtheEraseSuspendcommandrequeststheWSM tosuspendtheerasealgorithmatpredeterminedpoints.Thepartitionthatissuspendedcontinuesto outputStatusRegisterdataaftertheEraseSuspendcommandisissued.Blockeraseissuspended whenStatusRegisterbitsSR[7,6]areset.SuspendlatencyisspecifiedinSection12.3,“Program andEraseCharacteristics”onpage64. Toreaddatafromblockswithinthesuspendedpartition(otherthananerase-suspendedblock),the ReadArraycommandmustbeissuedtothatpartitionfirst.DuringEraseSuspend,aProgram commandcanbeissuedtoanyblockotherthantheerase-suspendedblock.Blockerasecannot resumeuntilprogramoperationsinitiatedduringerasesuspendcomplete.ReadArray,ReadStatus Register,ReadDeviceIdentifier,CFIQuery,andEraseResumearevalidcommandsduringErase Suspend.Additionally,ClearStatusRegister,Program,ProgramSuspend,BlockLock,Block Unlock,andBlockLock-DownarevalidcommandsduringEraseSuspend. Toreaddatafromablockinapartitionthatisnoterasing,theeraseoperationdoesnotneedtobe suspended.IftheotherpartitionisalreadyinReadArray,ReadDeviceIdentifier,orCFIQuery, issuingavalidaddressreturnscorrespondingdata.Iftheotherpartitionisnotinareadstate,oneof thereadcommandsmustbeissuedtothepartitionbeforedatacanberead. Duringanerasesuspend,deassertingCE#placesthedeviceinstandby,reducingactivecurrent. VPPmustremainatavalidlevel,andWP#mustremainunchangedwhileinerasesuspend.If RST#isasserted,thedeviceisreset.

6.3 Erase Resume

TheEraseResumecommandinstructsthedevicetocontinueerasing,andautomaticallyclears statusregisterbitsSR[7,6].Thiscommandcanbewrittentoanypartition.Whenreadatthe partitionthat’serasing,thedeviceoutputsdatacorrespondingtothepartition’slaststate.Ifstatus registererrorbitsareset,theStatusRegistershouldbeclearedbeforeissuingthenextinstruction. RST#mustremaindeasserted(seeFigure31,“ProgramSuspend/ResumeFlowchart”onpage75).

6.4 Erase Protection

WhenVPP=VIL,absolutehardwareeraseprotectionisprovidedforalldeviceblocks.IfVPPis belowVPPLK,eraseoperationshaltandSR[3]issetindicatingaVPP-levelerror.

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7.0 Security Modes

Thedevicefeaturessecuritymodesusedtoprotecttheinformationstoredintheflashmemory array.Thefollowingsectionsdescribeeachsecuritymodeindetail.

7.1 Block Locking

Individualinstantblocklockingisusedtoprotectusercodeand/ordatawithintheflashmemory array.Allblockspowerupinalockedstatetoprotectarraydatafrombeingalteredduringpower transitions.Anyblockcanbelockedorunlockedwithnolatency.Lockedblockscannotbe programmedorerased;theycanonlyberead. Software-controlledsecurityisimplementedusingtheBlockLockandBlockUnlockcommands. Hardware-controlledsecuritycanbeimplementedusingtheBlockLock-Downcommandalong withassertingWP#.Also,VPPdatasecuritycanbeusedtoinhibitprogramanderaseoperations (seeSection5.6,“ProgramProtection”onpage35andSection6.4,“EraseProtection”onpage37).

7.1.1 Lock Block

Tolockablock,issuetheLockBlockSetupcommand.ThenextcommandmustbetheLockBlock commandissuedtothedesiredblock’saddress(seeSection3.2,“DeviceCommands”onpage18 andFigure36,“BlockLockOperationsFlowchart”onpage80).IftheSetReadConfiguration RegistercommandisissuedaftertheBlockLockSetupcommand,thedeviceconfigurestheRCR instead. BlocklockandunlockoperationsarenotaffectedbythevoltagelevelonVPP.Theblocklockbits maybemodifiedand/orreadevenifVPPisbelowVPPLK.

7.1.2 Unlock Block

TheUnlockBlockcommandisusedtounlockblocks(seeSection3.2,“DeviceCommands”on page18).Unlockedblockscanberead,programmed,anderased.Unlockedblocksreturntoa lockedstatewhenthedeviceisresetorpowereddown.Ifablockisinalock-downstate,WP# mustbedeassertedbeforeitcanbeunlocked(seeFigure8,“BlockLockingStateDiagram”on page39).

7.1.3 Lock-Down Block

Alockedorunlockedblockcanbelocked-downbywritingtheLock-DownBlockcommand sequence(seeSection3.2,“DeviceCommands”onpage18).Blocksinalock-downstatecannot beprogrammedorerased;theycanonlyberead.However,unlikelockedblocks,theirlockedstate cannotbechangedbysoftwarecommandsalone.Alocked-downblockcanonlybeunlockedby issuingtheUnlockBlockcommandwithWP#deasserted.Toreturnanunlockedblocktolocked- downstate,aLock-DowncommandmustbeissuedpriortochangingWP#toVIL.Locked-down blocksreverttothelockedstateuponresetorpowerupthedevice(seeFigure8,“BlockLocking StateDiagram”onpage39).

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7.1.4 Block LockStatus

TheReadDeviceIdentifiercommandisusedtodetermineablock’slockstatus(seeSection9.2, “ReadDeviceIdentifier”onpage48).DatabitsD[1:0]displaytheaddressedblock’slockstatus; D0istheaddressedblock’slockbit,whileD1istheaddressedblock’slock-downbit.

7.1.5 Block LockingDuringSuspend

Blocklockandunlockchangescanbeperformedduringanerasesuspend.Tochangeblock lockingduringaneraseoperation,firstissuetheEraseSuspendcommand.MonitortheStatus RegisteruntilSR[7]andSR[6]areset,indicatingthedeviceissuspendedandreadytoaccept anothercommand. Next,writethedesiredlockcommandsequencetoablock,whichchangesthelockstateofthat block.Aftercompletingblocklockorunlockoperations,resumetheeraseoperationusingthe EraseResumecommand. Figure8.BlockLockingStateDiagram [000] [001] [011] [111] [101] [110] [100] 60h/ D0h 60h/01h 60h/ 2Fh 60h/2Fh 60h/D0h 60h/ 01h 60h/ D0h 60h/ 01h 60h/ 2Fh 60h/ 2Fh UNLOCKED LOCKED WP#=VIL=0 WP#=VIH=1 Power-Up/Reset Default Power-Up/Reset Default 60h/D0h=UnlockCommand 60h/01h=LockCommand 60h/2Fh=Lock-DownCommand Locked-down Locked-downisdisabledby WP#=VIH

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Note: ALockBlockSetupcommandfollowedbyanycommandotherthanLockBlock,UnlockBlock, orLock-DownBlockproducesacommandsequenceerrorandsetStatusRegisterbitsSR[4]and SR[5].Ifacommandsequenceerroroccursduringanerasesuspend,SR[4]andSR[5]remainsset, evenaftertheeraseoperationisresumed.UnlesstheStatusRegisterisclearedusingtheClear StatusRegistercommandbeforeresumingtheeraseoperation,possibleeraseerrorsmaybe maskedbythecommandsequenceerror. Ifablockislockedorlocked-downduringanerasesuspendofthesameblock,thelockstatusbits changeimmediately.However,theeraseoperationcompleteswhenitisresumed.Blocklock operationscannotoccurduringaprogramsuspend.SeeAppendixA,“WriteStateMachine (WSM)”onpage67,whichshowsvalidcommandsduringanerasesuspend.

7.2 Protection Registers

Thedevicecontains17ProtectionRegisters(PRs)thatcanbeusedtoimplementsystemsecurity measuresand/ordeviceidentification.EachProtectionRegistercanbeindividuallylocked. Thefirst128-bitProtectionRegisteriscomprisedoftwo64-bit(8-word)segments.Thelower64- bitsegmentispre-programmedatthefactorywithaunique64-bitnumber.Theother64-bit segment,aswellastheothersixteen128-bitProtectionRegisters,areblank.Userscanprogram theseregistersasneeded.Whenprogrammed,userscanthenlocktheProtectionRegister(s)to preventadditionalbitprogramming(seeFigure9,“ProtectionRegisterMap”onpage41). Theuser-programmableProtectionRegisterscontainone-timeprogrammable(OTP)bits;when programmed,registerbitscannotbeerased.EachProtectionRegistercanbeaccessedmultiple timestoprogramindividualbits,aslongastheregisterremainsunlocked. EachProtectionRegisterhasanassociatedLockRegisterbit.WhenaLockRegisterbitis programmed,theassociatedProtectionRegistercanonlyberead;itcannolongerbeprogrammed. Additionally,becausetheLockRegisterbitsthemselvesareOTP,whenprogrammed,Lock Registerbitscannotbeerased.Therefore,whenaProtectionRegisterislocked,itcannotbe unlocked

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7.2.1 Reading theProtectionRegisters

TheProtectionRegisterscanbereadfromwithinanypartition’saddressspace.Toreadthe ProtectionRegister,firstissuetheReadDeviceIdentifiercommandatanypartitions’addressto placethatpartitionintheReadDeviceIdentifierstate(seeSection3.2,“DeviceCommands”on page18).Next,performareadoperationatthatpartition’sbaseaddressplustheaddressoffset correspondingtotheregistertoberead.Table14,“DeviceIdentifierInformation”onpage49 showstheaddressoffsetsoftheProtectionRegistersandLockRegisters.Registerdataisread16 bitsatatime. Note: IfaprogramoreraseoperationoccurswithinthedevicewhileitisreadingaProtectionRegister, certainrestrictionsmayapply.SeeTable12,“SimultaneousOperationRestrictions”onpage46for details. Figure9.ProtectionRegisterMap 0x89 LockRegister1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x102 0x109 0x8A 0x91 128-bitProtectionRegister16 (User-Programmable) 128-bitProtectionRegister1 (User-Programmable) 0x88 0x85 64-bitSegment (User-Programmable) 0x84 0x81 0x80 LockRegister0 64-bitSegment (Factory-Programmed) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 128-BitProtectionRegister0

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7.2.2 Programming theProtectionRegisters

ToprogramanyoftheProtectionRegisters,firstissuetheProgramProtectionRegistercommand attheparameterpartition’sbaseaddressplustheoffsettothedesiredProtectionRegister(see Section3.2,“DeviceCommands”onpage18).Next,writethedesiredProtectionRegisterdatato thesameProtectionRegisteraddress(seeFigure9,“ProtectionRegisterMap”onpage41). Thedeviceprogramsthe64-bitand128-bituser-programmableProtectionRegisterdata16bitsat atime(seeFigure37,“ProtectionRegisterProgrammingFlowchart”onpage81).Issuingthe ProgramProtectionRegistercommandoutsideoftheProtectionRegister’saddressspacecausesa programerror(SR[4]set).AttemptingtoprogramalockedProtectionRegistercausesaprogram error(SR[4]set)andalockerror(SR[1]set). Note: IfaprogramoreraseoperationoccurswhenprogrammingaProtectionRegister,certain restrictionsmayapply.SeeTable12,“SimultaneousOperationRestrictions”onpage46fordetails.

7.2.3 Locking theProtectionRegisters

EachProtectionRegistercanbelockedbyprogrammingitsrespectivelockbitintheLock Register.TolockaProtectionRegister,programthecorrespondingbitintheLockRegisterby issuingtheProgramLockRegistercommand,followedbythedesiredLockRegisterdata(see Section3.2,“DeviceCommands”onpage18).ThephysicaladdressesoftheLockRegistersare 0x80forregister0and0x89forregister1.Theseaddressesareusedwhenprogrammingthelock registers(seeTable14,“DeviceIdentifierInformation”onpage49). Bit0ofLockRegister0isalreadyprogrammedatthefactory,lockingthelower,pre-programmed 64-bitregionofthefirst128-bitProtectionRegistercontainingtheuniqueidentificationnumberof thedevice.Bit1ofLockRegister0canbeprogrammedbytheusertolocktheuser-programmable, 64-bitregionofthefirst128-bitProtectionRegister.TheotherbitsinLockRegister0arenotused. LockRegister1controlsthelockingoftheuppersixteen128-bitProtectionRegisters.Eachofthe 16bitsofLockRegister1correspondtoeachoftheuppersixteen128-bitProtectionRegisters. ProgrammingabitinLockRegister1locksthecorresponding128-bitProtectionRegister. Caution: Afterbeinglocked,theProtectionRegisterscannotbeunlocked.

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8.0 Dual-OperationConsiderations

Themulti-partitionarchitectureofthedeviceallowsbackgroundprogramming(orerasing)to occurinonepartitionwhiledatareads(orcodeexecution)takeplaceinanotherpartition.

8.1 Memory Partitioning

TheL30flashmemoryarrayisdividedintomultiple8-Mbitpartitions,whichallowssimultaneous read-while-writeoperations.Simultaneousprogramanderaseisnotallowed.Onlyonepartitionat atimecanbeinprogramorerasemode. Theflashdevicesupportsread-while-writeoperationswithbuscyclegranularityandnotcommand granularity.Inotherwords,itisnotassumedthatbothbuscyclesofatwocyclecommand(anerase commandforexample)willalwaysoccurasbacktobackbuscyclestotheflashdevice.In practice,codefetches(reads)maybeinterspersedbetweenwritecyclestotheflashdevice,and theywilllikelybedirectedtoadifferentpartitionthantheonebeingwritten.Thisisespeciallytrue whenaprocessorisexecutingcodefromonepartitionthatinstructstheprocessortoprogramor eraseinanotherpartition.

8.2 Read-While-Write CommandSequences

Whenissuingcommandstothedevice,areadoperationcanoccurbetween2-cycleWrite command’s(Figure10,andFigure11).However,awriteoperationissuedbetweena2-cycle commandswritesequencecausesacommandsequenceerror.(SeeFigure12) WhenreadingfromthesamepartitionafterissuingaSetupcommand,StatusRegisterdatais returned,regardlessofthereadmodeofthepartitionpriortoissuingtheSetupcommand. Figure10.OperatingModewithCorrectCommandSequenceExample PartitionA PartitionA PartitionB 0x20 0xD0 0xFF Address[A] WE#[W] OE#[G] Data[D/Q]

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8.2.1 Simultaneous OperationDetails

TheL30flashmemorydevicesupportssimultaneousreadfromonepartitionwhileprogramming orerasinginanyotherpartition.CertainfeaturesliketheProtectionRegistersandQuerydatahave specialrequirementswithrespecttosimultaneousoperationcapability.Thesewillbedetailedin thefollowingsections.

8.2.2 Synchronous andAsynchronousRead-While-WriteCharacteristics

Thissectiondescribesthetransitionsofwriteoperationtoasynchronousread,andsynchronous readtowriteoperation.

8.2.2.1 Write operationtoasynchronousreadtransition

TheACparameterW18(tWHAV-WE#HightoAddressValid)isrequiredwhentransitioningfroma writecycle(WE#goinghigh)toperformanasynchronousread(onlyaddressvalidisrequired). W19andW20-tWHCVandtWHVH TheACparametersW19orW20(tWHCV-WE#HightoClockValid,andtWHVH-WE#Highto ADV#High)isrequiredwhentransitioningfromawritecycle(WE#goinghigh)toperforma synchronousburstread.AdelayfromWE#goinghightoavalidclockedgeorADV#goinghigh tolatchanewaddressmustbemet. Figure11.OperatingModewithCorrectCommandSequenceExample PartitionA PartitionB PartitionA 0x20 ValidArrayData 0xD0 Address[A] WE#[W] OE#[G] Data[D/Q] Figure12.OperatingModewithIllegalCommandSequenceExample PartitionA PartitionB PartitionA PartitionA 0x20 0xFF 0xD0 SR[7:0] Address[A] WE#[W] OE#[G] Data[D/Q]

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8.2.2.2 Synchronous readtowriteoperationtransition

TheACparametersW21(tVHWL-ADV#HightoWE#Low)andW22(tCHWL-Clockhighto WE#low)arerequiredwhenthedeviceisinasynchronousmodeandclockisactive.Awritebus cycleconsistsoftwoparts:

• thehostprovidesanaddresstotheflashdevice;and
• thehostthenprovidesdatatotheflashdevice. Theflashdeviceinturnbindsthereceiveddatawiththereceivedaddress.Whenoperating synchronously(RCR.15=0),theaddressofawritecyclemaybeprovidedtotheflashbythefirst activeclockedgewithADV#low,orrisingedgeofADV#aslongastheapplicablecycle separationconditionsaremetbetweeneachcycle. IfneitheraclockedgenorarisingADV#edgeisusedtoprovideanewaddressatthebeginningof awritecycle(theclockisstoppedandADV#islow),theaddressmayalsobeprovidedtotheflash devicebyholdingtheaddressbusstablefortherequiredamountoftime(W5,tAVWH)beforethe risingWE#edge. Alternatively,thehostmaychoosenottoprovideanaddresstotheflashdeviceduringsubsequent writecycles(ifADV#ishighandonlyCE#orWE#istoggledtoseparatethepriorcyclefromthe currentwritecycle).Inthiscase,theflashdevicewillusethemostrecentlyprovidedaddressfrom thehost. RefertoFigure22,“WritetoAsynchronousReadTiming”onpage62,Figure23,“Synchronous ReadtoWriteTiming”onpage62,andFigure24,“WritetoSynchronousReadTiming”on page63,forrepresentationofthesetimings.

8.2.3 Read OperationDuringBufferedProgrammingFlowchart

Themulti-partitionarchitectureofthedeviceallowsbackgroundprogramming(orerasing)to occurinonepartitionwhiledatareads(orcodeexecution)takeplaceinanotherpartition. Toperformareadwhilebufferedprogrammingoperation,firstissueaBufferedProgramsetup commandinapartition.Whenareadoperationoccursinthesamepartitionafterissuingasetup command,StatusRegisterdatawillbereturned,regardlessofthereadmodeofthepartitionpriorto issuingthesetupcommand. Toreaddatafromablockinotherpartitionandtheotherpartitionalreadyinreadarraymode,a newblockaddressmustbeissued.However,iftheotherpartitionisnotalreadyinreadarraymode, issuingareadarraycommandwillcausethebufferedprogramoperationtoabortandacommand sequenceerrorwouldbepostedintheStatusRegister.SeeFigure38,“ReadWhileBuffered ProgrammingFlowchart”onpage82formoredetails. Note: Simultaneousread-while-BufferedEFPisnotsupported.

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8.3 Simultaneous OperationRestrictions

SincetheL30flashmemorydevicesupportssimultaneousreadfromonepartitionwhile programmingorerasinginanotherpartition,certainfeaturesliketheProtectionRegistersandCFI Querydatahavespecialrequirementswithrespecttosimultaneousoperationcapability.(Table12 providesdetailsonrestrictionsduringsimultaneousoperations.) Table12.SimultaneousOperationRestrictions Protection Registeror CFIdata Parameter Partition ArrayData Other Partitions Notes Read (See Notes) Write/Erase Whileprogrammingorerasinginamainpartition,theProtection RegisterorCFIdatamaybereadfromanyotherpartition. Readingtheparameterpartitionarraydataisnotallowedifthe ProtectionRegisterorQuerydataisbeingreadfromaddresses withintheparameterpartition. (SeeNotes) Read Write/Erase Whileprogrammingorerasinginamainpartition,readoperations areallowedintheparameterpartition. AccessingtheProtectionRegistersorCFIdatafromparameter partitionaddressesisnotallowedwhenreadingarraydatafromthe parameterpartition. Read Read Write/Erase Whileprogrammingorerasinginamainpartition,readoperations areallowedintheparameterpartition. AccessingtheProtectionRegistersorCFIdatainapartitionthatis differentfromtheonebeingprogramed/erased,andalsodifferent fromtheparameterpartitionisallowed. Write NoAccess Allowed Read WhileprogrammingtheProtectionRegister,readsareonlyallowed intheothermainpartitions. Accesstoarraydataintheparameterpartitionisnotallowed. ProgrammingoftheProtectionRegistercanonlyoccurinthe parameterpartition,whichmeansthispartitionisinReadStatus. NoAccess Allowed Write/Erase Read Whileprogrammingorerasingtheparameterpartition,readsofthe ProtectionRegistersorCFIdataarenotallowedinanypartition. Readsinpartitionsotherthanthemainpartitionsaresupported.

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9.0 Special ReadStates

Thefollowingsectionsdescribenon-arrayreadstates.Non-arrayreadscanbeperformedin asynchronousreadorsynchronousburstmode.Anon-arrayreadoperationoccursasasynchronous single-wordmode.Whennon-arrayreadsareperformedinasynchronouspagemodeonlythefirst dataisvalidandallsubsequentdataareundefined.Whenanon-arrayreadoperationoccursas synchronousburstmode,thesamewordofdatarequestedwillbeoutputonsuccessiveclockedges untiltheburstlengthrequirementsaresatisfied. Eachpartitioncanbeinoneofitsreadstatesindependentofotherpartitions’modes.SeeFigure 13,“AsynchronousSingle-WordRead(ADV#Low)”onpage56,Figure14,“Asynchronous Single-WordRead(ADV#Latch)”onpage57,andFigure16,“SynchronousSingle-WordArrayor Non-arrayReadTiming”onpage58fordetails.

9.1 Read StatusRegister

ThestatusofanypartitionisdeterminedbyreadingtheStatusRegisterfromtheaddressofthat particularpartition.ToreadtheStatusRegister,issuetheReadStatusRegistercommandwithinthe desiredpartition’saddressrange.StatusRegisterinformationisavailableatthepartitionaddressto whichtheReadStatusRegister,WordProgram,orBlockErasecommandwasissued.Status RegisterdataisautomaticallymadeavailablefollowingaWordProgram,BlockErase,orBlock Lockcommandsequence.Readsfromapartitionafteranyofthesecommandsequencesoutputs thatpartition’sstatusuntilanothervalidcommandiswrittentothatpartition(e.g.ReadArray command). TheStatusRegisterisreadusingsingleasynchronous-modeorsynchronousburstmodereads. StatusRegisterdataisoutputonD[7:0],while0x00isoutputonD[15:8].Inasynchronousmode thefallingedgeofOE#,orCE#(whicheveroccursfirst)updatesandlatchestheStatusRegister contents.However,readingtheStatusRegisterinsynchronousburstmode,CE#orADV#mustbe toggledtoupdatestatusdata.TheStatusRegisterreadoperationsdonotaffectthereadstateofthe otherpartitions. TheDeviceWriteStatusbit(SR[7])providesoverallstatusofthedevice.ThePartitionStatusbit (SR[0])indicateswhethertheaddressedpartitionorsomeotherpartitionisactivelyprogramming orerasing.StatusregisterbitsSR[6:1]presentstatusanderrorinformationabouttheprogram, erase,suspend,VPP,andblock-lockedoperations. Table13.StatusRegisterDescription(Sheet1of2) StatusRegister(SR) DefaultValue=0x80 Device WriteStatus Erase Suspend Status Erase Status Program Status VPPStatus Program Suspend Status Block- Locked Status Partition Status DWS ESS ES PS VPPS PSS BLS PWS 76543210 Bit Name Description

7 DeviceWriteStatus

(DWS) 0=Deviceisbusy;programorerasecycleinprogress;SR[0]valid. 1=Deviceisready;SR[6:1]arevalid.

6 EraseSuspendStatus

(ESS) 0=Erasesuspendnotineffect. 1=Erasesuspendineffect.

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AlwayscleartheStatusRegisterpriortoresumingeraseoperations.AvoidsStatusRegister ambiguitywhenissuingcommandsduringEraseSuspend.Ifacommandsequenceerroroccurs duringanerase-suspendstate,theStatusRegistercontainsthecommandsequenceerrorstatus (SR[7,5,4]set).Whentheeraseoperationresumesandfinishes,possibleerrorsduringtheerase operationcannotbedetectedviatheStatusRegisterbecauseitcontainsthepreviouserrorstatus.

9.1.1 Clear StatusRegister

TheClearStatusRegistercommandclearsthestatusregister,leavingallpartitionreadstates unchanged.ItfunctionsindependentofVPP.TheWriteStateMachine(WSM)setsandclears SR[7,6,2,0],butitsetsbitsSR[5:3,1]withoutclearingthem.TheStatusRegistershouldbecleared beforestartingacommandsequencetoavoidanyambiguity.AdeviceresetalsoclearstheStatus Register.

9.2 Read DeviceIdentifier

TheReadDeviceIdentifiercommandinstructstheaddressedpartitiontooutputmanufacturer code,deviceidentifiercode,block-lockstatus,protectionregisterdata,orconfigurationregister datawhenthatpartition’saddressesareread(seeSection3.2,“DeviceCommands”onpage18for detailsonissuingtheReadDeviceIdentifiercommand).Table14,“DeviceIdentifierInformation” onpage49andTable15,“DeviceIDcodes”onpage49showtheaddressoffsetsanddatavalues forthisdevice. IssuingaReadDeviceIdentifiercommandtoapartitionthatisprogrammingorerasingplacesthat partitionintheReadIdentifierstatewhilethepartitioncontinuestoprogramoreraseinthe background. 5E r a s e Status(ES) 0=Erasesuccessful. 1=ErasefailorprogramsequenceerrorwhensetwithSR[4,7]. 4P r o g r a m Status(PS) 0=Programsuccessful. 1=ProgramfailorprogramsequenceerrorwhensetwithSR[5,7] 3V PPStatus(VPPS) 0=VPPwithinacceptablelimitsduringprogramoreraseoperation. 1=VPP<VPPLKduringprogramoreraseoperation.

2 ProgramSuspendStatus

(PSS) 0=Programsuspendnotineffect. 1=Programsuspendineffect.

1 Block-LockedStatus

(BLS) 0=Blocknotlockedduringprogramorerase. 1=Blocklockedduringprogramorerase;operationaborted.

0 PartitionWriteStatus

(PWS) DWSPWS 0 0=Programoreraseoperationinaddressedpartition. 0 1=Programoreraseoperationinotherpartition. 1 0=Noactiveprogramoreraseoperations. 1 1=Reserved. (Non-bufferedEFPoperation.ForBufferedEFPoperation,see Section5.3,“BufferedEnhancedFactoryProgramming”on page32). Table13.StatusRegisterDescription(Sheet2of2) StatusRegister(SR) DefaultValue=0x80

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9.3 CFI Query

TheCFIQuerycommandinstructsthedevicetooutputCommonFlashInterface(CFI)datawhen partitionaddressesareread.SeeSection3.2,“DeviceCommands”onpage18fordetailson issuingtheCFIQuerycommand.AppendixC,“CommonFlashInterface”onpage83showsCFI informationandaddressoffsetswithintheCFIdatabase. IssuingtheCFIQuerycommandtoapartitionthatisprogrammingorerasingplacesthatpartition’s outputsintheCFIQuerystate,whilethepartitioncontinuestoprogramoreraseinthebackground. TheCFIQuerycommandissubjecttoreadrestrictionsdependentonparameterpartition availability,asdescribedinTable12,“SimultaneousOperationRestrictions”onpage46. Table14.DeviceIdentifierInformation Item Address (1,2) Data ManufacturerCode PBA +0x00 0089h DeviceIDCode PBA +0x01 ID (seeTable15) BlockLockConfiguration: BBA+0x02 LockBit:

• BlockIsUnlocked DQ 0=0b0
• BlockIsLocked DQ 0=0b1
• BlockIsnotLocked-Down DQ 1=0b0
• BlockIsLocked-Down DQ 1=0b1 ConfigurationRegister PBA +0x05 Configuration RegisterData LockRegister0 PBA +0x80 PR-LK0 64-bitFactory-ProgrammedProtectionRegister PBA +0x81–0x84 FactoryProtectionRegisterData 64-bitUser-ProgrammableProtectionRegister PBA +0x85–0x88 UserProtectionRegisterData LockRegister1 PBA +0x89 Protection RegisterData 128-bitUser-ProgrammableProtectionRegisters PBA +0x8A–0x109 PR-LK1 NOTES: 1.PBA=PartitionBaseAddress. 2.BBA=BlockBaseAddress. Table15.DeviceIDcodes IDCodeType Device Density DeviceIdentifierCodes (TopParameter) (BottomParameter) DeviceCode 64Mbit 8811 8814 128Mbit 8812 8815 256Mbit 8813 8816

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10.0 Power andReset

10.1 Power-Up/Down Characteristics

PowersupplysequencingisnotrequiredifVCC,VCCQ,andVPPareconnectedtogether;If VCCQand/orVPParenotconnectedtotheVCCsupply,thenVCCshouldattainVCCMINbefore applyingVCCQandVPP.DeviceinputsshouldnotbedrivenbeforesupplyvoltageequalsVCCMIN. PowersupplytransitionsshouldonlyoccurwhenRST#islow.Thisprotectsthedevicefrom accidentalprogrammingorerasureduringpowertransitions.

10.2 Power SupplyDecoupling

Flashmemorydevicesrequirecarefulpowersupplyde-coupling.Threebasicpowersupplycurrent considerationsare:1)standbycurrentlevels;2)activecurrentlevels;and3)transientpeaks producedwhenCE#andOE#areassertedanddeasserted. Whenthedeviceisaccessed,manyinternalconditionschange.Circuitswithinthedeviceenable charge-pumps,andinternallogicstateschangeathighspeed.Alloftheseinternalactivities producetransientsignals.Transientcurrentmagnitudesdependonthedeviceoutputs’capacitive andinductiveloading.Two-linecontrolandcorrectde-couplingcapacitorselectionsuppress transientvoltagepeaks. BecauseIntel®Multi-LevelCell(MLC)flashmemorydevicesdrawtheirpowerfromVCC,VPP, andVCCQ,eachpowerconnectionshouldhavea0.1µFceramiccapacitorconnectedtoa correspondinggroundconnection(e.g.VCCQtoVSSQ).High-frequency,inherentlylow- inductancecapacitorsshouldbeplacedascloseaspossibletopackageleads. Additionally,foreveryeightdevicesusedinthesystem,a4.7µFelectrolyticcapacitorshouldbe placedbetweenpowerandgroundclosetothedevices.Thebulkcapacitorismeanttoovercome voltagedroopcausedbyPCBtraceinductance.

10.3 Automatic PowerSaving(APS)

AutomaticPowerSaving(APS)provideslowpoweroperationduringaread’sactivestate.ICCAPS istheaveragecurrentmeasuredoverany5mstimeinterval,5µsafterCE#isdeasserted.During APS,averagecurrentismeasuredoverthesametimeinterval5µsafterthefollowingevents happen:(1)thereisnointernalread,programoreraseoperationscease;(2)CE#isasserted;(3)the addresslinesarequiescentandatVSSQorVCCQ.OE#mayalsobedrivenduringAPS.

10.4 Reset Characteristics

AssertingRST#duringasystemresetisimportantwithautomatedprogram/erasedevicesbecause systemstypicallyexpecttoreadfromflashmemorywhencomingoutofreset.IfaCPUreset occurswithoutaflashmemoryreset,properCPUinitializationmaynotoccur.Thisisbecausethe flashmemorymaybeprovidingstatusinformation,insteadofarraydataasexpected.Connect RST#tothesameactive-lowresetsignalusedforCPUinitialization.

28F640L30,28F128L30,28F256L30 Datasheet 51 Also,becausethedeviceisdisabledwhenRST#isasserted,itignoresitscontrolinputsduring power-up/down.Invalidbusconditionsaremasked,providingalevelofmemoryprotection. SystemdesignersshouldguardagainstspuriouswriteswhenVCCvoltagesareaboveVLKO. BecausebothWE#andCE#mustbeassertedforawriteoperation,deassertingeithersignal inhibitswritestothedevice. TheCommandUserInterface(CUI)architectureprovidesadditionalprotectionbecausealteration ofmemorycontentscanonlyoccuraftersuccessfulcompletionofatwo-stepcommandsequence (seeSection3.2,“DeviceCommands”onpage18).

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11.0 Thermal andDCCharacteristics

11.1 Absolute MaximumRatings

Warning: Stressingthedevicebeyondthe“AbsoluteMaximumRatings”maycausepermanentdamage. Thesearestressratingsonly.

11.2 Operating Conditions

Warning: Operationbeyondthe“OperatingConditions”isnotrecommendedandextendedexposurebeyond the“OperatingConditions”mayaffectdevicereliability. Parameter Maximum Rating Notes Temperatureunderbias –25 °Cto+85°C Storagetemperature –65 °Cto+125°C Voltageonanysignal(exceptVCC,VPP) –0.5V to+3.8V 1 VPPvoltage –0.2 Vto+10V 1,2,3 VCCvoltage –0.2 Vto+2.5V1 VCCQvoltage –0.2 Vto+3.8V1 Outputshortcircuitcurrent 100 mA 4 NOTES: 1.VoltagesshownarespecifiedwithrespecttoVSS.MinimumDCvoltageis–0.5Voninput/outputsignals and –0.2VonV CC,VCCQ,andVPP.Duringtransitions,thislevelmayundershootto–2.0Vforperiods<20ns. MaximumDCvoltageonVCCisVCC+0.5V,which,duringtransitions,mayovershoottoVCC+2.0Vfor periods<20ns.MaximumDCvoltageoninput/outputsignalsandVCCQisVCCQ+0.5V,which,during transitions,mayovershoottoVCCQ+2.0Vforperiods<20ns. 2.MaximumDCvoltageonVPPmayovershootto+14.0Vforperiods<20ns. blocksfor1000cyclesmaximum.9.0Vprogram/erasevoltagemayreduceblockcyclingcapability. 4.Outputshortedfornomorethanonesecond.Nomorethanoneoutputshortedatatime. Symbol Parameter Min Max Units Notes TC OperatingTemperature –25 +85 °C 1VCC VCCSupplyVoltage 1.7 2.0 VVCCQ I/OSupplyVoltage 2.2 3.3 VPPL VPPVoltageSupply(LogicLevel) 0.9 2.0 VPPH FactorywordprogrammingVPP 8.5 9.5 tPPH MaximumVPPHours V PP=VPPH 80 Hours Block Erase Cycles MainandParameterBlocks V PP=VCC 100,000 CyclesMainBlocks V PP=VPPH 1000 ParameterBlocks V PP=VPPH 2500 NOTES: 1.TC=CaseTemperature 2.Intypicaloperation,theVPPprogramvoltageisVPPL.VPPcanbeconnectedto8.50V–9.5Vfor1000 cyclesonmainblocks,and2500cyclesonparameterblocks.

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11.3 DC CurrentCharacteristics

VCCQ 2.2V–3.3V Unit Test Conditions Notes Typ Max ILI InputLoadCurrent ±2 µA VCC=VCCMax VCCQ=VCCQMax VIN=VCCQorGND 1 ILO Output Leakage Current D[15:0],WAIT ±10 µA V CC=VCCMax VCCQ=VCCQMax VIN=VCCQorGND ICCS ICCD VCCStandby, PowerDown 64Mbit 20 35 µA VCC=VCCMax VCCQ=VCCQMax CE#=VCCQ RST#=VCCQ(forICCS) RST#=GND(forICCD) WP#=VIH 1,2 128Mbit 30 55 256Mbit 55 95 ICCAPS APS 64Mbit 20 35 µA VCC=VCCMax VCCQ=VCCQMax CE#=VSSQ RST#=VCCQ Allinputsareatrailtorail(VCCQorVSSQ). 128Mbit 30 55 256Mbit 55 95 ICCR Average VCCRead Current AsynchronousSingle-Word f=5MHz(1CLK) 14 16 mA VCC=VCCMAX CE#=VIL OE#=VIH Inputs:VILorVIH Page-ModeRead f=13MHz(5CLK) 9 10 mA 4-Word Read SynchronousBurstRead f=40MHz 16 19 mA Burst length=4 20 24 mA Burst length=8 23 27 mA Burst length=16 30 35 mA Burstlength= Continuous SynchronousBurstRead f=54MHz 18 21 mA Burst length=4 24 28 mA Burst length=8 28 33 mA Burst length=16 30 35 mA BurstLength= Continuous ICCW, ICCE VCCProgramCurrent, VCCEraseCurrent 36 51 mA V PP=VPPL,program/eraseinprogress 1,3,4, 26 33 mA V PP=VPPH,program/eraseinprogress 1,3,5, ICCWS, ICCES VCCProgramSuspendCurrent, VCCEraseSuspendCurrent 64Mbit 20 35 µA CE#=VCCQ;suspendinprogress 1,6,3128Mbit 30 55 256Mbit 55 95 IPPS, IPPWS, IPPES VPPStandbyCurrent, VPPProgramSuspendCurrent, VPPEraseSuspendCurrent 0.2 5 µA V PP=VPPL,suspendinprogress 1,3

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11.4 DC VoltageCharacteristics

IPPR VPPRead 2 15 µA V PP≤VCC 1,3IPPW VPPProgramCurrent 0.05 0.10 mA VPP=VPPL,programinprogress 82 2 V PP=VPPH,programinprogress IPPE VPPEraseCurrent 0.05 0.10 mA VPP=VPPL,eraseinprogress 82 2 V PP=VPPH,eraseinprogress NOTES: 1.AllcurrentsareRMSunlessnoted.TypicalvaluesattypicalVCC,TC=+25°C. 2.ICCSistheaveragecurrentmeasuredoverany5mstimeinterval5µsafterCE#isdeasserted. 3.Sampled,not100%tested. 4.VCCread+programcurrentisthesumofVCCreadandVCCprogramcurrents. 5.VCCread+erasecurrentisthesumofVCCreadandVCCerasecurrents. 6.ICCESisspecifiedwiththedevicedeselected.Ifdeviceisreadwhileinerasesuspend,currentisICCESplusICCR. 7.ICCW,ICCEmeasuredovertypicalormaxtimesspecifiedinSection12.3,“ProgramandEraseCharacteristics”on page64 Sym Parameter VCCQ 2.2V–3.3V Unit Test Condition Notes Min Max VIL InputLowVoltage 0 0.4 V 1 VIH InputHighVoltage VCCQ –0.4 VCCQ V VOL OutputLowVoltage 0.1 V VCC=VCCMIN VCCQ=VCCQMIN IOL=100µA VOH OutputHighVoltage VCCQ –0.1 V VCC=VCCMIN VCCQ=VCCQMIN IOH=–100µA VPPLK VPPLock-OutVoltage 0.4 V 2 VLKO VCCLockVoltage 1.0 V VLKOQ VCCQLockVoltage 0.9 V NOTES: 1.VILcanundershootto–0.4VandVIHcanovershoottoVCCQ+0.4Vfordurationsof20nsorless. 2.VPP<VPPLKinhibitseraseandprogramoperations.DonotuseVPPLandVPPHoutsidetheirvalidranges. Sym Parameter VCCQ 2.2V–3.3V Unit Test Conditions Notes Typ Max

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12.0 AC Characteristics

12.1 AC ReadSpecifications(VCCQ=2.2V–3.3V) Num Symbol Parameter Speed –85 –110 Units Notes Min Max Min Max AsynchronousSpecifications R1 t AVAV Readcycletime 85 110 ns 6R2 tAVQV Addresstooutputvalid 85 110 ns R3 tELQV CE#lowtooutputvalid 85 110 ns R4 tGLQV OE#lowtooutputvalid 25 30 ns 1,2 R5 t PHQV RST#hightooutputvalid 150 150 ns 1 R6 t ELQX CE#lowtooutputinlow-Z 0 0 ns 1,3 R7 t GLQX OE#lowtooutputinlow-Z 0 0 ns 1,2,3 R8 t EHQZ CE#hightooutputinhigh-Z 24 24 ns 1,3R9 t GHQZ OE#hightooutputinhigh-Z 24 24 ns R10 t OH Outputholdfromfirstoccurringaddress,CE#,orOE# change 00 n s R11 t EHEL CE#pulsewidthhigh 20 20 ns 1 R12 t ELTV CE#lowtoWAITvalid 16 20 ns 1 R13 t EHTZ CE#hightoWAIThighZ1 7 2 0 n s 1 , 3 R15 t GLTV OE#lowtoWAITvalid 17 20 ns 1 R16 tGLTX OE#lowtoWAITinlow-Z 0 0 ns 1,3 R17 tGHTZ OE#hightoWAITinhigh-Z 20 24 ns 1,3 LatchingSpecifications R101 t AVVH AddresssetuptoADV#high 10 12 ns R102 t ELVH CE#lowtoADV#high 10 12 ns R103 t VLQV ADV#lowtooutputvalid 85 110 ns R104 t VLVH ADV#pulsewidthlow 10 12 ns R105 t VHVL ADV#pulsewidthhigh 10 12 ns R106 t VHAX AddressholdfromADV#high 9 10 ns 1,4 R108 t APA Pageaddressaccess 25 25 ns 1 R111 t phvh RST#hightoADV#high 30 30 ns 1 ClockSpecifications R200 f CLK CLKfrequency 52 40 MHz 1,3R201 t CLK CLKperiod 19.2 25 ns R202 t CH/CL CLKhigh/lowtime 9 9 ns R203 t FCLK/RCLK CLKfall/risetime 3 3 ns SynchronousSpecifications R301 t AVCH/L AddresssetuptoCLK 9 9 ns R302 t VLCH/L ADV#lowsetuptoCLK 9 9 ns R303 t ELCH/L CE#lowsetuptoCLK 9 9 ns R304 tCHQV/tCLQV CLKtooutputvalid 17 20 ns R305 t CHQX OutputholdfromCLK 3 3 ns 1,5 R306 t CHAX AddressholdfromCLK 10 10 ns 1,4,5 R307 t CHTV CLKtoWAITvalid 20 22 ns 1,5

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l NOTE: WAITshownde-assertedduringasynchronousreadmode(CR[10]=0Waitassertedlow). R311 t CHVL CLKValidtoADV#Setup 0 0 ns 1 R312 t CHTX WAITHoldfromCLK 3 3 ns 1,5 NOTES: 1.SeeFigure26,“ACInput/OutputReferenceWaveform”onpage65fortimingmeasurementsandmaximum allowableinputslewrate. 2.OE#maybedelayedbyuptotELQV–tGLQVafterCE#’sfallingedgewithoutimpacttotELQV. 3.Sampled,not100%tested. 4.AddressholdinsynchronousburstmodeistCHAXortVHAX,whichevertimingspecificationissatisfiedfirst. 5.Appliesonlytosubsequentsynchronousreads. Figure13.AsynchronousSingle-WordRead(ADV#Low) Num Symbol Parameter Speed –85 –110 Units Notes Min Max Min Max R17R15 R9R4 R8R3 Address[A] ADV# CE#[E} OE#[G] WAIT[T] Data[D/Q] RST#[P]

28F640L30,28F128L30,28F256L30 Datasheet 57 NOTE: WAITshownde-assertedduringasynchronousreadmode(CR[10]=0Waitassertedlow). NOTE: WAITshownde-assertedduringasynchronousreadmode(CR[10]=0Waitassertedlow) Figure14.AsynchronousSingle-WordRead(ADV#Latch) R10 R17R15 R9R4 R8R3 R106 R101 R105R105 Address[A] A[1:0][A] ADV# CE#[E} OE#[G] WAIT[T] Data[D/Q] Figure15.AsynchronousPage-ModeReadTiming R108 R9R7 R17R15 R10R4 R8R3 R106 R101 R105R105 R1R1 A[Max:2][A] A[1:0] ADV# CE#[E] OE#[G] WAIT[T] DATA[D/Q]

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NOTES: 1.WAITisdrivenperOE#assertionduringsynchronousarrayornon-arrayread,andcanbeconfiguredto asserteitherduringoronedatacyclebeforevaliddata. 2.Thisdiagramillustratesthecaseinwhichann-wordburstisinitiatedtotheflashmemoryarrayanditis terminatedbyCE#deassertionafterthefirstwordintheburst. Figure16.SynchronousSingle-WordArrayorNon-arrayReadTiming LatencyCount R312 R305R304 R17R307R15 R9R7 R303 R102 R104 R106R101 R104 R105R105 R306R301 CLK[C] Address[A] ADV#[V] CE#[E] OE#[G] WAIT[T] Data[D/Q] Figure17.ContinuousBurstRead,showinganOutputDelayTiming R305R305R305R305 R304 R312R307R15 R303 R102 R106 R105R105 R101 R304R304R304R306 R302 R301 CLK[C] Address[A] ADV#[V] CE#[E] OE#[G] WAIT[T] Data[D/Q]

28F640L30,28F128L30,28F256L30 Datasheet 59 NOTE: AttheendofWordLine;thedelayincurredwhenaburstaccesscrossesa16-wordboundaryandthe startingaddressisnot4-wordboundaryaligned. NOTE: WAITisdrivenperOE#assertionduringsynchronousarrayornon-arrayread.WAITassertedduring initiallatencyanddeassertedduringvaliddata(CR.10=0Waitassertedlow). NOTES: 1.CLKcanbestoppedineitherhighorlowstate. 2.WAITisdrivenperOE#assertionduringsynchronousarrayornon-arrayread.WAITassertedduringinitial latencyanddeassertedduringvaliddata(CR.10=0Waitassertedlow). Figure18.SynchronousBurst-ModeFour-WordReadTiming LatencyCount A Q0 Q1 Q2 Q3 R307 R10 R304 R305R304 R17R15 R303 R106 R102 R105R105 R101 R306 R302 R301 CLK[C] Address[A] ADV#[V] CE#[E] OE#[G] WAIT[T] Data[D/Q] Figure19.BurstSuspendTiming Q0 Q1 Q1 Q2 R15R17 R304R304 R312R15 R4R9R4 R106 R101 R105R105 R1R1 R305R305R304 CLK Address[A] ADV# CE#[E] OE#[G] WAIT[T] WE#[W] DATA[D/Q]

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12.2 AC WriteSpecifications

Nbr. Symbol Parameter (1,2) Min Max Units Notes W1 t PHWL RST#highrecoverytoWE#low 150 ns 1,2,3 W2 t ELWL CE#setuptoWE#low 0 ns 1,2,3 W3 t WLWH WE#writepulsewidthlow 50 ns 1,2,4 W4 t DVWH DatasetuptoWE#high 50 ns 1,2 W5 t AVWHA d d r e s s setuptoWE#high 50 ns W6 t WHEHC E # holdfromWE#high 0 ns W7 t WHDXD a t a holdfromWE#high 0 ns W8 t WHAXA d d r e s s holdfromWE#high 0 ns W9 t WHWLW E # pulsewidthhigh 20 ns 1,2,5 W10 t VPWHV PPsetuptoWE#high 200 ns 1,2,3,7 W11 t QVVL VPPholdfromStatusread 0 ns W12 t QVBL WP#holdfromStatusread 0 ns 1,2,3,7 W13 t BHWHW P # setuptoWE#high 200 ns W14 t WHGLW E # hightoOE#low 0 ns 1,2,9 W16 t WHQV WE#hightoreadvalid t AVQV+35 ns 1,2,3,6,10 WritetoAsynchronousReadSpecifications W18 t WHAV WE#hightoAddressvalid 0 ns 1,2,3,6 WritetoSynchronousReadSpecifications W19 t WHCH/L WE#hightoClockvalid 19 ns 1,2,3,6,10 W20 t WHVH WE#hightoADV#high 19 ns SynchronousReadtoWriteSpecifications W21 t VHWL ADV#hightoWE#low 20 ns 1,2,3,11 W22 t CHWL ClockhightoWE#low 20 ns NOTES: 1.Writetimingcharacteristicsduringerasesuspendarethesameaswrite-onlyoperations. 2.AwriteoperationcanbeterminatedwitheitherCE#orWE#. 3.Sampled,not100%tested. 4.Writepulsewidthlow(tWLWHortELEH)isdefinedfromCE#orWE#low(whicheveroccurslast)toCE#or WE#high(whicheveroccursfirst).Hence,tWLWH=tELEH=tWLEH=tELWH. 5.Writepulsewidthhigh(tWHWLortEHEL)isdefinedfromCE#orWE#high(whicheveroccursfirst)toCE#or WE#low(whicheveroccurslast).Hence,tWHWL=tEHEL=tWHEL=tEHWL). 6.tWHVHortWHCH/Lmustbemetwhentransitioningfromawritecycletoasynchronousburstread. 7.VPPandWP#shouldbeatavalidleveluntileraseorprogramsuccessisdetermined. 8.Thisspecificationisonlyapplicablewhentransitioningfromawritecycletoanasynchronousread.See specW19andW20forsynchronousread. 9.WhendoingaReadStatusoperationfollowingaprogramorerasewritecycle,W14is20ns. 10.Add10nsifthewriteoperationsresultsinaRCRorblocklockstatuschange,forthesubsequentread operationtoreflectthischange. 11.Thesespecsarerequiredonlywhenthedeviceisinasynchronousmodeandclockisactiveduring addresssetupphase.

28F640L30,28F128L30,28F256L30 Datasheet 61 NOTE: Waitde-assertedduringasynchronousreadandduringwrite.WAITHigh-ZduringwriteperOE#de- asserted. Figure20.WritetoWriteTiming Figure21.AsynchronousReadtoWriteTiming W7W4W7W4 W3W9 W3W9W3W3 W6W2W6W2 W8W8 W5W5 Address[A] CE#[E} WE#[W] OE#[G] Data[D/Q] RST#[P] Q D W4R10 R17R15 W6W3W3W2 R9R4 R8R3 W8W5 Address[A] CE#[E} OE#[G] WE#[W] WAIT[T] Data[D/Q] RST#[P]

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NOTE: WAITshownde-assertedandHigh-ZperOE#de-assertionduringwriteoperation(CR[10]=0Wait assertedlow).Clockisignoredduringwriteoperation. Figure22.WritetoAsynchronousReadTiming D Q W7W4 R17R15 W14 W18W3W3 R10W6W2 R1R1W8W5 Address[A] ADV#[V] CE#[E} WE#[W] OE#[G] WAIT[T] Data[D/Q] RST#[P] Figure23.SynchronousReadtoWriteTiming LatencyCount Q D D W7R305R304R7 R312R307R16 W15 W19 W9W3W3W2 R11 R13 R11 R303 W20R104R104 R106 R102 R105R105 W18 R101 R306 R302 R301 CLK[C] Address[A] ADV#[V] CE#[E] OE#[G] WE# WAIT[T] Data[D/Q]

28F640L30,28F128L30,28F256L30 Datasheet 63 NOTE: WAITshownde-assertedandHigh-ZperOE#de-assertionduringwriteoperation(CR[10]=0Wait assertedlow). Figure24.WritetoSynchronousReadTiming LatencyCount D Q Q R304 R305R304 R307R15 W18W3W3 R11 R303 R11 R104 R106 R104 R306W8W5 R302 R301 CLK Address[A] ADV# CE#[E} WE#[W] OE#[G] WAIT[T] Data[D/Q] RST#[P]

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12.3 Program andEraseCharacteristics

12.4 Reset Specifications

Nbr. Symbol Parameter VPPL VPPH Units Notes Min Typ Max Min Typ Max ConventionalWordProgramming W200 tPROG/W Program Time Singleword 150 TBD 150 TBD µs 1Singlecell 30 TBD 30 TBD BufferedProgramming W200 tPROG/W Program Time Singleword 150 TBD 150 TBD µs 1W251 tBUFF OneBuffer(32words) 640 TBD 288 864 BufferedEnhancedFactoryProgramming W451 tBEFP/W Program Singleword N/A N/A N/A N/A 7 21 µs 1,2 W452 tBEFP/ Setup BufferedEFPSetup N/A N/A N/A 5 N/A N/A 1 ErasingandSuspending W500 tERS/PB EraseTime16-KWordParameter 0.4 2.5 0.4 2.5 s 1W501 tERS/MB 64-KWordMain 0.8 4 0.7 4 W600 tSUSP/P Suspend Latency Programs u s p e n d 2 02 5 2 02 5 µsW601 tSUSP/E Erases u s p e n d 2 02 5 2 02 5 NOTES: 1.TypicalvaluesmeasuredatTC=+25°Candnominalvoltages.Performancenumbersarevalidforallspeed versions.Excludessystemoverhead.Sampled,butnot100%tested. 2.Averagedoverentiredevice. Nbr. Symbol Parameter Min Max Unit Notes P1 tPLPH RST#pulsewidthlow 100 ns 1,2,3,4 P2 tPLRH RST#lowtodeviceresetduringerase 25 µs 1,3,4,7 RST#lowtodeviceresetduringprogram 25 1,3,4,7 P3 tVCCPH VCCPowervalidtoRST#de-assertion(high) 60 1,4,5,6 NOTES: 1.Thesespecificationsarevalidforalldeviceversions(packagesandspeeds). 2.ThedevicemayresetiftPLPHis<tPLPHMIN,butthisisnotguaranteed. 3.NotapplicableifRST#istiedtoVcc. 4.Sampled,butnot100%tested. 5.IfRST#istiedtotheVCCsupply,devicewillnotbereadyuntiltVCCPHafterVCC>=VCCmin. 6.IfRST#istiedtoanysupply/signalwithVCCQvoltagelevels,theRST#inputvoltagemustnotexceedVCC untilVCC>=VCC(min). 7.ResetcompleteswithintPLPHifRST#isassertedwhilenoeraseorprogramoperationisexecuting.

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12.5 AC TestConditions

NOTE: ACtestinputsaredrivenatVCCQforLogic"1"and0.0VforLogic"0."Input/outputtimingbegins/ends atVCCQ/2.Inputriseandfalltimes(10%to90%)<5ns.WorstcasespeedoccursatVCC=VCCMin. NOTES: 1.Seethefollowingtableforcomponentvalues. 2.Testconfigurationcomponentvalueforworstcasespeedconditions. 3.CLincludesjigcapacitance Figure25.ResetOperationWaveforms Figure26.ACInput/OutputReferenceWaveform (A) Resetduring readmode (B) Resetduring programorblockerase P1 ≤P2 (C) Resetduring programorblockerase P1≥ P2 VIH VIL VIH VIL VIH VIL RST#[P] RST#[P] RST#[P] Abort Complete Abort Complete VCC VCC (D) VCCPower-upto RST#high P1 R5 P2 R5 RESETWMF O InputVCCQ/2 VCCQ/2Output VCCQ TestPoints Figure27.TransientEquivalentTestingLoadCircuit Device UnderTest VCCQ Out CL Table16.Testconfigurationcomponentvalueforworstcasespeedconditions TestConfiguration C L(pF) R 1(Ω )R 2(Ω ) 2.0VStandardTest 30 22K 22K

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12.6 Capacitance

Figure28.ClockInputACWaveform Table17.Capacitance Symbol Parameter 1 Typ Max Unit Condition Note CIN InputCapacitance 6 8 pF V IN=0.0V 1,2,3 COUT OutputCapacitance 8 12 pF V OUT=0.0V 1,2CCE# CE#InputCapacitance 10 12 pF V IN=0.0V NOTES: 1.TC=+25°C,f=1MHz. 2.Sampled,not100%tested. 3.CIN(Max)=10pFfor256MbitDensity CLK[C] VIH VIL R203R202 R201 CLKINPUTWMF

28F640L30,28F128L30,28F256L30 Datasheet 67 AppendixAWriteStateMachine(WSM) Figure29showsthecommandstatetransitions(NextStateTable)basedonincomingcommands.Onlyone partitioncanbeactivelyprogrammingorerasingatatime.Eachpartitionstaysinitslastreadstate(Read Array,ReadDeviceID,CFIQueryorReadStatusRegister)untilanewcommandchangesit.ThenextWSM statedoesnotdependonthepartition’soutputstate. Figure29.WriteStateMachine—NextStateTable(Sheet1of6) Read Array(3) Word Program (4,5) Writeto Buffered Program (BP) Erase Setup(4,5) Buffered Enhanced Factory PgmSetup (4) BEConfirm, P/E Resume, ULB, Confirm(9) BP/Prg/ Erase Suspend Read Status Clear Status Register(6) Read ID/Query Lock, Unlock, Lock-down, CRsetup(5) Ready Program Setup BPSetup Erase Setup BEFPSetup Lock/CR Setup Ready (Unlock Block) Setup Busy Setup Busy Word Program Suspend Suspend Word Program Busy Setup BPLoad1 BPLoad2 BP Confirm BPBusy BPBusy BP Suspend BP Suspend BPBusy Setup Erase Busy Busy Erase Suspend Suspend Erase Suspend Word Program Setupin Erase Suspend BPSetupin Erase Suspend EraseBusy Lock/CR Setupin Erase Suspend Setup Busy Word Program Suspend inErase Suspend Suspend Word Program Busyin Erase Suspend WordProgramSuspend BPLoad1{Givewordcountload[N-1]};IfN=0(wordcount=1)gotoBPConfirm;Else(Nnot=0)gotoBPLoad2 BPLoad2(Givedataload) Ready(LockError[Botch]) OTPBusy Ready(Error[Botch])Ready(Error[Botch]) WordProgramBusy BPConfirmwhencount=0,ELSEBPload2(note:BPwillBotchatthispointifanyblockaddressisdifferentfromthefirstaddress) CurrentChip State(8) CommandInputtoChipandresultingChipNextState BP BPBusy Lock/CRSetup OTP Ready(LockError[Botch]) Ready Ready Word Program ProgramBusy WordProgramSuspend WordProgramBusy Word Programin Erase Suspend WordProgramBusyinEraseSuspend WordProgramSuspendinEraseSuspend WordProgramBusyinEraseSuspendBusy WordProgramSuspendinEraseSuspend BPSuspend Ready(Error[Botch]) EraseBusy Ready(Error[Botch]) EraseBusy BPBusy BPSuspend Erase EraseSuspend Erase Suspend WordProgramBusyinEraseSuspend

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Figure29.WriteStateMachine—NextStateTable(Sheet2of6) Setup BPLoad1 BPLoad2 BP Confirm BPBusyin Erase Suspend BPBusy BP Suspendin Erase Suspend BP Suspend BPBusyin Erase Suspend Erase Suspend (Unlock Block) Setup BEFP Loading Data (X=32) BPLoad1inEraseSuspend{Givewordcountload[N-1]};IfN=0(wordcount=1)gotoBPConfirm;Else(Nnot=0)gotoBPLoad2 BEFP Busy Buffered Enhanced Factory Program Mode BEFP ProgramandVerifyBusy(ifBlockAddressgivenmatchesaddressgivenonBEFPSetupcommand).Commandstreatedasdata.(7) Lock/CRSetupinErase Suspend EraseSuspend(LockError[Botch]) BPConfirminEraseSuspendwhencount=0,ELSEBPload2(note:BPwillBotchatthispointifanyblockaddressisdifferentfromthefirst address) BPinErase Suspend BPLoad2inEraseSuspend(Givedataload) BPSuspendinEraseSuspend Ready(Error[BotchBP]inEraseSuspend) BPBusyinEraseSuspend BPSuspendinEraseSuspend BPBusyinEraseSuspend EraseSuspend(Error[BotchBP]) EraseSuspend(LockError[Botch]) Ready(Error[Botch]) Ready (Error[Botch])

28F640L30,28F128L30,28F256L30 Datasheet 69 Figure29.WriteStateMachine—NextStateTable(Sheet3of6) Read Array(3) Word Program Setup(4,5) BPSetup Erase Setup(4,5) Buffered Enhanced Factory PgmSetup (4) BEConfirm, P/E Resume, ULB Confirm(9) Program/ Erase Suspend Read Status Clear Status Register(6) Read ID/Query Lock, Unlock, Lock-down, CRsetup(5) StatusRead StatusRead StatusRead CommandInputtoChipandresultingOutputMuxNextState Ready, EraseSuspend, BPSuspend StatusRead Lock/CRSetup, Lock/CRSetupin EraseSusp Outputmuxdoesnot change. BEFPSetup, BEFPPgm& VerifyBusy, EraseSetup, OTPSetup, BP:Setup,Load1, Load2,Confirm, WordPgmSetup, WordPgmSetupin EraseSusp, BPSetup,Load1, Load2,Confirmin EraseSuspend Currentchipstate StatusRead Outputmux doesnot change. Status Read IDRead OTPBusy BPBusy, WordProgram Busy, EraseBusy, BPBusy BPBusyinErase Suspend WordPgm Suspend, WordPgmBusyin EraseSuspend, PgmSuspendIn EraseSuspend Read Array

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Figure29.WriteStateMachine—NextStateTable(Sheet4of6) OTPSetup (5) Lock Block Confirm(9) Lock-Down BlockConfirm (9) WriteCR Confirm(9) Block Address (WA0) IllegalCmds orBEFPData (2) (C0H) (01H) (2FH) (03H) (XXXXH) (allother codes) OTPSetup Ready (LockError [Botch]) Ready (LockBlock) Ready (LockDown Blk) Ready (SetCR) Ready N/A Ready Exit Ready Ready Erase Suspend N/AWordProgramSuspendinEraseSuspend BPConfirmwhencount=0,ELSEBPload2(note:BPwillBotchatthispointifany blockaddressisdifferentfromthefirstaddress) WordProgramSuspend BPLoad1{Givewordcountload[N-1]};IfN=0(wordcount=1)gotoBPConfirm; Else(Nnot=0)gotoBPLoad2 BPLoad2(Givedataload) OTPBusy Ready(Error[Botch]) WordProgramBusy WordProgramBusy WSM Operation Completes CommandInputtoChipandresultingChip NextState N/AReady(LockError [Botch]) Ready BPBusy BPSuspend Ready(Error[Botch]) EraseBusy WordProgramBusyinEraseSuspendBusy N/A N/A N/A EraseSuspend WordProgramBusyinEraseSuspend

28F640L30,28F128L30,28F256L30 Datasheet 71 Figure29.WriteStateMachine—NextStateTable(Sheet5of6) Exit Erase Suspend Erase Suspend (LockError [Botch]) Erase Suspend (LockBlock) Erase Suspend (LockDown Block) Erase Suspend(Set CR) BEFPProgramandVerifyBusy(ifBlockAddressgiven matchesaddressgivenonBEFPSetupcommand). Commandstreatedasdata.(7) BPLoad1inEraseSuspend{Givewordcountload[N-1]};IfN=0(wordcount=1) gotoBPConfirm;ElseN?0gotoBPLoad2 N/A Ready BPConfirminEraseSuspendwhencount=0,ELSEBPload2(note:BPwillBotch atthispointifanyblockaddressisdifferentfromthefirstaddress) BPLoad2inEraseSuspend(Givedataload) BEFPBusyReady EraseSuspend(Lock Error[Botch]) N/A Ready(Error[BotchBP]inEraseSuspend) BPBusyinEraseSuspend BPSuspendinEraseSuspend Ready(Error[Botch])

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Figure29.WriteStateMachine—NextStateTable(Sheet6of6) NOTES: 1.The"PartitionDataWhenRead"fieldshowswhattheuserwillreadfromtheflashchipafterissuingthe appropriatecommandgiventhePartitionAddressisnotchangedfromtheaddressgivenduringthe command."Read-while-write"functionalitygivesmoreflexibilityindataoutputfromthedevice.Thedataread fromthechipdependsonthePartitionAddressappliedtothedevice;Eachpartitionisplacedintooneof3 OTPSetup (5) Lock Block Confirm(9) Lock-Down BlockConfirm (9) WriteCR Confirm(9) Block Address (WA0) IllegalCmds orBEFPData (2) (C0H) (01H) (2FH) (03H) (FFFFH) (allother codes) StatusRead StatusRead StatusRead CommandInputtoChipandresultingOutputMuxNextState WSM Operation Completes Outputmux doesnot change. Array Read StatusRead Array Read Outputmux doesnot change. Outputmuxdoesnotchange.

28F640L30,28F128L30,28F256L30 Datasheet 73 possibleoutputstatesduringcommands:ReadArray,ReadStatusorReadID/CFI,dependingonthe commandgiventothechip;Thispartition'soutputstateisretaineduntilanewcommandisgiventothechip atthatPartitionAddress;Forexample,thisallowstheusertosetpartition#1'soutputstatetoReadArray, andpartition#4'soutputstatetoReadStatus;Everytimethepartitionaddressischangedtopartition#4 (withoutissuinganewcommand),theStatuswillbereadfromthechip. 2."Illegalcommands"includecommandsoutsideoftheallowedcommandset(allowedcommands:40H[pgm], 20H[erase],etc.) 3.Ifa"ReadArray"isattemptedfromabusypartition,theresultwillbe"garbage"data.Thekeypointisthatthe outputmuxforthatpartitionwillbepointingtothe"array",butgarbagedatawillbeoutput.Whentheuser returnstothispartitionaddresssometimeinthefuture,theoutputmuxwillbeinthe"ReadArray"statefrom itslastvisit."ReadID"and"ReadQuery"commandsdotheexactsamethinginthedevice.TheIDand Querydataarelocatedatdifferentlocationsintheaddressmap. 4.1stand2ndcyclesof"2cycleswritecommands"mustbegiventothesamepartitionaddress,orunexpected resultswilloccur. 5.The2ndcycleofthefollowing2cyclecommandswillbeignoredbytheuserinterface:ProgramSetup,Erase Setup,OTPSetupandLock/Unlock/Lock-down/CRsetupwhenissuedinan"illegalcondition".Illegal conditionsaresuchas"pgmsetupwhilebusy","erasesetupwhilebusy",etc. 6.TheClearStatuscommandonlyclearstheerrorbitsinthestatusregisterifthedeviceisnotinthefollowing modes:WSMrunning(PgmBusy,EraseBusy,PgmBusyInEraseSuspend,OTPBusy,BEFPmodes). 7.BEFPwritesareonlyallowedwhenthestatusregisterbit#0=0,orelsethedataisignored. 8.The"currentstate"isthatofthe"chip"andnotofthe"partition";Eachpartition"remembers"whichoutput (Array,ID/CFIorStatus)itwaslastpointedtoonthelastinstructiontothe"chip",butthenextstateofthechip doesnotdependonwherethepartition'soutputmuxispresentlypointingto. 9.Confirmcommands(LockBlock,UnlockBlock,Lock-DownBlock,ConfigurationRegister)performthe operationandthenmovetotheReadyState. 10.Alltwocyclecommandswillbeconsideredasacontiguouswholeduringdevicesuspendstates.Individual commandswillnotbeparsedseparately.Thusforexamplethesecondcycleofanerasecommandissuedin programsuspendwillNOTresumetheprogramoperation.

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Figure30.WordProgramFlowchart Program Suspend Loop Start Write0x40, WordAddress WriteData, WordAddress ReadStatus Register SR[7]= FullStatus Check (ifdesired) Program Complete Suspend? No Yes WORDPROGRAMPROCEDURE RepeatforsubsequentWordProgramoperations. FullStatusRegistercheckcanbedoneaftereachprogram,or afterasequenceofprogramoperations. Write0xFFafterthelastoperationtosettotheReadArray state. CommentsBus OperationCommand Data=0 x 4 0 Addr= LocationtoprogramWrite Program Setup Data= Datatoprogram Addr= LocationtoprogramWrite Data StatusregisterdataRead None CheckSR[7] 1=W S M Ready 0=W S M Busy Idle None (Setup) (Confirm) FULLSTATUSCHECKPROCEDURE ReadStatus Register Program Successful SR[3]= SR[1]= SR[4]=

1 VPPRange

SR[3]MUSTbeclearedbeforetheWriteStateMachinewill allowfurtherprogramattempts. Ifanerrorisdetected,cleartheStatusRegisterbefore continuingoperations-onlytheClearStausRegister commandclearstheStatusRegistererrorbits. Idle Idle Bus Operation None None Command CheckSR[3]: 1=V PPError CheckSR[4]: 1= DataProgramError Comments Idle None CheckSR[1]: 1= Blocklocked;operationaborted

28F640L30,28F128L30,28F256L30 Datasheet 75 Figure31.ProgramSuspend/ResumeFlowchart ReadStatus Register SR.7= SR.2= WriteFFh SuspPartition ReadArray Data Program Completed Done Reading WriteFFh Pgm'dPartition WriteD0h AnyAddress Program Resumed ReadArray Data No Yes PROGRAMSUSPEND/RESUMEPROCEDURE Write Program Resume Data=D 0 h Addr= Suspendedblock(BA) Bus OperationCommand Comments Write Program Suspend Data=B 0 h Addr= Blocktosuspend(BA) Standby CheckSR.7 1=W S M ready 0=W S M busy Standby CheckSR.2 1= Programsuspended 0= Programcompleted Write Read Array Data=F F h Addr=A n y addresswithinthe suspendedpartition Read Readarraydatafromblockotherthan theonebeingprogrammed Read Statusregisterdata Addr= Suspendedblock(BA) PGM_SUS.WMF Start WriteB0h AnyAddress ProgramSuspend ReadStatus ProgramResume Read Array ReadArray Write70h SamePartition Write Read Status Data=7 0 h Addr= Samepartition IfthesuspendedpartitionwasplacedinReadArraymode: Write Read Status ReturnpartitiontoStatusmode: Data=7 0 h Addr= Samepartition Write70h SamePartition ReadStatus

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Figure32.BufferedProgramFlowchart Start GetNext TargetAddress IssueBufferProg.Cmd. 0xE8, BlockAddress ReadStatusRegister atBlockAddress WriteBuffer Available? SR[7]= 1=Yes Device SupportsBuffer Writes? SetTimeoutor LoopCounter Timeout orCount Expired? WriteConfirm0xD0 andBlockAddress Yes No BufferProgramData, StartAddress X=0 Yes 0=No Yes UseSingleWord Programming AbortBuffer Program? No X=N? WriteBufferData, BlockAddress X=X+1 Writetoanother BlockAddress BufferProgramAborted No Yes Yes WriteWordCount, BlockAddress Suspend Program Loop ReadStatusRegister SR[7]=? FullStatus CheckifDesired ProgramComplete Suspend Program?

0 Yes

1.WordcountvalueonD[7:0]isloadedintothewordcount register.CountrangesforthisdeviceareN=0x00to0x1F. 2.ThedeviceoutputstheStatusRegisterwhenread. 3.WriteBuffercontentswillbeprogrammedatthedevicestart addressordestinationflashaddress. 4.AlignthestartaddressonaWriteBufferboundaryfor maximumprogrammingperformance(i.e.,A[4:0]ofthestart address=0x00). 5.ThedeviceabortstheBufferProgramcommandifthe currentaddressisoutsidetheoriginalblockaddress. 6.TheStatusRegisterindicatesanimpropercommand sequenceiftheBufferProgramcommandisaborted;usethe ClearStatusRegistercommandtoclearerrorbits. Fullstatuscheckcanbedoneafteralleraseandwrite sequencescomplete.Write0xFFafterthelastoperationto placethepartitionintheReadArraystate. Bus Operation Standby Read Command None None Write BufferProg. Setup Read None Idle None Comments CheckSR[7]: 1=WSMReady 0=WSMBusy StatusregisterData Addr=BlockAddress Data=0xE8 Addr=BlockAddress SR[7]=Valid Addr=BlockAddress CheckSR[7]: 1=WriteBufferavailable 0=NoWriteBufferavailable Write (Notes5,6) BufferProg. Conf. Data=0xD0 Addr=BlockAddress Write (Notes1,2) None Data=N-1=WordCount N=0correspondstocount=1 Addr=BlockAddress Write (Notes3,4) None Data=WriteBufferData Addr=StartAddress Write (Notes5,6) None Data=WriteBufferData Addr=BlockAddress BufferProgrammingProcedure

28F640L30,28F128L30,28F256L30 Datasheet 77 Figure33.BufferedEFPFlowchart WriteData@1ST WordAddress Last Data? Write0xFFFF, AddressNotwithin CurrentBlock Program Done? ReadStatusReg. Y No(SR[7]=0) FullStatusCheck Procedure Program Complete ReadStatusReg. BEFP Exited? Yes(SR[7]=1) Start Write0x80@ 1STWordAddress VPPapplied, Blockunlocked Write0xD0@ 1STWordAddress BEFPSetup Done? ReadStatusReg. Exit N Program&VerifyPhase ExitPhaseSetupPhase BUFFEREDENHANCEDFACTORYPROGRAMMING(Buffered-EFP)PROCEDURE X=32? InitializeCount: X=0 IncrementCount: X=X+1 Y NOTES: 1.First-wordaddresstobeprogrammedwithinthetargetblockmustbealignedonawrite-bufferboundary. 2.Write-buffercontentsareprogrammedsequentiallytotheflasharraystartingatthefirstwordaddress;WSMinternallyincrementsaddressing. N CheckVPP,Lock Errors(SR[3,1]) Yes(SR[7]=0) CommentsBus State Operation BEFPsetupdelay DataStream Ready? ReadStatusReg. No(SR[0]=1) Repeatforsubsequentblocks; AfterBEFPexit,afullStatusRegistercheckcan determineifanyprogramerroroccurred; SeefullStatusRegistercheckprocedureinthe WordProgramflowchart. Write0xFFtoenterReadArraystate. CheckSR[7]: 0=ExitNotCompleted 1=ExitCompleted CheckExit Status Read Status Register Data=StatusReg.Data Address=1STWordAddr BEFPExit Standby IfSR[7]isset,check: SR[3]set=VPPError SR[1]set=LockedBlock Error Condition Check Standby CheckSR[7]: 0=BEFPReady 1=BEFPNotReady BEFP Setup Done? Standby Data=StatusReg.Data Address=1STWordAddr Status RegisterRead Data=0x80@1STWord Address BEFP ConfirmWrite Data=0x80@1STWord Address BEFP Setup Write (Note1) VPPHappliedtoVPPUnlock BlockWrite BEFPSetup Bus State CommentsOperation No(SR[0]=1) Yes(SR[0]=0) No(SR[7]=1) Yes(SR[0]=0) BEFPProgram&Verify CommentsBusState Operation Write (Note2) Load Buffer Standby Increment Count Standby Initialize Count Data=DatatoProgram Address=1STWordAddr. X=X+1 X=0 Standby Buffer Full? X=32? Yes=ReadSR[0] No=LoadNextDataWord Read Standby Status Register DataStream Ready? Data=StatusRegisterData Address=1STWordAddr. CheckSR[0]: 0=ReadyforData 1=NotReadyforData Read Standby Standby Write Status Register Program Done? Last Data? ExitProg& VerifyPhase Data=StatusReg.data Address=1STWordAddr. CheckSR[0]: 0=ProgramDone 1=PrograminProgress No=Fillbufferagain Yes=Exit Data=0xFFFF@addressnotin currentblock

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Figure34.BlockEraseFlowchart Start FULLERASESTATUSCHECKPROCEDURE Repeatforsubsequentblockerasures. FullStatusregistercheckcanbedoneaftereachblockerase orafterasequenceofblockerasures. Write0xFFafterthelastoperationtoenterreadarraymode. SR[1,3]mustbeclearedbeforetheWriteStateMachinewill allowfurthereraseattempts. OnlytheClearStatusRegistercommandclearsSR[1,3,4,5]. Ifanerrorisdetected,cleartheStatusregisterbefore attemptinganeraseretryorothererrorrecovery. No Suspend Erase 1,1 Write0x20, BlockAddress Write0xD0, BlockAddress ReadStatus Register SR[7]= FullErase StatusCheck (ifdesired) BlockErase Complete ReadStatus Register BlockErase Successful SR[1]= BlockLocked Error BLOCKERASEPROCEDURE Bus OperationCommand Comments Write Block Erase Setup Data=0 x 2 0 Addr= Blocktobeerased(BA) Write Erase Confirm Data=0 x D 0 Addr= Blocktobeerased(BA) Read None StatusRegisterdata. Idle None CheckSR[7]: 1=W S M ready 0=W S M busy Bus OperationCommand Comments SR[3]= VPPRange Error SR[4,5]= Command SequenceError SR[5]= BlockErase Error Idle None CheckSR[3]: 1=V PPRangeError Idle None CheckSR[4,5]: Both1=CommandSequenceError Idle None CheckSR[5]: 1= BlockEraseError Idle None CheckSR[1]: 1= Attemptederaseoflockedblock; eraseaborted. (BlockErase) (EraseConfirm)

28F640L30,28F128L30,28F256L30 Datasheet 79 Figure35.EraseSuspend/ResumeFlowchart Erase Completed ReadArray Data No Read Program Program Loop ReadArray Data Start ReadStatus Register SR[7]= SR[6]= Erase Resumed Reador Program? Done Write Write Idle Idle Write Erase Suspend ReadArray orProgram None None Program Resume Data=0xB0 Addr=Samepartitionaddressas above Data=0xFFor0x40 Addr=Anyaddresswithinthe suspendedpartition CheckSR[7]: 1=W S M ready 0=W S M busy CheckSR[6]: 1=E r a s e suspended 0=E r a s e completed Data=0xD0 Addr=Anyaddress Bus OperationCommand Comments Read None StatusRegisterdata. Addr=Samepartition Reador Write None Readarrayorprogramdatafrom/to blockotherthantheonebeingerased ERASESUSPEND/RESUMEPROCEDURE Ifthesuspendedpartitionwasplacedin ReadArraymodeoraProgramLoop: Write0xB0, AnyAddress (EraseSuspend) Write0x70, SamePartition (ReadStatus) Write0xD0, AnyAddress(EraseResume) Write0x70, SamePartition(ReadStatus) Write0xFF, ErasedPartition (ReadArray) Write Read Status Data=0x70 Addr=Anypartitionaddress Write Read Status Register ReturnpartitiontoStatusmode: Data=0x70 Addr=Samepartition

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Figure36.BlockLockOperationsFlowchart No Start Write0x60, BlockAddress Write0x90 ReadBlock LockStatus Locking Change? LockChange Complete Writeeither 0x01/0xD0/0x2F, BlockAddress Write0xFF PartitionAddress Yes Write Write Write (Optional) Read (Optional) Idle Write Lock Setup Lock, Unlock,or Lock-Down Confirm Read DeviceID BlockLock Status None Read Array Data=0x60 Addr=Blocktolock/unlock/lock-down Data=0x01(BlockLock) 0xD0(BlockUnlock) 0x2F(Lock-DownBlock) Addr=Blocktolock/unlock/lock-down Data=0x90 Addr=Blockaddress+offset2 BlockLockstatusdata Addr=Blockaddress+offset2 ConfirmlockingchangeonD[1,0]. Data=0xFF Addr=Blockaddress Bus OperationCommand Comments LOCKINGOPERATIONSPROCEDURE (LockConfirm) (ReadDeviceID) (ReadArray) Optional (LockSetup)

28F640L30,28F128L30,28F256L30 Datasheet 81 Figure37.ProtectionRegisterProgrammingFlowchart FULLSTATUSCHECKPROCEDURE ProgramProtectionRegisteroperationaddressesmustbe withintheProtectionRegisteraddressspace.Addresses outsidethisspacewillreturnanerror. Repeatforsubsequentprogrammingoperations. FullStatusRegistercheckcanbedoneaftereachprogram,or afterasequenceofprogramoperations. Write0xFFafterthelastoperationtosetReadArraystate. SR[3]mustbeclearedbeforetheWriteStateMachinewill allowfurtherprogramattempts. OnlytheClearStausRegistercommandclearsSR[1,3,4]. Ifanerrorisdetected,cleartheStatusregisterbefore attemptingaprogramretryorothererrorrecovery. PROTECTIONREGISTERPROGRAMMINGPROCEDURE Start Write0xC0, PRAddress WritePR Address&Data ReadStatus Register SR[7]= FullStatus Check (ifdesired) Program Complete ReadStatus RegisterData Program Successful SR[3]= SR[4]= SR[1]= VPPRangeError ProgramError RegisterLocked; ProgramAborted Idle Idle Bus Operation None None Command CheckSR[3]: 1=VPPRangeError CheckSR[4]: 1=ProgrammingError Comments Write Write Idle Program PRSetup Protection Program None Data=0xC0 Addr=FirstLocationtoProgram Data=DatatoProgram Addr=LocationtoProgram CheckSR[7]: 1=WSMReady 0=WSMBusy Bus OperationCommand Comments Read None StatusRegisterData. Idle None CheckSR[1]: 1=Blocklocked;operationaborted (ProgramSetup) (ConfirmData)

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Figure38.ReadWhileBufferedProgrammingFlowchart Start GetNext TargetAddress IssueBufferedProgram CommandE8hand BlockAddress ReadStatusRegister (atBlockAddress) SetTimeoutor LoopCounter WriteConfirmD0h andBlockAddress WriteBufferData, StartAddress X=0 Abort Buffered Program? No X=N? WriteBufferData, BlockAddress X=X+1 Writetoanother BlockAddress BufferedProgram Aborted Yes Yes WriteWordCount, BlockAddress 1.WordcountvaluesonDQ0-DQ7areloadedintotheCount register.CountrangesforthisdeviceareN=0000hto0001Fh 2.Thedeviceoutputsthestatusregisterwhenread,orthe deviceoutputsarraydatawhenreadfromblockinother partition(toggleOE#toupdatearraydata). 3.WriteBuffercontentswillbeprogrammedatthedevicestart addressordestinationflashaddress. 4.AlignthestartaddressonaWriteBufferboundaryfor maximumprogrammingperformance(i.e.,A4–A0ofthestart address=0). 5.ThedeviceabortstheBufferedProgramcommandifthe currentaddressisoutsidetheoriginalblockaddress. 6.TheStatusregisterindicatesan"impropercommand sequence"iftheBufferedProgramcommandisaborted.Follow thiswithaClearStatusRegistercommand. 7.Anewwritecyclecommandtoreadmustbeprecededwith aConfirmCommand. 8.Ifareadarrayoperationoccursinapartitionotherthanthe onebeingProgrammed,thatisnotinreadarraymode,aRead Arraycommandmustbewritten. Fullstatuscheckcanbedoneafteralleraseandwrite sequencescomplete.WriteFFhafterthelastoperationtorese thepartitiontoreadarraymode. Bus Operation Read Write (Note7,and Command ReadArray ReadArray Write Buffered Program Read Standby Comments CheckSR.7 1=WSMReady 0=WSMBusy Data=FFH Addr=NewBlockAddress Data=E8H Addr=BlockAddress StatusRegisterData SR.7=Valid Addr=BlockAddress CheckSR.7 1=DeviceWSMisBusy 0=DeviceWSMisReady Write Program Confirm Data=D0H Addr=BlockAddress Write (Notes1,2) Data=N-1=WordCount N=0correspondstocount=1 Addr=BlockAddress Write (Notes3,4) Data=WriteBufferData Addr=StartAddress Write (Notes5,6) Data=WriteBufferData Addr=BlockAddress SR.7=? FullStatus CheckifDesired ProgramComplete ReadArrayDatafrom BlockinotherPartition (NewBlockAddress) or WriteFFHtoRead fromaBlockinotherPartition? Read Status? ReadStatusRegister Read Array? No Yes Yes ReadArrayData No ReadArrayDatafrom BlockinotherPartition (NewBlockAddress) or ReadArrayDatafrom BlockinotherPartition (NewBlockAddress) or ReadArrayDatafrom BlockinotherPartition (NewBlockAddress) or ReadArrayDatafrom BlockinotherPartition (NewBlockAddress) No

28F640L30,28F128L30,28F256L30 Datasheet 83 AppendixCCommonFlashInterface TheCommonFlashInterface(CFI)ispartofanoverallspecificationformultiplecommand-set andcontrol-interfacedescriptions.Thisappendixdescribesthedatabasestructurecontainingthe datareturnedbyareadoperationafterissuingtheCFIQuerycommand(seeSection3.2,“Device Commands”onpage18).Systemsoftwarecanparsethisdatabasestructuretoobtaininformation abouttheflashdevice,suchasblocksize,density,buswidth,andelectricalspecifications.The systemsoftwarewillthenknowwhichcommandset(s)tousetoproperlyperformflashwrites, blockerases,readsandotherwisecontroltheflashdevice. C.1 Query StructureOutput TheQuerydatabaseallowssystemsoftwaretoobtaininformationforcontrollingtheflashdevice. Thissectiondescribesthedevice’sCFI-compliantinterfacethatallowsaccesstoQuerydata. Querydataarepresentedonthelowest-orderdataoutputs(DQ7-0)only.Thenumericaloffsetvalue istheaddressrelativetothemaximumbuswidthsupportedbythedevice.Onthisfamilyof devices,theQuerytabledevicestartingaddressisa10h,whichisawordaddressforx16devices. Foraword-wide(x16)device,thefirsttwoQuery-structurebytes,ASCII“Q”and“R,”appearon thelowbyteatwordaddresses10hand11h.ThisCFI-compliantdeviceoutputs00hdataonupper bytes.ThedeviceoutputsASCII“Q”inthelowbyte(DQ7-0)and00hinthehighbyte(DQ15-8). AtQueryaddressescontainingtwoormorebytesofinformation,theleastsignificantdatabyteis presentedattheloweraddress,andthemostsignificantdatabyteispresentedatthehigheraddress. Inallofthefollowingtables,addressesanddataarerepresentedinhexadecimalnotation,sothe “h”suffixhasbeendropped.Inaddition,sincetheupperbyteofword-widedevicesisalways “00h,”theleading“00”hasbeendroppedfromthetablenotationandonlythelowerbytevalueis shown.Anyx16deviceoutputscanbeassumedtohave00hontheupperbyteinthismode. Table18.SummaryofQueryStructureOutputasaFunctionofDeviceandMode Device Hex Offset Hex Code ASCII Value 00010: 51 "Q" DeviceAddresses 00011: 52 "R" 00012: 59 "Y"

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Table19.ExampleofQueryStructureOutputofx16-Devices C.2 Query StructureOverview TheQuerycommandcausestheflashcomponenttodisplaytheCommonFlashInterface(CFI) Querystructureor“database.”Thestructuresub-sectionsandaddresslocationsaresummarized below. Table20.QueryStructure NOTES: 1.RefertotheQueryStructureOutputsectionandoffset28hforthedetaileddefinitionofoffsetaddressasa functionofdevicebuswidthandmode. 2.BA=BlockAddressbeginninglocation(i.e.,08000hisblock1’sbeginninglocationwhentheblocksizeis 16K-word). 3.Offset15defines“P”whichpointstothePrimaryIntel-specificExtendedQueryTable. WordAddressing: ByteAddressing: Offset Hex Code Value Offset Hex Code Value AX–A0 D15–D0 AX–A0 D7–D0 00010h 0051 "Q" 00010h 51 "Q" 00011h 0052 "R" 00011h 52 "R" 00012h 0059 "Y" 00012h 59 "Y" 00013h P_ID LO PrVendor 00013h P_IDLO PrVendor 00014h P_IDHI ID# 00014h P_IDLO ID# 00015h PLO PrVendor 00015h P_IDHI ID# 00017h A_IDLO AltVendor 00017h 00018h A_IDHI ID# 00018h Offset Sub-Section Name Description(1) 00001-Fh Reserved Reserved forvendor-specificinformation 00010h CFIqueryidentificationstring Command setIDandvendordataoffset 0001Bh Systeminterfaceinformation Device timing&voltageinformation 00027h Devicegeometrydefinition Flash devicelayout P(3) PrimaryIntel-specificExtendedQueryTableVendor-definedadditionalinformationspecific

28F640L30,28F128L30,28F256L30 Datasheet 85 C.3 CFI QueryIdentificationString TheIdentificationStringprovidesverificationthatthecomponentsupportstheCommonFlash Interfacespecification.Italsoindicatesthespecificationversionandsupportedvendor-specified commandset(s). Table21.CFIIdentification Table22.SystemInterfaceInformation Offset Length Description Add. Hex Code Value 10h 3 Query-uniqueASCIIstring“QRY“ 10: --51 "Q" 11: --52 "R" 12: --59 "Y" 13h 2 Primary vendorcommandsetandcontrolinterfaceIDcode. 13: --03 16-bitIDcodeforvendor-specifiedalgorithms 14: --00 15h 2 ExtendedQueryTableprimaryalgorithmaddress 15: --0A 16: --01 17h 2 AlternatevendorcommandsetandcontrolinterfaceIDcode. 17: --00 0000hmeansnosecondvendor-specifiedalgorithmexists 18: --00 19h 2 SecondaryalgorithmExtendedQueryTableaddress. 19: --00 0000hmeansnoneexists 1A: --00 Offset Length Description Add. Hex Code Value 1Bh 1 1B: --17 1.7V 1Ch 1 1C: --20 2.0V 1Dh 1 1D: --85 8.5V 1Eh 1 1E: --95 9.5V 1Fh 1 “n”suchthattypicalsinglewordprogramtime-out=2nµ-sec 1F: --08 256µs 20h 1 “n”suchthattypicalmax.bufferwritetime-out=2nµ-sec 20: --09 512µs 21h 1 “n”suchthattypicalblockerasetime-out=2nm-sec 21: --0A 1s 22h 1 “n”suchthattypicalfullchiperasetime-out=2nm-sec 22: --00 NA 23h 1 “n”suchthatmaximumwordprogramtime-out=2ntimestypical 23: --01 512µs 24h 1 “n”suchthatmaximumbufferwritetime-out=2ntimestypical 24: --01 1024µs 25h 1 “n”suchthatmaximumblockerasetime-out=2ntimestypical 25: --02 4s 26h 1 “n”suchthatmaximumchiperasetime-out=2ntimestypical 26: --00 NA VPP[programming]supplyminimumprogram/erasevoltage bits0–3BCD100mV bits4–7HEXvolts VPP[programming]supplymaximumprogram/erasevoltage bits0–3BCD100mV bits4–7HEXvolts VCClogicsupplyminimumprogram/erasevoltage bits0–3BCD100mV bits4–7BCDvolts VCClogicsupplymaximumprogram/erasevoltage bits0–3BCD100mV bits4–7BCDvolts

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C.4 Device GeometryDefinition Table23.DeviceGeometryDefinition Offset Length Description Code 27h 1 “n”suchthatdevicesize=2ninnumberofbytes 27: Seetablebelow 76543210 28h 2 — — — — x64 x32 x16 x8 28: --01 x16 15 14 13 12 11 10 9 8 2Ah 2 “n”suchthatmaximumnumberofbytesinwritebuffer=2n 2A: --06 64 2B: --00 2Ch 1 2C: 2Dh 4E r a s e BlockRegion1Information 2D: bits0–15=y,y+1=numberofidentical-sizeeraseblocks 2E: bits16–31=z,regioneraseblock(s)sizearezx256bytes 2F: 30: 31h 4E r a s e BlockRegion2Information 31: bits0–15=y,y+1=numberofidentical-sizeeraseblocks 32: bits16–31=z,regioneraseblock(s)sizearezx256bytes 33: 34: 35h 4 Reserved forfutureeraseblockregioninformation 35: 36: 37: 38: Seetablebelow Seetablebelow Seetablebelow Seetablebelow Flashdeviceinterfacecodeassignment: "n"suchthatn+1specifiesthebitfieldthatrepresentstheflash devicewidthcapabilitiesasdescribedinthetable: Numberoferaseblockregions(x)withindevice: 1.x=0meansnoeraseblocking;thedeviceerasesinbulk 2.xspecifiesthenumberofdeviceregionswithoneor morecontiguoussame-sizeeraseblocks. 3.Symmetricallyblockedpartitionshaveoneblockingregion Address 64Mbit 128Mbit 256 Mbit

28F640L30,28F128L30,28F256L30 Datasheet 87 C.5 Intel-Specific ExtendedQueryTable Table24.PrimaryVendor-SpecificExtendedQuery Offset(1) Length Description Hex P=10Ah (Optional flashfeaturesandcommands) Add. Code Value (P+0)h 3 Primary extendedquerytable 10A --50 "P" (P+1)h Unique ASCIIstring“PRI“ 10B: --52 "R" (P+3)h 1 Major versionnumber,ASCII 10D: --31 "1" (P+4)h 1 Minor versionnumber,ASCII 10E: --33 "3" (P+5)h 4 Optional featureandcommandsupport(1=yes,0=no) 10F: --E6 (P+6)h bits10–31arereserved;undefinedbitsare“0.”Ifbit31is 110: --03 (P+7)h “1”thenanother31bitfieldofOptionalfeaturesfollowsat 111: --00 (P+8)h theendofthebit–30field. 112: --00 bit0Chiperasesupported bit 0=0N o bit1Suspenderasesupported bit 1=1Y e s bit2Suspendprogramsupported bit 2=1Y e s bit3Legacylock/unlocksupported bit 3=0N o bit4Queuederasesupported bit 4=0N o bit5Instantindividualblocklockingsupported bit 5=1Y e s bit6Protectionbitssupported bit 6=1Y e s bit7Pagemodereadsupported bit 7=1Y e s bit8Synchronousreadsupported bit 8=1Y e s bit9Simultaneousoperationssupported bit 9=1Y e s (P+9)h 1 113: --01 bit0Programsupportedaftererasesuspend bit 0=1Y e s (P+A)h 2B l o c k statusregistermask 114: --03 (P+B)h bits2–15areReserved;undefinedbitsare“0” 115: --00 bit0BlockLock-BitStatusregisteractive bit0=1Y e s bit1BlockLock-DownBitStatusactive bit1=1Y e s Supportedfunctionsaftersuspend:readArray,Status,Query Othersupportedoperationsare: bits1–7reserved;undefinedbitsare“0” VCClogicsupplyhighestperformanceprogram/erasevoltage bits0–3BCDvaluein100mV bits4–7BCDvalueinvolts VPPoptimumprogram/erasesupplyvoltage bits0–3BCDvaluein100mV bits4–7HEXvalueinvolts

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Table25.ProtectionRegisterInformation Table26.BurstReadInformation Offset(1) Length Description Hex P=10Ah (Optional flashfeaturesandcommands) Add. Code Value (P+F)h 4 Protection Field1:ProtectionDescription 119: --80 80h (P+10)h This fielddescribesuser-availableOneTimeProgrammable 11A: --00 00h (P+11)h (OTP)Protectionregisterbytes.Somearepre-programmed 11B: --03 8 byte (P+12)h 11C: --03 8 byte (P+13)h 10 Protection Field2:ProtectionDescription 11D: --89 89h (P+18)h bits40–47=“n”∴ n=factorypgm'dgroups(highbyte) 122: --00 0 bits48–55=“n”\\2n=factoryprogrammablebytes/group bits56–63=“n”∴ n=userpgm'dgroups(lowbyte) bits64–71=“n”∴ n=userpgm'dgroups(highbyte) bits72–79=“n”∴ 2n=userprogrammablebytes/group withdevice-uniqueserialnumbers.Othersareuser programmable.Bits0–15pointtotheProtectionregisterLock byte,thesection’sfirstbyte.Thefollowingbytesarefactory pre-programmedanduser-programmable. bits0–7=Lock/bytesJedec-planephysicallowaddress bits8–15=Lock/bytesJedec-planephysicalhighaddress bits16–23=“n”suchthat2n=factorypre-programmedbytes bits24–31=“n”suchthat2n=userprogrammablebytes Bits0–31pointtotheProtectionregisterphysicalLock-word addressintheJedec-plane. Followingbytesarefactoryoruser-programmable. bits32–39=“n”∴ n=factorypgm'dgroups(lowbyte) NumberofProtectionregisterfieldsinJEDECIDspace. “00h,”indicatesthat256protectionfieldsareavailable Offset(1) Length Description Hex P=10Ah (Optional flashfeaturesandcommands) Add. Code Value (P+1D)h 1 127: --03 8 byte (P+20)h 1 Synchronous modereadcapabilityconfiguration2 12A: --02 8 (P+21)h 1 Synchronous modereadcapabilityconfiguration3 12B: --03 16 (P+22)h 1 Synchronous modereadcapabilityconfiguration4 12C: --07 Cont PageModeReadcapability bits0–7=“n”suchthat2nHEXvaluerepresentsthenumberof read-pagebytes.Seeoffset28hfordevicewordwidthto determinepage-modedataoutputwidth.00hindicatesno readpagebuffer. Numberofsynchronousmodereadconfigurationfieldsthat follow.00hindicatesnoburstcapability. Synchronousmodereadcapabilityconfiguration1 Bits3–7=Reserved bits0–2“n”suchthat2n+1HEXvaluerepresentsthe maximumnumberofcontinuoussynchronousreadswhen thedeviceisconfiguredforitsmaximumwordwidth.Avalue of07hindicatesthatthedeviceiscapableofcontinuous linearburststhatwilloutputdatauntiltheinternalburst counterreachestheendofthedevice’sburstableaddress space.Thisfield’s3-bitvaluecanbewrittendirectlytothe ReadConfigurationRegisterbits0–2ifthedeviceis configuredforitsmaximumwordwidth.Seeoffset28hfor wordwidthtodeterminetheburstdataoutputwidth.

28F640L30,28F128L30,28F256L30 Datasheet 89 Table27.PartitionandErase-blockRegionInformation Offset(1) Seetablebelow P=10Ah Description Address Bottom Top (Optionalflashfeaturesandcommands) Len Bot Top (P+23)h (P+23)h 1 12D: 12D:Numberofdevicehardware-partitionregionswithinthedevice. x=0:asinglehardwarepartitiondevice(nofieldsfollow). xspecifiesthenumberofdevicepartitionregionscontaining oneormorecontiguouseraseblockregions.

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PartitionRegion1Information Offset(1) Seetablebelow P=10Ah Description Address Bottom Top (Optionalflashfeaturesandcommands) Len Bot Top (P+24)h (P+24)h Numberofidenticalpartitionswithinthepartitionregion 2 12E: 12E: (P+2A)h (P+2A)h PartitionRegion1EraseBlockType1Information 4 134: 134: (P+2B)h (P+2B)h bits 0–15=y,y+1=numberofidentical-sizeeraseblocks 135: 135: (P+2C)h (P+2C)h bits 16–31=z,regioneraseblock(s)sizearezx256bytes 136: 136: (P+2E)h (P+2E)h Partition1(EraseBlockType1) 21 3 8 : 1 3 8 : (P+2F)h (P+2F)h Minimumblockerasecyclesx1000 139: 139: (P+32)h Partition Region1EraseBlockType2Information 4 13C: (P+33)h bits 0–15=y,y+1=numberofidentical-sizeeraseblocks 13D: (P+34)h bits 16–31=z,regioneraseblock(s)sizearezx256bytes 13E: (P+35)h (bottom parameterdeviceonly) 13F: (P+36)h Partition 1(EraseblockType2) 2 140: (P+37)h Minimumblockerasecyclesx1000 141: (P+38)h 11 4 2 : (P+39)h 11 4 3 : Partition1(eraseblockType1)bitspercell;internalECC bits0–3=bitspercellineraseregion bit4=reservedfor“internalECCused”(1=yes,0=no) bits5–7=reserveforfutureuse Partition1(eraseblockType1)pagemodeandsynchronous modecapabilitiesdefinedinTable10. bit0=page-modehostreadspermitted(1=yes,0=no) bit1=synchronoushostreadspermitted(1=yes,0=no) bit2=synchronoushostwritespermitted(1=yes,0=no) bits3–7=reservedforfutureuse Partition1(EraseblockType2)bitspercell bits0–3=bitspercellineraseregion bit4=reservedfor“internalECCused”(1=yes,0=no) bits5–7=reserveforfutureuse Partition1(EraseblockType2)pagemodeandsynchronous modecapabilitiesdefinedinTable10 bit0=page-modehostreadspermitted(1=yes,0=no) bit1=synchronoushostreadspermitted(1=yes,0=no) bit2=synchronoushostwritespermitted(1=yes,0=no) bits3–7=reservedforfutureuse Numberofprogramoreraseoperationsallowedinapartition bits0–3=numberofsimultaneousProgramoperations bits4–7=numberofsimultaneousEraseoperations Simultaneousprogramoreraseoperationsallowedinother partitionswhileapartitioninthisregionisinProgrammode bits0–3=numberofsimultaneousProgramoperations bits4–7=numberofsimultaneousEraseoperations Simultaneousprogramoreraseoperationsallowedinother partitionswhileapartitioninthisregionisinErasemode bits0–3=numberofsimultaneousProgramoperations bits4–7=numberofsimultaneousEraseoperations TypesoferaseblockregionsinthisPartitionRegion. x=0=noeraseblocking;thePartitionRegionerasesinbulk x=numberoferaseblockregionsw/contiguoussame-size eraseblocks.Symmetricallyblockedpartitionshaveone blockingregion.Partitionsize=(Type1blocks)x(Type1 blocksizes)+(Type2blocks)x(Type2blocksizes)+…+ (Typenblocks)x(Typenblocksizes)

28F640L30,28F128L30,28F256L30 Datasheet 91 PartitionRegion2Information Offset(1) Seetablebelow P=10Ah Description Address Bottom Top (Optionalflashfeaturesandcommands) Len Bot Top (P+3A)h (P+32)h Numberofidenticalpartitionswithinthepartitionregion 2 144: 13C: (P+40)h (P+38)h PartitionRegion2EraseBlockType1Information 4 14A: 142: (P+41)h (P+39)h bits 0–15=y,y+1=numberofidentical-sizeeraseblocks 14B: 143: (P+42)h (P+3A)h bits 16–31=z,regioneraseblock(s)sizearezx256bytes 14C: 144: (P+44)h (P+3C)h Partition2(EraseblockType1) 2 14E: 146: (P+45)h (P+3D)h Minimumblockerasecyclesx1000 14F: 147: (P+40)h PartitionRegion2EraseBlockType2Information 4 14A: (P+41)h bits0–15=y,y+1=numberofidentical-sizeeraseblocks 14B: (P+42)h bits16–31=z,regioneraseblock(s)sizearezx256bytes 14C: (P+43)h 14D: (P+44)h Partition2(EraseblockType2) 21 4 E : (P+45)h Minimumblockerasecyclesx1000 14F: (P+46)h 1 150: (P+47)h 1 151: Partition2(EraseblockType1)bitspercell bits0–3=bitspercellineraseregion bit4=reservedfor“internalECCused”(1=yes,0=no) bits5–7=reserveforfutureuse Partition2(eraseblockType1)pagemodeandsynchronous modecapabilitiesasdefinedinTable10. bit0=page-modehostreadspermitted(1=yes,0=no) bit1=synchronoushostreadspermitted(1=yes,0=no) bit2=synchronoushostwritespermitted(1=yes,0=no) bits3–7=reservedforfutureuse Partition2(EraseblockType2)bitspercell bits0–3=bitspercellineraseregion bit4=reservedfor“internalECCused”(1=yes,0=no) bits5–7=reserveforfutureuse Partition2(eraseblockType2)pagemodeandsynchronous modecapabilitiesasdefinedinTable10. bit0=page-modehostreadspermitted(1=yes,0=no) bit1=synchronoushostreadspermitted(1=yes,0=no) bit2=synchronoushostwritespermitted(1=yes,0=no) bits3–7=reservedforfutureuse Numberofprogramoreraseoperationsallowedinapartition bits0–3=numberofsimultaneousProgramoperations bits4–7=numberofsimultaneousEraseoperations Simultaneousprogramoreraseoperationsallowedinother partitionswhileapartitioninthisregionisinProgrammode bits0–3=numberofsimultaneousProgramoperations bits4–7=numberofsimultaneousEraseoperations Simultaneousprogramoreraseoperationsallowedinother partitionswhileapartitioninthisregionisinErasemode bits0–3=numberofsimultaneousProgramoperations bits4–7=numberofsimultaneousEraseoperations TypesoferaseblockregionsinthisPartitionRegion. x=0=noeraseblocking;thePartitionRegionerasesinbulk x=numberoferaseblockregionsw/contiguoussame-size eraseblocks.Symmetricallyblockedpartitionshaveone blockingregion.Partitionsize=(Type1blocks)x(Type1 blocksizes)+(Type2blocks)x(Type2blocksizes)+…+ (Typenblocks)x(Typenblocksizes)

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PartitionandErase-blockRegionInformation Address 64 Mbit 128Mbit 256 Mbit

28F640L30,28F128L30,28F256L30 Datasheet 93 AppendixDMechanicalInformation Figure39.MechanicalSpecificationforthe64-and128-Mbit;56-BallVFBGAPackage DrawingandDimensions E Seating Plane TopView-BallSideDown BottomView-BallSideUp Y A D A1Index Mark e b A1Index Mark A B C D E F G 87654321 8765432 1 A B C D E F G Note:Drawingnottoscale SideView Millimeters Inches Dimensions Symbol Min Nom Max Notes Min Nom Max PackageHeight A 1.000 0.0394 BallHeight A1 0.150 0.0059 PackageBodyThickness A2 0.665 0.0262 Pitch e 0.750 0.0295 Ball(Lead)Count N 56 56 SeatingPlaneCoplanarity Y 0.100 0.0039

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Figure40.MechanicalSpecificationforthe256-Mbit;79-BallVFBGAPackageDrawingand Dimensions DimensionsTable SideView TopView-BallSideDown BottomView-BallSideUp A2 A Seating Plane Y A1Index Mark E b A1Index Mark e D A B C D E F G 45673 2 18910111213 A B C D E F G 45673218 9 1011 1213 Drawingnottoscale Millimeters Inches Dimensions Symbol Min Nom Max Notes Min Nom Max PackageHeight A 1.000 0.0394 BallHeight A1 0.150 0.0059 PackageBodyThickness A2 0.665 0.0262 Pitch e 0.750 0.0295 Ball(Lead)CountN 7 9 7 9 SeatingPlaneCoplanarity Y 0.100 0.0039

28F640L30,28F128L30,28F256L30 Datasheet 95 Figure41.MechanicalSpecificationforthe128-Mbitdeviceinan88-ball(80-activeball)Intel® StackedChipScalePackageDrawingandDimensions Millimeters Inches Dimensions Symbol Min Nom Max Notes Min Nom Max PackageHeight A 1.200 0.0472 BallHeight A1 0.200 0.0079 PackageBodyThickness A2 0.860 0.0339 Pitche 0 . 8 0 0 0 . 0 3 1 5 Ball(Lead)CountN 8 8 8 8 SeatingPlaneCoplanarity Y 0.100 0.0039 TopView-BallDown BottomView-Ball Up A D E Y Drawingnottoscale. A C B E D G F J H K L M e 12345678 b A C B E D G F J H K L M A1Index Mark 12345678 8x10x1.2Q

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Figure42.MechanicalSpecificationforthe256-Mbitdeviceinan88-ball(80-activeball)Intel® Ultra-ThinStackedChipScalePackageDrawingandDimensions Millimeters Inches Dimensions Symbol Min Nom Max Notes Min Nom Max PackageHeight A 1.00 0.0394 BallHeight A1 0.117 0.0046 PackageBodyThickness A2 0.740 0.0291 Pitch e 0.80 0.0315 Ball(Lead)Count N 88 88 SeatingPlaneCoplanarity Y 0.100 0.0039 TopView-BallDown BottomView-BallUp A D E Y Drawingnottoscale. A C B E D G F J H K L M e 12345678 b A C B E D G F J H K L M A1Index Mark 12345678 UT8x11x1.0Q Note:DimensionsA1,A2,andbarepreliminary

28F640L30,28F128L30,28F256L30 Datasheet 97 AppendixEAdditionalInformation Order/Document Number Document/Tool 251903 1.8 VoltIntelStrataFlash®WirelessMemoryDatasheetwith3-VoltI/O 290701 1.8 VoltIntel®WirelessFlashMemoryDatasheet 290702 1.8 VoltIntel®WirelessFlashMemorywith3VoltI/ODatasheet 290737 3 VoltSynchronousIntelStrataFlash®MemoryDatasheet 251908 MigrationGuidefor1.8VoltIntel®WirelessFlashMemory(W18/W30)to1.8VoltIntel StrataFlash®WirelessMemory(L18/L30),ApplicationNote753 251909 MigrationGuidefor3VoltSynchronousIntelStrataFlash®Memory(K3/K18)to1.8Volt IntelStrataFlash®WirelessMemory(L18/L30),ApplicationNote754

298161 Intel ®FlashMemoryChipScalePackageUser’sGuide

297833 Intel ®FlashDataIntegrator(FDI)User’sGuide

298136 Intel ®PersistentStorageManagerUserGuide

NOTES: 1.PleasecalltheIntelLiteratureCenterat(800)548-4725torequestInteldocumentation.International customersshouldcontacttheirlocalIntelordistributionsalesoffice. 2.VisitIntel’sWorldWideWebhomepageathttp://www.intel.comfortechnicaldocumentationandtools. 3.ForthemostcurrentinformationonIntelStrataFlash®memory,visitourwebsiteathttp:// developer.intel.com/design/flash/isf.

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AppendixFOrderingInformationforVFBGAPackage F 6 4 3 0 T 88E 2G 0 L 5 ProductLineDesignator forallIntel®Flashproducts PackageDesignator ExtendedTemperature (-25Cto+85C) GE=0.75mmVFBGA T=TopParameterBlocking B=BottomParameterBlocking DeviceDensity 640=x16(64-Mbit) 128=x16(128-Mbit) 256=x16(256-Mbit) ProductFamily L30=1.8VoltIntelStrataflash ® wirelessmemorywith3.0-VoltI/O VCC=1.7V-2.0V VCCQ=2.2V-3.3V AccessSpeed(ns) 85,110

28F640L30,28F128L30,28F256L30 Datasheet 99 AppendixGOrderingInformationforS-CSPPackage Figure43showsthedecoderforthe1.8VoltIntelStrataFlash®wirelessmemoryinQuad+ballout products. Figure43.Decoderfor1.8VoltIntelStrataFlash®WirelessMemory(L30)inQuad+Ballout Table28.ValidCombinationsforS-CSPPackage I/O 128-Mbit 256-Mbit 3.0VI/O RD48F3000L0ZTQ0 NZ48F4000L0ZTQ0 RD48F3000L0ZBQ0 NZ48F4000L0ZBQ0 B=BottomParameter T=TopParameter F 3 0 L 0 Y B Q8D 4R Package PinoutIndicator FlashDensity Voltage ProductFamily RD=Intel®StackedChipScale Package NZ=Intel®Ultra-ThinStackedChip ScalePackage 0=Nodie 3=128-Mbit 4=256-Mbit L=1.8VoltIntelStrataFlash®WirelessFlashMemory 0=NoDie Y=1.8VoltCoreandI/O Z=3VoltI/O,1.8VoltCore Q=Quad+ballout 0 0 0 ParameterLocation DeviceDetails 0=Originalversionofthe products(refertothelatest versionofthedatasheetfor details). Flash#1 Flash#3 Flash#4 Flash#2 FlashFamily1/2 FlashFamily3/4 ProductLineDesignator 48F=FlashMemoryOnly

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