28F008C3 INTEL | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1.0 INTRODUCTION
- 1.2 Product Overview
- 2.0 PRODUCT DESCRIPTION
- 2.1 Package Pinouts
- 2.2 Block Organization
- 2.2.1 Parameter Blocks
- 2.2.2 Main Blocks
- 3.0 PRINCIPLES OF OPERATION
- 3.1 Bus Operation
- 3.1.1 Read
- 3.1.2 Output Disable
- 3.1.3 Standby
- 3.1.4 Reset
- 3.1.5 Write
- 3.2 Modes of Operation
- 3.2.1 Read Array
- 3.2.2 Read Configuration
- 3.2.3 Read Status Register
- 3.2.3.1 Clearing the Status Register
- 3.2.4 Read Query
- 3.2.5 Program Mode
- 3.2.5.1 Suspending and Resuming
- 3.2.6 Erase Mode
- 3.3 Flexible Block Locking
- 3.3.1 Locking Operation
- 3.3.2 Locked State
- 3.3.3 Unlocked State
- 3.3.4 Lock-Down State
- 3.3.5 Reading a Block’s Lock Status
- 3.3.6 Locking Operations during Erase
- 3.3.7 Status Register Error Checking
- 3.4.1 Reading the Protection Register
- 3.4.3 Locking the Protection Register
- 3.5.1 Easy-12 V Operation for Fast
- 3.5.2 VPP ≤ VPPLK for Complete Protection
- 3.5.3 VPP Usage
- 3.6 Power Consumption
- 3.6.1 Active Power (Program/Erase/Read)
- 3.6.2 Automatic Power Savings (APS)
- 3.6.3 Standby Power
- 3.6.4 Deep Power-Down Mode
- 3.7 Power-Up/Down Operation
- 3.7.1 RP# Connected to System Reset
- 3.8 Power Supply Decoupling
- 4.0 ABSOLUTE MAXIMUM RATINGS
- 4.2 Operating Conditions
- 4.3 Capacitance
- 4.4 DC Characteristics
- 4.5 AC Characteristics—Read Operations—
- 4.6 AC Characteristics—Write Operations—
- 4.7 Erase and Program Timings
- 4.8 Reset Operations
- 5.0 ORDERING INFORMATION
- 6.0 ADDITIONAL INFORMATION
E PRODUCT PREVIEW Ma y 1998 Order Number: 290645-001 /c110 Flexible SmartVoltage Technology 2.7 V–3.6 V Read/Program/Erase 2.7 V or 1.65 V I/O Option Reduces Overall System Power 12 V for Fast Production Programming /c110 High Performance 2.7 V–3.6 V: 90 ns Max Access Time 3.0 V–3.6 V: 80 ns Max Access Time /c110 Optimized Architecture for Code Plus Data Storage Eight 8-Kbyte Blocks, Top or Bottom Locations Up to Sixty-Three 64-KB Blocks Fast Program Suspend Capability Fast Erase Suspend Capability /c110 Flexible Block Locking Lock/Unlock Any Block Full Protection on Power-Up WP# Pin for Hardware Block Protection VPP = GND Option VCC Lockout Voltage /c110 Low Power Consumption 9 mA Typical Read Power 10 µA Typical Standby Power with Automatic Power Savings Feature /c110 Extended Temperature Operation –40 °C to +85 °C /c110 Easy-12 V Faster Production Programming No Additional System Logic /c110 128-bit Protection Register 64-bit Unique Device Identifier 64-bit User Programmable OTP Cells /c110 Extended Cycling Capability Minimum 100,000 Block Erase Cycles /c110 Flash Data Integrator Software Flash Memory Manager System Interrupt Manager Supports Parameter Storage, Streaming Data (e.g., voice) /c110 Automated Word/Byte Program and Block Erase Command User Interface Status Registers /c110 SRAM-Compatible Write Interface /c110 Cross-Compatible Command Support Intel Basic Command Set Common Flash Interface /c110 x 16 for High Performance 48-Ball µBGA* Package 48-Lead TSOP Package /c110 x 8 I/O for Space Savings 48-Ball µBGA* Package 40-Lead TSOP Package /c110 0.25 µ ETOX™ VI Flash Technology The 0.25 µm 3 Volt Advanced+ Boot Block, manufactured on Intel’s latest 0.25 µ technology, represents a feature-rich solution at overall lower system cost. Smart 3 flash memory devices incorporate low voltage capability (2.7 V read, program and erase) with high-speed, low-power operation. Flexible block locking allows any block to be independently locked or unlocked. Add to this the Intel-developed Flash Data Integrator (FDI) software and you have a cost-effective, flexible, monolithic code plus data storage solution on the market today. 3 Volt Advanced+ Boot Block products will be available in 48-lead TSOP, 40-lead TSOP, and 48-ball µBGA* packages. Additional information on this product family can be obtained by accessing Intel’s WWW page: http://www.intel.com/design/flcomp.
3 VOLT ADVANCED+ BOOT BLOCK
8-, 16-, 32-MBIT FLASH MEMORY FAMILY 28F008C3, 28F016C3, 28F032C3 28F800C3, 28F160C3, 28F320C3
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 28F008C3, 28F016C3, 28F032C3, 28F800C3, 28F160C3, 28F320C3 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 5937 Denver, CO 80217-9808 or call 1-800-548-4725 or visit Intel’s website at http:\\\\www.intel.com COPYRIGHT © INTEL CORPORATION 1998 CG-041493 *Third-party brands and names are the property of their respective owners.
3 VOLT ADVANCED+ BOOT BLOCK E
4 PRODUCT PREVIEW
APPENDIX E: Word-Wide Memory Map APPENDIX F: Byte-Wide Memory Map APPENDIX H: Protection Register
REVISION HISTORY
05/12/98 -001 Original version
1.0 INTRODUCTION
3 Volt Advanced+ Boot Block flash memory family. block locking and a protection register. Section 4 contains the operating specifications.
- Zero-latency, flexible block locking
- 128-bit Protection Register
- Simple system implementation for 12 V production programming with 2.7 V in-field programming
- Ultra-low power operation at 2.7 V
- Minimum 100,000 block erase cycles
- Common Flash Interface for software query of device specs and features
Table 1. 3 Volt Advanced+ Boot Block Feature Summary
8 M(2)
32 M(1)
- 32-Mbit density not available in 40-lead TSOP.
- 8-Mbit density not available in µBGA* CSP.
CCQ operation at 1.65 V — 2.5 V available upon request.
6 PRODUCT PREVIEW
1.2 Product Overview
Intel provides secure low voltage memory solutions with the Advanced Boot Block family of products. A new block locking feature allows instant locking/unlocking of any block with zero-latency. A 128-bit protection register allows unique flash device identification. Discrete supply pins provide single voltage read, program, and erase capability at 2.7 V while also allowing 12 V V PP for faster production programming. Easy-12 V, a new feature designed to reduce external logic, simplifies board designs when combining 12 V production programming with 2.7 V in-field programming. The 3 Volt Advanced+ Boot Block flash memory products are available in either x8 or x16 packages in the following densities: (see Section 6, Ordering Information)
- 8-Mbit (8,388,608 bit) flash memories organized as either 512 Kwords of 16 bits each or 1024 Kbytes or 8 bits each.
- 16-Mbit (16,777,216 bit) flash memories organized as either 1024 Kwords of 16 bits each or 2048 Kbytes of 8 bits each.
- 32-Mbit (33,554,432 bit) flash memories organized as either 2048 Kwords of 16 bits each or 4096 Kbytes of 8 bits each. Eight 8-KB parameter blocks are located at either the top (denoted by -T suffix) or the bottom (-B suffix) of the address map in order to accommodate different microprocessor protocols for kernel code location. The remaining memory is grouped into 64- Kbyte main blocks. All blocks can be locked or unlocked instantly to provide complete protection for code or data. (see Section 3.3 for details). The Command User Interface (CUI) serves as the interface between the microprocessor or microcontroller and the internal operation of the flash memory. The internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for program and erase operations, including verification, thereby unburdening the microprocessor or microcontroller. The status register indicates the status of the WSM by signifying block erase or word program completion and status. Program and erase automation allows program and erase operations to be executed using an industry- standard two-write command sequence to the CUI. Program operations are performed in word or byte increments. Erase operations erase all locations within a block simultaneously. Both program and erase operations can be suspended by the system software in order to read from any other block. In addition, data can be programmed to another block during an erase suspend. The 3 Volt Advanced+ Boot Block flash memories offer two low power savings features: Automatic Power Savings (APS) and standby mode. The device automatically enters APS mode following the completion of a read cycle. Standby mode is initiated when the system deselects the device by driving CE# inactive. Combined, these two power savings features significantly reduce power consumption. The device can be reset by lowering RP# to GND. This provides CPU-memory reset synchronization and additional protection against bus noise that may occur during system reset and power-up/down sequences (see Section 3.5 and 3.6). Refer to the DC Characteristics Section 4.4 for complete current and voltage specifications. Refer to the AC Characteristics Sections 4.5 and 4.6, for read and write performance specifications. Program and erase times and shown in Section 4.7.
2.0 PRODUCT DESCRIPTION
This section provides device pin descriptions and package pinouts for the 3 Volt Advanced+ Boot Block flash memory family, which is available in 40- Lead TSOP (x8, Figure 1), 48-lead TSOP (x16, Figure 2) and 48-ball µBGA packages (Figures 3 and 4).
2.1 Package Pinouts
In each diagram, upgrade pins from one density to the next are circled.
8 PRODUCT PREVIEW
- Shaded connections indicate the upgrade address connections. Lower density devices will not have the upper address
upgrade address for the 32-Mbit device.
- 8-Mbit not available on µBGA* CSP.
**Figure 3. x16 48-Ball µBGA* Chip Size Package (Top View, Ball Down)**
- Shaded connections indicate the upgrade address connections. Lower density devices will not have the upper address
upgrade address for the 32-Mbit device.
- 8-Mbit not available on µBGA* CSP.
**Figure 4. x8 48-Ball µBGA* Chip Size Package (Top View, Ball Down)**
Table 2. 3 Volt Advanced+ Boot Block Pin Descriptions latched during a program or erase cycle. internally latched. Outputs array, configuration and status register data. WE# cycle during a Program command. Data is internally latched. the chip is de-selected. Not included on x8 products. the memory device and reduces power consumption to standby levels. buffers during a read operation. OE# is active low. the rising edge of the second WE# pulse. control reset/deep power-down mode. Machine, and minimizes current levels (ICCD ). When RP# is at logic high, the device is in standard operation. blocks to locked and defaults to the read array mode. blocks marked lock-down cannot be unlocked through software. marked lock-down revert to that state. See Section 3.3 for details on block locking.
10 PRODUCT PREVIEW
Table 2. 3 Volt Advanced+ Boot Block Pin Descriptions (Continued) VCCQ INPUT I/O POWER SUPPLY: Supplies power for input/output buffers. [2.7 V–3.6 V] This input should be tied directly to VCC . [1.65 V– 2.5 V] Lower I/O power supply voltage available upon request. Contact your Intel representative for more information. Operates as a input at logic levels to control complete device protection. 5% range. This pin cannot be left floating. maximum. See Section 3.4 for details on VPP voltage configurations. NC NO CONNECT: Pin may be driven or left floating.
2.2 Block Organization
independently of the others up to 100,000 times. memory maps in Appendix E and F.
2.2.1 PARAMETER BLOCKS
2.2.2 MAIN BLOCKS
3.0 PRINCIPLES OF OPERATION
requests during WSM operation.
3.1 Bus Operation
3.1.1 READ
defaults to read array mode. when active it enables the flash memory device.
3.1.2 OUTPUT DISABLE
3.1.3 STANDBY
program or erase operation is complete. Table 3. Bus Operations
- 8-bit devices use only DQ[0:7], 16-bit devices use DQ[0:15]
IL, VIH for control pins and addresses.
- See DC Characteristics for VPPLK , VPP1 , VPP2 , VPP3 , voltages.
- Manufacturer and device codes may also be accessed in read configuration mode (A1–A20 = 0). See Table 4.
- Refer to Table 5 for valid DIN during a write operation.
- To program or erase the lockable blocks, hold WP# at VIH.
- RP# must be at GND ± 0.2 V to meet the maximum deep power-down current specified.
12 PRODUCT PREVIEW
3.1.4 RESET
From read mode, RP# at V IL for time tPLPH deselects the memory, places output drivers in a high-impedance state, and turns off all internal circuits. After return from reset, a time tPHQV is required until the initial read access outputs are valid. A delay (t PHWL or tPHEL ) is required after return from reset before a write can be initiated. After this wake -up interval, normal operation is restored. The CUI resets to read array mode, and the status register is set to 80H. This case is shown in Figure 11A. If RP# is taken low for time t PLPH during a program or erase operation, the operation will be aborted and the memory contents at the aborted location (for a program) or block (for an erase) are no longer valid, since the data may be partially erased or written. The abort process goes through the following sequence: When RP# goes low, the device shuts down the operation in progress, a process which takes time t PLRH to complete. After this time tPLRH , the part will either reset to read array mode (if RP# has gone high during tPLRH , Figure 11B) or enter reset mode (if RP# is still logic low after t PLRH , Figure 11C). In both cases, after returning from an aborted operation, the relevant time t PHQV or tPHWL /tPHEL must be waited before a read or write operation is initiated, as discussed in the previous paragraph. However, in this case, these delays are referenced to the end of t PLRH rather than when RP# goes high. As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, processor expects to read from the flash memory. Automated flash memories provide status information when read during program or block erase operations. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. Intel’s flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU.
3.1.5 WRITE
A write takes place when both CE# and WE# are low and OE# is high. Commands are written to the Command User Interface (CUI) using standard microprocessor write timings to control flash operations. The CUI does not occupy an addressable memory location. The address and data buses are latched on the rising edge of the second WE# or CE# pulse, whichever occurs first. Figure 10 illustrates a program and erase operation. The available commands are shown in Table 6, and Appendix A provides detailed information on moving between the different modes of operation using CUI commands. There are two commands that modify array data: Program (40H) and Erase (20H). Writing either of these commands to the internal Command User Interface (CUI) initiates a sequence of internally timed functions that culminate in the completion of the requested task (unless that operation is aborted by either RP# being driven to V IL for tPLRH or an appropriate suspend command).
3.2 Modes of Operation
The flash memory has four read modes and two write modes. The read modes are read array, read configuration, read status, and read query. The write modes are program and block erase. Three additional modes (erase suspend to program, erase suspend to read and program suspend to read) are available only during suspended operations. These modes are reached using the commands summarized in Tables 5 and 6. A comprehensive chart showing the state transitions is in Appendix A.
3.2.1 READ ARRAY
When RP# transitions from V IL (reset) to VIH, the device defaults to read array mode and will respond to the read control inputs (CE#, address inputs, and OE#) without any additional CUI commands. When the device is in read array mode, four control signals control data output:
- WE# must be logic high (V IH)
- CE# must be logic low (VIL)
- OE# must be logic low (VIL)
- RP# must be logic high (VIH) In addition, the address of the desired location must be applied to the address pins. If the device is not in read array mode, as would be the case after a program or erase operation, the Read Array command (FFH) must be written to the CUI before array reads can take place.
3.2.2 READ CONFIGURATION
array mode, write the Read Array command (FFH). the block locking status, and the protection register. Table 4. Read Configuration Table
- Block Is Unlocked DQ 0 = 0
- Block Is Locked DQ 0 = 1
- Block Is Locked-Down DQ 1 = 1 Protection Register Lock3 80 PR-LK Protection Register (x16) 81-88 PR Protection Register (x8) (App. H) PR NOTES: 1. “XX” specifies the block address of lock configuration being read. 2. See Section 3.3.4 for valid lock status outputs. 3. See Section 3.4 for protection register information. 4. Other locations within the configuration address space are reserved by Intel for future use.
3.2.3 READ STATUS REGISTER
Read Status Register command. in performing the desired operation (see Table 7).
3.2.3.1 Clearing the Status Register
before data can be read from the memory array. Resetting the device also clears the status register.
3.2.4 READ QUERY
array mode, write the Read Array command (FFH).
14 PRODUCT PREVIEW
3.2.5 PROGRAM MODE
Programming is executed using a two -write sequence. The Program Setup command (40H) is written to the CUI followed by a second write which specifies the address and data to be programmed. The WSM will execute a sequence of internally timed events to program desired bits of the addressed location, then verify the bits are sufficiently programmed. Programming the memory results in specific bits within an address location being changed to a “0.” If the user attempts to program “1”s, the memory cell contents do not change and no error occurs. The status register indicates programming status: while the program sequence executes, status bit 7 is “0.” The status register can be polled by toggling either CE# or OE#. While programming, the only valid commands are Read Status Register, Program Suspend, and Program Resume. When programming is complete, the Program Status bits should be checked. If the programming operation was unsuccessful, bit SR.4 of the status register is set to indicate a program failure. If SR.3 is set then V PP was not within acceptable limits, and the WSM did not execute the program command. If SR.1 is set, a program operation was attempted on a locked block and the operation was aborted. The status register should be cleared before attempting the next operation. Any CUI instruction can follow after programming is completed; however, to prevent inadvertent status register reads, be sure to reset the CUI to read array mode.
3.2.5.1 Suspending and Resuming
The Program Suspend command halts an in progress program operation so that data can be read from other locations of memory. Once the programming process starts, writing the Program Suspend command to the CUI requests that the WSM suspend the program sequence (at predetermined points in the program algorithm). The device continues to output status register data after the Program Suspend command is written. Polling status register bits SR.7 and SR.2 will determine when the program operation has been suspended (both will be set to “1”). t WHRH1 /tEHRH1 specify the program suspend latency. A Read Array command can now be written to the CUI to read data from blocks other than that which is suspended. The only other valid commands, while program is suspended, are Read Status Register, Read Configuration, Read Query, and Program Resume. After the Program Resume command is written to the flash memory, the WSM will continue with the programming process and status register bits SR.2 and SR.7 will automatically be cleared. The device automatically outputs status register data when read (see Figure 13 in Appendix Program Suspend/Resume Flowchart) after the Program Resume command is written. VPP must remain at the same VPP level used for program while in program suspend mode. RP# must also remain at V IH.
3.2.6 ERASE MODE
To erase a block, write the Erase Set-up and Erase Confirm commands to the CUI, along with an address identifying the block to be erased. This address is latched internally when the Erase Confirm command is issued. Block erasure results in all bits within the block being set to “1.” Only one block can be erased at a time. The WSM will execute a sequence of internally timed events to program all bits within the block to “0,” erase all bits within the block to “1,” then verify that all bits within the block are sufficiently erased. While the erase executes, status bit 7 is a “0.” When the status register indicates that erasure is complete, check the erase status bit to verify that the erase operation was successful. If the Erase operation was unsuccessful, SR.5 of the status register will be set to a “1,” indicating an erase failure. If V PP was not within acceptable limits after the Erase Confirm command was issued, the WSM will not execute the erase sequence; instead, SR.5 of the status register is set to indicate an erase error, and SR.3 is set to a “1” to identify that V PP supply voltage was not within acceptable limits. After an erase operation, clear the status register (50H) before attempting the next operation. Any CUI instruction can follow after erasure is completed; however, to prevent inadvertent status register reads, it is advisable to place the flash in read array mode after the erase is complete.
3.2.6.1 Suspending and Resuming Erase
VIH. This reduces active current consumption. cleared before the next instruction is issued. Table 5. Command Bus Definitions X = Don’t Care PA = Prog Addr BA = Block Addr IA = Identifier Addr. QA = Query Addr.
- Bus operations are defined in Table 3.
- Following the Read Configuration or Read Query commands, read operations output device configuration or CFI query
- Either 40H or 10H command is valid, but the Intel standard is 40H.
- When writing commands, the upper data bus [DQ
8–DQ 15] should be either VIL or VIH, to minimize current draw.
16 PRODUCT PREVIEW
Table 6. Command Codes and Descriptions
40 Program
after programming to read array data. See Section 3.2.5.
20 Erase
and (c) wait for another command. See Section 3.2.6. output status register data when CE# or OE# is toggled.
70 Read Status
program or erase operation has been initiated. See Section 3.2.3.
50 Clear Status
90 Read
will output the manufacturer/device codes or block lock status. Section 3.2.2.
60 Configuration
indicate a command sequence error. See Section 3.3.
01 Lock-Block If the previous command was Configuration Set-Up, the CUI will latch the
Table 6. Command Codes and Descriptions (Continued) latch the address and lock-down the block indicated on the address pins.
98 Read
output Common Flash Interface information. See Section 3.2.4 and Appendix C. to read array data. See Section 3.4.
00 Invalid/
redefine these codes for future functions. See Appendix A for mode transition information.
18 PRODUCT PREVIEW
Table 7. Status Register Bit Definition Program or Erase Status bits. When this bit is set to “1,” WSM has applied the max. verify successful block erasure. out when polling the status register.
E 3 VOLT ADVANCED+ BOOT BLOCK 19PRODUCT PREVIEW
3.3 Flexible Block Locking
3 Volt Advanced+ Boot Block products
offer an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. This locking scheme offers two levels of protection. The first level allows software-only control of block locking (useful for data blocks that change frequently), while the second level requires hardware interaction before locking can be changed (useful for code blocks that change infrequently). The following sections will discuss the operation of the locking system. The term “state [XYZ]” will be used to specify locking states; e.g., “state [001],” where X = value of WP#, Y = bit DQ 1 of the Block Lock status register, and Z = bit DQ0 of the Block Lock status register. Table 9 defines all of these possible locking states.
3.3.1 LOCKING OPERATION
The following concisely summarizes the locking functionality.
- All blocks power-up locked, then can be unlocked or locked with the Unlock and Lock commands.
- The Lock-Down command lo cks a block and prevents it from being unlocked when WP# = 0. When WP# = 1, Lock-Down is overridden and commands can unlock/lock locked- down blocks. When WP# returns to 0, locked-down blocks return to Lock-Down. Lock-Down is cleared only when the device is reset or powered-down. The locking status of each block can set to Locked, Unlocked, and Lock-Down, each of which will be described in the following sections. A comprehensive state table for the locking functions is shown in Table 9, and a flowchart for locking operations is shown in Figure 16.
3.3.2 LOCKED STATE
The default status of all blocks upon power-up or reset is locked (states [001] or [101]). Locked blocks are fully protected from alteration. Any program or erase operations attempted on a locked block will return an error on bit SR.1 of the status register. The status of a locked block can be changed to Unlocked or Lock-Down using the appropriate software commands. An Unlocked block can be locked by writing the Lock command sequence, 60H followed by 01H.
3.3.3 UNLOCKED STATE
Unlocked blocks (states [000], [100], [110]) can be programmed or erased. All unlocked blocks return to the Locked state when the device is reset or powered down. The status of an unlocked block can be changed to Locked or Locked-Down using the appropriate software commands. A Locked block can be unlocked by writing the Unlock command sequence, 60H followed by D0H.
3.3.4 LOCK-DOWN STATE
Blocks that are Locked-Down (state [011]) are protected from program and erase operations (just like Locked blocks), but their protection status cannot be changed using software commands alone. A Locked or Unlocked block can be Locked- down by writing the Lock-Down command sequence, 60H followed by 2FH. Locked-Down blocks revert to the Locked state when the device is reset or powered down. The Lock-Down function is dependent on the WP# input pin. When WP# = 0, blocks in Lock-Down [011] are protected from program, erase, and lock status changes. When WP# = 1, the Lock-Down function is disabled ([111]) and locked-down blocks can be individually unlocked by software command to the [110] state, where they can be erased and programmed. These blocks can then be relocked [111] and unlocked [110] as desired while WP# remains high. When WP# goes low, blocks that were previously locked-down return to the Lock-Down state [011] regardless of any changes made while WP# was high. Device reset or power- down resets all blocks, including those in Lock- Down, to Locked state.
20 PRODUCT PREVIEW
3.3.5 READING A BLOCK’S LOCK STATUS
Table 8. Block Lock Status
- Block Is Unlocked DQ 0 = 0
- Block Is Locked DQ 0 = 1
- Block Is Locked-Down DQ 1 = 1
3.3.6 LOCKING OPERATIONS DURING
3.3.7 STATUS REGISTER ERROR
ambiguity into status register results. of the previous locking command error.
Table 9. Block Locking State Transitions
- In this table, the notation [XYZ] denotes the locking state of a block, where X = WP#, Y = DQ1, and Z = DQ0. The current
a block is locked (1) or unlocked (0). DQ1 indicates if a block has been locked-down (1) or not (0).
- At power-up or device reset, all blocks default to Locked state [001] (if WP# = 0). Holding WP# = 0 is the recommended
- The “Erase/Program Allowed?” column shows whether erase and program operations are enabled (Yes) or disabled (No)
in that block’s current locking state.
- The “Lock Command Input Result [Next State]” column shows the result of writing the three locking commands (Lock,
block in the current locking state would change it to [001]. Advanced+ Boot Block Flash Memory Architecture.
3.4.1 READING THE PROTECTION
writing the Read Configuration command (90H).
3.4.2 PROGRAMMING THE PROTECTION
Register Programming Flowchart.
22 PRODUCT PREVIEW
3.4.3 LOCKING THE PROTECTION
the values stored in the protection register. bit SR.4 and Lock Error bit SR.1 will be set to 1). Protection register lockout state is not reversible.
4 Words
1 Word Lock
Figure 5. Protection Register Memory Map
3.5 V PP Program and Erase
3.5.1 EASY-12 V OPERATION FOR FAST
and erase current is drawn through the VCC pin. switching transistor to control the voltage VPP . connected to 12 V for a total of 80 hours maximum. corresponding status register bit (SR.3) to be set. protection and fast production programming.
12 V Fast Programming
12 V Supply
- A resistor can be used if the VCC supply can sink adequate current based on resistor value. See AP-657 Designing with
the Advanced+ Boot Block Flash Memory Architecture for details. Figure 6. Example Power Supply Configurations traces by the printed circuit board designer. decrease spikes and overshoots.
3.6 Power Consumption
3.6.1 ACTIVE POWER
the DC Characteristic tables for ICC current values.
3.6.2 AUTOMATIC POWER SAVINGS (APS)
until a new location is read.
3.6.3 STANDBY POWER
24 PRODUCT PREVIEW
substantially reduces power consumption. Outputs are placed in a high-impedance state independent of the status of the OE# signal. If CE# transitions to a logic -high level during erase or program operations, the device will continue to perform the operation and consume corresponding active power until the operation is completed. System engineers should analyze the breakdown of standby time versus active time and quantify the respective power consumption in each mode for their specific application. This will provide a more accurate measure of application -specific power and energy requirements.
3.6.4 DEEP POWER-DOWN MODE
The deep power-down mode is activated when RP# = VIL (GND ± 0.2 V). During read modes, RP# going low de-selects the memory and places the outputs in a high impedance state. Recovery from deep power-down requires a minimum time of t PHQV for read operations and tPHWL /tPHEL for write operations. During program or erase modes, RP# transitioning low will abort the in-progress operation. The memory contents of the address being programmed or the block being erased are no longer valid as the data integrity has been compromised by the abort. During deep power-down, all internal circuits are switched to a low power savings mode (RP# transitioning to V IL or turning off power to the device clears the status register).
3.7 Power-Up/Down Operation
The device is protected against accidental block erasure or programming during power transitions. Power supply sequencing is not required, since the device is indifferent as to which power supply, V PP or VCC , powers-up first.
3.7.1 RP# CONNECTED TO SYSTEM
The use of RP# during system reset is important with automated program/erase devices since the system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization will not occur because the flash memory may be providing status information instead of array data. Intel recommends connecting RP# to the system CPU RESET# signal to allow proper CPU/flash initialization following system reset. System designers must guard against spurious writes when V CC voltages are above VLKO . Since both WE# and CE# must be low for a command write, driving either signal to V IH will inhibit writes to the device. The CUI architecture provides additional protection since alteration of memory contents can only occur after successful completion of the two- step command sequences. The device is also disabled until RP# is brought to V IH, regardless of the state of its control inputs. By holding the device in reset (RP# connected to system PowerG ood) during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection. 3.7.2 V CC , VPP AND RP# TRANSITIONS The CUI latches commands as issued by system software and is not altered by VPP or CE# transitions or WSM actions. Its default state upon power-up, after exit from reset mode or after V CC transitions above VLKO (Lockout voltage), is read array mode. After any program or block erase operation is complete (even after VPP transitions down to VPPLK ), the CUI must be reset to read array mode via the Read Array command if access to the flash memory array is desired.
3.8 Power Supply Decoupling
Flash memory’s power switching characteristics require careful device decoupling. System designers should consider three supply current issues: 1. Standby current levels (I CCS ) 2. Read current levels (ICCR ) 3. Transient peaks produced by falling and rising edges of CE#. Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. Each flash device should have a 0.1 µF ceramic capacitor connected between each V CC and GND, and between its VPP and GND. These high- frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads.
4.0 ABSOLUTE MAXIMUM
datasheet before finalizing a design.
- Minimum DC voltage is –0.5 V on input/output pins.
- Maximum DC voltage on VPP may overshoot to +14.0 V
- Output shorted for no more than one second. No more
than one output shorted at a time.
- V PP voltage is normally 1.65 V–3.6 V. Connection to
connected to 12 V for a total of 80 hours maximum. See Section 3.5 for details.
4.2 Operating Conditions
Table 10. Temperature and Voltage Operating Conditions
- V CC and VCCQ must share the same supply when they are in the VCC1 range.
- Applying VPP = 11.4 V–12.6 V during a program/erase can only be done for a maximum of 1000 cycles on the main blocks
26 PRODUCT PREVIEW
4.3 Capacitance
TA = 25 °C, f = 1 MHz Sym Parameter Notes Typ Max Units Conditions C IN Input Capacitance 1 6 8 pF V IN = 0 V C OUT Output Capacitance 1 10 12 pF V OUT = 0 V NOTE: 1. Sampled, not 100% tested.
4.4 DC Characteristics
VCC 2.7 V–3.6 V VCCQ 2.7 V–3.6 V Sym Parameter Note Typ Max Unit Test Conditions ILI Input Load Current 1,7 ± 1 µA VCC = VCC Max VCCQ = VCCQ Max VIN = VCCQ or GND ILO Output Leakage Current 1,7 0.2 ± 10 µA VCC = VCC Max VCCQ = VCCQ Max VIN = VCCQ or GND ICCS VCC Standby Current 1 10 25 µA V CC = VCC Max CE# = RP# = VCC ICCD VCC Deep Power-Down Current 1,7 7 20 µA VCC = VCC Max VCCQ = VCC Q Max VIN = VCCQ or GND RP# = GND ± 0.2 V ICCR VCC Read Current 1,5,7 9 18 mA VCC = VCC Max VCCQ = VCCQ Max OE# = VIH , CE# = VIL f = 5 MHz, IOUT = 0 mA Inputs = VIL or VIH ICCW VCC Program Current 1,4 18 55 mA VPP = VPP1 Program in Progress 81 5 m A VPP = VPP2 (12 V) Program in Progress ICCE VCC Erase Current 1,4 16 45 mA VPP = VPP1 Erase in Progress 81 5 m A VPP = VPP2 (12 V) Erase in Progress ICCES VCC Erase Suspend Current 1,2,4 10 25 µA CE# = V IH, Erase Suspend in Progress ICCWS VCC Program Suspend Current 1,2,4 10 25 µA CE# = V IH, Program Suspend in Progress
E 3 VOLT ADVANCED+ BOOT BLOCK 27PRODUCT PREVIEW
4.4 DC Characteristics, Continued
VCC 2.7 V–3.6 V VCCQ 2.7 V–3.6 V Sym Parameter Note Typ Max Unit Test Conditions IPPD VPP Deep Power-Down Current 1 0.2 5 µA RP# = GND ± 0.2 V IPPS VPP Standby Current 1 0.2 5 µA V PP ≤ VCC IPPR VPP Read Current 1 2 ±15 µA V PP ≤ VCC 1,4 50 200 µA V PP ≥ VCC IPPW VPP Program Current 1,4 0.05 0.1 mA VPP =VPP1 Program in Progress 82 2 m A VPP = VPP2 (12 V) Program in Progress IPPE VPP Erase Current 1,4 0.05 0.1 mA VPP = VPP1 Program in Progress 82 2 m A VPP = VPP2 (12 V) Program in Progress IPPES VPP Erase Suspend Current 1,4 0.2 5 µA VPP = VPP1 Erase Suspend in Progress 50 200 µA VPP = VPP2 (12 V) Erase Suspend in Progress IPPWS VPP Program Suspend Current 1,4 0.2 5 µA VPP = VPP1 Program Suspend in Progress 50 200 µA VPP = VPP2 (12 V) Program Suspend in Progress
28 PRODUCT PREVIEW
VCC 2.7 V–3.6 V VCCQ 2.7 V–3.6 V Sym Parameter Note Min Max Unit Test Conditions VIL Input Low Voltage -0.4 0.4 V VIH Input High Voltage VCCQ - 0.4 V V VOL Output Low Voltage 7 -0.10 0.10 V V CC = VCC Min VCCQ = VCCQ Min IOL = 100 µA VOH Output High Voltage 7 V CCQ - 0.1 V V VCC = VCC Min VCCQ = VCCQ Min IOH = –100 µA VPPLK VPP Lock-Out Voltage 3 1.0 V Complete Write Protection VPP1 VPP during Program / Erase 3 1.65 3.6 V VPP2 Operations 3,6 11.4 12.6 VLKO VCC Prog/Erase Lock Voltage 1.5 V VLKO2 VCCQ Prog/Erase Lock Voltage 1.2 V NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC , TA = +25 °C. 2. ICCES and ICCWS are specified with device de-selected. If device is read while in erase suspend, current draw is sum of ICCES and ICCR . If the device is read while in program suspend, current draw is the sum of ICCWS and ICCR . 3. Erase and Program are inhibited when VPP < VPPLK and not guaranteed outside the valid VPP ranges of VPP1 and VPP2 . 4. Sampled, not 100% tested. 5. Automatic Power Savings (APS) reduces I CCR to approximately standby levels in static operation (CMOS inputs). 6. Applying VPP = 11.4 V–12.6 V during program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum. See Section 3.4 for details. 7. The test conditions VCC Max, VCCQ Max, VCC Min, and VCCQ Min refer to the maximum or minimum VCC or VCCQ voltage listed at the top of each column.
30 PRODUCT PREVIEW
4.5 AC Characteristics—Read Operations(1)—Extended Temperature
Product –90 –110 # Sym Parameter Note Min Max Min Max Min Max Min Max Unit R1 t AVAV Read Cycle Time 80 90 100 110 ns R2 t AVQV Address to Output Delay 80 90 100 110 ns R3 t ELQV CE# to Output Delay 2 80 90 100 110 ns R4 t GLQV OE# to Output Delay 2 3 03 03 03 0 n s R5 t PHQV RP# to Output Delay 150 150 150 150 ns R6 t ELQX CE# to Output in Low Z 3 0000 n s R7 t GLQX OE# to Output in Low Z 3 0000 n s R8 t EHQZ CE# to Output in High Z 3 2 02 02 02 0 n s R9 t GHQZ OE# to Output in High Z 3 2 02 02 02 0 n s R10 t OH Output Hold from Address, CE#, or OE# Change, Whichever Occurs First 3 0000 n s NOTES: 1. See AC Waveform: Read Operations. 2. OE# may be delayed up to tELQV –tGLQV after the falling edge of CE# without impact on tELQV . 3. Sampled, but not 100% tested. 4. See Test Configuration (Figure 8).
Figure 9. AC Waveform: Read Operations
32 PRODUCT PREVIEW
4.6 AC Characteristics—Write Operations(1)—Extended Temperature
3.0 V – 3.6 V 80 100 2.7 V – 3.6 V 90 110 # Symbol Parameter Note Min Min Min Min Unit W1 tPHWL / tPHEL RP# High Recovery to WE# (CE#) Going Low 150 150 150 150 ns W2 tELWL / tWLEL CE# (WE#) Setup to WE# (CE#) Going Low 0000 n s W3 tELEH / tWLWH WE# (CE#) Pulse Width 4 50 60 70 70 ns W4 tDVWH / tDVEH Data Setup to WE# (CE#) Going High 2 5 05 06 06 0n s W5 tAVWH / tAVEH Address Setup to WE# (CE#) Going High 2 5 06 07 07 0n s W6 tWHEH / tEHWH CE# (WE#) Hold Time from WE# (CE#) High 0000 n s W7 tWHDX / tEHDX Data Hold Time from WE# (CE#) High 20000 n s W8 tWHAX / tEHAX Address Hold Time from WE# (CE#) High 20000 n s W9 tWHWL / tEHEL WE# (CE#) Pulse Width High 4 30 30 30 30 ns W10 tVPWH / tVPEH VPP Setup to WE# (CE#) Going High 3 200 200 200 200 ns W11 t QVVL VPP Hold from Valid SRD 30000 n s NOTES: 1. Write timing characteristics during erase suspend are the same as during write-only operations. 2. Refer to Table 5 for valid A IN or DIN. 3. Sampled, but not 100% tested. 4. Write pulse width (t WP ) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH . Similarly, Write pulse width high (tWPH ) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL . 5. See Test Configuration (Figure 8).
E 3 VOLT ADVANCED+ BOOT BLOCK 33PRODUCT PREVIEW
4.7 Erase and Program Timings (1)
VPP 1.65 V–3.6 V 11.4 V–12.6 V Symbol Parameter Note Typ (1) Max Typ (1) Max Unit tBWPB 8-KB Parameter Block Program Time (Byte) 2, 3 0.16 0.48 0.08 0.24 s 4-KW Parameter Block Program Time (Word) 2, 3 0.10 0.30 0.03 0.12 s tBWMB 64-KB Main Block Program Time (Byte) 2, 3 1.2 3.7 0.6 1.7 s 32-KW Main Block Program Time(Word) 2, 3 0.8 2.4 0.24 1 s tWHQV1 / tEHQV1 Byte Program Time 2, 3 17 165 8 185 µs Word Program Time 2, 3 22 200 8 185 µs tWHQV2 / tEHQV2 8-KB Parameter Block Erase Time (Byte) 2, 3 1 5 0.8 4.8 s 4-KW Parameter Block Erase Time (Word) 2, 3 0.5 5 0.4 4.8 s tWHQV3 / tEHQV3 64-KB Main Block Erase Time (Byte) 2, 3 1 8 1 7 s 32-KW Main Block Erase Time (Word) 2, 3 1 8 0.6 7 s tWHRH1 / tEHRH1 Program Suspend Latency 3 5 10 5 10 µs tWHRH2 / tEHRH2 Erase Suspend Latency 3 5 20 5 20 µs NOTES: 1. Typical values measured at TA = +25 °C and nominal voltages. 2. Excludes external system-level overhead. 3. Sampled, but not 100% tested.
34 PRODUCT PREVIEW
- CE# must be toggled low when reading Status Register Data. WE# must be inactive (high) when reading Status Register
A. V CC Power-Up and Standby. B. Write Program or Erase Setup Command. C. Write Valid Address and Data (for Program) or Erase Confirm Command. D. Automated Program or Erase Delay. E. Read Status Register Data (SRD): reflects completed program/erase operation. F. Write Read Array Command. Figure 10. AC Waveform: Program and Erase Operations
4.8 Reset Operations
Figure 11. AC Waveform: Reset Operation Table 11. Reset Specifications(1)
- See Section 3.1.4 for a full description of these conditions.
PLPH is < 100 ns the device may still reset but this is not guaranteed.
- If RP# is asserted while a block erase or word program operation is not executing, the reset will complete within 100 ns.
- Sampled, but not 100% tested.
36 PRODUCT PREVIEW
5.0 ORDERING INFORMATION
TE = 48-Lead TSOP GT = 48-Ball µBGA* CSP Product line designator for all Intel® Flash products Access Speed (ns) (90, 110) Product Family C3 = Advanced+ Boot Block V CC = 2.7 V - 3.6 V VPP = 2.7 V - 3.6 V or 11.4 V - 12.6 V Device Density 320 = x16 (32 Mbit) 032 = x8 (32 Mbit) 160 = x16 (16 Mbit) 800 = x16 (8 Mbit) 016 = x8 (16 Mbit) 008 = x8 (8 Mbit) T = Top Blocking B = Bottom Blocking VALID COMBINATIONS (All Extended Temperature) 40-Lead TSOP 48-Ball µBGA* CSP (1) 48-Lead TSOP 48-Ball µBGA CSP (1) Extended 32M GT28F032C3T90 TE28F320C3T90 GT28F320C3T90 GT28F032C3B90 TE28F320C3B90 GT28F320C3B90 GT28F032C3T110 TE28F320C3T110 GT28F320C3T110 GT28F032C3B110 TE28F320C3B110 GT28F320C3B110 Extended 16M TE28F016C3T90 GT28F016C3T90 TE28F160C3T90 GT28F160C3T90 TE28F016C3B90 GT28F016C3B90 TE28F160C3B90 GT28F160C3B90 TE28F016C3T110 GT28F016C3T110 TE28F160C3T110 GT28F160C3T110 TE28F016C3B110 GT28F016C3B110 TE28F160C3B110 GT28F160C3B110 Extended 8M TE28F008C3T90 TE28F800C3T90 TE28F008C3B90 TE28F800C3B90 TE28F008C3T110 TE28F800C3T110 TE28F008C3B110 TE28F800C3B110 NOTE: 1. The 48-Ball µBGA package top side mark reads FXX0C3 where XX is the device density. This mark is identical for both x8 and x16 products. All product shipping boxes or trays provide the correct information regarding bus architecture, however once the devices are removed from the shipping media, it may be difficult to differentiate based on the top side mark. The device identifier (accessible through the Device ID command: see Section 3.2.2 for further details) enables x8 and x16 µBGA package product differentiation.
E 3 VOLT ADVANCED+ BOOT BLOCK 37PRODUCT PREVIEW
6.0 ADDITIONAL INFORMATION (1,2)
Order Number Document/Tool 210830 1998 Flash Memory Databook
292216 AP-658 Designing for Upgrade to the Advanced+ Boot Block Flash Memory
292215 AP-657 Designing with the Advanced+ Boot Block Flash Memory
3 Volt Advanced+ Boot Block Algorithms (‘C’ and assembly)
http://developer.intel.com/design/flcomp Contact your Intel Representative Flash Data Integrator (FDI) Software Developer’s Kit
297874 FDI Interactive: Play with Intel’s Flash Data Integrator on Your PC
NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. and tools.
38 PRODUCT PREVIEW
Command Input (and Next State) Current State SR.7 Data When Read Read Array (FFH) Program Setup (10/40H) Erase Setup (20H) Erase Confirm (D0H) Prog/Ers Suspend (B0H) Prog/Ers Resume (D0) Read Status (70H) Clear Status (50H) Read Array “1” Array Read Array Program Setup Erase Setup Read Array Read Status Read Array Read Status “1” Status Read Array Program Setup Erase Setup Read Array Read Status Read Array Read Config. “1” Config Read Array Program Setup Erase Setup Read Array Read Status Read Array Read Query “1” CFI Read Array Program Setup Erase Setup Read Array Read Status Read Array Lock Setup “1” Status Lock Command Error Lock (Done) Lock Cmd. Error Lock (Done) Lock Cmd. Error Lock Cmd. Error “1” Status Read Array Program Setup Erase Setup Read Array Read Status Read Array Lock Oper. (Done) “1” Status Read Array Program Setup Erase Setup Read Array Read Status Read Array Prot. Prog. Setup “1” Status Protection Register Program Prot. Prog. (Not Done) “0” Status Protection Register Program (Not Done) Prot. Prog. (Done) “1” Status Read Array Program Setup Erase Setup Read Array Read Status Read Array Prog. Setup “1” Status Program Program (Not Done) “0” Status Program (Not Done) Prog. Sus. Status Program (Not Done) Prog. Susp. Status “1” Status Prog. Sus. Read Array Program Suspend Read Array Program (Not Done) Prog. Sus. Rd. Array Program (Not Done) Prog. Sus. Status Prog. Sus. Rd. Array Prog. Susp. Read Array “1” Array Prog. Sus. Read Array Program Suspend Read Array Program (Not Done) Prog. Sus. Rd. Array Program (Not Done) Prog. Sus. Status Prog. Sus. Rd. Array Prog. Susp. Read Config “1” Config Prog. Sus. Read Array Program Suspend Read Array Program (Not Done) Prog. Sus. Rd. Array Program (Not Done) Prog. Sus. Status Prog. Sus. Rd. Array Prog. Susp. Read Query “1” CFI Prog. Sus. Read Array Program Suspend Read Array Program (Not Done) Prog. Sus. Rd. Array Program (Not Done) Prog. Sus. Status Prog. Sus. Rd. Array Program (Done) “1” Status Read Array Program Setup Erase Setup Read Array Read Status Read Array Erase Setup “1” Status Erase Command Error Erase (Not Done) Erase Cmd. Error Erase (Not Done) Erase Command Error Erase Cmd. Error “1” Status Read Array Program Setup Erase Setup Read Array Read Status Read Array Erase (Not Done) “0” Status Erase (Not Done) Erase Sus. Status Erase (Not Done) Ers. Susp. Status “1” Status Erase Sus. Read Array Program Setup Ers. Sus. Rd. Array Erase Ers. Sus. Rd. Array Erase Erase Sus. Status Ers. Sus. Rd. Array Erase Susp. Array “1” Array Erase Sus. Read Array Program Setup Ers. Sus. Rd. Array Erase Ers. Sus. Rd. Array Erase Erase Sus. Status Ers. Sus. Rd. Array Ers. Susp. Read Config “1” Config Erase Sus. Read Array Program Setup Ers. Sus. Rd. Array Erase Ers. Sus. Rd. Array Erase Erase Sus. Status Ers. Sus. Rd. Array Ers. Susp. Read Query “1” CFI Erase Sus. Read Array Program Setup Ers. Sus. Rd. Array Erase Ers. Sus. Rd. Array Erase Erase Sus. Status Ers. Sus. Rd. Array Erase (Done) “1” Status Read Array Program Setup Erase Setup Read Array Read Status Read Array
E 3 VOLT ADVANCED+ BOOT BLOCK 39PRODUCT PREVIEW APPENDIX A WSM CURRENT/NEXT STATES (Continued) Command Input (and Next State) Current State Read Config (90H) Read Query (98H) Lock Setup (60H) Prot. Prog. Setup (C0H) Lock Confirm (01H) Lock Down Confirm (2FH) Unlock Confirm (D0H) Read Array Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array Read Status Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array Read Config. Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array Read Query Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array Lock Setup Locking Command Error Lock Operation (Done) Lock Cmd. Error Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array Lock Operation (Done) Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array Prot. Prog. Setup Protection Register Program Prot. Prog. (Not Done) Protection Register Program (Not Done) Prot. Prog. (Done) Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array Prog. Setup Program Program (Not Done) Program (Not Done) Prog. Susp. Status Prog. Susp. Read Config. Prog. Susp. Read Query Program Suspend Read Array Program (Not Done) Prog. Susp. Read Array Prog. Susp. Read Config. Prog. Susp. Read Query Program Suspend Read Array Program (Not Done) Prog. Susp. Read Config. Prog. Susp. Read Config. Prog. Susp. Read Query Program Suspend Read Array Program (Not Done) Prog. Susp. Read Query. Prog. Susp. Read Config. Prog. Susp. Read Query Program Suspend Read Array Program (Not Done) Program (Done) Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array Erase Setup Erase Command Error Erase (Not Done) Erase Cmd. Error Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array Erase (Not Done) Erase (Not Done) Erase Suspend Status Erase Suspend Read Config. Erase Suspend Read Query Lock Setup Erase Suspend Read Array Erase (Not Done) Erase Suspend Array Erase Suspend Read Config. Erase Suspend Read Query Lock Setup Erase Suspend Read Array Erase (Not Done) Eras Sus. Read Config Erase Suspend Read Config. Erase Suspend Read Query Lock Setup Erase Suspend Read Array Erase (Not Done) Eras Sus. Read Query Erase Suspend Read Config. Erase Suspend Read Query Lock Setup Erase Suspend Read Array Erase (Not Done) Ers.(Done) Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array
40 PRODUCT PREVIEW
Repeat for subsequent programming operations. Write FFH after the last program operation to reset device to read array mode. attempts are allowed by the Write State Machine. in cases where multiple bytes are programmed before full status is checked. Figure 12. Automated Word Programming Flowchart
Figure 13. Program Suspend/Resume Flowchart
42 PRODUCT PREVIEW
Repeat for subsequent block erasures. Write FFH after the last write operation to reset device to read array mode. attempts are allowed by the Write State Machine. where multiple bytes are erased before full status is checked. Figure 14. Automated Block Erase Flowchart
Figure 15. Erase Suspend/Resume Flowchart
44 PRODUCT PREVIEW
Figure 16. Locking Operations Flowchart
Repeat for subsequent programming operations. Write FFH after the last program operation to reset device to read array mode. attempts are allowed by the Write State Machine. Figure 17. Protection Register Programming Flowchart
46 PRODUCT PREVIEW
COMMON FLASH INTERFACE QUERY STRUCTURE This appendix defines the data structure or “database” returned by the Common Flash Interface (CFI) Query command. System software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. Once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. The Query is part of an overall specification for multiple command set and control interface descriptions called Common Flash Interface, or CFI. C.1 QUERY STRUCTURE OUTPUT The Query “database” allows system software to gain critical information for controlling the flash component. This section describes the device’s CFI-compliant interface that allows the host system to access Query data. Query data are always presented on the lowest-order data outputs (DQ 0-7) only. The numerical offset value is the address relative to the maximum bus width supported by the device. On this family of devices, the Query table device starting address is a 10h, which is a word address for x16 devices or a byte address for x8 devices. For a word-wide (x16) device, the first two bytes of the Query structure, “Q”, ”R”, and “Y” in ASCII, appear on the low byte at word addresses 10h, 11h, and 12h. This CFI-compliant device outputs 00H data on upper bytes. Thus, the device outputs ASCII “Q” in the low byte (DQ 0-7) and 00h in the high byte (DQ8-15). At Query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. In all of the following tables, addresses and data are represented in hexadecimal notation, so the “h” suffix has been dropped. In addition, since the upper byte of word-wide devices is always “00h,” the leading “00” has been dropped from the table notation and only the lower byte value is shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode. Table C1. Summary of Query Structure Output As a Function of Device and Mode Device Location Quer y Data (Hex, ASCII) 8-Mbit x8/8-Mbit x 16, 16-Mbit x 8/16-Mbit x 16 10 51 “Q” (Word or Byte Addresses) 11 52 “R” 12 59 “Y”
E 3 VOLT ADVANCED+ BOOT BLOCK 47PRODUCT PREVIEW Table C2. Example of Query Structure Output of x16 and x8 Devices Device Address Word Addressing: Query Data B yte Address Byte Addressing: Query Data A 16–A 1 D 15–D 0 A 7–A 0 D 7–D 0 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h ... 0051h “Q” 0052h “R” 0059h “Y” P_ID LO PrVendor ID# (Lo byte) P_IDHI PrVendor ID# (HI byte) PLO PrVendor TblAddr (Lo) PHI PrVendor TblAddr (Hi) A_IDLO AltVendor ID# (Lo) A_IDHI AltVendor ID# (Hi) ... 10h 11h 12h 13h 14h 15h 16h 17h 18h ... 51h “Q” 52h “R” 59h “Y” P_ID LO PrVendor ID# (Lo) P_IDHI PrVendor ID# (Hi) PLO PrVndr TblAdr (Lo) PHI PrVndr TblAdr (Hi) A_IDLO AltVndr ID# (Lo) A_IDHI AltVndr ID# (Hi) C.2 QUERY STRUCTURE OVERVIEW The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or “database.” The structure sub-sections and address locations are summarized in Table D3. The following sections describe the Query structure sub-sections in detail. Table C3. Query Structure(1) Offset Sub-Section Name Description 00h Manufacturer Code 01h Device Code 02-0Fh Reserved Reserved for vendor-specific information 10h CFI Query Identification String Command set ID and vendor data offset 1Bh System Interface Information Device timing & voltage information 27h Device Geometry Definition Flash device layout P(3) Primary Intel-specific Extended Query table Vendor-defined additional information specific to the Primary Vendor Algorithm NOTES: 1. Refer to Section D.1 and Table D1 for the detailed definition of offset address as a function of device bus width and mode. 2. BA = The beginning location of a Block Address (e.g., 08000h is the beginning location of block 1 when the block size is 32 Kword). 3. Offset 15 defines “P” which points to the Primary Intel -specific Extended Query Table.
48 PRODUCT PREVIEW
C.3 BLOCK LOCK STATUS The Block Lock Status indicates the locking settings of a block. Table C4. Block Lock Status Register Offset Len gth (bytes) Description C3 x16 Device/Mode (BA+2)h(1) 01h Block Lock Status BA+2: (see Section 3.3) NOTE: 1. BA = The beginning location of a Block Address (i.e., 008000h is the beginning location of block 1 in word mode.) C.4 CFI QUERY IDENTIFICATION STRING The Identification String provides verification that the component supports the Common Flash Interface specification. Additionally, it indicates which version of the spec and which vendor-specified command set(s) is (are) supported. Table C5. CFI Identification Offset Len gth (Bytes) Description 8-Mbit, 16-Mbit, 32-Mbit 10h 03h Query -Unique ASCII string “QRY“ 10: 51 11: 52 12: 59 13h 02h Primary Vendor Command Set and Control Interface ID Code -bit ID Code for Vendor-Specified Algorithms 13: 03 14: 00 15h 02h Address for Primary Algorithm Extended Query Table Offset value = P = 35h 15: 35 16: 00 17h 02h Alternate Vendor Command Set and Control Interface ID Code Second Vendor -Specified Algorithm Supported Note: 0000h means none exists 17: 00 18: 00 19h 02h Address for Secondary Algorithm Extended Query Table Note: 0000h means none exists 19: 00 1A: 00
E 3 VOLT ADVANCED+ BOOT BLOCK 49PRODUCT PREVIEW C.5 SYSTEM INTERFACE INFORMATION The following device information can be useful in optimizing system interface software Table C6. System Interface Information Offset Len gth (bytes) Description 8-Mbit, 16-Mbit, 32-Mbit 1Bh 01h V CC Logic Supply Minimum Program/Erase Voltage bits 7–4 BCD volts bits 3–0 BCD 100 mv 1B:27 1Ch 01h V CC Logic Supply Maximum Program/Erase Voltage bits 7–4 BCD volts bits 3–0 BCD 100 mv 1C:36 1Dh 01h V PP [Programming] Supply Minimum Program/Erase Voltage bits 7–4 HEX volts bits 3–0 BCD 100 mv 1D:B4 1Eh 01h V PP [Programming] Supply Maximum Program/Erase Voltage bits 7–4 HEX volts bits 3–0 BCD 100 mv 1E:C6 1Fh 01h Typical Time -Out per Single Byte/Word Program, 2N µ-sec 1F:05 20h 01h Typical Time -Out for Max. Buffer Write, 2N µ-sec 20:00 21h 01h Typical Time -Out per Individual Block Erase, 2N m-sec 21:0A 22h 01h Typical Time -Out for Full Chip Erase, 2N m-sec 22:00 23h 01h Maximum Time -Out for Byte/Word Program, 2N Times Typical 23:04 24h 01h Maximum Time -Out for Buffer Write, 2N Times Typical 24:00 25h 01h Maximum Time -Out per Individual Block Erase, 2N Times Typical 25:03 26h 01h Maximum Time -Out for Chip Erase, 2N Times Typical 26:00
50 PRODUCT PREVIEW
C.6 DEVICE GEOMETRY DEFINITION This field provides critical details of the flash device geometry. Table C7. Device Geometry Definition Offset Length (bytes) Description 27h 01h Device Size = 2 N in Number of Bytes 28h 02h Flash Device Interface Description value meaning 28:00, 29:00 x8 asynch 28:01,29:00 x16 asynch 2Ah 02h Maximum Number of Bytes in Write Buffer = 2 N 2Ch 01h Number of Erase Block Regions within Device: bits 7–0 = x = # of Erase Block Regions 2Dh 04h Erase Block Region Information bits 15–0 = y, Where y+1 = Number of Erase Blocks of Identical Size within Region bits 31–16 = z, Where the Erase Block(s) within This Region are (z) × 256 Bytes Device Geometry Definition Offset 8 Mbit 16 Mbit 32 Mbit -T -B -T -B -T -B 27h 27:14 27:14 27:15 27:15 27:16 27:16 28h 28:00 (008) 29:00 (008) 28:01 (800) 29:00 (800) 28:00 (008) 29:00 (008) 28:01 (800) 29:00 (800) 28:00 (016) 29:00 (016) 28:01 (160) 29:00 (160) 28:00 (016) 29:00 (016) 28:01 (160) 29:00 (160) 28:00 (032) 29:00 (032) 28:01 (320) 29:00 (320) 28:00 (032) 29:00 (032) 28:01 (320) 29:00 (320) 2Ah 2A:00 2B:00 2A:00 2B:00 2A:00 2B:00 2A:00 2B:00 2A:00 2B:00 2A:00 2B:00 2Ch 2C:02 2C:02 2C:02 2C:02 2C:02 2C:02 2Dh 2D:0E 2E:00 2F:00 30:01 31:07 32:00 33:20 34:00 2D:07 2E:00 2F:20 30:00 31:0E 32:00 33:00 34:01 2D:1E 2E:00 2F:00 30:01 31:07 32:00 33:20 34:00 2D:07 2E:00 2F:20 30:00 31:1E 32:00 33:00 34:01 2D:3E 2E:00 2F:00 30:01 31:07 32:00 33:20 34:00 2D:07 2E:00 2F:20 30:00 31:3E 32:00 33:00 34:01
E 3 VOLT ADVANCED+ BOOT BLOCK 51PRODUCT PREVIEW C.7 INTEL-SPECIFIC EXTENDED QUERY TABLE Certain flash features and commands are optional. The Intel-Specific Extended Query table specifies this and other similar types of information. Table C8. Primary-Vendor Specific Extended Query Offset(1) Length (bytes) Description 8-Mbit, 16-Mbit, 32-Mbit (P)h 03h Primary Extended Query Table Unique ASCII String “PRI“ 35: 50 36: 52 37: 49 (P+3)h 01h Major Version Number, ASCII 38: 31 (P+4)h 01h Minor Version Number, ASCII 39: 30 (P+5)h 04h Optional Feature & Command Support bit 0 Chip Erase Supported (1=yes, 0=no) bit 1 Suspend Erase Supported (1=yes, 0=no) bit 2 Suspend Program Supported (1=yes, 0=no) bit 3 Lock/Unlock Supported (1=yes, 0=no) bit 4 Queued Erase Supported (1=yes, 0=no) bits 5–31 reserved for future use; undefined bits are “0” 3A: 06 3B: 00 3C: 00 3D: 00 (P+9)h 01h Supported Functions after Suspend Read Array, Status, and Query are always supported during suspended Erase or Program operation. This field defines other operations supported. bit 0 Program Supported after Erase Suspend (1=yes, 0=no) bits 1-7 reserved for future use; undefined bits are “0” 3E: 01 (P+A)h 02h Block Lock Status Defines which bits in the Block Status Register section of the Query are implemented. bit 0 Block Lock Status Register Lock/Unlock bit (bit 0) active (1=yes, 0=no) bit 1 Block Lock Status Register Lock-Down bit (bit 1) active (1=yes, 0=no) Bits 2—15 reserved for future use. Undefined bits are 0. 3F: 03 40: 00
52 PRODUCT PREVIEW
Table C8. Primary-Vendor Specific Extended Query (Continued) Offset(1) Length (bytes) Description 8-Mbit, 16-Mbit, 32-Mbit (P+C)h 01h V CC Logic Supply Optimum Program/Erase voltage (highest performance) bits 7–4 BCD value in volts bits 3–0 BCD value in 100 mv 41: 27 (P+D)h 01h V PP [Programming] Supply Optimum Program/Erase voltage bits 7–4 HEX value in volts bits 3–0 BCD value in 100 mv 42: C0 (P+E)h Reserved Reserved for future use NOTE: 1. The variable P is a pointer which is defined at offset 15h in Table D5.
E 3 VOLT ADVANCED+ BOOT BLOCK 53PRODUCT PREVIEW APPENDIX D ARCHITECTURE BLOCK DIAGRAM Output Multiplexer 4-KWord Parameter Block 32-KWord Main Block 32-KWord Main Block 4-KWord Parameter Block Y-Gating/Sensing Write State Machine Program/Erase Voltage Switch Data Comparator Status Register Identifier Register Data Register I/O Logic Address Latch Address Counter X-Decoder Y-Decoder Power Reduction Control Input Buffer Output Buffer GND VCC VPP CE# WE# OE# RP# Command User Interface Input Buffer A0-A19 DQ 0-DQ15 VCCQ WP# TEMP
54 PRODUCT PREVIEW
WORD-WIDE MEMORY MAP DIAGRAMS 8-Mbit, 16-Mbit, and 32-Mbit Word-Wide Memory Addressing Top Boot Bottom Boot Size (KW) 8M 16M 32M Size (KW) 8M 16M 32M 4 7F000-7FFFF FF000-FFFFF 1FF000-1FFFFF 32 1F8000-1FFFFF 4 7E000-7EFFF FE000-FEFFF 1FE000-1FEFFF 32 1F0000-1F7FFF 4 7D000-7DFFF FD000-FDFFF 1FD000-1FDFFF 32 1E8000-1EFFFF 4 7C000-7CFFF FC000-FCFFF 1FC000-1FCFFF 32 1E0000-1E7FFF 4 7B000-7BFFF FB000-FBFFF 1FB000-1FBFFF 32 1D8000-1DFFFF 4 7A000-7AFFF FA000-FAFFF 1FA000-1FAFFF 32 1D0000-1D7FFF 4 79000-79FFF F9000-F9FFF 1F9000-1F9FFF 32 1C8000-1CFFFF 4 78000-78FFF F8000-F8FFF 1F8000-1F8FFF 32 1C0000-1C7FFF 32 70000-77FFF F0000-F7FFF 1F0000-1F7FFF 32 1B8000-1BFFFF 32 68000-6FFFF E8000-EFFFF 1E8000-1EFFFF 32 1B0000-1B7FFF 32 60000-67FFF E0000-E7FFF 1E0000-1E7FFF 32 1A8000-1AFFFF 32 58000-5FFFF D8000-DFFFF 1D8000-1DFFFF 32 1A0000-1A7FFF 32 50000-57FFF D0000-D7FFF 1D0000-1D7FFF 32 198000-19FFFF 32 48000-4FFFF C8000-CFFFF 1C8000-1CFFFF 32 190000-197FFF 32 40000-47FFF C0000-C7FFF 1C0000-1C7FFF 32 188000-18FFFF 32 38000-3FFFF B8000-BFFFF 1B8000-1BFFFF 32 180000-187FFF 32 30000-37FFF B0000-B7FFF 1B0000-1B7FFF 32 178000-17FFFF 32 28000-2FFFF A8000-AFFFF 1A8000-1AFFFF 32 170000-177FFF 32 20000-27FFF A0000-A7FFF 1A0000-1A7FFF 32 168000-16FFFF 32 18000-1FFFF 98000-9FFFF 198000-19FFFF 32 160000-167FFF 32 10000-17FFF 90000-97FFF 190000-197FFF 32 158000-15FFFF 32 08000-0FFFF 88000-8FFFF 188000-18FFFF 32 150000-157FFF 32 00000-07FFF 80000-87FFF 180000-187FFF 32 148000-14FFFF 32 78000-7FFFF 178000-17FFFF 32 140000-147FFF 32 70000-77FFF 170000-177FFF 32 138000-13FFFF 32 68000-6FFFF 168000-16FFFF 32 130000-137FFF 32 60000-67FFF 160000-167FFF 32 128000-12FFFF 32 58000-5FFFF 158000-15FFFF 32 120000-127FFF 32 50000-57FFF 150000-157FFF 32 118000-11FFFF 32 48000-4FFFF 148000-14FFFF 32 110000-117FFF 32 40000-47FFF 140000-147FFF 32 108000-10FFFF 32 38000-3FFFF 138000-13FFFF 32 100000-107FFF 32 30000-37FFF 130000-137FFF 32 F8000-FFFFF 0F8000-0FFFFF 32 28000-2FFFF 128000-12FFFF 32 F0000-F7FFF 0F0000-0F7FFF 32 20000-27FFF 120000-127FFF 32 E8000-EFFFF 0E8000-0EFFFF 32 18000-1FFFF 118000-11FFFF 32 E0000-E7FFF 0E0000-0E7FFF 32 10000-17FFF 110000-117FFF 32 D8000-DFFFF 0D8000-0DFFFF 32 08000-0FFFF 108000-10FFFF 32 D0000-D7FFF 0D0000-0D7FFF 32 00000-07FFF 100000-107FFF 32 C8000-CFFFF 0C8000-0CFFFF
E 3 VOLT ADVANCED+ BOOT BLOCK 55PRODUCT PREVIEW 8-Mbit, 16-Mbit, and 32-Mbit Word-Wide Memory Addressing (Continued) Top Boot Bottom Boot Size (KW) 8M 16M 32M Size (KW) 8M 16M 32M 32 0F8000-0FFFFF 32 C0000-C7FFF 0C0000-0C7FFF 32 0F0000-0F7FFF 32 B8000-BFFFF 0B8000-0BFFFF 32 0E8000-0EFFFF 32 B0000-B7FFF 0B0000-0B7FFF 32 0E0000-0E7FFF 32 A8000-AFFFF 0A8000-0AFFFF 32 0D8000-0DFFFF 32 A0000-A7FFF 0A0000-0A7FFF 32 0D0000-0D7FFF 32 98000-9FFFF 098000-09FFFF 32 0C8000-0CFFFF 32 90000-97FFF 090000-097FFF 32 0C0000-0C7FFF 32 88000-8FFFF 088000-08FFFF 32 0B8000-0BFFFF 32 80000-87FFF 080000-087FFF 32 0B0000-0B7FFF 32 78000-7FFFF 78000-7FFFF 78000-7FFFF 32 0A8000-0AFFFF 32 70000-77FFF 70000-77FFF 70000-77FFF 32 0A0000-0A7FFF 32 68000-6FFFF 68000-6FFFF 68000-6FFFF 32 098000-09FFFF 32 60000-67FFF 60000-67FFF 60000-67FFF 32 090000-097FFF 32 58000-5FFFF 58000-5FFFF 58000-5FFFF 32 088000-08FFFF 32 50000-57FFF 50000-57FFF 50000-57FFF 32 080000-087FFF 32 48000-4FFFF 48000-4FFFF 48000-4FFFF 32 078000-07FFFF 32 40000-47FFF 40000-47FFF 40000-47FFF 32 070000-077FFF 32 38000-3FFFF 38000-3FFFF 38000-3FFFF 32 068000-06FFFF 32 30000-37FFF 30000-37FFF 30000-37FFF 32 060000-067FFF 32 28000-2FFFF 28000-2FFFF 28000-2FFFF 32 058000-05FFFF 32 20000-27FFF 20000-27FFF 20000-27FFF 32 050000-057FFF 32 18000-1FFFF 18000-1FFFF 18000-1FFFF 32 048000-04FFFF 32 10000-17FFF 10000-17FFF 10000-17FFF 32 040000-047FFF 32 08000-0FFFF 08000-0FFFF 08000-0FFFF 32 038000-03FFFF 4 07000-07FFF 07000-07FFF 07000-07FFF 32 030000-037FFF 4 06000-06FFF 06000-06FFF 06000-06FFF 32 028000-02FFFF 4 05000-05FFF 05000-05FFF 05000-05FFF 32 020000-027FFF 4 04000-04FFF 04000-04FFF 04000-04FFF 32 018000-01FFFF 4 03000-03FFF 03000-03FFF 03000-03FFF 32 010000-017FFF 4 02000-02FFF 02000-02FFF 02000-02FFF 32 008000-00FFFF 4 01000-01FFF 01000-01FFF 01000-01FFF 32 000000-007FFF 4 00000-00FFF 00000-00FFF 00000-00FFF
56 PRODUCT PREVIEW
BYTE-WIDE MEMORY MAP DIAGRAMS Byte-Wide Memory Addressing Top Boot Bottom Boot Size (KB) 8M 16M 32M Size (KB) 8M 16M 32M
8 FE000-FFFFF 1FE000-1FFFFF 3FE000-3FFFFF 64 3F0000-3FFFFF
8 FC000-FDFFF 1FC000-1FDFFF 3FC000-3FDFFF 64 3E0000-3EFFFF
8 FA000-FBFFF 1FA000-1FBFFF 3FA000-3FBFFF 64 3D0000-3DFFFF
8 F8000-F9FFF 1F8000-1F9FFF 3F8000-3F9FFF 64 3C0000-3CFFFF
8 F6000-F7FFF 1F6000-1F7FFF 3F6000-3F7FFF 64 3B0000-3BFFFF
8 F4000-F5FFF 1F4000-1F5FFF 3F4000-3F5FFF 64 3A0000-3AFFFF
8 F2000-F3FFF 1F2000-1F3FFF 3F2000-3F3FFF 64 390000-39FFFF
8 F0000-F1FFF 1F0000-1F1FFF 3F0000-3F1FFF 64 380000-38FFFF
64 E0000-EFFFF 1E0000-1EFFFF 3E0000-3EFFFF 64 370000-37FFFF
64 D0000-DFFFF 1D0000-1DFFFF 3D0000-3DFFFF 64 360000-36FFFF
64 C0000-CFFFF 1C0000-1CFFFF 3C0000-3CFFFF 64 350000-35FFFF
64 B0000-BFFFF 1B0000-1BFFFF 3B0000-3BFFFF 64 340000-34FFFF
64 A0000-AFFFF 1A0000-1AFFFF 3A0000-3AFFFF 64 330000-33FFFF
64 90000-9FFFF 190000-19FFFF 390000-39FFFF 64 320000-32FFFF 64 80000-8FFFF 180000-18FFFF 380000-38FFFF 64 310000-31FFFF 64 70000-7FFFF 170000-17FFFF 370000-37FFFF 64 300000-30FFFF 64 60000-6FFFF 160000-16FFFF 360000-36FFFF 64 2F0000-2FFFFF 64 50000-5FFFF 150000-15FFFF 350000-35FFFF 64 2E0000-2EFFFF 64 40000-4FFFF 140000-14FFFF 340000-34FFFF 64 2D0000-2DFFFF 64 30000-3FFFF 130000-13FFFF 330000-33FFFF 64 2C0000-2CFFFF 64 20000-2FFFF 120000-12FFFF 320000-32FFFF 64 2B0000-2BFFFF 64 10000-1FFFF 110000-11FFFF 310000-31FFFF 64 2A0000-2AFFFF 64 00000-0FFFF 100000-10FFFF 300000-30FFFF 64 290000-29FFFF 64 0F0000-0FFFFF 2F0000-2FFFFF 64 280000-28FFFF 64 0E0000-0EFFFF 2E0000-2EFFFF 64 270000-27FFFF 64 0D0000-0DFFFF 2D0000-2DFFFF 64 260000-26FFFF 64 0C0000-0CFFFF 2C0000-2CFFFF 64 250000-25FFFF 64 0B0000-0BFFFF 2B0000-2BFFFF 64 240000-24FFFF 64 0A0000-0AFFFF 2A0000-2AFFFF 64 230000-23FFFF 64 090000-09FFFF 290000-29FFFF 64 220000-22FFFF 64 080000-08FFFF 280000-28FFFF 64 210000-21FFFF 64 070000-07FFFF 270000-27FFFF 64 200000-20FFFF 64 060000-06FFFF 260000-26FFFF 64 1F0000-1FFFFF 1F0000-1FFFFF 64 050000-05FFFF 250000-25FFFF 64 1E0000-1EFFFF 1E0000-1EFFFF 64 040000-04FFFF 240000-24FFFF 64 1D0000-1DFFFF 1D0000-1DFFFF 64 030000-03FFFF 230000-23FFFF 64 1C0000-1CFFFF 1C0000-1CFFFF 64 020000-02FFFF 220000-22FFFF 64 1B0000-1BFFFF 1B0000-1BFFFF 64 010000-01FFFF 210000-21FFFF 64 1A0000-1AFFFF 1A0000-1AFFFF 64 000000-00FFFF 200000-20FFFF 64 190000-19FFFF 190000-19FFFF
E 3 VOLT ADVANCED+ BOOT BLOCK 57PRODUCT PREVIEW Byte-Wide Memory Addressing (Continued) Top Boot Bottom Boot Size (KB) 8M 16M 32M Size (KB) 8M 16M 32M 64 1F0000-1FFFFF 64 180000-18FFFF 180000-18FFFF 64 1E0000-1EFFFF 64 170000-17FFFF 170000-17FFFF 64 1D0000-1DFFFF 64 160000-16FFFF 160000-16FFFF 64 1C0000-1CFFFF 64 150000-15FFFF 150000-15FFFF 64 1B0000-1BFFFF 64 140000-14FFFF 140000-14FFFF 64 1A0000-1AFFFF 64 130000-13FFFF 130000-13FFFF 64 190000-19FFFF 64 120000-12FFFF 120000-12FFFF 64 180000-18FFFF 64 110000-11FFFF 110000-11FFFF 64 170000-17FFFF 64 100000-10FFFF 100000-10FFFF 64 160000-16FFFF 64 F0000-FFFFF 0F0000-0FFFFF 0F0000-0FFFFF 64 150000-15FFFF 64 E0000-EFFFF 0E0000-0EFFFF 0E0000-0EFFFF 64 140000-14FFFF 64 D0000-DFFFF 0D0000-0DFFFF 0D0000-0DFFFF 64 130000-13FFFF 64 C0000-CFFFF 0C0000-0CFFFF 0C0000-0CFFFF 64 120000-12FFFF 64 B0000-BFFFF 0B0000-0BFFFF 0B0000-0BFFFF 64 110000-11FFFF 64 A0000-AFFFF 0A0000-0AFFFF 0A0000-0AFFFF 64 100000-10FFFF 64 90000-9FFFF 090000-09FFFF 090000-09FFFF 64 0F0000-0FFFFF 64 80000-8FFFF 080000-08FFFF 080000-08FFFF 64 0E0000-0EFFFF 64 70000-7FFFF 070000-07FFFF 070000-07FFFF 64 0D0000-0DFFFF 64 60000-6FFFF 060000-06FFFF 060000-06FFFF 64 0C0000-0CFFFF 64 50000-5FFFF 050000-05FFFF 050000-05FFFF 64 0B0000-0BFFFF 64 40000-4FFFF 040000-04FFFF 040000-04FFFF 64 0A0000-0AFFFF 64 30000-3FFFF 030000-03FFFF 030000-03FFFF 64 090000-09FFFF 64 20000-2FFFF 020000-02FFFF 020000-02FFFF 64 080000-08FFFF 64 10000-1FFFF 010000-01FFFF 010000-01FFFF 64 070000-07FFFF 8 0E000-0FFFF 00E000-00FFFF 00E000-00FFFF 64 060000-06FFFF 8 0C000-0DFFF 00C000-00DFFF 00C000-00DFFF 64 050000-05FFFF 8 0A000-0BFFF 00A000-00BFFF 00A000-00BFFF 64 040000-04FFFF 8 08000-09FFF 008000-009FFF 008000-009FFF 64 030000-03FFFF 8 06000-07FFF 006000-007FFF 006000-007FFF 64 020000-02FFFF 8 04000-05FFF 004000-005FFF 004000-005FFF 64 010000-01FFFF 8 02000-03FFF 002000-003FFF 002000-003FFF 64 000000-00FFFF 8 00000-01FFF 000000-001FFF 000000-001FFF
58 PRODUCT PREVIEW
Read Configuration Addresses and Data Item Address Data Manufacturer Code x16 00000 0089 x8 00000 89 Device Code 8-Mbit x 16-T x16 00001 88C0 8-Mbit x 16-B x16 00001 88C1 16-Mbit x 16-T x16 00001 88C2 16-Mbit x 16-B x16 00001 88C3 32-Mbit x 16-T x16 00001 88C4 32-Mbit x 16-B x16 00001 88C5 8-Mbit x 8-T x8 00001 C0 8-Mbit x 8-B x8 00001 C1 16-Mbit x 8-T x8 00001 C2 16-Mbit x 8-B x8 00001 C3 32-Mbit x 8-T x8 00001 C4 32-Mbit x 8-B x8 00001 C5 NOTE: Other locations within the configuration address space are reserved by Intel for future use.
E 3 VOLT ADVANCED+ BOOT BLOCK 59PRODUCT PREVIEW APPENDIX H PROTECTION REGISTER ADDRESSING Word-Wide Protection Register Addressing Word Use A7 A6 A5 A4 A3 A2 A1 A0 LOCK Both 10000000
0 Factory 10000001
1 Factory 10000010
2 Factory 10000011
3 Factory 10000100
4 User 10000101
5 User 10000110
6 User 10000111
7 User 10001000
Byte-Wide Protection Register Addressing Byte Use A11 A7 A6 A5 A4 A3 A2 A1 A0 LOCK Both 010000000