RC28F160C3TA90

28F800C3 INTEL | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 68

Technical content

Datasheet sections

• 1.0 Introduction
• 1.1 Document Purpose
• 1.2 Nomenclature
• 1.3 Conventions
• 2.0 Device Description
• 2.1 Product Overview
• 2.2 Ballout Diagram
• 2.3 Signal Descriptions
• 2.4 Block Diagram
• 2.5 Memory Map
• 3.0 Device Operations
• 3.1 Bus Operations
• 3.1.1 Read
• 3.1.2 Write
• 3.1.3 Output Disable
• 3.1.5 Reset
• 4.0 Modes of Operation
• 4.1 Read Mode
• 4.1.1 Read Array
• 4.1.2 Read Identifier
• 4.1.3 CFI Query
• 4.1.4 Read Status Register
• 4.1.4.1 Clear Status Register
• 4.2 Program Mode
• 4.2.2 Suspending and Resuming Program
• 4.3 Erase Mode
• 4.3.1 Suspending and Resuming Erase
• 5.0 Security Modes
• 5.1 Flexible Block Locking
• 5.1.1 Locking Operation
• 5.1.1.1 Locked State
• 5.1.1.2 Unlocked State
• 5.1.1.3 Lock-Down State
• 5.2 Reading Block-Lock Status
• 5.3 Locking Operations during Erase Suspend
• 5.4 Status Register Error Checking
• 5.5.1 Reading the Protection Register
• 5.5.2 Programming the Protection Register
• 5.5.3 Locking the Protection Register

Datasheet sections

• 4 Datasheet
• 5.6.1 Program Protection
• 6.0 Power Consumption
• 6.1 Active Power (Program/Erase/Read)
• 6.2 Automatic Power Savings (APS)
• 6.3 Standby Power
• 6.4 Deep Power-Down Mode
• 6.5 Power and Reset Considerations
• 6.5.1 Power-Up/Down Characteristics
• 6.5.2 RP# Connected to System Reset
• 6.5.3 VCC, VPP and RP# Transitions
• 6.6 Power Supply Decoupling
• 7.0 Thermal and DC Characteristics
• 7.1 Absolute Maximum Ratings
• 7.3 DC Current Characteristics
• 7.4 DC Voltage Characteristics
• 8.0 AC Characteristics
• 8.1 AC Read Characteristics
• 8.3 Erase and Program Timings
• 8.4 Reset Specifications
• 8.5 AC I/O Test Conditions
• 8.6 Device Capacitance

Datasheet sections

Datasheet sections

• 6 Datasheet

Intel/Ga3Advanced+ Boot Block Flash Memory (C3) 28F800C3, 28F160C3, 28F320C3, 28F640C3 (x16) Datasheet Product Features The Intel® Advanced+ Book Block Flash Memory (C3) device, manufactured on Intel’s latest 0.13 µm and 0.18 µm technologies, represents a feature-rich solution for low-power applications. The C3 device incorporates low-voltage capability (3 V read, program, and erase) with high- speed, low-power operation. Flexible block locking allows any block to be independently locked or unlocked. Add to this the Intel ® Flash Data Integrator (FDI) software and you have a cost- effective, flexible, monolithic code plus data storage solution. Intel® Advanced+ Boot Block Flash Memory (C3) products will be available in 48-lead TSOP, 48-ball CSP, and 64-ball Easy BGA packages. Additional information on this product family can be obtained by accessing the Intel Flash website: http://www.intel.com/design/flash. ■ Flexible SmartVoltage Technology —2.7 V– 3.6 V Read/Program/Erase —12 V for Fast Production Programming ■ 1.65 V–2.5 V or 2.7 V–3.6 V I/O Option —Reduces Overall System Power ■ High Performance —2.7 V– 3.6 V: 70 ns Max Access Time ■ Optimized Architecture for Code Plus Data Storage —Eight 4 Kword Blocks, Top or Bottom Parameter Boot —Up to One Hundred-Twenty-Seven 32 Kword Blocks —Fast Program Suspend Capability —Fast Erase Suspend Capability ■ Flexible Block Locking —Lock/Unlock Any Block —Full Protection on Power-Up —WP# Pin for Hardware Block Protection ■ Low Power Consumption —9 mA Typical Read —7 A Typical Standby with Automatic Power Savings Feature (APS) ■ Extended Temperature Operation —–40 °C to +85 °C ■ 128-bit Protection Register —64 bit Unique Device Identifier —64 bit User Programmable OTP Cells ■ Extended Cycling Capability —Minimum 100,000 Block Erase Cycles ■ Software —Intel® Flash Data Integrator (FDI) —Supports Top or Bottom Boot Storage, Streaming Data (e.g., voice) —Intel Basic Command Set —Common Flash Interface (CFI) ■ Standard Surface Mount Packaging —48-Ball µBGA*/VFBGA —64-Ball Easy BGA Packages —48-Lead TSOP Package ■ ETOX™ VIII (0.13 µm)Flash Technology —16, 32 Mbit ■ ETOX™ VII (0.18 µm)Flash Technology —16, 32, 64 Mbit ■ ETOX™ VI (0.25 µm) Flash Technology —8, 16 and 32 Mbit Order Number: 290645-017 October 2003 Notice: This specification is subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.

2 Datasheet

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY , RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY , OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 28F800C3, 28F160C3, 28F320C3, 28F640C3 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 2003 *Third-party brands and names are the property of their respective owners.

Intel/Ga3Advanced+ Boot Block Flash Memory (C3) Datasheet 7

1.0 Introduction

1.1 Document Purpose

This datasheet contains the specifications for the Intel ® Advanced+ Boot Block Flash Memory (C3) device family. These flash memories add features such as instant block locking and protection registers that can be used to enhance the security of systems.

1.2 Nomenclature

Mword 1,048,576 words Kb 1024 bits KB 1024 bytes Mb 1,048,576 bits MB 1,048,576 bytes APS Automatic Power Savings CUI Command User Interface OTP One Time Programmable PR Protection Register PRD Protection Register Data PLR Protection Lock Register RFU Reserved for Future Use SR Status Register SRD Status Register Data WSM Write State Machine

1.3 Conventions

The terms pin and signal are often used interchangeably to refer to the external signal connections on the package. (ball is the term used for CSP). Group Membership Brackets: Square brackets will be used to designate group membership or to define a group of signals with similar function (i.e. A[21:1], SR[4:1]) Set: When referring to registers, the term set means the bit is a logical 1. Clear: When referring to registers, the term clear means the bit is a logical 0. Block: A group of bits (or words) that erase simultaneously with one block erase instruction. Main Block: A block that contains 32 Kwords. Parameter Block: A block that contains 4 Kwords.

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2.0 Device Description

This section provides an overview of the Intel® Advanced+ Boot Block Flash Memory (C3) device features, packaging, signal naming, and device architecture.

2.1 Product Overview

The C3 device provides high-performance asynchronous reads in package-compatible densities with a 16 bit data bus. Individually-erasable memory blocks are optimally sized for code and data storage. Eight 4 Kword parameter blocks are located in the boot block at either the top or bottom of the device’s memory map. The rest of the memory array is grouped into 32 Kword main blocks. The device supports read-array mode operations at various I/O voltages (1.8 V and 3 V) and erase and program operations at 3 V or 12 V VPP. With the 3 V I/O option, VCC and VPP can be tied together for a simple, ultra-low-power design. In addition to I/O voltage flexibility, the dedicated VPP input provides complete data protection when V PP ≤ VPPLK. The device features a 128-bit protection register enabling security techniques and data protection schemes through a combination of factory-programmed and user-programmable OTP data registers. Zero-latency locking/unlocking on any memory block provides instant and complete protection for critical system code and data. Additional block lock-down capability provides hardware protection where software commands alone cannot change the block’s protection status. A command User Interface(CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence issued to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations. The device offers three low-power saving features: Automatic Power Savings (APS), standby mode, and deep power-down mode. The device automatically enters APS mode following read cycle completion. Standby mode begins when the system deselects the flash memory by deasserting CE#. The deep power-down mode begins when RP# is asserted, which deselects the memory and places the outputs in a high-impedance state, producing ultra-low power savings. Combined, these three power-savings features significantly enhanced power consumption flexibility.

2.2 Ballout Diagram

The C3 device is available in 48-lead TSOP, 48-ball VF BGA, 48-ball µBGA, and Easy BGA packages. (Refer to F i g u r e1o np a g e9, Figure 3 on page 11,a n dFigure 4 on page 12, respectively.)

1. For lower densities, upper address should be treated as NC. For example, a 16-Mbit device will have NC on

Figure 1. 48-Lead TSOP Package

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Figure 2. Mark for Pin-1 indicator on 48-Lead 8Mb, 16Mb and 32Mb TSOP Table 1. 48-Lead TSOP

1. Shaded connections indicate the upgrade address connections. Routing is not recommended in this area.
2. A19 denotes 16 Mbit; A20 denotes 32 Mbit; A21 denotes 64 Mbit.
3. Unused address balls are not populated.

**Figure 3. 48-Ball µBGA* and 48-Ball Very Fine Pitch BGA (VF BGA) Chip Size Package**

12 Datasheet

Figure 4. 64-Ball Easy BGA Package 1,2

1. A19 denotes 16 Mbit; A20 denotes 32 Mbit; A21 denotes 64 Mbit.
2. Unused address balls are not populated.

2.3 Signal Descriptions

Table 2 lists the active signals used and provides a brief description of each. Table 2. Signal Descriptions

8 Mbit: AMAX= A18

16 Mbit: AMAX = A19

32 Mbit: AMAX = A20

64 Mbit: AMAX = A21

RESET/DEEP POWER-DOWN: Active-low input. High-Z, resets the Write State Machine, and minimizes current levels (ICCD). logic-high, the device resets all blocks to locked and defaults to the read array mode. t h er i s i n ge d g eo ft h eW E #p u l s e . WRITE PROTECT: Active-low input. be unlocked through software. previously marked lock-down revert to the lock-down state. See Section 5.0, “Security Modes” on page 27 for details on block locking. Lower VPP ≤ VPPLK to protect all contents against Program and Erase commands. drop as low as 1.65 V to allow for resistor or diode drop from the system supply. details on VPP voltage configurations. DEVICE CORE POWER SUPPLY: Supplies power for device operations. GND POWER GROUND: For all internal circuitry. All ground inputs must be connected. other balls, and must be left floating. NC - NO CONNECT: Pin must be left floating.

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2.4 Block Diagram

Y-Gating/Sensing Write State Machine Program/Erase Voltage Switch Dat a Comparator Status Register Ide ntifie r Register Da ta Re gi ster I/O Logic Address Latch Address Counter X-Decoder Y-Decoder Power Reduction Control Input Buffer Outp ut Bu ffer GN D VCC VPP CE# WE# OE# RP# Command User Interface Inpu t Bu ffer DQ 0-DQ15 VCCQ WP# A[MAX:MIN]

2.5 Memory Map

Map” on page 16 for details. Table 3. Top Boot Memory Map

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Table 4. Bottom Boot Memory Map

3.0 Device Operations

The C3 device uses a CUI and automated algorithms to simplify Program and Erase operations. interface to the data and address latches, as well as system status requests during WSM operation.

3.1 Bus Operations

the flash device. Table 5 on page 17 summarizes these bus operations.

3.1.1 Read

When performing a read cycle, CE# and OE# must be asserted; WE# and RP# must be deasserted.

3.1.2 Write

occurs first. See Figure 9, “Write Operations Waveform” on page 47.

3.1.3 Output Disable

Table 5. Bus Operations

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18 Datasheet

3.1.4 Standby

Deselecting the device by bringing CE# to a logic-high level (VIH) places the device in standby mode, which substantially reduces device power consumption without any latency for subsequent read accesses. In standby, outputs are placed in a high-impedance state independent of OE#. If deselected during a Program or Erase operation, the device continues to consume active power until the Program or Erase operation is complete.

3.1.5 Reset

From read mode, RP# at VIL for time tPLPH deselects the memory, places output drivers in a high- impedance state, and turns off all internal circuits. After return from reset, a time tPHQV is required until the initial read-access outputs are valid. A delay (tPHWL or tPHEL) is required after return from reset before a write cycle can be initiated. After this wake-up interval, normal operation is restored. The CUI resets to read-array mode, the status register is set to 0x80, and all blocks are locked. See Figure 10, “Reset Operations Waveforms” on page 48. If RP# is taken low for time t PLPH during a Program or Erase operation, the operation will be aborted and the memory contents at the aborted location (for a program) or block (for an erase) are no longer valid, since the data may be partially erased or written. The abort process goes through the following sequence: 1. When RP# goes low, the device shuts down the operation in progress, a process which takes time t PLRH to complete. 2. After time tPLRH, the part will either reset to read-array mode (if RP# is asserted during tPLRH)o r enter reset mode (if RP# is deasserted after tPLRH). See Figure 10, “Reset Operations Waveforms” on page 48. In both cases, after returning from an aborted operation, the relevant time tPHQV or tPHWL/tPHEL must be observed before a Read or Write operation is initiated, as discussed in the previous paragraph. However, in this case, these delays are referenced to the end of tPLRH rather than when RP# goes high. As with any automated device, it is important to assert RP# during a system reset. When the system comes out of reset, the processor expects to read from the flash memory. Automated flash memories provide status information when read during program or Block-Erase operations. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. Intel ® Flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU.

Intel/Ga3Advanced+ Boot Block Flash Memory (C3) Datasheet 19

4.0 Modes of Operation

4.1 Read Mode

The flash memory has four read modes (read array, read identifier, read status, and CFI query), and two write modes (program and erase). Three additional modes (erase suspend to program, erase suspend to read, and program suspend to read) are available only during suspended operations. Table 7, “Command Bus Operations” on page 24 and Table 8, “Command Codes and D e s c r i p t i o n s ”o np a g e2 5summarize the commands used to reach these modes. Appendix A, “Write State Machine States” on page 50 is a comprehensive chart showing the state transitions.

4.1.1 Read Array

When RP# transitions from VIL (reset) to VIH, the device defaults to read-array mode and will respond to the read-control inputs (CE#, address inputs, and OE#) without any additional CUI commands. When the device is in read array mode, four control signals control data output.

• WE# must be logic high (VIH)
• CE# must be logic low (VIL)
• OE# must be logic low (VIL)
• R P #m u s tb el o g i ch i g h( VIH) In addition, the address of the desired location must be applied to the address pins. If the device is not in read-array mode, as would be the case after a Program or Erase operation, the Read Array command (0xFF) must be issued to the CUI before array reads can occur.

4.1.2 Read Identifier

The read-identifier mode outputs three types of information: the manufacturer/device identifier, the block locking status, and the protection register. The device is switched to this mode by issuing the Read Identifier command (0x90). Once in this mode, read cycles from addresses shown in Table 6 retrieve the specified information. To return to read-array mode, issue the Read Array command (0xFF).

20 Datasheet

4.1.3 CFI Query

mode, issue the Read Array command (0xFF).

4.1.4 Read Status Register

Read Status Register command is issued. Table 6. Device Identification Codes

2 Block 0x02

1. The address is constructed from a base address plus an offset. For example, to read the Block Lock Status

for block number 38 in a bottom boot device, set the address to 0x0F8000 plus theoffset (0x02), i.e. 0x0F8002. Then examine DQ0 of the data to determine if the block is locked.

1. See Section 5.2, “Reading Block-Lock Status” on page 28for valid lock status.

Intel/Ga3Advanced+ Boot Block Flash Memory (C3) Datasheet 21 The contents of the status register are latched on the falling edge of OE# or CE# (whichever occurs last) which prevents possible bus errors that might occur if Status Register contents change while being read. CE# or OE# must be toggled with each subsequent status read, or the Status Register will not indicate completion of a Program or Erase operation. When the WSM is active, SR[7] will indicate the status of the WSM; the remaining bits in the status register indicate whether the WSM was successful in performing the preferred operation (see Table 9, “Status Register Bit Definition” on page 26).

4.1.4.1 Clear Status Register

The WSM can set Status Register bits 1 through 7 and can clear bits 2, 6, and 7; but, the WSM cannot clear Status Register bits 1, 3, 4 or 5. Because bits 1, 3, 4, and 5 indicate various error conditions, these bits can be cleared only through the Clear Status Register (0x50) command. By allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several addresses or erasing multiple blocks in sequence) before reading the status register to determine if an error occurred during that series. Clear the status register before beginning another command or sequence. The Read Array command must be issued before data can be read from the memory array. Resetting the device also clears the Status Register.

4.2 Program Mode

Programming is executed using a two-write cycle sequence. The Program Setup command (0x40) is issued to the CUI followed by a second write which specifies the address and data to be programmed. The WSM will execute a sequence of internally timed events to program preferred bits of the addressed location, then verify the bits are sufficiently programmed. Programming the memory results in specific bits within an address location being changed to a “0.” If users attempt to program “1”s, the memory cell contents do not change and no error occurs. The Status Register indicates programming status. While the program sequence executes, status bit 7 is “0.” The status register can be polled by toggling either CE# or OE#. While programming, the only valid commands are Read Status Register, Program Suspend, and Program Resume. When programming is complete, the program-status bits should be checked. If the programming operation was unsuccessful, bit SR[4] of the Status Register is set to indicate a program failure. If SR[3] is set, then V PP was not within acceptable limits, and the WSM did not execute the program command. If SR[1] is set, a program operation was attempted on a locked block and the operation was aborted. The status register should be cleared before attempting the next operation. Any CUI instruction can follow after programming is completed; however, to prevent inadvertent status-register reads, be sure to reset the CUI to read-array mode. 4.2.1 12-Volt Production Programming When VPP is between 1.65 V and 3.6 V , all program and erase current is drawn through the VCC pin. Note that if VPP is driven by a logic signal, VIH min = 1.65 V . That is, VPP must remain above 1.65 V to perform in-system flash modifications. When VPP is connected to a 12 V power supply, the device draws program and erase current directly from the VPP pin. This eliminates the need for an external switching transistor to control V PP. Figure 7 on page 31 shows examples of how the flash power supplies can be configured for various usage models.

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22 Datasheet

The 12 V VPP mode enhances programming performance during the short period of time typically found in manufacturing processes; however, it is not intended for extended use. 12 V may be applied to VPP during Program and Erase operations for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum. Stressing the device beyond these limits may cause permanent damage.

4.2.2 Suspending and Resuming Program

The Program Suspend command halts an in-progress program operation so that data can be read from other locations of memory. Once the programming process starts, issuing the Program Suspend command to the CUI requests that the WSM suspend the program sequence at predetermined points in the program algorithm. The device continues to output status-register data after the Program Suspend command is issued. Polling status-register bits SR[7] and SR[2] will determine when the program operation has been suspended (both will be set to “1”). t WHRH1/ tEHRH1 specify the program-suspend latency. A Read-Array command can now be issued to the CUI to read data from blocks other than that which is suspended. The only other valid commands while program is suspended are Read Status Register, Read Identifier, CFI Query, and Program Resume. After the Program Resume command is issued to the flash memory, the WSM will continue with the programming process and status register bits SR[2] and SR[7] will automatically be cleared. The device automatically outputs status register data when read (see Figure 14, “Program Suspend /R e s u m eF l o w c h a r t ”o np a g e5 3) after the Program Resume command is issued. V PP must remain a tt h es a m eVPP level used for program while in program-suspend mode. RP# must also remain at VIH.

4.3 Erase Mode

To erase a block, issue the Erase Set-up and Erase Confirm commands to the CUI, along with an address identifying the block to be erased. This address is latched internally when the Erase Confirm command is issued. Block erasure results in all bits within the block being set to “1.” Only one block can be erased at a time. The WSM will execute a sequence of internally timed events to program all bits within the block to “0,” erase all bits within the block to “1,” then verify that all bits within the block are sufficiently erased. While the erase executes, status bit 7 is a “0.” When the status register indicates that erasure is complete, check the erase-status bit to verify that the Erase operation was successful. If the Erase operation was unsuccessful, SR[5] of the status register will be set to a “1,” indicating an erase failure. If V PP was not within acceptable limits after the Erase Confirm command was issued, the WSM will not execute the erase sequence; instead, SR[5] of the status register is set to indicate an erase error, and SR[3] is set to a “1” to identify that V PP supply voltage was not within acceptable limits. After an Erase operation, clear the status register (0x50) before attempting the next operation. Any CUI instruction can follow after erasure is completed; however, to prevent inadvertent status- register reads, it is advisable to place the flash in read-array mode after the erase is complete.

Intel/Ga3Advanced+ Boot Block Flash Memory (C3) Datasheet 23

4.3.1 Suspending and Resuming Erase

Since an Erase operation requires on the order of seconds to complete, an Erase Suspend command is provided to allow erase-sequence interruption in order to read data from—or program data to— another block in memory. Once the erase sequence is started, issuing the Erase Suspend command to the CUI suspends the erase sequence at a predetermined point in the erase algorithm. The status register will indicate if/when the Erase operation has been suspended. Erase-suspend latency is specified by t WHRH2/tEHRH2. A Read Array or Program command can now be issued to the CUI to read/program data from/to blocks other than that which is suspended. This nested Program command can subsequently be suspended to read yet another location. The only valid commands while Erase is suspended are Read Status Register, Read Identifier, CFI Query, Program Setup, Program Resume, Erase Resume, Lock Block, Unlock Block, and Lock-Down Block. During erase-suspend mode, the chip can be placed in a pseudo -s t a n d b ym o d eb yt a k i n gC E #t oVIH, which reduces active current consumption. Erase Resume continues the erase sequence when CE# = VIL. Similar to the end of a standard Erase operation, the status register should be read and cleared before the next instruction is issued.

24 Datasheet

Bus operations are defined in Table 5, “Bus Operations” on page 17. Table 7. Command Bus Operations X = "Don’t Care" PA = Prog Addr BA = Block Addr IA = Identifier Addr. QA = Query Addr.

1. Following the Read Identifier or CFI Query commands, read operations output device identification data or
2. Either 0x40 or 0x10 command is valid, but the Intel standard is 0x40.
3. When writing commands, the upper data bus [DQ8-DQ15] should be either V

Table 8. Command Codes and Descriptions

40 Program Set-Up

20 Erase Set-Up

for another command. See Section 4.3, “Erase Mode” on page 22. Suspend commands, and will output status-register data when CE# or OE# is toggled. Issuing this command will begin to suspend the currently executing Program/Erase operation.

70 Read Status

output the contents of the status register, regardless of the address presented to the device. initiated. See Section 4.1.4, “Read Status Register” on page 20.

50 Clear Status

90 Read

bits to indicate a command-sequence error. SeeSection 5.0, “Security Modes” on page 27.

01 Lock-Block If the previous command was Lock Set-Up, the CUI will latch the address and lock the block

98 CFI

Interface information. See Section 4.1.3 and Appendix C, “Common Flash Interface”. programming to read array data. See Section 5.5.

26 Datasheet

00 Invalid/

NOTE: See Appendix A, “Write State Machine States”for mode transition information. Table 9. Status Register Bit Definition an Erase Resume command is issued. feedback between VPPLK and VPP1Min. until a Program Resume command is issued. when polling the status register. NOTE: A Command-Sequence Error is indicated when SR[4], SR[5], and SR[7] are set.

5.0 Security Modes

5.1 Flexible Block Locking

locked or unlocked with no latency, enabling instant code and data protection. Locking State Diagram” on page 27 displays all of the possible locking states. Figure 5. Block Locking State Diagram Notes: 1. [a,b,c] represents [WP#, D1, D0]. X = Don’t Care.

1. D1 indicates block Lock-down status. D1 = ‘0’, Lock-down has not been issued to

this block. D1 = ‘1’, Lock-down has been issued to this block.

1. D0 indicates block lock status. D0 = ‘0’, block is unlocked. D0 = ‘1’, block is locked.
2. Locked-down = Hardware + Software locked.
3. [011] states should be tracked by system software to determine difference

between Hardware Locked and Locked-Down states.

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5.1.1 Locking Operation

The locking status of each block can be set to Locked, Unlocked, or Lock-Down, each of which will be described in the following sections. See Figure 5, “Block Locking State Diagram” on page 27 and Figure 17, “Locking Operations Flowchart” on page 56. The following concisely summarizes the locking functionality.

5.1.1.1 Locked State

The default state of all blocks upon power-up or reset is locked (states [001] or [101]). Locked blocks are fully protected from alteration. Any Program or Erase operations attempted on a locked block will return an error on bit SR[1] of the Status Register. The state of a locked block can be changed to Unlocked or Lock Down using the appropriate software commands. An Unlocked block can be locked by writing the Lock command sequence, 0x60 followed by 0x01.

5.1.1.2 Unlocked State

Unlocked blocks (states [000], [100], [110]) can be programmed or erased. All unlocked blocks return to the Locked state when the device is reset or powered down. The status of an unlocked block can be changed to Locked or Locked Down using the appropriate software commands. A Locked block can be unlocked by writing the Unlock command sequence, 0x60 followed by 0xD0.

5.1.1.3 Lock-Down State

Blocks that are Locked-Down (state [011]) are protected from Program and Erase operations (just like Locked blocks), but their protection status cannot be changed using software commands alone. A Locked or Unlocked block can be Locked Down by writing the Lock-Down command sequence, 0x60 followed by 0x2F. Locked-Down blocks revert to the Locked state when the device is reset or powered down. The Lock-Down function depends on the WP# input pin. When WP# = 0, blocks in Lock Down [011] are protected from program, erase, and lock status changes. When WP# = 1, the Lock-Down function is disabled ([111]) and Locked-Down blocks can be individually unlocked by software command to the [110] state, where they can be erased and programmed. These blocks can then be relocked [111] and unlocked [110] as required while WP# remains high. When WP# goes low, blocks that were previously Locked Down return to the Lock-Down state [011], regardless of any changes made while WP# was high. Device reset or power-down resets all blocks, including those in Lock-Down, to Locked state.

5.2 Reading Block-Lock Status

The Lock status of each block can be read in read-identifier mode of the device by issuing the read- identifier command (0x90). Subsequent reads at Block Address + 0x00002 will output the Lock status of that block. The Lock status is represented by DQ0 and DQ1. DQ0 indicates the Block Lock/Unlock status and is set by the Lock command and cleared by the Unlock command. It is also automatically set when entering Lock Down. DQ1 indicates Lock-Down status, and is set by the Lock-Down command. It cannot be cleared by software—only by device reset or power-down. See Table 6, “Device Identification Codes” on page 20 for block-status information.

Intel/Ga3Advanced+ Boot Block Flash Memory (C3) Datasheet 29

5.3 Locking Operations during Erase Suspend

Changes to block-lock status can be performed during an erase-suspend by using the standard locking command sequences to Unlock, Lock, or Lock Down a block. This is useful in the case when another block needs to be updated while an Erase operation is in progress. To change block locking during an Erase operation, first issue the Erase Suspend command (0xB0), then check the status register until it indicates that the Erase operation has been suspended. Next, write the preferred Lock command sequence to a block and the Lock status will be changed. After completing any preferred Lock, Read, or Program operations, resume the Erase operation with the Erase Resume command (0xD0). If a block is Locked or Locked Down during a Suspended Erase of the same block, the locking status bits will be changed immediately. But when the Erase is resumed, the Erase operation will complete. Locking operations cannot be performed during a Program Suspend. Refer to Appendix A, “Write State Machine States” on page 50 for detailed information on which commands are valid during Erase Suspend.

5.4 Status Register Error Checking

Using nested-locking or program-command sequences during Erase Suspend can introduce ambiguity into status register results. Since locking changes are performed using a two-cycle command sequence, e.g., 0x60 followed by 0x01 to lock a block, following the Block Lock, Block Unlock, or Block Lock-Down Setup command (0x60) with an invalid command will produce a Lock-Command error (SR[4] and SR[5] will be set to 1) in the Status Register. If a Lock-Command error occurs during an Erase Suspend, SR[4] and SR[5] will be set to 1 and will remain at 1 after the Erase is resumed. When Erase is complete, any possible error during the Erase cannot be detected via the status register because of the previous Lock-Command error. A similar situation happens if an error occurs during a Program-Operation error nested within an Erase Suspend. 5.5 128-Bit Protection Register The C3 device architecture includes a 128-bit protection register than can be used to increase the security of a system design. For example, the number contained in the protection register can be used to “match” the flash component with other system components, such as the CPU or ASIC, preventing device substitution. The Intel application note, AP-657 Designing with the Advanced+ Boot Block Flash Memory Architecture, contains additional application information. The 128 bits of the protection register are divided into two 64-bit segments. One of the segments is programmed at the Intel factory with a unique 64-bit number, which is unchangeable. The other segment is left blank for customer designs to program, as preferred. Once the customer segment is programmed, it can be locked to prevent further programming.

30 Datasheet

5.5.1 Reading the Protection Register

array mode, issue the Read Array command (0xFF).

5.5.2 Programming the Protection Register

The protection register bits are programmed using the two-cycle Protection Program command. result in a Status Register error (Program Error bit SR[4] and Lock Error bit SR[1] will be set to 1).

5.5.3 Locking the Protection Register

5.6 V PP Program and Erase Voltages

Supply Configurations” on page 31. Figure 6. Protection Register Mapping

5.6.1 Program Protection

1. A resistor can be used if the VCC supply can sink adequate current based on resistor value. SeeAP-657

Designing with the Advanced+ Boot Block Flash Memory Architecture for details. Figure 7. Example Power Supply Configurations

12 V Fast Programming

12 V Supply

Intel/Ga3Advanced+ Boot Block Flash Memory (C3)

32 Datasheet

6.0 Power Consumption

Intel Flash devices have a tiered approach to power savings that can significantly reduce overall system power consumption. The Automatic Power Savings (APS) feature reduces power consumption when the device is selected but idle. If CE# is deasserted, the flash enters its standby mode, where current consumption is even lower. If RP# is deasserted, the flash enter deep power- down mode for ultra-low current consumption. The combination of these features can minimize memory power consumption, and therefore, overall system power consumption.

6.1 Active Power (Program/Erase/Read)

With CE# at a logic-low level and RP# at a logic-high level, the device is in the active mode. Refer to the DC Characteristic tables for ICC current values. Active power is the largest contributor to overall system power consumption. Minimizing the active current could have a profound effect on system power consumption, especially for battery -operated devices.

6.2 Automatic Power Savings (APS)

Automatic Power Savings provides low-power operation during read mode. After data is read from the memory array and the address lines are idle, APS circuitry places the device in a mode where typical current is comparable to I CCS. The flash stays in this static state with outputs valid until a new location is read.

6.3 Standby Power

When CE# is at a logic-high level (VIH), the flash memory is in standby mode, which disables much of the device’s circuitry and substantially reduces power consumption. Outputs are placed in ah i g h -impedance state independent of the status of the OE# signal. If CE# transitions to a logic - high level during Erase or Program operations, the device will continue to perform the operation and consume corresponding active power until the operation is completed. System engineers should analyze the breakdown of standby time versus active time, and quantify the respective power consumption in each mode for their specific application. This approach will provide a more accurate measure of application -specific power and energy requirements.

6.4 Deep Power-Down Mode

The deep power-down mode is activated when RP# = VIL. During read modes, RP# going low de- selects the memory and places the outputs in a high-impedance state. Recovery from deep power- down requires a minimum time of tPHQV for Read operations, and tPHWL/tPHEL for Write operations.

Intel/Ga3Advanced+ Boot Block Flash Memory (C3) Datasheet 33 During program or erase modes, RP# transitioning low will abort the in-progress operation. The memory contents of the address being programmed or the block being erased are no longer valid as the data integrity has been compromised by the abort. During deep power-down, all internal circuits are switched to a low-power savings mode (RP# transitioning to V IL or turning off power to the device clears the status register).

6.5 Power and Reset Considerations

6.5.1 Power-Up/Down Characteristics

In order to prevent any condition that may result in a spurious write or erase operation, it is recommended to power-up VCC and VCCQ together. Conversely, VCC and VCCQ must power- down together. It is also recommended to power-up VPP with or after VCC has reached VCC min. Conversely, VPP must powerdown with or slightly before VCC. If VCCQ and/or VPP are not connected to the VCC supply, then VCC should attain VCCmin before applying VCCQ and VPP. Device inputs should not be driven before supply voltage reaches VCC min. Power supply transitions should only occur when RP# is low.

6.5.2 RP# Connected to System Reset

The use of RP# during system reset is important with automated program/erase devices since the system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization will not occur because the flash memory may be providing status information instead of array data. Intel recommends connecting RP# to the system CPU RESET# signal to allow proper CPU/flash initialization following system reset. System designers must guard against spurious writes when V CC voltages are above VLKO. Because both WE# and CE# must be low for a command write, driving either signal to V IH will inhibit writes to the device. The CUI architecture provides additional protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. The device is also disabled until RP# is brought to V IH, regardless of the state of its control inputs. By holding the device in reset during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection.

6.5.3 V CC,V PP and RP# Transitions

The CUI latches commands as issued by system software and is not altered by V PP or CE# transitions or WSM actions. Its default state upon power-up, after exit from reset mode or after V CC transitions above VLKO (Lockout voltage), is read-array mode. After any program or Block-Erase operation is complete (even after V PP transitions down to VPPLK), the CUI must be reset to read-array mode via the Read Array command if access to the flash-memory array is desired.

Intel/Ga3Advanced+ Boot Block Flash Memory (C3)

34 Datasheet

6.6 Power Supply Decoupling

Flash memory power-switching characteristics require careful device decoupling. System designers should consider the following three supply current issues:

• Standby current levels (ICCS)
• Read current levels (ICCR)
• Transient peaks produced by falling and rising edges of CE#. Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two- line control and proper decoupling capacitor selection will suppress these transient voltage peaks. Each flash device should have a 0.1 µF ceramic capacitor connected between each V CC and GND, and between its VPP and VSS. These high- frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads.

7.0 Thermal and DC Characteristics

7.1 Absolute Maximum Ratings

Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended, and extended exposure beyond the “Operating Conditions” may affect device reliability. NOTICE: Specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. Parameter Maximum Rating Notes Extended Operating Temperature During Read –40 °C to +85 °C During Block Erase and Program –40 °C to +85 °C Temperature under Bias –40 °C to +85 °C Storage Temperature –65 °C to +125 °C Voltage On Any Pin (except V CC and VPP) with Respect to GND –0.5 V to +3.7 V 1 VPP Voltage (for Block Erase and Program) with Respect to GND –0.5 V to +13.5 V 1,2,3 VCC and VCCQ Supply Voltage with Respect to GND –0.2 V to +3.6 V Output Short Circuit Current 100 mA 4 NOTES: 1. Minimum DC voltage is –0.5 V on input/output pins. During transitions, this level may undershoot to –2.0 V for periods <20 ns. Maximum DC voltage on input/output pins is VCC +0.5 V which, during transitions, may overshoot to VCC +2.0 V for periods <20 ns. 2. Maximum DC voltage on VPP may overshoot to +14.0 V for periods <20 ns. done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase. V PP may be connected to 12 V for a total of 80 hours maximum. 4. Output shorted for no more than one second. No more than one output shorted at a time.

7.2 Operating Conditions

7.3 DC Current Characteristics

Table 10. Temperature and Voltage Operating Conditions

1. VCC and VCCQ must share the same supply when they are in the VCC1 range.
2. VCCMax = 3.3 V for 0.25µm 32-Mbit devices.
3. Applying VPP = 11.4 V–12.6 V during a program/erase can only be done for a maximum of 1000 cycles on

Table 11. DC Current Characteristics (Sheet 1 of 3)

36 Datasheet

0.18 Micron Product

0.25 Micron Product 1,2,3 10 18 8 15 9 15 mA

Table 11. DC Current Characteristics (Sheet 2 of 3)

1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC,T A =+ 2 5° C .
2. The test conditions VCCMax, VCCQMax, VCCMin, and VCCQMin refer to the maximum or minimum VCC or

VCCQ voltage listed at the top of each column. VCCMax = 3.3 V for 0.25µm 32-Mbit devices.

1. Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation (CMOS
2. Sampled, not 100% tested.

Table 11. DC Current Characteristics (Sheet 3 of 3)

38 Datasheet

7.4 DC Voltage Characteristics

Table 12. DC Voltage Characteristics

1. Erase and Program are inhibited when VPP <V PPLK and not guaranteed outside the valid VPP ranges of VPP1 and VPP2.
2. Applying VPP = 11.4 V–12.6 V during program/erase can only be done for a maximum of 1000 cycles on the main blocks and

2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum.

8.0 AC Characteristics

8.1 AC Read Characteristics

Table 13. Read Operations—8 Mbit Density 1 .O E #m a yb ed e l a y e du pt otELQV–tGLQV after the falling edge of CE# without impact on tELQV.

1. Sampled, but not 100% tested.
2. See Figure 8, “Read Operation Waveform” on page 42.
3. See Figure 11, “AC Input/Output Reference Waveform” on page 49for timing measurements and maximum allowable input

40 Datasheet

Table 14. Read Operations—16 Mbit Density 1 .O E #m a yb ed e l a y e du pt otELQV–tGLQV after the falling edge of CE# without impact on tELQV.

1. Sampled, but not 100% tested.
2. See Figure 8, “Read Operation Waveform” on page 42.
3. See Figure 11, “AC Input/Output Reference Waveform” on page 49for timing measurements and maximum allowable input

Table 15. Read Operations—32 Mbit Density 1 .O E #m a yb ed e l a y e du pt otELQV–tGLQV after the falling edge of CE# without impact on tELQV.

1. Sampled, but not 100% tested.
2. See Figure 8, “Read Operation Waveform” on page 42.
3. See Figure 11, “AC Input/Output Reference Waveform” on page 49for timing measurements and maximum allowable

42 Datasheet

Table 16. Read Operations — 64 Mbit Density 1 .O E #m a yb ed e l a y e du pt otELQV–tGLQV after the falling edge of CE# without impact on tELQV.

1. Sampled, but not 100% tested.
2. See Figure 8, “Read Operation Waveform” on page 42.
3. See Figure 11, “AC Input/Output Reference Waveform” on page 49for timing measurements and

maximum allowable input slew rate. Figure 8. Read Operation Waveform

Intel/Ga3Advanced+ Boot Block Flash Memory (C3) Datasheet 43

8.2 AC Write Characteristics

T a b l e1 7 . W r i t eO p e r a t i o n s — 8M b i tD e n s i t y #S y m P a r a m e t e r Density 8 Mbit Unit Product 90 ns 110 ns VCC 3 . 0V–3 . 6V 8 0 1 0 0 2 . 7V–3 . 6V 9 0 1 1 0 Note Min Min Min Min W1 tPHWL / tPHEL RP# High Recovery to WE# (CE#) Going Low 4,5 150 150 150 150 ns W2 tELWL / tWLEL CE# (WE#) Setup to WE# (CE#) Going Low 4,5 0 0 0 0 ns W3 tWLWH / tELEH W E #( C E # )P u l s eW i d t h 4 , 5 5 0 6 0 7 0 7 0 n s W4 tDVWH / tDVEH Data Setup to WE# (CE#) Going High 2,4,5 50 50 60 60 ns W5 tAVWH / tAVEH Address Setup to WE# (CE#) Going High 2,4,5 50 60 70 70 ns W6 tWHEH / tEHWH CE# (WE#) Hold Time from WE# (CE#) High 4,5 0 0 0 0 ns W7 tWHDX / tEHDX Data Hold Time from WE# (CE#) High 2,4,5 0 0 0 0 ns W8 tWHAX / tEHAX Address Hold Time from WE# (CE#) High 2,4,5 0 0 0 0 ns W9 tWHWL / tEHEL WE# (CE#) Pulse Width High 2,4,5 30 30 30 30 ns W10 tVPWH / tVPEH VPP Setup to WE# (CE#) Going High 3,4,5 200 200 200 200 ns W11 t QVVL VPP Hold from Valid SRD 3,4 0 0 0 0 ns W12 tBHWH / tBHEH WP# Setup to WE# (CE#) Going High 3,4 0 0 0 0 ns W13 t QVBL WP# Hold from Valid SRD 3,4 0 0 0 0 ns W14 t WHGL W E #H i g ht oO E #G o i n gL o w 3 , 4 3 0 3 0 3 0 3 0 n s NOTES: 1. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever goes high first). Hence, tWP =t WLWH =t ELEH =t WLEH =t ELWH. Similarly, write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low last). Hence, t WPH =t WHWL =t EHEL =t WHEL =t EHWL. 2. Refer to Table 7, “Command Bus Operations” on page 24for valid AIN or DIN. 3. Sampled, but not 100% tested. 4. See Figure 11, “AC Input/Output Reference Waveform” on page 49for timing measurements and maximum allowable input slew rate. 5. See Figure 9, “Write Operations Waveform” on page 47 .

44 Datasheet

Table 18. Write Operations—16 Mbit Density

1. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high

WPH =t WHWL =t EHEL =t WHEL =t EHWL.

1. Refer to Table 7, “Command Bus Operations” on page 24for valid AIN or DIN.
2. Sampled, but not 100% tested.
3. See Figure 11, “AC Input/Output Reference Waveform” on page 49for timing measurements and maximum allowable input

Figure 9, “Write Operations Waveform” on page 47 .

Table 19. Write Operations—32 Mbit Density

1. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever

WPH =t WHWL =t EHEL =t WHEL =t EHWL.

1. Refer to Table 7, “Command Bus Operations” on page 24for valid AIN or DIN.
2. Sampled, but not 100% tested.
3. See Figure 11, “AC Input/Output Reference Waveform” on page 49for timing measurements and maximum allowable input

Figure 9, “Write Operations Waveform” on page 47 .

1. VCCMax = 3.3 V for 32-Mbit 0.25 Micron product.

46 Datasheet

Table 20. Write Operations—64Mbit Density

1. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or

WE# going high (whichever goes high first). Hence, tWP =t WLWH =t ELEH =t WLEH =t ELWH. WPH =t WHWL =t EHEL =t WHEL =t EHWL.

1. Refer to Table 7, “Command Bus Operations” on page 24for valid AIN or DIN.
2. Sampled, but not 100% tested.
3. See Figure 11, “AC Input/Output Reference Waveform” on page 49for timing measurements and

maximum allowable input slew rate. Figure 9, “Write Operations Waveform” on page 47 .

8.3 Erase and Program Timings

Table 21. Erase and Program Timings Figure 9. Write Operations Waveform

1. Typical values measured at TA= +25 °C and nominal voltages.
2. Excludes external system-level overhead.
3. Sampled, but not 100% tested.

48 Datasheet

8.4 Reset Specifications

Table 22. Reset Specifications

1. If tPLPH is < 100 ns the device may still reset but this is not guaranteed.
2. If RP# is asserted while a Block Erase or Word Program operation is not executing, the reset will complete
3. Sampled, but not 100% tested.

Figure 10. Reset Operations Waveforms

8.5 AC I/O Test Conditions

NOTE: Input timing begins, and output timing ends, at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns. Worst case speed conditions are when VCC =V CCMin. NOTE: See T able 17 for component values.

8.6 Device Capacitance

Figure 11. AC Input/Output Reference Waveform Figure 12. Transient Equivalent Testing Load Circuit Table 23. Test Configuration Component Values for Worst Case Speed Conditions NOTE: CL includes jig capacitance.

Intel/Ga3Advanced+ Boot Block Flash Memory (C3)

50 Datasheet

Appendix A Write State Machine States This table shows the command state transitions based on incoming commands. C o m m a n dI n p u t( a n dN e x tS t a t e ) Current State SR.7 Data When Read Read Array (FFH) Program Setup (10/ 40H) Erase Setup (20H) Erase Confirm (D0H) Prog/Ers Suspend (B0H) Prog/Ers Resume (D0) Read Status (70H) Clear Status (50H) Read Array “1” Array Read Array Prog. Setup Ers. Setup Read Array Read Sts. Read Array Read Status “1” Status Read Array Prog. Setup Ers. Setup Read Array Read Sts. Read Array Read Config. “1” Config Read Array Prog. Setup Ers. Setup Read Array Read Sts. Read Array Read Query “1” CFI Read Array Prog. Setup Ers. Setup Read Array Read Sts. Read Array Lock Setup “1” Status Lock Command Error Lock (Done) Lock Cmd. Error Lock (Done) Lock Cmd. Error Lock Cmd. Error “1” Status Read Array Prog. Setup Ers. Setup Read Array Read Sts. Read Array Lock Oper. (Done) “1” Status Read Array Prog. Setup Ers. Setup Read Array Read Sts. Read Array Prot. Prog. Setup “1” Status Protection Register Program Prot. Prog. (Not Done) “0” Status Protection Register Program (Not Done) Prog. Setup “1” Status Program Program (Not Done) “0” Status Program (Not Done) Prog. Sus. Status Program (Not Done) Prog. Susp. Status “1” Status Prog. Sus. Read Array Program Suspend Read Array Prog. (Not Done) Prog. Sus.Rd. Array Program (Not Done) Prog. Sus. Status Prog. Sus. Rd. Array Prog. Susp. Read Array “1” Array Prog. Sus. Read Array Program Suspend Read Array Prog. (Not Done) Prog. Sus.Rd. Array Program (Not Done) Prog. Sus. Status Prog. Sus. Rd. Array Prog. Susp. Read Config “1” Config Prog. Sus. Read Array Program Suspend Read Array Prog. (Not Done) Prog. Sus.Rd. Array Program (Not Done) Prog. Sus. Status Prog. Sus. Rd. Array Prog. Susp. Read Query “1” CFI Prog. Sus. Read Array Program Suspend Read Array Prog. (Not Done) Prog. Sus.Rd. Array Program (Not Done) Prog. Sus. Status Prog. Sus. Rd. Array Program (Done) “1” Status Read Array Prog. Setup Ers. Setup Read Array Read Status Read Array Erase Setup “1” Status Erase Command Error Erase (Not Done) Erase Cmd. Error Erase (Not Done) Erase Command Error Erase Cmd. Error “1” Status Read Array Prog. Setup Ers. Setup Read Array Read Status Read Array Erase (Not Done) “0” Status Erase (Not Done) Erase Sus. Status Erase (Not Done) Ers. Susp. Status “1” Status Erase Sus. Read Array Prog. Setup Ers. Sus. Rd. Array Erase Ers. Sus. Rd. Array Erase Erase Sus. Status Ers. Sus. Rd. Array Erase Susp. Array “1” Array Erase Sus. Read Array Prog. Setup Ers. Sus. Rd. Array Erase Ers. Sus. Rd. Array Erase Erase Sus. Status Ers. Sus. Rd. Array Ers. Susp. Read Config “1” Config Erase Sus. Read Array Prog. Setup Ers. Sus. Rd. Array Erase Ers. Sus. Rd. Array Erase Erase Sus. Status Ers. Sus. Rd. Array Ers. Susp. Read Query “1” CFI Erase Sus. Read Array Prog. Setup Ers. Sus. Rd. Array Erase Ers. Sus. Rd. Array Erase Erase Sus. Status Ers. Sus. Rd. Array Erase (Done) “1” Status Read Array Prog. Setup Ers. Setup Read Array Read Sts. Read Array

Intel/Ga3Advanced+ Boot Block Flash Memory (C3) Datasheet 51 C o m m a n dI n p u t( a n dN e x tS t a t e ) Current State Read Config (90H) Read Query (98H) Lock Setup (60H) Prot. Prog. Setup (C0H) Lock Confirm (01H) Lock Down Confirm (2FH) Unlock Confirm (D0H) Read Array Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array Read Status Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array Read Config. Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array Read Query Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array Lock Setup Locking Command Error Lock Operation (Done) Lock Cmd. Error Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array Lock Oper. (Done) Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array Prot. Prog. Setup Protection Register Program Prot. Prog. (Not Done) Protection Register Program (Not Done) Prot. Prog. (Done) Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array Prog. Setup Program Program (Not Done) Program (Not Done) Prog. Susp. Status Prog. Susp. Read Config. Prog. Susp. Read Query Program Suspend Read Array Program (Not Done) Prog. Susp. Read Array Prog. Susp. Read Config. Prog. Susp. Read Query Program Suspend Read Array Program (Not Done) Prog. Susp. Read Config. Prog. Susp. Read Config. Prog. Susp. Read Query Program Suspend Read Array Program (Not Done) Prog. Susp. Read Query. Prog. Susp. Read Config. Prog. Susp. Read Query Program Suspend Read Array Program (Not Done) Program (Done) Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array Erase Setup Erase Command Error Erase (Not Done) Erase Cmd. Error Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array Erase (Not Done) Erase (Not Done) Erase Susp. Status Ers. Susp. Read Config. Erase Suspend Read Query Lock Setup Erase Suspend Read Array Erase (Not Done) Erase Suspend Array Ers. Susp. Read Config. Erase Suspend Read Query Lock Setup Erase Suspend Read Array Erase (Not Done) Eras Sus. Read Config Erase Suspend Read Config. Erase Suspend Read Query Lock Setup Erase Suspend Read Array Erase (Not Done) Eras Sus. Read Query Erase Suspend Read Config. Erase Suspend Read Query Lock Setup Erase Suspend Read Array Erase (Not Done) Ers.(Done) Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array

52 Datasheet

Figure 13. Word Program Flowchart Repeat for subsequent Word Program operations. after a sequence of program operations.

1 VPP Range

allow further program attempts. command clears the Status Register error bits.

Figure 14. Program Suspend / Resume Flowchart

54 Datasheet

Figure 15. Erase Suspend / Resume Flowchart

Figure 16. Block Erase Flowchart Repeat for subsequent block erasures. or after a sequence of block erasures. Write 0xFF after the last operation to enter read array mode. allow further erase attempts. Only the Clear Status Register command clears SR[1, 3, 4, 5]. attempting an erase retry or other error recovery.

0 Yes

56 Datasheet

Figure 17. Locking Operations Flowchart Confirm locking change on D[1,0] .

Figure 18. Protection Register Programming Flowchart outside this space will return an error. Repeat for subsequent programming operations. after a sequence of program operations. Write 0xFF after the last operation to set Read Array state. allow further program attempts. Only the Clear Staus Register command clears SR[1, 3, 4]. attempting a program retry or other error recovery.

58 Datasheet

multiple command set and control interface descriptions called Common Flash Interface, or CFI. The Query database allows system software to obtain information for controlling the flash device. This section describes the device’s CFI-compliant interface that allows access to Query data. devices, the Query table device starting address is a 0x10, which is a word address for x16 devices. presented at the lower address, and the most significant data byte is presented at the higher address. shown. Any x16 device outputs can be assumed to have 0x00 on the upper byte in this mode. Table 24. Summary of Query Structure Output as a Function of Device and Mode Table 25. Example of Query Structure Output of x16 Devices (Sheet 1 of 2)

a given block is locked or can be accessed for flash program/erase operations. accidentally removed during an erase operation. Table 25. Example of Query Structure Output of x16 Devices (Sheet 2 of 2) Table 26. Query Structure

1. Refer to the Query Structure Output section and offset 0x28 for the detailed definition of offset address as a

function of device bus width and mode.

1. BA = Block Address beginning location (i.e., 0x08000 is block 1’s beginning location when the block size is
2. Offset 15 defines “P” which points to the Primary Intel-specific Extended Query Table.

60 Datasheet

1. BA = Block Address beginning location (i.e., 0x08000 is block 1’s beginning location when the block size is

Table 28. CFI Identification Table 29. System Interface Information

Table 30. Device Geometry Definition

1. x = 0 means no erase blocking; the device erases in “bulk”
2. x specifies the number of device or partition regions

with one or more contiguous same-size erase blocks.

1. Symmetrically blocked partitions have one blocking region
2. Partition size = (total blocks) x (individual block size)

62 Datasheet

specifies this and other similar types of information. Table 31. Device Geometry Details

16 Mbit 32 Mbit 64 Mbit

Table 32. Primary-Vendor Specific Extended Query (Sheet 1 of 2)

3 Primary extended query table

features follows at the end of the bit-30 field.

1. The variable P is a pointer which is defined at CFI offset 0x15.

Table 32. Primary-Vendor Specific Extended Query (Sheet 2 of 2) Table 33. Protection Register Information 0x(P+E) 1 Number of Protection register fields in JEDEC ID space. point to the Protection register Lock byte, the section’s first byte.

1. The variable P is a pointer which is defined at CFI offset 0x15.

64 Datasheet

**Figure 19. µBGA* and VF BGA Package Drawing & Dimensions**

1. One dimple on package denotes Pin 1.
2. If two dimples, then the larger dimple denotes Pin 1.
3. Pin 1 will always be in the upper left corner of the package, in reference to the product mark.
4. Pin 1 will always supersede above pin one notes.

Figure 20. TSOP Package Drawing & Dimensions

66 Datasheet

Figure 21. Easy BGA Package Drawing & Dimension on die size, and are subject to change.

Intel/Ga3Advanced+ Boot Block Flash Memory (C3) Datasheet 67 Appendix E Additional Information Order Number Document/Tool 297938 3 Volt Advanced+ Boot Block Flash Memory Specification Update

292216 AP-658 Designing for Upgrade to the Advanced+ Boot Block Flash Memory

292215 AP-657 Designing with the Advanced+ Boot Block Flash Memory

Representative Intel® Flash Data Integrator (FDI) Software Developer’s Kit

297874 IFDI Interactive: Play with Intel ® Flash Data Integrator on Your PC

NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at ‘http://www.intel.com/design/flash’ for technical documentation and tools.

68 Datasheet

Figure 22. Component Ordering Information

64 Mbit

32 Mbit

16 Mbit

samples. All other assembly codes without an “E” or “S” as the first character are production units.