QX6000 INTEL | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1.1 Terminology
- 1.1.1 Processor Terminology
- 1.2 References
- 2 Electrical Specifications
- 2.1 Power and Ground Lands
- 2.2 Decoupling Guidelines
- 2.2.1 VCC Decoupling
- 2.2.2 VTT Decoupling
- 2.2.3 FSB Decoupling
- 2.3 Voltage Identification
- 2.4 Reserved, Unused, and TESTHI Signals
- 2.5 Voltage and Current Specification
- 2.5.1 Absolute Maximum and Minimum Ratings
- 2.5.2 DC Voltage and Current Specification
- 2.5.3 VCC Overshoot
- 2.5.4 Die Voltage Validation
- 2.6 Signaling Specifications
- 2.6.1 FSB Signal Groups
- 2.6.2 CMOS and Open Drain Signals
- 2.6.3 Processor DC Specifications
- 2.6.3.1 GTL+ Front Side Bus Specifications
- 2.7 Clock Specifications
- 2.7.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking
- 2.7.2 FSB Frequency Select Signals (BSEL[2:0])
- 2.7.3 Phase Lock Loop (PLL) and Filter
- 2.7.4 BCLK[1:0] Specifications
- 3 Package Mechanical Specifications
- 3.1 Package Mechanical Drawing
- 3.2 Processor Component Keep-Out Zones
- 3.3 Package Loading Specifications
- 3.4 Package Handling Guidelines
- 3.5 Package Insertion Specifications
- 3.6 Processor Mass Specification
- 3.7 Processor Materials
- 3.8 Processor Markings
- 3.9 Processor Land Coordinates
- 4 Land Listing and Signal Descriptions
- 4.1 Processor Land Assignments
- 4.2 Alphabetical Signals Reference
- 5 Thermal Specifications and Design Considerations
- 5.1 Processor Thermal Specifications
- 5.1.1 Thermal Specifications
- 5.1.2 Thermal Metrology
- 5.2 Processor Thermal Features
- 5.2.1 Thermal Monitor
- 5.2.2 Thermal Monitor
- 5.2.3 On-Demand Mode
- 5.2.4 PROCHOT# Signal
Document Number: 315592-005 Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and Intel® Core™2 Quad Processor Q6000Δ Sequence Datasheet —on 65 nm Process in the 775- land LGA Package supporting Intel® 64 architecture and Intel® Virtualization Technology± August 2007
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel ® Core™2 Extreme quad-core processor QX6000 sequence and Intel ® Core™2 quad processor Q6000 sequen ce may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. ΔIntel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. Over time processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increases in any particular feature. Current roadmap processor number progression is not necessarily representative of future roadmaps. See www.intel.com/products/ processor_number for details. Intel® 64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers, and applications enabled for Intel 64. Processor will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary depending on your hardware and software configurations. See http://www.intel.com/technology/intel64/index.htm for more information including details on which processors support Intel 64, or consult with your system vendor for more information. Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality. ± Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) and, for some uses, certain platform software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update. Software applications may not be compatible with all operating systems. Please check with your application vendor. Intel, Pentium, Itanium, Xeon, Intel SpeedStep, andand the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.. *Other names and brands may be claimed as the property of others. Copyright © 2006–2007 Intel Corporation.
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6.2.4 Extended HALT Snoop or HALT Snoop State,
7.3.2 Fan Speed Control Operation (Intel
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Revision History
-001 • Initial release November 2006 -002
- Added specificatio ns for the Intel® Core™2 Quad Processor Q6600
- Updated Table 8, “Signal Characteristics”.
- Updated VTT_SEL description in Table 24.
- Updated Table 29, “Fan Heatsink Power and Signal Specifications”. January 2007 -003 • Added specificatio ns for the Intel ® Core™2 Quad Processor Q6700 and Intel ® Core™2 Extreme quad-core processor QX6850 July 2007 -003 • Added Intel ® Core™2 Quad Processor Q6600 for 775_VR_CONFIG_05A July 2007 -004 • Added Intel ® Core™2 Extreme quad-core processor QX6850 July 2007 -005 • Added Intel ® Core™2 Extreme quad-core processor QX6800 August 2007
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Intel® Core™2 Extreme Quad-Core Processor QX6000 and Intel® Core™2 Quad Processor Q6000 Sequence Features The Intel Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 quad processor Q6000 sequence deliver Intel's advanced, powerful processors for desktop PCs. The processor is designed to deliver performance across applications and usages where end-users can truly appreciate and experience the performance. These applications include Internet audio and streaming video, image processing, video content creation, speech, 3D, CAD, games, multimedia, and multitasking user environments. Intel ® 64Φ architecture enables the processor to execute operating systems and applications written to take advantage of the Intel 64 architecture. The processor, supporting Enhanced Intel Speedstep® technology, allows tradeoffs to be made between performance and power consumption. The Core™2 Extreme quad-core processor QX6000 sequence and Intel ® Core™2 quad processor Q6000 sequence also include the Execute Disable Bit capability. This feature, combined with a supported operating system, allows memory to be marked as executable or non-executable. The Core™2 Extreme quad-core processor QX6000 sequence and Intel ® Core™2 quad processor Q6000 sequence support Intel® Virtualization Technology. Virtualization Technology provides silicon- based functionality that works together with compatible Virtual Machine Monitor (VMM) software to improve on software-only solutions. § §
- Available at 3.00 GHz (Intel ® Core™2 Extreme Quad-Core Processor QX6850 only)
- Available at 2.66 GHz (Intel ® Core™2 Extreme Quad-Core Processor QX6700 and Intel ® Core™2 Quad Processor Q6700 only)
- Available at 2.40 GHz (Intel ® Core™2 Quad Processor Q6600 only)
- Available at 2.93 GHz (Intel ® Core™2 Extreme Quad-Core Processor QX6800 only)
- Enhanced Intel Speedstep ® Technology
- S u p p o r t s I n t e l® 64Φ architecture
- S u p p o r t s I n t e l® Virtualization Technology
- Supports Execute Disable Bit capability
- FSB frequency at 1066 MHz (Intel ® Core™2 Extreme Quad-Core Processor QX6700, QX6800 and Intel® Core™2 Quad Processor Q6700 and Q6600 only)
- FSB frequency at 1333 MHz (Intel ® Core™2 Extreme Quad-Core Processor QX6850 only)
- Binary compatible with applications running on previous members of the Intel microprocessor line
- Advance Dynamic Execution
- Very deep out-of-order execution
- Enhanced branch prediction
- Optimized for 32-bit applications running on advanced 32-bit operating systems
- Four 32-KB Level 1 data caches
- Two 4 MB Level 2 caches
- I n t e l ® Advanced Digital Media Boost
- Enhanced floating point and multimedia unit for enhanced video, audio, encryption, and 3D performance
- Power Management capabilities
- System Management mode
- Multiple low-power states
- 8-way cache associativity provides improved cache hit rate on load/store operations
- 775-land Package
1 Introduction
The Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 quad processor Q6000 sequence are the first desktop quad-core processors that combine the performance and power efficiencies of four low-power microarchitecture cores to enable a new level of multi-tasking, multi-media, and gaming experiences. They are 64-bit processors that maintain compatibility with IA-32 software. The processors use Flip-Chip Land Grid Array (FC-LGA6) package technology, and plug into a 775-land surface mount, Land Grid Array (LGA) socket, referred to as the LGA775 socket. The processors are based on 65 nm process technology. Note: In this document the Intel ® Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 quad processor Q6000 sequence are referred to simply as “processor.” Note: In this document the Intel® Core™2 quad-core processor Q6000 sequence refers to the Intel® Core™2 quad processor Q6600 and Q6700. The Intel ® Core™2 Extreme quad- core processor QX6000 sequence refers to the Intel® Core™2 Extreme quad-core processors QX6700, QX6800, and QX6850. The processor supports all the existing Streaming SIMD Extensions 2 (SSE2) and Streaming SIMD Extensions 3 (SSE3). The processor supports several advanced technologies including Execute Disable Bit, Intel® 64 architecture, and Intel® Virtualization Technology (VT). The processor's front side bus (FSB) uses a split-transaction, deferred reply protocol like the Intel® Pentium® 4 processor. The FSB uses Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a "double- clocked" or 2X address bus. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 10.7 GB/s. The processor uses some of the infrastructure already enabled by the 775_VR_CONFIG_05 platforms including heatsink, heatsink retention mechanism, and socket. Supported platforms may need to be refreshed to ensure the correct voltage regulation (VRD11) and PECI support is enabled. Manufacturability is a high priority; hence, mechanical assembly may be completed from the top of the baseboard and should not require any special tooling. The processor includes an address bus power-down capability that removes power from the address and data signals when the FSB is not in use. This feature is always enabled on the processor.
1.1 Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
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“Front Side Bus” refers to the interface between the processor and system core logic (a.k.a. the chipset components). The FSB is a multiprocessing interface to processors, memory, and I/O.
1.1.1 Processor Terminology
Commonly used terms are explained here for clarification:
- Intel® Core™2 Extreme quad -core processor QX6000 sequence — Quad core processor in the FC-LGA6 package with a 2x4 MB L2 cache.
- Intel® Core™2 quad processor Q6000 sequence — Quad core processor in the FC-LGA6 package with a 2x4 MB L2 cache.
- Processor — For this document, the term processor is the generic form of the Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 quad processor Q6000 sequence. The processor is a single package that contains one or more execution units.
- Keep-out zone — The area on or near the processor that system design can not utilize.
- Processor core — Processor core die with integrated L2 cache.
- LGA775 socket — The processor mates with the system board through a surface mount, 775-land, LGA socket.
- Integrated heat spreader (IHS) —A component of the processor package used to enhance the thermal performance of the package. Component thermal solutions interface with the processor at the IHS surface.
- Retention mechanism (RM) — Since the LGA775 socket does not include any mechanical features for heatsink attach, a retention mechanism is required. Component thermal solutions should attach to the processor via a retention mechanism that is independent of the socket.
- FSB (Front Side Bus) — The electrical interface that connects the processor to the chipset. Also referred to as the processor system bus or the system bus. All memory and I/O transactions as well as interrupt messages pass between the processor and chipset over the FSB.
- Storage conditions — Refers to a non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor lands should not be connected to any supply voltages, have any I/Os biased, or receive any clocks. Upon exposure to “free air”(i.e., unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material.
- Functional operation — Refers to normal operating conditions in which all processor specifications, including DC, AC, system bus, signal quality, mechanical and thermal are satisfied.
- Execute Disable Bit — The Execute Disable bit allows memory to be marked as executable or non-executable, when combined with a supporting operating system. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer over run vulnerabilities and can thus help improve the overall security of the system. See the Intel ® Architecture Software Developer's Manual for more detailed information.
- Intel® 64 Architecture — An enhancement to Intel's IA-32 architecture, allowing the processor to execute operating systems and applications written to take advantage of the Intel 64 architecture. Further details on Intel 64 architecture and programming model can be found in the Intel Extended Memory 64 Technology Software Developer Guide at http://www.intel.com/technology/intel64/index.htm.
- Enhanced Intel Technology SpeedStep® Technology — Enhanced Intel Technology SpeedStep® Technology allows trade-offs to be made between performance and power consumptions, based on processor utilization. This may lower average power consumption (in conjunction with OS support).
- Intel® Virtualization Technology (Intel® VT) — Intel Virtualization Technology provides silicon-based functionality that works together with compatible Virtual Machine Monitor (VMM) software to improve upon software-only solutions. Because this virtualization hardware provides a new architecture upon which the operating system can run directly, it removes the need for binary translation. Thus, it helps eliminate associated performance overhead and vastly simplifies the design of the VMM, in turn allowing VMMs to be written to common standards and to be more robust. See the Intel® Virtualization Technology Specification for the IA-32 Intel® Architecture for more details.
1.2 References
Table 1. References
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2 Electrical Specifications
This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided.
2.1 Power and Ground Lands
The processor has VCC (power), VTT and VSS (ground) inputs for on-chip power distribution. All power lands must be connected to V CC, while all VSS lands must be connected to a system ground plane. The processor VCC lands must be supplied the voltage determined by the Voltage IDentification (VID) lands. The signals are denoted as VTT, which provide termination for the front side bus and power to the I/O buffers. A separate supply must be implemented for these lands, that meets the VTT specifications outlined in Table 4.
2.2 Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large current swings. This may cause voltages on power planes to sag below their minimum specified values if bulk decoupling is not adequate. Larger bulk storage (CBULK), such as electrolytic or aluminum-polymer capacitors, supply current during longer lasting changes in current demand by the component, such as coming out of an idle condition. Similarly, they act as a storage well for current when entering an idle condition from a running condition. The motherboard must be designed to ensure that the voltage provided to the processor remains within the specifications listed in Table 4. Failure to do so can result in timing violations or reduced lifetime of the component.
2.2.1 V CC Decoupling
VCC regulator solutions need to provide sufficient decoupling capacitance to satisfy the processor voltage specifications. This includes bulk capacitance with low effective series resistance (ESR) to keep the voltage rail within specifications during large swings in load current. In addition, ceramic decoupling capacitors are required to filter high frequency content generated by the front side bus and processor activity. Consult the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket.
2.2.2 V TT Decoupling
Decoupling must be provided on the motherboard. Decoupling solutions must be sized to meet the expected load. To insure compliance with the specifications, various factors associated with the power delivery solution must be considered including regulator type, power plane and trace sizing, and component placement. A conservative decoupling solution would consist of a combination of low ESR bulk capacitors and high frequency ceramic capacitors.
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2.2.3 FSB Decoupling
The processor integrates signal termination on the die. In addition, some of the high frequency capacitance required for the FSB is included on the processor package. However, additional high frequency capacitance must be added to the motherboard to properly decouple the return currents from the front side bus. Bulk decoupling must also be provided by the motherboard for proper [A]GTL+ bus operation.
2.3 Voltage Identification
The Voltage Identification (VID) specification for the processor is defined by the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket. The voltage set by the VID signals is the reference VR output voltage to be delivered to the processor VCC pins (see Chapter 2.5.3 for VCC overshoot specifications). Refer to Table 12 for the DC specifications for these signals. Voltages for each processor frequency is provided in Table 4. Individual processor VID values may be calibrated during manufacturing such that two devices at the same core speed may have different default VID settings. This is reflected by the VID Range values provided in Table 4. Refer to the Intel ® Core™2 Extreme Quad-Core Processor QX6000 Sequence and Intel® Core™2 Quad Processor Q6000 Sequence Specification Update for further details on specific valid core frequency and VID values of the processor. Note that this differs from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep® Technology, or Extended HALT State). The processor uses six voltage identification signals, VID[7:0], to support automatic selection of power supply voltages. Table 2 specifies the voltage level corresponding to the state of VID[7:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to a low voltage level. If the processor socket is empty (VID[7:0] = 11111111), or the voltage regulation circuit cannot supply the voltage that is requested, it must disable itself. The Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket defines VID [7:0], VID7 and VID0 are not used on the processor; VID0 and VID7 are strapped to V SS on the processor package. VID0 and VID7 must be connected to the VR controller for compatibility with future processors. The processor provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage (V CC). This will represent a DC shift in the load line. It should be noted that a low-to-high or high-to-low voltage state change may result in as many VID transitions as necessary to reach the target core voltage. Transitions above the specified VID are not permitted. Table 4 includes VID step sizes and DC shift ranges. Minimum and maximum voltages must be maintained as shown in Table 5 and Figure 1 as measured across the VCC_SENSE and VSS_SENSE lands. The VRM or VRD utilized must be capable of regulating its output to the value defined by the new VID. DC specifications for dynamic VID transitions are included in Table 4 and Table 5. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for further details.
Table 2. Voltage Identification Definition
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2.4 Reserved, Unused, and TESTHI Signals
All RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS, VTT, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 4 for a land listing of the processor and the location of all RESERVED lands. In a system level design, on-die termination has been included by the processor to allow signals to be terminated within the processor silicon. Most unused GTL+ inputs should be left as no connects as GTL+ termination is provided on the processor silicon. However, see Table 7 for details on GTL+ signals that do not include on-die termination. Unused active high inputs, should be connected through a resistor to ground (VSS). Unused outputs can be left unconnected, however this may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. Resistor values should be within ± 20% of the impedance of the motherboard trace for front side bus signals. For unused GTL+ input or I/O signals, use pull-up resistors of the same value as the on-die termination resistors (RTT). For details see Table 14. TAP and CMOS signals do not include on-die termination. Inputs and utilized outputs must be terminated on the motherboard. Unused outputs may be terminated on the motherboard or left unconnected. Note that leaving unused outputs unterminated may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. All TESTHI[13,11:10,7:0] lands should be individually connected to V TT via a pull-up resistor which matches the nominal trace impedance. The TESTHI signals may use individual pull-up resistors or be grouped together as detailed below. A matched resistor must be used for each group:
- T E S T H I [ 1 : 0 ]
- T E S T H I [ 7 : 2 ]
- TESTHI10 – cannot be groupe d with other TESTHI signals
- TESTHI11 – cannot be groupe d with other TESTHI signals
- TESTHI13 – cannot be groupe d with other TESTHI signals However, use of boundary scan test will not be functional if these lands are connected together. For optimum noise margin, all pull-up resistor values used for TESTHI[13,11:10,7:0] lands should have a resistance value within ±20% of the impedance of the board transmission line traces. For example, if the nominal trace impedance is 50 Ω, then a value between 40 Ω and 60 Ω should be used.
2.5 Voltage and Current Specification
2.5.1 Absolute Maximum and Minimum Ratings
long-term reliability can be expected. Table 3. Absolute Maximu m and Minimum Ratings
- For functional operation, all processor electrical, signal qu ality, mechanical and thermal
specifications must be satisfied.
- Excessive overshoot or undershoot on any signal wi ll likely result in permanent damage to the
- Storage temperature is applicable to storage co nditions only. In this scenario, the processor
processor case temperature specifications.
- This rating applies to the processor and does not include any tray or packaging.
- Failure to adhere to this specification can affect the long term reliability of the processor.
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2.5.2 DC Voltage and Current Specification
Table 4. Voltage and Current Specifications
- Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data.
These specifications will be updated with characterized data from silicon measurements at a later date.
- Adherence to the voltage specifications for the processor are required to ensure reliable processor operation.
- Each processor is programmed with a maximum valid voltage identification value (VID), which is set at
® Technology, or Extended HALT State).
3.00 GHz
2.93 GHz
2.66 GHz
2.40 GHz
- These voltages are targets only. A variable voltage source should exist on systems in the event that a different
voltage is required. See Section 2.3 and Table 2 for more information.
- The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket
with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 M Ω minimum impedance. system is not coupled into the oscilloscope probe.
- Refer to Table 5 and Figure 1 for the minimum, typical, and maximum V CC allowed for a given current. The
- These processors have CPUID = 06F7h
7.0 A 13
- ICC_MAX specification is based on the VCC_MAX loadline. Refer to Figure 1 for details.
- These Processors have CPUID = 06FBh
indicated by the assertion of PROCHOT#) is the same as the maximum ICC for the processor. 12.Baseboard bandwidth is limited to 20 MHz. Power Delivery Design Guidelines For Desktop LGA775 Socket to determine the total ITT drawn by the system. This parameter is based on design characterization and is not tested. Table 5. V CC Static and Transient Tolerance
- The loadline specification includes both static and transient limits except for overshoot allowed
- This table is intended to aid in reading discrete points on Figure 1.
- The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE
Guidelines For Desktop LGA775 Socket for socket loadline guidelines and VR implementation details.
- Adherence to this loadline specification is required to ensure reliable processor operation.
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- The loadline specification includes both static and transient limits except for overshoot
allowed as shown in Section 2.5.3.
- This loadline specification shows the deviation from the VID set point.
- The loadlines specify voltage limits at the die measured at the VCC_SENSE and
guidelines and VR implementation details. Figure 1. V CC Static and Transient Tolerance
2.5.3 V CC Overshoot
cannot exceed VID + VOS_MAX (VOS_MAX is the maximum allowable overshoot voltage). processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands.
- V OS is measured overshoot voltage.
- T OS is measured time duration above VID.
2.5.4 Die Voltage Validation
Table 6. V CC Overshoot Specifications
- Adherence to these specifications is requir ed to ensure reliable processor operation.
Figure 2. V CC Overshoot Example Waveform
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2.6 Signaling Specifications
critical than with previous processor families. bus on the motherboard for most GTL+ signals.
2.6.1 FSB Signal Groups
group as well as the GTL+ I/O group when driving. Table 7. FSB Signal Groups (Sheet 1 of 2)
- Refer to Section 4.2 for signal descriptions.
- In processor systems where no debug port is implemented on the system board, these
implemented on the system board, these signals are no connects.
- The value of these signals during the acti ve-to-inactive edge of RESET# defines the
processor configuration options. See Section 6.1 for details.
- PROCHOT# signal type is open drain output and CMOS input.
Table 7. FSB Signal Groups (Sheet 2 of 2) Table 8. Signal Characteristics
- Signals that do not have RTT, nor are actively driven to their high-voltage level.
Table 9. Signal Reference Voltages
- These signals also have hysteresis added to the reference voltage. See Table 11 for more
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2.6.2 CMOS and Open Drain Signals
requirements for entering and leaving the low power states.
2.6.3 Processor DC Specifications
Table 10. GTL+ Signal Group DC Specifications
- Unless otherwise noted, all specifications in this table apply to all processor frequencies.
- VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low
- The VTT referred to in these specifications is the instantaneous VTT.
- VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high
- VIH and VOH may experience excursions above VTT.
- Leakage to VSS with land held at VTT.
- Leakage to VTT with land held at 300 mV.
Table 11. Open Drain and TAP Output Signal Group DC Specifications
- Unless otherwise noted, all specifications in this table apply to all processor frequencies.
- V OH is determined by the value of the external pull-up resister to VTT.
- For Vin between 0 and VOH.
- V TT supplies the PECI interface. PECI behavior does not affect VTT min/max specifications.
Refer to Table 4 for VTT specifications.
- The leakage specification applies to powered devices on the PECI bus.
- The input buffers us e a Schmitt-triggered input design for improved noise immunity.
Table 12. CMOS Signal Group DC Specifications
- Unless otherwise noted, all specifications in this table apply to all processor frequencies.
- VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low
- The VTT referred to in these specifications refers to instantaneous VTT.
- VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high
- VIH and VOH may experience excursions above VTT.
- All outputs are open drain.
- Leakage to VSS with land held at VTT.
- Leakage to VTT with land held at 300 mV
Table 13. PECI DC Electrical Limits
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2.6.3.1 GTL+ Front Side Bus Specifications
precision voltage divider circuits.
2.7 Clock Specifications
2.7.1 Front Side Bus Clock (BCL K[1:0]) and Processor Clocking
default ratio during manufacturing. processor clocking, contact your Intel field representative. Table 14. GTL+ Bus Voltage Definitions
- Unless otherwise noted, all specifications in this table apply to all processor frequencies.
- GTLREF is to be generated from V TT by a voltage divider of 1% resistors (one divider for each
GTLEREF land). Refer to the applicable platform design guide for implementation details.
- RTT is the on-die termination resistance measured at VTT/3 of the GTL+ output driver.
- COMP resistance must be prov ided on the system board with 1% resistors. COMP[3:0] and
Table 15. Core Frequency to FSB Multiplier Configuration
1066 MHz FSB)
1333 MHz FSB)
- Individual processors operate only at or below the rated frequency.
- Listed frequencies are not necessarily committed production frequencies.
2.7.2 FSB Frequency Select Signals (BSEL[2:0])
frequency). Individual processors will only operate at their specified FSB frequency.
2.7.3 Phase Lock Loop (PLL) and Filter
used for the PLL. Refer to Table 4 for DC specifications. Table 16. BSEL[2:0] Frequency Table for BCLK[1:0]
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2.7.4 BCLK[1:0] Specifications
Table 17. Front Side Bus Diffe rential BCLK Specifications
- Unless otherwise noted, all specifications in this table apply to all processor frequencies.
- "Steady state" voltage, not including overshoot or undershoot.
- Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0
equals the falling edge of BCLK1.
- The crossing point must meet the absolute and relative crossing point specifications
- VHavg is the statistical average of the VH measured by the oscilloscope.
- Overshoot is defined as the absolute value of the maximum voltage. Undershoot is defined as
the absolute value of the minimum voltage.
- Measurement taken from differential waveform.
Table 18. FSB Differential Clock Specifications (1066 MHz FSB)
- Unless otherwise noted, all specifications in this table apply to all processor core frequencies
based on a 266 MHz BCLK[1:0].
- Duty Cycle (High time/Period) must be between 40 and 60%.
- The period specified here is the average period. A given period may vary from this specification
- In this context, period stability is defined as the worst case timing difference between successive
periods must be less than the period stability.
- Measurement taken from differential waveform.
- Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured
use for the edge rate calculations.
Table 19. FSB Differential Cloc k Specifications (1333 MHz FSB)
- Unless otherwise noted, all specifications in this table apply to all processor core frequencies
based on a 333 MHz BCLK[1:0].
- Duty Cycle (High time/Period) must be between 40 and 60%.
- The period specified here is the average period. A given period may vary from this specification
- For the clock jitter specification, refer to the CK505 Clock Synthesizer/Driver Specification.
- In this context, period stability is defined as the worst case timing difference between successive
periods must be less than the period stability.
- Measurement taken from differential waveform.
- Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured
use for the edge rate calculations. Slew rate matching is a single ended measurement. Figure 3. Differential Clock Waveform
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Figure 4. Differential Clock Crosspoint Specification Figure 5. Differential Measurements
3 Package Mechanical
LGA775 Socket Mechanical Design Guide for complete details on the LGA775 socket.
- Integrated Heat Spreader (IHS)
- Thermal Interface Material (TIM)
- Processor core (die)
- Package substrate
- Capacitors NOTE: 1. Socket and motherboard are included for refe rence and are not part of processor package.
3.1 Package Mechanical Drawing
- Package reference with tolerances (total height, length, width, etc.)
- IHS parallelism and tilt
- Land dimensions
- Top-side and back-side component keep-out dimensions
- Reference datums
- All drawing dimensions are in mm [in].
- Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal and Mechanical Design Guidelines.
Figure 6. Processor Package Assembly Sketch
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Figure 7. Processor Package Drawing Sheet 1 of 3
Figure 8. Processor Package Drawing Sheet 2 of 3
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Figure 9. Processor Package Drawing Sheet 3 of 3
3.2 Processor Component Keep-Out Zones
manufacturing efficiencies but will remain within the component keep-in.
3.3 Package Loading Specifications
Table 20 provides dynamic and static load specifications for the processor package. maintained by any thermal and mechanical solutions.
3.4 Package Handling Guidelines
handling loads may be experienced during heatsink removal. Table 20. Processor Lo ading Specifications
- These specifications apply to uniform compressive loading in a direction normal to the
- This is the maximum force that can be applied by a heatsink retention clip. The clip must also
provide the minimum specified load on the processor package.
- These specifications are based on limited testing for design characterization. Loading limits are
for the package only and do not include the limits of the processor socket.
- Dynamic loading is defined as an 11 ms duration average load superimposed on the static load
Table 21. Package Handling Guidelines
- A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface.
- These guidelines are based on limited testing for design characterization.
- A tensile load is defined as a pulling load appl ied to the IHS in a direction normal to the IHS
- A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the
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3.5 Package Insertion Specifications
3.6 Processor Mass Specification
the components that are included in the package.
3.7 Processor Materials
Table 22 lists some of the package components and associated materials.
3.8 Processor Markings
identification of the processor. Table 22. Processor Materials Figure 10. Processor Top-Side Markin gs Example for 1066 MHz Processors
Figure 11. Processor Top- Side Markings Example for 1333 MHz Processors
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3.9 Processor Land Coordinates
referred to throughout the document to identify processor lands. Figure 12. Processor Land Coordinates and Quadrants (Top View)
Land Listing and Signal Descriptions
4 Land Listing and Signal
This chapter provides the processor land assignment and signal descriptions.
4.1 Processor Land Assignments
This section contains the land listings for the processor. The land-out footprint is shown in Figure 13 and Figure 14. These figures represent the land-out arranged by land number and they show the physical location of each signal on the package land array (top view). Table 23 is a listing of all processor lands ordered alphabetically by land (signal) name. Table 24 is also a listing of all processor lands; the ordering is by land number.
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Figure 13. land-out Diagram (Top View – Left Side)
Figure 14. land-out Diagram (Top View – Right Side)
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Table 23. Alphabetical Land
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Table 24. Numerical Land
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4.2 Alphabetical Signals Reference
Table 25. Signal Descript ion (Sheet 1 of 9) configuration. See Section 6.1 for more details. Output Write bus transaction. operations associated with the new transaction. drive their outputs and latch their inputs. current bus owner cannot issue any new transactions.
associated with core 0. BPMb[3:0]# are associated with core 1. for termination requirements. completed, then releases the bus by de-asserting BPRI#. signal is sampled to determine the agent ID = 0. including termination recommendations refer to Section 2.7.2. board using precision resistors. Table 25. Signal Description (Sheet 2 of 9)
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asserts DRDY# to indicate a valid data transfer. data signals correspond to a pair of one DSTBP# and one DSTBN#. group is inverted and therefore sampled active high. signals for that particular sub-phase for that 16-bit group. connect in the system. DBR# is not a processor signal. Table 25. Signal Descript ion (Sheet 3 of 9)
of all processor FSB agents. clock data transfer, DRDY# may be de-asserted to insert idle clocks. DSTBN[3:0]# are the data strobes used to latch in D[63:0]#. DSTBP[3:0]# are the data strobes used to latch in D[63:0]#. Identification and the CPUID Instruction application note. signal is a logical 0 or logical 1. Table 25. Signal Description (Sheet 4 of 9)
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be continued by reasserting HIT# and HITM# together. for termination requirements. no effect when the NE bit in control register 0 (CR0) is set. Output Write bus transaction. appropriate pins/lands of all processor FSB agents. systems where no debug port is implemented on the system board. Pentium processor. Both signals are asynchronous. Table 25. Signal Descript ion (Sheet 5 of 9)
end of the last transaction. the processor FSB, it will wait until it observes LOCK# de-asserted. before a subsequent rising edge of PWRGOOD. should be driven high throughout boundary scan operation. signals are source synchronous to ADSTB0#. asserted for more than 10 ms while PWRGOOD is asserted. configuration options are described in the Section 6.1. terminated on the system board. Table 25. Signal Description (Sheet 6 of 9)
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if the processor is present. processor begins program execution from the SMM handler. processor will tri-state its outputs. signals to all processor core units except the FSB and APIC units. STPCLK# is an asynchronous input. (also known as the Test Access Port). processor operation. See Section 2.4 for more details. Table 25. Signal Descript ion (Sheet 7 of 9)
(provided VTT and VCC are valid). must connect the appropriate pins/lands of all FSB agents. must be driven low during power on Reset. these pins is determined by the VID[7:0] pins. VCCPLL Input VCCPLL provides isolated po wer for internal processor FSB PLLs. the silicon with little noise.
11.0 Processor Power Delivery Design Guidelines For Desktop
disabled until the voltage supply for the VID signals becomes valid. specification variations. See Table 2 for definitions of these signals. Desktop LGA775 Socket for more information. Table 25. Signal Description (Sheet 8 of 9)
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VSSA Input VSSA is the isolated ground for internal PLLs. VTT Miscellaneous voltage supply. Table 25. Signal Descript ion (Sheet 9 of 9)
Thermal Specifications and Design Considerations
5 Thermal Specifications and
5.1 Processor Thermal Specifications
The processor requires a thermal solution to maintain temperatures within the operating limits as set forth in Section 5.1.1. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems. Maintaining the proper thermal environment is key to reliable, long-term system operation. A complete thermal solution includes both component and system level thermal management features. Component level thermal solutions can include active or passive heatsinks attached to the processor Integrated Heat Spreader (IHS). Typical system level thermal solutions may consist of system fans combined with ducting and venting. For more information on designing a component level thermal solution, refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2). Note: The boxed processor will ship with a component thermal solution. Refer to Chapter 7 for details on the boxed processor.
5.1.1 Thermal Specifications
To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed such that the processor remains within the minimum and maximum case temperature (T specifications when operating at or below the Thermal Design Power (TDP) value listed per frequency in Table 26. Thermal solutions not designed to provide this level of thermal capability may affect the long-term reliability of the processor and system. For more details on thermal solution design, refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2). The processor uses a methodology for managing processor temperatures which is intended to support acoustic noise reduction through fan speed control. Selection of the appropriate fan speed is based on the relative temperature data reported by the processor’s Platform Environment Control Interface (PECI) bus as described in Section 5.3.1.1. The temperature reported over PECI is always a negative value and represents a delta below the onset of thermal control circuit (TCC) activation, as indicated by PROCHOT# (see Section 5.2). Systems that implement fan speed control must be designed to take these conditions in to account. Systems that do not alter the fan speed only need to guarantee the case temperature meets the thermal profile specifications. To determine a processor's case temperature specification based on the thermal profile, it is necessary to accurately measure processor power dissipation. Intel has developed a methodology for accurate power measurement that correlates to Intel test temperature and voltage conditions. Refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2).
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Table 26. Processor Thermal Specifications
- Specification is at 50 °C TC and typical voltage loadline.
- 775_VR_CONFIG_05B guidelines provide a design ta rget for meeting future thermal requirements.
5 See
- Thermal Design Power (TDP) should be used for processor thermal solution design targets. The TDP is not
the maximum power that the processor can dissipate.
- This table shows the maximum TDP for a given frequency range. Individual processors may have a lower
thermal profile figure and associated table for the allowed combinations of power and TC.
- These processors have CPUID = 06F7h
- These processors have CPUID = 06FBh
Table 27. Thermal Profile for 130 W Processors Figure 15. Thermal Profile for 130 W Processors
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Table 28. Thermal Profil e for 105 W Processors Figure 16. Thermal Prof ile for 105 W Processors
Table 29. Thermal Profile 95 W Processors Figure 17. Thermal Profile 95 W Processors
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5.1.2 Thermal Metrology
Table 26. This temperature specification is meant to help ensure proper operation of refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2).
5.2 Processor Thermal Features
5.2.1 Thermal Monitor
Figure 18. Case Temperature (T
Thermal Specifications and Design Considerations under-designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss, and in some cases may result in a TC that exceeds the specified maximum temperature and may affect the long-term reliability of the processor. In addition, a thermal solution that is significantly under-designed may not be capable of cooling the processor even when the TCC is active continuously. Refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2) for information on designing a thermal solution. The duty cycle for the TCC, when activated by the Thermal Monitor, is factory configured and cannot be modified. The Thermal Monitor does not require any additional hardware, software drivers, or interrupt handling routines.
5.2.2 Thermal Monitor 2
The processor also supports an additional power reduction capability known as Thermal Monitor 2. This mechanism provides an efficient means for limiting the processor temperature by reducing the power consumption within the processor. When Thermal Monitor 2 is enabled, and a high temperature situation is detected, the Thermal Control Circuit (TCC) will be activated. The TCC causes the processor to adjust its operating frequency (via the bus multiplier) and input voltage (via the VID signals). This combination of reduced frequency and VID results in a reduction to the processor power consumption. A processor enabled for Thermal Monitor 2 includes two operating points, each consisting of a specific operating frequency and voltage. The first operating point represents the normal operating condition for the processor. Under this condition, the core-frequency-to-FSB multiple utilized by the processor is that contained in the CLOCK_FLEX_MAX MSR and the VID is that specified in Table 4. These parameters represent normal system operation. The second operating point consists of both a lower operating frequency and voltage. When the TCC is activated, the processor automatically transitions to the new frequency. This transition occurs very rapidly (on the order of 5 μs). During the frequency transition, the processor is unable to service any bus requests, and consequently, all bus traffic is blocked. Edge-triggered interrupts will be latched and kept pending until the processor resumes operation at the new frequency. Once the new operating frequency is engaged, the processor will transition to the new core operating voltage by issuing a new VID code to the voltage regulator. The voltage regulator must support dynamic VID steps in order to support Thermal Monitor 2. During the voltage change, it will be necessary to transition through multiple VID codes to reach the target operating voltage. Each step will likely be one VID table entry (see Table 4). The processor continues to execute instructions during the voltage transition. Operation at the lower voltage reduces the power consumption of the processor. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near its maximum operating temperature. Once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the operating frequency and voltage transition back to the normal system operating point. Transition of the VID code will occur first, in order to insure proper operation once the processor reaches its normal operating frequency. Refer to Figure 19 for an illustration of this ordering.
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regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled.
5.2.3 On-Demand Mode
Figure 19. Thermal Monitor 2 Frequency and Voltage Ordering
Thermal Specifications and Design Considerations
5.2.4 PROCHOT# Signal
An external signal, PROCHOT# (processor hot), is asserted when the processor core temperature has reached its maximum operating temperature. If the Thermal Monitor is enabled (note that the Thermal Monitor must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or de- assertion of PROCHOT#. As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that one or both cores has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled. As an input, assertion of PROCHOT# by the system will activate the TCC, if enabled, for both cores. The TCC will remain active until the system de-asserts PROCHOT#. PROCHOT# allows for some protection of various components from over-temperature situations. The PROCHOT# signal is bi-directional in that it can either signal when the processor (either core) has reached its maximum operating temperature or be driven from an external source to activate the TCC. The ability to activate the TCC via PROCHOT# can provide a means for thermal protection of system components. PROCHOT# can allow VR thermal designs to target maximum sustained current instead of maximum current. Systems should still provide proper cooling for the VR, and rely on PROCHOT# only as a backup in case of system cooling failure. The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its Thermal Design Power. With a properly designed and characterized thermal solution, it is anticipated that PROCHOT# would only be asserted for very short periods of time when running the most power intensive applications. An under-designed thermal solution that is not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may cause a noticeable performance loss. Refer to the the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for details on implementing the bi-directional PROCHOT# feature.
5.2.5 THERMTRIP# Signal
Regardless of whether or not Thermal Monitor or Thermal Monitor 2 is enabled, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in Table 25). At this point, the FSB signal THERMTRIP# will go active and stay active as described in Table 25. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles. If THERMTRIP# is asserted, processor core voltage CC) must be removed within the timeframe defined in Table 10.
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5.3 Platform Environment Control Interface (PECI)
5.3.1 Introduction
by default and must be enabled through BIOS.
5.3.1.1 T CONTROL and TCC Activation on PECI-Based Systems
fan control diagram using PECI temperatures. Figure 20. Conceptual Fan Control on PECI-Based Platforms
5.3.2 PECI Specifications
5.3.2.1 PECI Device Address
5.3.2.2 PECI Command Support
5.3.2.3 PECI Fault Handling Requirements
however, certain scenarios where the PECI is known to be unresponsive. data is not available via PECI. software in the event of a critical or continuous fault condition.
5.3.2.4 PECI GetTemp0() and Ge tTemp1() Error Code Support
Table 30. GetTemp0() and GetTemp1() Error Codes
Thermal Specifications and Design Considerations
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Features
6 Features
6.1 Power-On Configuration Options
Several configuration options can be configured by hardware. The processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 31. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset. All resets reconfigure the processor; for reset purposes, the processor does not distinguish between a "warm" reset and a "power-on" reset.
6.2 Clock Control and Low Power States
The processor allows the use of AutoHALT and Stop Grant states to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. See Figure 21 for a visual representation of the processor low power states. Table 31. Power-On Configuration Option Signals
- Asserting this signal during RESET# will select the corresponding option.
- Address signals not identified in this table as configuration options should not
- Disabling of any of the cores within the processor must be handled by
for the disabling of a single core per die within the package.
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6.2.1 Normal State
This is the normal operating state for the processor.
6.2.2 HALT and Extended HALT Powerdown States
The processor supports the HALT or Extended HALT powerdown state. The Extended HALT Powerdown must be enabled via the BIOS for the processor to remain within its specification. The Extended HALT state is a lower power state as compared to the Stop Grant State. If Extended HALT is not enabled, the default Powerdown state entered will be HALT. Refer to the sections below for details about the HALT and Extended HALT states.
6.2.2.1 HALT Powerdown State
HALT is a low power state entered when all the processor cores have executed the HALT or MWAIT instructions. When one of the processor cores executes the HALT instruction, that processor core is halted, however, the other processor continues normal operation. The processor will transition to the Normal state upon the occurrence of SMI#, INIT#, or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize itself. The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the HALT Power Down state. See the Intel Architecture Software Developer's Manual, Volume III: System Programmer's Guide for more information. Figure 21. Processor Low Power State Machine
The system can generate a STPCLK# while the processor is in the HALT Power Down state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state. While in HALT Power Down state, the processor will process bus snoops.
6.2.2.2 Extended HALT Powerdown State
Extended HALT is a low power state entered when all processor cores have executed the HALT or MWAIT instructions and Extended HALT has been enabled via the BIOS. When one of the processor cores executes the HALT instruction, that logical processor is halted; however, the other processor continues normal operation. The Extended HALT Powerdown must be enabled via the BIOS for the processor to remain within its specification. Not all processors are capable of supporting Extended HALT State. More details on which processor frequencies will support this feature will be provided in future releases of the Intel ® Core™2 Extreme Quad-Core Processor QX6700 and Intel® Core™2 Quad Processor Q6000 Sequence Specification Update when available. The processor will automatically transition to a lower frequency and voltage operating point before entering the Extended HALT state. Note that the processor FSB frequency is not altered; only the internal core frequency is changed. When entering the low power state, the processor will first switch to the lower bus ratio and then transition to the lower VID. While in Extended HALT state, the processor will process bus snoops. The processor exits the Extended HALT state when a break event occurs. When the processor exits the Extended HALT state, it will first transition the VID to the original value and then change the bus ratio back to the original value.
6.2.3 Stop Grant State
When the STPCLK# signal is asserted, the Stop Grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. The processor will issue two Stop Grant Acknowledge special bus cycles, once for each die. Once the STPCLK# pin has been asserted, it may only be deasserted once the processor is in the Stop Grant state. All processor cores will enter the Stop Grant state once the STPCLK# pin is asserted. Additionally, all processor cores must be in the Stop Grant state before the deassertion of STPCLK#. Since the GTL+ signals receive power from the FSB, these signals should not be driven (allowing the level to return to V TT) for minimum power drawn by the termination resistors in this state. In addition, all other input signals on the FSB should be driven to the inactive state. RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop Grant state. A transition back to the Normal state will occur with the de- assertion of the STPCLK# signal. A transition to the Grant Snoop state will occur when the processor detects a snoop on the FSB (see Section 6.2.4). While in the Stop Grant State, SMI#, INIT#, and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal State. Only one occurrence of each event will be recognized upon return to the Normal state. While in Stop Grant state, the processor will process a FSB snoop.
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6.2.4 Extended HALT Snoo p or HALT Snoop State,
The Extended HALT Snoop State is used in conjunction with the new Extended HALT state. If Extended HALT state is not enabled in the BIOS, the default Snoop State entered will be the HALT Snoop State. Refer to the sections below for details on HALT Snoop State, Grant Snoop State and Extended HALT Snoop State.
6.2.4.1 HALT Snoop State, Stop Grant Snoop State
The processor will respond to snoop transactions on the FSB while in Stop Grant state or in HALT Power Down state. During a snoop transaction, the processor enters the HALT Snoop State:Stop Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the FSB). After the snoop is serviced, the processor will return to the Stop Grant state or HALT Power Down state, as appropriate.
6.2.4.2 Extended HALT Snoop State
The Extended HALT Snoop State is the default Snoop State when the Extended HALT state is enabled via the BIOS. The processor will remain in the lower bus ratio and VID operating point of the Extended HALT state. While in the Extended HALT Snoop State, snoops are handled the same way as in the HALT Snoop State. After the snoop is serviced the processor will return to the Extended HALT state. § §
7 Boxed Processor Specifications
mechanical representation of a boxed processor. Guidelines (see Section 1.2). NOTE: The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink. Figure 22. Mechanical Represen tation of the Boxed Processor
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7.1 Mechanical Specifications
7.1.1 Boxed Processor Cooling Solution Dimensions
mechanical representation of the boxed processor. assembled fan heatsink are shown in Figure 23 (Side View), and Figure 24 (Top View). (marked with alphabetic designations) to clarify relative dimensioning. Figure 23. Space Requir ements for the Boxed Processor (Side View)
Boxed Processor Specifications
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7.1.2 Boxed Processor Fan Heatsink Weight
The boxed processor fan heatsink will not weigh more than 550 grams. Refer to Chapter 5 and the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2) for details on the processor weight and heatsink requirements.
7.1.3 Boxed Processor Retention Mechanism and Heatsink
The boxed processor thermal solution requires a heatsink attach clip assembly, to secure the processor and fan heatsink in the baseboard socket. The boxed processor will ship with the heatsink attach clip assembly.
7.2 Electrical Requirements
7.2.1 Fan Heatsink Power Supply
The boxed processor's fan heatsink requires a +12 V power supply. A fan power cable will be shipped with the boxed processor to draw power from a power header on the baseboard. The power cable connector and pinout are shown in Figure 26. Baseboards must provide a matched power header to support the boxed processor. Table 32 contains specifications for the input and output signals at the fan heatsink connector. The fan heatsink outputs a SENSE signal, which is an open- collector output that pulses at a rate of 2 pulses per fan revolution. A baseboard pull-up resistor provides V OH to match the system board-mounted fan speed monitor requirements, if applicable. Use of the SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector should be tied to GND. The fan heatsink receives a PWM signal from the motherboard from the 4th pin of the connector labeled as CONTROL. The boxed processor's fanheat sink requires a constant +12 V supplied to pin 2 and does not support variable voltage control or 3-pin PWM control. The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it. The power header identification and location should be documented in the platform documentation, or on the system board itself. Figure 27 shows the location of the fan power connector relative to the processor socket. The baseboard power header should be positioned within 110 mm [4.33 inches] from the center of the processor socket.
Figure 26. Boxed Processo r Fan Heatsink Power Cable Connector Description Table 32. Fan Heatsink Powe r and Signal Specifications
- Baseboard should pull this pin up to 5 V with a resistor.
- Open drain type, pulse width modulated.
- Fan will have pull-up resistor to 4.75 V maximum of 5.25 V.
polarizing ribs and friction locking ramp. 0.100" pitch, 0.025" square pin width.
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7.3 Thermal Specifications
7.3.1 Boxed Processor Cooling Requirements
for the fan heatsink. The air temperature entering the fan should be kept below 39 ºC. Figure 27. Baseboard Power Header Pl acement Relative to Processor Socket
Boxed Processor Specifications
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7.3.2 Fan Speed Control Operation (Intel ® Core™2 Extreme
processors only) The boxed processor fan heatsink is designed to operate continuously at full speed to allow maximum user control over fan speed. The fan speed can be controlled by hardware and software from the motherboard. This is accomplished by varying the duty cycle of the Control signal on the 4th pin (see Table 32). The motherboard must have a 4-pin fan header and must be designed with a fan speed controller with PWM output and Digital Thermometer measurement capabilities. For more information on specific motherboard requirements for 4-wire based fan speed control refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2). The Internal chassis temperature should be kept below 39 ºC. Meeting the processor's temperature specification (see Chapter 5) is the responsibility of the system integrator. The motherboard must supply a constant +12 V to the processor's power header to ensure proper operation of the fan for the boxed processor. See Table 32 for specific requirements.
7.3.3 Fan Speed Control Operation (Intel ® Core™2 Quad
processor) If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin motherboard header it will operate as follows: The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures. This allows the processor fan to operate at a lower speed and noise level, while internal chassis temperatures are low. If internal chassis temperature increases beyond a lower set point, the fan speed will rise linearly with the internal temperature until the higher set point is reached. At that point, the fan speed is at its maximum. As fan speed increases, so does fan noise levels. Systems should be designed to provide adequate air around the boxed processor fan heatsink that remains cooler then lower set point. These set points, represented in Figure 30 and Table 33, can vary by a few degrees from fan heatsink to fan heatsink. The internal chassis temperature should be kept below 38 ºC. Meeting the processor's temperature specification (see Chapter 5) is the responsibility of the system integrator. The motherboard must supply a constant +12 V to the processor's power header to ensure proper operation of the variable speed fan for the boxed processor. Refer to Table 32 for the specific requirements.
system integrators to have a quieter system in the most common usage. processor temperature instead of internal ambient chassis temperatures. Figure 30. Boxed Processo r Fan Heatsink Set Points Table 33. Fan Heatsink Powe r and Signal Specifications this set point, the fan operates at its lowest speed. nominal operating environment.
- Set point variance is approximately ± 1 °C from fan heatsink to fan heatsink.
fan operates between its lowest and highest speeds. worst-case operating environment.
Boxed Processor Specifications
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If the new 4-pin active fan heat sink solution is connected to an older 3-pin baseboard processor fan header it will default back to a thermistor controlled mode, allowing compatibility with existing 3-pin baseboard designs. Under thermistor controlled mode, the fan RPM is automatically varied based on the Tinlet temperature measured by a thermistor located at the fan inlet. For more details on specific motherboard requirements for 4-wire based fan speed control refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2). § §
Debug Tools Specifications
8 Debug Tools Specifications
8.1 Logic Analyzer Interface (LAI)
Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging systems. Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature. Specific information must be obtained from the logic analyzer vendor. Due to the complexity of systems, the LAI is critical in providing the ability to probe and capture FSB signals. There are two sets of considerations to keep in mind when designing a r system that can make use of an LAI: mechanical and electrical.
8.1.1 Mechanical Considerations
The LAI is installed between the processor socket and the processor. The LAI lands plug into the processor socket, while the processor lands plug into a socket on the LAI. Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer. The maximum volume occupied by the LAI, known as the keepout volume, as well as the cable egress restrictions, should be obtained from the logic analyzer vendor. System designers must make sure that the keepout volume remains unobstructed inside the system. Note that it is possible that the keepout volume reserved for the LAI may differ from the space normally occupied by the processor’s heatsink. If this is the case, the logic analyzer vendor will provide a cooling solution as part of the LAI.
8.1.2 Electrical Considerations
The LAI will also affect the electrical performance of the FSB; therefore, it is critical to obtain electrical load models from each of the logic analyzers to be able to run system level simulations to prove that their tool will work in the system. Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution it provides. § §
Debug Tools Specifications