PRIXP425BD

PRIXP425BD INTEL | Alldatasheet

Document overview

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• PDF pages: 112

Technical content

Datasheet sections

• 1.0 Product Features
• 1.1 Product Line Features
• 1.2 Processor Features
• 1.3 About this Document
• 2.0 Functional Overview
• 2.1 Functional Units
• 2.1.1 Network Processor Engines (NPEs)
• 2.1.2 Internal Bus
• 2.1.2.1 North AHB
• 2.1.2.2 South AHB
• 2.1.2.3 APB Bus
• 2.1.3 MII Interfaces
• 2.1.4 UTOPIA
• 2.1.5 USB Interface
• 2.1.6 PCI Controller
• 2.1.7 SDRAM Controller
• 2.1.8 Expansion Bus
• 2.1.9 High-Speed, Serial Interfaces
• 2.1.10 High-Speed and Console UARTs
• 2.1.11 GPIO
• 2.1.12 Internal Bus Performance Monitoring Unit (IBPMU)
• 2.1.13 Interrupt Controller
• 2.1.14 Timers
• 2.1.15 AHB Queue Manager
• 2.2 Intel XScale
• 2.2.1 Super Pipeline
• 2.2.2 Branch Target Buffer (BTB)
• 2.2.3 Instruction Memory Management Unit (IMMU)
• 2.2.4 Data Memory Management Unit (DMMU)
• 2.2.5 Instruction Cache (I-Cache)
• 2.2.6 Data Cache (D-Cache)
• 2.2.7 Mini-Data Cache
• 2.2.8 Fill Buffer (FB) and Pend Buffer (PB)
• 2.2.9 Write Buffer (WB)
• 2.2.10 Multiply-Accumulate Coprocessor (CP0)
• 2.2.11 Performance Monitoring Unit (PMU)
• 2.2.12 Debug Unit
• 3.0 Functional Signal Descriptions
• 4.0 Package and Pinout Information
• 4.1 Package Description
• 4.2 Signal-Pin Descriptions
• 4.3 Package Thermal Specifications
• 4.3.1 Commercial Temperature
• 4.3.2 Extended Temperature

Datasheet sections

• 4 Datasheet
• 5.0 Electrical Specifications
• 5.1 Absolute Maximum Ratings
• 5.2 V CCPLL1, VCCPLL2, VCCOSCP, VCCOSC Pin Requirements
• 5.2.1 V CCPLL1 Requirement
• 5.2.2 V CCPLL2 Requirement
• 5.2.3 V CCOSCP Requirement
• 5.2.4 V CCOSC Requirement
• 5.3 RCOMP Pin Requirements
• 5.4 DC Specifications
• 5.4.1 Operating Conditions
• 5.4.2 PCI DC Parameters
• 5.4.3 USB DC Parameters
• 5.4.4 UTOPIA-2 DC Parameters
• 5.4.5 MII DC Parameters
• 5.4.6 MDIO DC Parameters
• 5.4.7 SDRAM Bus DC Parameters
• 5.4.8 Expansion Bus DC Parameters
• 5.4.9 High-Speed, Serial Interface 0 DC Parameters
• 5.4.10 High-Speed, Serial Interface 1 DC Parameters
• 5.4.11 High-Speed and Console UART DC Parameters
• 5.4.12 GPIO DC Parameters
• 5.4.13 JTAG DC Parameters
• 5.4.14 Reset DC Parameters
• 5.5 AC Specifications
• 5.5.1 Clock Signal Timings
• 5.5.1.1 Processor Clock Timings
• 5.5.1.2 PCI Clock Timings
• 5.5.1.3 MII Clock Timings
• 5.5.1.4 UTOPIA-2 Clock Timings
• 5.5.1.5 Expansion Bus Clock Timings
• 5.5.2 Bus Signal Timings
• 5.5.2.1 PCI
• 5.5.2.2 USB Interface
• 5.5.2.3 UTOPIA-2
• 5.5.2.4 MII
• 5.5.2.5 MDIO
• 5.5.2.6 SDRAM Bus
• 5.5.2.7 Expansion Bus
• 5.5.2.8 High-Speed, Serial Interfaces
• 5.5.2.9 JTAG
• 5.5.3 Reset Timings
• 5.6 Power Sequence

Datasheet sections

• 1 Intel ® IXP425 Network Processor Block Diagram
• 2 Intel ® IXP422 Network Processor Block Diagram
• 3 Intel ® IXP421 Network Processor Block Diagram
• 4 Intel ® IXP420 Network Processor Block Diagram
• 5 Intel XScale ® Core Block Diagram
• 7 Package Markings
• 10 V CCOSCP Power Filtering Diagram
• 11 V CCOSC Power Filtering Diagram
• 12 RCOMP Pin External Resistor Requirements
• 13 Typical Connection to a Crystal
• 14 Typical Connection to an Oscillator
• 15 PCI Output Timing
• 16 PCI Input Timing
• 17 UTOPIA-2 Input Timings
• 18 UTOPIA-2 Output Timings
• 19 MII Output Timings
• 20 MII Input Timings
• 21 MDIO Output Timings
• 22 MDIO Input Timings
• 23 SDRAM Input Timings
• 24 SDRAM Output Timings
• 25 Intel Multiplexed Mode
• 26 Intel Simplex Mode
• 27 Motorola* Multiplexed Mode
• 28 Motorola* Simplex Mode
• 29 HPI – 8 Mode Write Accesses
• 30 HPI-16 Multiplex Write Mode
• 31 HPI-16 Multiplex Read Mode
• 32 HPI-16 Non-Multiplex Read Mode
• 34 High-Speed, Serial Timings
• 37 Reset Timings
• 38 Power-up Sequence Timing

Datasheet sections

• 6 Datasheet
• 1 Processor Features
• 2 Related Documents
• 3 Processor Functions
• 4 Signal Type Definitions
• 5 SDRAM Interface
• 6 PCI Controller
• 7 High-Speed, Serial Interface
• 8 High-Speed, Serial Interface
• 9 MII Interfaces
• 10 UTOPIA-2 Interface
• 11 Expansion Bus Interface
• 12 UART Interfaces
• 13 USB Interface
• 14 Oscillator Interface
• 15 GPIO Interface
• 16 JTAG Interface
• 17 System Interface
• 18 Power Interface
• 19 Part Numbers
• 20 Ball Map Assignment for the Intel ® IXP425 Network Processor
• 21 Ball Map Assignment for the Intel ® IXP422 Network Processor
• 22 Ball Map Assignment for the Intel ® IXP421 Network Processor
• 23 Ball Map Assignment for the Intel ® IXP420 Network Processor
• 24 Operating Conditions
• 25 PCI DC Parameters
• 27 UTOPIA-2 DC Parameters
• 28 MII DC Parameters
• 29 MDIO DC Parameters
• 30 SDRAM Bus DC Parameters
• 31 Expansion Bus DC Parameters
• 32 High-Speed, Serial Interface 0 DC Parameters
• 33 High-Speed, Serial Interface 1 DC Parameters
• 34 UART DC Parameters
• 35 GPIO DC Parameters
• 36 JTAG DC Parameters
• 37 PWRON_Reset _N DC Parameters
• 38 Device Clock Timings (Oscillator Reference)
• 39 Device Clock Timings (Crystal Reference)
• 40 PCI Clock Timings
• 41 MII Clock Timings
• 42 UTOPIA-2 Clock Timings
• 43 Expansion Bus Clock Timings
• 44 PCI Bus Signal Timings
• 45 UTOPIA-2 Input Timings Values
• 47 MII Output Timings Values

Datasheet sections

• 48 MII Input Timings Values
• 49 MDIO Timings Values
• 50 SDRAM Input Timings Values
• 52 Intel Multiplexed Mode Values
• 53 Intel Simplex Mode Values
• 55 Motorola* Simplex Mode Values
• 56 HPI Timing Symbol Description
• 57 HPI – 8 Mode Write Accesses Values
• 58 Setup/Hold Timing Values
• 59 HPI-16 Multiplexed Write Accesses Values
• 60 HPI-16 Multiplex Read Accesses Values
• 61 HPI-16 Non-Multiplex Read Accesses Values
• 62 HPI-16 Non-Multiplexed Write Accesses Values
• 64 Boundary-Scan Interface Timings Values

Datasheet sections

• 8 Datasheet

Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet Product Features For a complete list of product features, see “Product Features” on page 9. Typical Applications ■ Intel XScale® Core ■ Three Network Processor Engines ■ PCI Interface ■ Two MII Interfaces ■ UTOPIA-2 Interface ■ USB v 1.1 Device Controller ■ Two High-Speed, Serial Interfaces ■ SDRAM Interface ■ Encryption/Authentication ■ High-Speed UART ■ Console UART ■ Internal Bus Performance Monitoring Unit ■ 16 GPIOs ■ Four Internal Timers ■ Packaging —492-pin PBGA —Commercial/Extended Temperature ■ High-Performance DSL Modem ■ High-Performance Cable Modem ■ Residential Gateway ■ SME Router ■ Network Printers ■ Control Plane ■ Integrated Access Device (IAD) ■ Set-Top Box ■ Access Points (802.11a/b/g) ■ Industrial Controllers Document Number: 252479-004 June 2004

Intel® IXP42X Product Line and IXC1100 Control Plane Processor

2 Datasheet

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTELR PRODUCTS. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND/OR USE OF INTEL PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY , OR INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property right s that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725, or by visiting Intel's website at http://www.intel.com. BunnyPeople, Celeron, Chips, Dialogic, EtherExpress, ETOX, FlashFile, i386, i486, i960, iCOMP, InstantIP, Intel, Intel Centrino, Intel Centrino logo, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetMerge, Intel NetStructure, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel Xeon, Intel XScale, IPLink, Itanium, MCS, MMX, MMX logo, Optimizer logo, OverDrive, Paragon, PDCharm, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, Sound Mark, The Computer Inside., Th e Journey Inside, VTune, and Xircom are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © Intel Corporation 2004

Intel® IXP42X Product Line and IXC1100 Control Plane Processor Product Features Datasheet 9

1.0 Product Features

1.1 Product Line Features

Table 1 on page 12 describes which features apply to the Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor.

• Intel XScale® Core (compliant with ARM* architecture) — High-performance processor based on Intel XScale ® Microarchitecture — Seven/eight-stage Intel ® Super-Pipelined RISC Technology — Management unit
• 32-entry, data memory management unit
• 32-entry, instruction memory management unit
• 32-Kbyte, 32-way, set associative instruction cache
• 32-Kbyte, 32-way, set associative data cache
• 2-Kbyte, two-way, set associative mini-data cache
• 128-entry, branch target buffer
• Eight-entry write buffer
• Four-entry fill and pend buffers — Clock speeds:
• 2 6 6 M H z
• 4 0 0 M H z
• 5 3 3 M H z —A R M * Version V5TE Compliant —I n t e l® Media Processing Technology Multiply-accumulate coprocessor — Debug unit Accessible through JTAG port
• Three network processor engines (NPEs) Used to offload typical Layer-2 networking functions such as: — Ethernet filtering —A T M S A R i n g — HDLC
• PCI interface — 32-bit interface — Selectable clock
• 33-MHz clock output
• 0- to 66-MHz clock input — PCI Local Bus Specification, Rev. 2.2 compatible

Intel® IXP42X Product Line and IXC1100 Control Plane Processor Product Features

10 Datasheet

— PCI arbiter supporting up to four external PCI devices (four REQ/GNT pairs) — Host/option capable — Master/target capable — Two DMA channels

• Two MII interfaces — 802.3 MII interfaces — Single MDIO interface to control both MII interfaces
• UTOPIA-2 Interface — Eight-bit interface — Up to 33 MHz clock speed — Five transmit and five receive address lines
• USB v 1.1 device controller — Full-speed capable — Embedded transceiver — 16 endpoints
• Two high-speed, serial interfaces —S i x - w i r e — Supports speeds up to 8.192 MHz — Supports connection to T1/E1 framers — Supports connection to CODEC/SLICs — Eight HDLC Channels
• SDRAM interface — 32-bit data — 13-bit address — 133 MHz — Up to eight open pages simultaneously maintained — Programmable auto-refresh — Programmable CAS/data delay — Support for 8 MB, minimum, up to 256 MB maximum
• Expansion interface — 24-bit address — 16-bit data — Eight programmable chip selects — Supports Intel/Motorola* microprocessors
• Multiplexed-style bus cycles
• Simplex-style bus cycles

Intel® IXP42X Product Line and IXC1100 Control Plane Processor Product Features Datasheet 11

• Encryption/Authentication —D E S —D E S 3 — AES 128-bit and 256-bit
• DSP support for: — Texas Instruments* DSPs supporting HPI-8 bus cycles — Texas Instruments DSPs supporting HPI-16 bus cycles
• High-speed/Console UARTs — 1,200 baud to 921 Kbaud — 16550 compliant — 64-byte Tx and Rx FIFOs — CTS and RTS modem control signals
• Internal bus performance monitoring unit — Seven 27-bit event counters — Monitoring of internal bus occurrences and duration events
• 16 GPIOs
• Four internal timers
• Packaging —4 9 2 - p i n P B G A — Commercial temperature (0° to +70° C) — Extended temperature (-40° to +85° C)

12 Datasheet

1.2 Processor Features

1.3 About this Document

IXC1100 Control Plane Processor Developer’ s Manual. Other related documents are shown in Table 2. Table 1. Processor Features

1. Only the 266-MHz version of the Intel ® IXP420 Network Processor supports extended temperature.

Table 2. Related Documents

14 Datasheet

2.0 Functional Overview

range of low-cost networking applications, with industry-leading performance. Figure 1. Intel ® IXP425 Network Processor Block Diagram

66 MHz Advanced Peripheral Bus

133 MHz Advanced

8 KB SRAM

32 KB Data Cache

32 KB Instruction Cache

2 KB Mini-Data Cache

16 Pins 32-Bit

133 MHz Advanced High-

Figure 2. Intel ® IXP422 Network Processor Block Diagram Figure 3. Intel ® IXP421 Network Processor Block Diagram

266 MHz

16 Pins 32-Bit 16-BitJTAG

16 Datasheet

Figure 4. Intel ® IXP420 Network Processor Block Diagram

2.1 Functional Units

IXC1100 Control Plane Processor Developer’ s Manual.

2.1.1 Network Processor Engines (NPEs)

NPEs are used to off-load processing functions required by the Intel XScale core.

• A Universal Test and Operation PHY Interface for ATM (UTOPIA) 2 interface
• Two High-Speed Serial (HSS) interfaces
• Two Media-Independent Interfaces (MII) Table 3 specifies which devices, in the IXP42X product line and IXC1100 control plane processors, have which of these capabilities. The NPE core is a hardware-multi-threaded processor engine that is used to accelerate functions that are difficult to achieve high performance in a standard RISC processor. Each NPE core is a 133-MHz processor core that has self-contained instruction memory and self-contained data memory that operate in parallel.

Table 3. Processor Functions

Intel® IXP42X Product Line and IXC1100 Control Plane Processor Functional Overview

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In addition to having separate instruction/data memory and local-code store, the NPE core supports hardware multi-threading with support for multiple contexts. The support of hardware multi-threading creates an efficient processor engine with minimal processor stalls due to the ability of the processor core to switch contexts in a single clock cycle, based on a prioritized/preemptive basis. The prioritized/preemptive nature of the context switching allows time-critical applications to be implemented in a low-latency fashion — which is required when processing multi-media applications. The NPE core also connects several hardware-based coprocessors that are used to implement functions that are difficult for a processor to implement. These functions include: These coprocessors are implemented in hardware, enabling the coprocessors and the NPE processor core to operate in parallel. The combined forces of the hardware multi-threading, local-code store, independent instruction memory, independent data memory, and parallel processing allows the Intel XScale core to be utilized for application purposes. The multi-processing capability of the peripheral interface functions allows unparalleled performance to be achieved by the application running on the Intel XScale core.

2.1.2 Internal Bus

The internal bus architecture of the IXP42X product line and IXC1100 control plane processors is designed to allow parallel processing to occur and to isolate bus utilization, based on particular traffic patterns. The bus is segmented into three major buses: the North AHB, South AHB, and APB.

2.1.2.1 North AHB

The North AHB is a 133.32-MHz, 32-bit bus that can be mastered by the NPEs. The targets of the North AHB can be the SDRAM or the AHB/AHB bridge. The AHB/AHB bridge allows the NPEs to access the peripherals and internal targets on the South AHB. Data transfers by the NPEs on the North AHB to the South AHB are targeted predominately to the queue manager. Transfers to the AHB/AHB bridge may be “posted,” when writing, or “split,” when reading. When a transaction is “posted,” a master on the North AHB requests a write to a peripheral on the South AHB. If the AHB/AHB Bridge has a free FIFO location, the write request will be transferred from the master on the North AHB to the AHB/AHB bridge. The AHB/AHB bridge will complete the write on the South AHB, when it can obtain access to the peripheral on the South AHB. The North AHB is released to complete another transaction. When a transaction is “split,” a master on the North AHB requests a read of a peripheral on the South AHB. If the AHB/AHB bridge has a free FIFO location, the read request will be transferred from the master on the North AHB to the AHB/AHB bridge. The AHB/AHB bridge will complete the read on the South AHB, when it can obtain access to the peripheral on the South AHB.

• Serialization/De-serialization • CRC checking/generation
• DES/3DES/AES • SHA-1
• MD5 • HDLC bit stuffing/de-stuffing

Intel® IXP42X Product Line and IXC1100 Control Plane Processor Functional Overview Datasheet 19 Once the AHB/AHB bridge has obtained the read information from the peripheral on the South AHB, the AHB/AHB bridge notifies the arbiter, on the North AHB, that the AHB/AHB bridge has the data for the master that requested the “split” transfer. The master on the North AHB — that requested the split transfer — will arbitrate for th e North AHB and transfer the read data from the AHB/AHB bridge. The North AHB is released to complete another transaction while the North AHB master — that requested the “split” tr ansfer — waits for the data to arrive. These “posting” and “splitting” transfers allow control of the North AHB to be given to another master on the North AHB — enabling the North AHB to achieve maximum efficiency. Transfers to the AHB/AHB bridge are considered to be small and infrequent, relative to the traffic passed between the NPEs on the North AHB and the SDRAM.

2.1.2.2 South AHB

The South AHB is a 133.32-MHz, 32-bit bus that can be mastered by the Intel XScale® Core, PCI controller, and the AHB/AHB bridge. The targets of the South AHB Bus can be the SDRAM, PCI interface, queue manager, expansion bus, or the APB/AHB bridge. Accessing across the APB/AHB bridge allows interfacing to peripherals attached to the APB.

2.1.2.3 APB Bus

The APB Bus is a 66.66-MHz (which is 2 * OSC_IN input pin.), 32-bit bus that can be mastered by the AHB/APB bridge only. The targets of the APB bus can be: The APB interface is also used as an alternate-path interface to the NPEs and is used for NPE code download and configuration.

2.1.3 MII Interfaces

Two industry-standard, media-independent interface (MII) interfaces are integrated into most of the IXP42X product line and IXC1100 control plane processors with separate media-access controllers and independent network processing engines. (See Table 3 on page 17.) The independent NPEs and MACs allow parallel processing of data traffic on the MII interfaces and off-loading of processing required by the Intel XScale® Core. The IXP42X product line and IXC1100 control plane processors are compliant with the IEEE, 802.3 specification. In addition to two MII interfaces, the IXP42X product line and IXC1100 control plane processors include a single management data interface that is used to configure and control PHY devices that are connected to the MII interface.

• High-speed UART interface • Console UART interface
• USB v 1.1 interface • All NPEs
• Internal bus performance monitoring unit (IBPMU)
• Interrupt controller
• GPIO • Timers

Intel® IXP42X Product Line and IXC1100 Control Plane Processor Functional Overview

20 Datasheet

2.1.4 UTOPIA 2

The integrated, UTOPIA-2 interface works with a network processing engine, for several of the IXP42X product line and IXC1100 control plane processors. (See Table 3 on page 17.) The UTOPIA-2 interface supports a single- or a multiple-physical-interface configuration with cell-level or octet-level handshaking. The network processing engine handles segmentation and reassembly of ATM cells, CRC checking/generation, and transfer of data to/from memory. This allows parallel processing of data traffic on the UTOPIA-2 interface, off-loading processor overhead required by the Intel XScale® Core. The IXP42X product line and IXC1100 control plane processors are compliant with the A TM Forum, UTOPIA Level-2 Specification, Revision 1.0.

2.1.5 USB Interface

The integrated USB 1.1 interface is a device-only controller. The interface supports full-speed operation and 16 endpoints and includes an integrated transceiver. There are:

• Six isochronous endpoints (three input and three output)
• One control endpoints
• Three interrupt endpoints
• Six bulk endpoints (three input and three output)

2.1.6 PCI Controller

The IXP42X product line and IXC1100 control plane processors’ PCI controller is compatible with the PCI Local Bus Specification, Rev. 2.2. The PCI interface is 32-bit compatible bus and capable of operating as either a host or an option (i.e. not the Host) For more information on PCI Controller support and configuration see the Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Developer’ s Manual

2.1.7 SDRAM Controller

The memory controller manages the interface to external SDRAM memory chips. The interface:

• Operates at 133.32 MHz (which is 4 * OSC_IN input pin.)
• Supports eight open pages simultaneously
• Has two banks to support memory configurations from 8 Mbyte to 256 Mbyte The memory controller only supports 32-bit memory. If a x16 memory chip is used, a minimum of two memory chips would be required to facilitate the 32-bit interface required by the IXP42X product line and IXC1100 control plane processors. A maximum of four SDRAM memory chips may be attached to the processors. For more information on SDRAM support and configuration see the Intel ® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Developer’ s Manual.

Intel® IXP42X Product Line and IXC1100 Control Plane Processor Functional Overview Datasheet 21 The memory controller internally interfaces to the North AHB and South AHB with independent interfaces. This architecture allows SDRAM transfers to be interleaved and pipelined to achieve maximum possible efficiency. The maximum burst size supported to the SDRAM interface is eight 32-bit words. This burst size allows the best efficiency/fairness performance between accesses from the North AHB and the South AHB.

2.1.8 Expansion Bus

The expansion interface allows easy and — in most cases — glue-less connection to peripheral devices. It also provides input information for device configuration after reset. Some of the peripheral device types are flash, A TM control interfaces, and DSPs used for voice applications. (Some voice configurations can be supported by the HSS interfaces and the Intel XScale ® Core, implementing voice-compression algorithms.) The expansion bus interface is a 16-bit interface that allows an address range of 512 bytes to 16 Mbytes, using 24 address lines for each of the eight independent chip selects. Accesses to the expansion bus interface consists of five phases. Each of the five phases can be lengthened or shortened by setting various configuration registers on a per-chip-select basis. This feature allows the IXP42X product line and IXC1100 control plane processors to connect to a wide variety of peripheral devices with varying speeds. The expansion bus interface supports Intel or Motorola* microprocessor-style bus cycles. The bus cycles can be configured to be multiplexed address/data cycles or separate address/data cycles for each of the eight chip-selects. Additionally, Chip Selects 4 through 7 can be configured to support Texas Instruments HPI-8 or HPI-16 style accesses for DSPs. The expansion bus interface is an asynchronous interface to externally connected chips. However, a clock must be supplied to the IXP42X product line and IXC1100 control plane processors’ expansion bus interface for the interface to operate. This clock can be driven from GPIO 15 or an external source. The maximum clock rate that the expansion bus interface can accept is 66.66 MHz. At the de-assertion of reset, the 24-bit address bus is used to capture configuration information from the levels that are applied to the pins at this time. External pull-up/pull-down resistors are used to tie the signals to particular logic levels. (For additional details, see “Package and Pinout Information” on page 42.)

2.1.9 High-Speed, Serial Interfaces

The high-speed, serial interfaces are six-signal interfaces that support serial transfer speeds from 512 KHz to 8.192 MHz, for some models of the IXP42X product line and IXC1100 control plane processors. (See Table 3 on page 17.) Each interface allows direct connection of up to four T1/E1 framers and CODEC/SLICs to the IXP42X product line and IXC1100 control plane processors. The high-speed, serial interfaces are capable of supporting various protocols, based on the implementation of the code developed for the network processor engine core. For a list of supported protocols, see the Intel ® IXP400 Software Programmer’ s Guide.

Intel® IXP42X Product Line and IXC1100 Control Plane Processor Functional Overview

22 Datasheet

2.1.10 High-Speed and Console UARTs

The UART interfaces are 16550-compliant UARTs with the exception of transmit and receive buffers. Transmit and receive buffers are 64 bytes-deep versus the 16 bytes required by the 16550 UART specification. The interface can be configured to support speeds from 1,200 baud to 921 Kbaud. The interface support configurations of:

• Five, six, seven, or eight data-bit transfers
• One or two stop bits
• Even, odd, or no parity The request-to-send (RTS_N) and clear-to-send (CTS_N) modem control signals also are available with the interface for hardware flow control.

2.1.11 GPIO

There are 16 GPIO pins supported by the IXP42X product line and IXC1100 control plane processors. GPIO pins 0 through 13 can be configured to be general-purpose input or general-purpose output. Additionally, GPIO pins 0 through 12 can be configured to be an interrupt input. GPIO Pin 14 can be configured similar to GPIO pin 13 or as a clock output. The output-clock configuration can be set at various speeds, up to 33.33 MHz, with various duty cycles. GPIO Pin 14 is configured as an input, upon reset. GPIO Pin 15 can be configured similar to GPIO pin 13 or as a clock output. The output-clock configuration can be set at various speeds, up to 33.33 MHz, with various duty cycles. GPIO Pin 15 is configured as a clock output, upon reset. GPIO Pin 15 can be used to clock the expansion interface, after reset.

2.1.12 Internal Bus Performance Monitoring Unit (IBPMU)

The IXP42X product line and IXC1100 control plane processors consists of seven 27-bit counters that may be used to capture predefined durations or occurrence events on the North AHB, South AHB, or SDRAM controller page hits/misses.

2.1.13 Interrupt Controller

The IXP42X product line and IXC1100 control plane processors consists of 32 interrupt sources to allow an extension of the Intel XScale® Core FIQ and IRQ interrupt sources. These sources can originate from some external GPIO pins or internal peripheral interfaces. The interrupt controller can configure each interrupt source as an FIQ, IRQ, or disabled. The interrupt sources tied to Interrupt 0 to 7 can be prioritized. The remaining interrupts are prioritized in ascending order. For example, Interrupt 8 has a higher priority than 9, 9 has a higher priority than 10, and 30 has a higher priority that 31.

Intel® IXP42X Product Line and IXC1100 Control Plane Processor Functional Overview Datasheet 23

2.1.14 Timers

The IXP42X product line and IXC1100 control plane processors consists of four internal timers operating at 66.66 MHz (which is 2 * OSC_IN input pin.) to allow task scheduling and prevent software lock-ups. The device has four 32-bit counters:

2.1.15 AHB Queue Manager

The AHB Queue Manager (AQM) provides queue functionality for various internal blocks. It maintains the queues as circular buffers in an embedded 8KB SRAM. It also implements the status flags and pointers required for each queue. The AQM manages 64 independent queues. Each qu eue is configurable for buffer and entry size. Additionally status flags are maintained for each queue. The AQM interfaces include an Advanced High -performance Bus (AHB) interface to the NPEs and Intel XScale core (or any other AHB bus master ), a Flag Bus interface, an event bus (to the NPE condition select logic) and two interrupts to the Intel XScale core. The AHB interface is used for configuration of the AQM and provides access to queues, queue status and SRAM. Individual queue status for queues 0-31 is communicated to the NPEs via the flag bus. Combined queue status for queues 32-63 are communicated to the NPEs via the event bus. The two interrupts, one for queues 0-31 and one for queues 32-63, provide status interrupts to the Intel XScale core.

2.2 Intel XScale ® Core

The Intel XScale® Core technology is compliant with the ARM* Version 5TE instruction-set architecture (ISA). The Intel XScale core — shown in Figure 5 — is designed with Intel state-of-the-art, 0.18-µ-production semiconductor process technology. This process technology enables the Intel XScale core to operate over a wide speed and power range, producing industry-leading mW/MIPS performance. Intel XScale core features include:

• Seven/eight-stage super-pipeline promotes high-speed, efficient core performance
• 128-entry branch target buffer keeps pipeline filled with statistically correct branch choices
• 32-entry instruction memory-management unit for logical-to-physical address translation, access permissions, I-cache attributes
• 32-entry data-memory management unit for logical-to-physical address translation, access permissions, D-cache attributes
• 32-Kbyte instruction cache can hold entire programs, preventing core stalls caused by multi-cycle memory accesses
• 32-Kbyte data cache reduces core stalls caused by multi-cycle memory accesses
• 2-Kbyte mini-data cache for frequently changing data streams avoids “thrashing” of the D-cache
• Four-entry fill-and-pend buffers to promote core efficiency by allowing “hit-under-miss” operation with data caches
• Watch-Dog Timer • Timestamp Timer • Two general-purpose timers

24 Datasheet

• Eight-entry write buffer allows the core to continue execution while data is written to memory
• Multiple-accumulate coprocessor that can do two simultaneous, 16-bit, SIMD multiplies with 40-bit accumulation for efficient, high-quality media and signal processing
• Performance monitoring unit (PMU) furnishing two 32-bit event counters and one 32-bit cycle counter for analysis of hit rates, etc. This PMU is for the Intel XScale core only. An additional PMU is supplied for monitoring of internal bus performance.
• JTAG debug unit that uses hardware break points and 256-entry trace history buffer (for flow-change messages) to debug programs

2.2.1 Super Pipeline

The super pipeline is composed of integer, multiply-accumulate (MAC), and memory pipes.

• Branch Target Buffer (BTB)/Fetch 1
• Fetch 2
• Decode
• Register File/Shift
• ALU Execute
• State Execute

Figure 5. Intel XScale ® Core Block Diagram

Intel® IXP42X Product Line and IXC1100 Control Plane Processor Functional Overview Datasheet 25

• Integer Writeback The memory pipe has eight stages:
• The first five stages of the Integer pipe (BTB/Fetch 1 through ALU Execute) . . . then finish with the following memory stages:
• Data Cache 1
• Data Cache 2
• Data Cache Writeback The MAC pipe has six to nine stages:
• The first four stages of the Integer pipe (BTB/Fetch 1 through Register File/ Shift) . . . then finish with the following MAC stages:
• MAC 1
• MAC 2
• MAC 3
• MAC 4
• Data Cache Writeback The MAC pipe supports a data-dependent early terminate where stages MAC 2, MAC 3, and/or MAC 4 are bypassed. Deep pipes promote high instruction execution rates only when a means exists to successfully predict the outcome of branch instructions. The branch target buffer provides such a means.

2.2.2 Branch Target Buffer (BTB)

Each entry of the 128-entry BTB contains the address of a branch instruction, the target address associated with the branch instruction, and a previous history of the branch being taken or not taken. The history is recorded as one of four states: The BTB can be enabled or disabled via Coprocessor 15, Register 1. When the address of the branch instruction hits in the BTB and its history is strongly or weakly taken, the instruction at the branch target address is fetched. When its history is strongly or weakly not-taken, the next sequential instruction is fetched. In either case the history is updated. Data associated with a branch instruction enters the BTB the first time the branch is taken. This data enters the BTB in a slot with a history of strongly not-taken (overwriting previous data when present). Successfully predicted branches avoid any branch-latency penalties in the super pipeline. Unsuccessfully predicted branches result in a four to five cycle branch-latency penalty in the super pipeline.

• Strongly taken • Weakly taken • Weakly not taken • Strongly not taken

Intel® IXP42X Product Line and IXC1100 Control Plane Processor Functional Overview

26 Datasheet

2.2.3 Instruction Memory Management Unit (IMMU)

For instruction pre-fetches, the IMMU controls logical-to-physical address translation, memory access permissions, memory-domain identifications, and attributes (governing operation of the instruction cache). The IMMU contains a 32-entry, fully associative instruction-translation, look-aside buffer (ITLB) that has a round-robin replacement policy. ITLB entries zero through 30 can be locked. When an instruction pre-fetch misses in the ITLB, the IMMU invokes an automatic table-walk mechanism that fetches an associated descriptor from memory and loads it into the ITLB. The descriptor contains information for logical-to-physical address translation, memory-access permissions, memory-domain identifications, and attributes governing operation of the I-cache. The IMMU then continues the instruction pre-fetch by using the address translation just entered into the ITLB. When an instruction pre-fetch hits in the ITLB, the IMMU continues the pre-fetch using the address translation already resident in the ITLB. Access permissions for each of up to 16 memory domains can be programmed. When an instruction pre-fetch is attempted to an area of memory in violation of access permissions, the attempt is aborted and a pre-fetch abort is sent to the core for exception processing. The IMMU and DMMU can be enabled or disabled together.

2.2.4 Data Memory Management Unit (DMMU)

For data fetches, the DMMU controls logical-to-physical address translation, memory-access permissions, memory-domain identifications, and attributes (governing operation of the data cache or mini-data cache and write buffer). The DMMU contains a 32-entry, fully associative data-translation, look-aside buffer (DTLB) that has a round-robin replacement policy. DTLB entries 0 through 30 can be locked. When a data fetch misses in the DTLB, the DMMU invokes an automatic table-walk mechanism that fetches an associated descriptor from memory and loads it into the DTLB. The descriptor contains information for logical-to-physical address translation, memory-access permissions, memory-domain identifications, and attributes (governing operation of the D-cache or mini-data cache and write buffer). The DMMU continues the data fetch by using the address translation just entered into the DTLB. When a data fetch hits in the DTLB, the DMMU continues the fetch using the address translation already resident in the DTLB. Access permissions for each of up to 16 memory domains can be programmed. When a data fetch is attempted to an area of memory in violation of access permissions, the attempt is aborted and a data abort is sent to the core for exception processing. The IMMU and DMMU can be enabled or disabled together.

2.2.5 Instruction Cache (I-Cache)

The I-cache can contain high-use, multiple-code segments or entire programs, allowing the core access to instructions at core frequencies. This prevents core stalls caused by multi-cycle accesses to external memory.

Intel® IXP42X Product Line and IXC1100 Control Plane Processor Functional Overview Datasheet 27 The 32-Kbyte I-cache is 32-set/32-way associative, where each set contains 32 ways and each way contains a tag address, a cache line of instructions (eight 32-bit words and one parity bit per word), and a line-valid bit. For each of the 32 sets, 0 through 28 ways can be locked. Unlocked ways are replaceable via a round-robin policy. The I-cache can be enabled or disabled. Attribute bits within the descriptors — contained in the ITLB of the IMMU — provide some control over an enabled I-cache. When a needed line (eight 32-bit words) is not present in the I-cache, the line is fetched (critical word first) from memory via a two-level, deep-fetch queue. The fetch queue allows the next instruction to be accessed from the I-cache, but only when its data operands do not depend on the execution results of the instruction being fetched via the queue.

2.2.6 Data Cache (D-Cache)

The D-cache can contain high-use data such as lookup tables and filter coefficients, allowing the core access to data at core frequencies. This prevents core stalls caused by multi-cycle accesses to external memory. The 32-Kbyte D-cache is 32-set/32-way associative, where each set contains 32 ways and each way contains a tag address, a cache line (32 bytes with one parity bit per byte) of data, two dirty bits (one for each of two eight-byte groupings in a line), and one valid bit. For each of the 32 sets, zero through 28 ways can be locked, unlocked, or used as local SRAM. Unlocked ways are replaceable via a round-robin policy. The D-cache (together with the mini-data cache) can be enabled or disabled. Attribute bits within the descriptors, contained in the DTLB of the DMMU, provide significant control over an enabled D-cache. These bits specify cache operating modes such as read and write allocate, write-back, write-through, and D-cache versus mini-data cache targeting. The D-cache (and mini-data cache) work with the load buffer and pend buffer to provide “hit-under-miss” capability that allows the core to access other data in the cache after a “miss” is encountered. The D-cache (and mini-data cache) works in conjunction with the write buffer for data that is to be stored to memory.

2.2.7 Mini-Data Cache

The mini-data cache can contain frequently changing data streams such as MPEG video, allowing the core access to data streams at core frequencies. This prevents core stalls caused by multi-cycle accesses to external memory. The mini-data cache relieves the D-cache of data “thrashing” caused by frequently changing data streams. The 2-Kbyte, mini-data cache is 32-set/two-way associative, where each set contains two ways and each way contains a tag address, a cache line (32 bytes with one parity bit per byte) of data, two dirty bits (one for each of two eight-byte groupings in a line), and a valid bit. The mini-data cache uses a round-robin replacement policy, and cannot be locked. The mini-data cache (together with the D-cache) can be enabled or disabled. Attribute bits contained within a coprocessor register specify operating modes write and/or read allocate, write-back, and write-through.

Intel® IXP42X Product Line and IXC1100 Control Plane Processor Functional Overview

28 Datasheet

The mini-data cache (and D-cache) work with the load buffer and pend buffer to provide “hit-under-miss” capability that allows the core to access other data in the cache after a “miss” is encountered. The mini-data cache (and D-cache) works in conjunction with the write buffer for data that is to be stored to memory.

2.2.8 Fill Buffer (FB) and Pend Buffer (PB)

The four-entry fill buffer (FB) works with the core to hold non-cacheable loads until the bus controller can act on them. The FB and the four-entry pend buffer (PB) work with the D-cache and mini-data cache to provide “hit-under-miss” capability, allowing the core to seek other data in the caches while “miss” data is being fetched from memory. The FB can contain up to four unique “miss” addresses (logical), allowing four “misses” before the core is stalled. The PB holds up to four addresses (logical) for additional “misses” to those addresses that are already in the FB. A coprocessor register can specify draining of the fill and pend (write) buffers.

2.2.9 Write Buffer (WB)

The write buffer (WB) holds data for storage to memory until the bus controller can act on it. The WB is eight entries deep, where each entry holds 16 bytes. The WB is constantly enabled and accepts data from the core, D-cache, or mini-data cache. Coprocessor 15, Register 1 specifies whether WB coalescing is enabled or disabled. When coalescing is disabled, stores to memory occur in program order regardless of the attribute bits within the descriptors located in the DTLB. When coalescing is enabled, the attribute bits within the descriptors located in the DTLB are examined to determine when coalescing is enabled for the destination region of memory. When coalescing is enabled in both CP15, R1 and the DTLB, data entering the WB can coalesce with any of the eight entries (16 bytes) and be stored to the destination memory region, but possibly out of program order. Stores to a memory region specified to be non-cacheable and non-bufferable by the attribute bits within the descriptors located in the DTLB causes the core to stall until the store completes. A coprocessor register can specify draining of the write buffer.

2.2.10 Multiply-Accumulate Coprocessor (CP0)

For efficient processing of high-quality, media-and-signal-processing algorithms, CP0 provides 40-bit accumulation of 16 x 16, dual-16 x 16 (SIMD), and 32 x 32 signed multiplies. Special MAR and MRA instructions are implemented to move the 40-bit accumulator to two core-general registers (MAR) and move two core-general registers to the 40-bit accumulator (MRA). The 40-bit accumulator can be stored or loaded to or from D-cache, mini-data cache, or memory using two STC or LDC instructions. The 16 x 16 signed multiply-accumulates (MIAxy) multiply either the high/high, low/low, high/low, or low/high 16 bits of a 32-bit core general register (multiplier) and another 32-bit core general register (multiplicand) to produce a full, 32-bit product that is sign-extended to 40 bits and added to the 40-bit accumulator. Dual-signed, 16 x 16 (SIMD) multiply-accumulates (MIAPH) multiply the high/high and low/low 16-bits of a packed 32-bit, core-general register (multiplier) and another packed 32-bit, core-general register (multiplicand) to produce two 16-bits products that are both sign-extended to 40 bits and added to the 40-bit accumulator.

Intel® IXP42X Product Line and IXC1100 Control Plane Processor Functional Overview Datasheet 29 The 32 x 32 signed multiply-accumulates (MIA) multiply a 32-bit, core-general register (multiplier) and another 32-bit, core-general register (multiplicand) to produce a 64-bit product where the 40 LSBs are added to the 40-bit accumulator. The 16 x 32 versions of the 32 x 32 multiply-accumulate instructions complete in a single cycle.

2.2.11 Performance Monitoring Unit (PMU)

The performance monitoring unit contains two 32-bit, event counters and one 32-bit, clock counter. The event counters can be programmed to monitor I-cache hit rate, data caches hit rate, ITLB hit rate, DTLB hit rate, pipeline stalls, BTB prediction hit rate, and instruction execution count.

2.2.12 Debug Unit

The debug unit is accessed through the JTAG port. The industry-standard, IEEE 1149.1 JTAG port consists of a test access port (TAP) controller, boundary-scan register, instruction and data registers, and dedicated signals TDI, TDO, TCK, TMS, and TRST#. The debug unit — when used with debugger application code running on a host system outside of the Intel XScale core — allows a program, running on the Intel XScale core, to be debugged. It allows the debugger application code or a debug exception to stop program execution and redirect execution to a debug-handling routine. Debug exceptions are instruction breakpoint, data breakpoint, software breakpoint, external debug breakpoint, exception vector trap, and trace buffer full breakpoint. Once execution has stopped, the debugger application code can examine or modify the core’s state, coprocessor state, or memory. The debugger application code can then restart program execution. The debug unit has two hardware-instruction, break point registers; two hardware, data-breakpoint registers; and a hardware, data-breakpoint control register. The second data-breakpoint register can be alternatively used as a mask register for the first data-breakpoint register. A 256-entry trace buffer provides the ability to capture control flow messages or addresses. A JTAG instruction (LDIC) can be used to download a debug handler via the JTAG port to the mini-instruction cache (the I-cache has a 2-Kbyte, mini-instruction cache to hold a debug handler).

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3.0 Functional Signal Descriptions

the particular interface enabled and the interface is not required in the application. Warning: All IXP42X product line and IXC1100 control plane processors I/O pins are not 5-V tolerant. as part of the disabled interface. control plane processors, see Table 1 on page 12. Table 4. Signal Type Definitions

1 Driven to Vcc

0 Driven to Vss

• Table 5 — SDRAM Interface signals
• Table 6 — PCI Controller signals
• Table 7 — High-Speed, Serial Interface 0 signals
• Table 8 — High-Speed, Serial Interface 1 signals
• Table 9 — MII Interfaces signals
• Table 10 — UTOPIA-2 Interface signals
• Table 11 — Expansion Bus Interface signals
• Table 12 — UART Interfaces signals
• Table 13 — USB Interface signals
• Table 14 — Oscillator Interface signals
• Table 15 — GPIO Interface signals
• Table 16 — JTAG Interface signals
• Table 17 — System Interface signals
• Table 18 — Power Interface signals Note: 1. The Power On Reset Column of the Tables indicate the state of the signals during the Power On Reset process 2. The Reset Column of the Tables indicate the state of the signals during the Reset.

Table 5. SDRAM Interface (Sheet 1 of 2) current command is attempting to access. current command to be executed. current command to be executed. in the external SDRAM when logic high. † For a legend of the Type codes, see Table 4 on page 30.

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read/write access to an external SDRAM. Table 5. SDRAM Interface (Sheet 2 of 2) † For a legend of the Type codes, see Table 4 on page 30.

Table 6. PCI Controller (Sheet 1 of 2) and from multiple PCI devices. cycles and as byte enables for data cycles. phase of a given transaction. complete the current data phase of a given transaction. to stop the current transaction. data will drive this signal. signal can function as an input or an open drain output.

• When used as an output, PCI_DEVSEL_N indicates that device has decoded that address as the target of the requested transaction.
• When used as an input, PCI_DEVSEL_N indicates if any device on the PCI bus exists with the given address. Should be pulled high with a 10-KΩ resistor when not being utilized in the system. PCI_IDSEL Z Z I PCI Initialization Device Select is a chip select during configuration reads and writes. Should be pulled low with a 10-KΩ resistor when not being utilized in the system. PCI_REQ_N[3:1] Z Z I PCI arbitration request: Used by the internal PCI arbiter to allow an agent to request the PCI bus. Should be pulled high with a 10-KΩ resistor when not being utilized in the system. PCI_REQ_N[0] Z Z I/O PCI arbitration request:
• When configured as an input (PCI arbiter enabled), the internal PCI arbiter will allow an agent to request the PCI bus.
• When configured as an output (PCI arbiter disabled), the pin will be used to request access to the PCI bus from an external arbiter. Should be pulled high with a 10-KΩ resistor, when the PCI bus is not being utilized in the system. PCI_GNT_N[3:1] Z Z O PCI arbitration grant: Generated by the internal PCI arbiter to allow an agent to claim control of the PCI bus. † For a legend of the Type codes, see Table 4 on page 30.

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• When configured as an output (PCI arbiter enabled), the internal PCI arbiter to allow an agent to claim control of the PCI bus.
• When configured as an input (PCI arbiter disabled), the pin will be used to claim access of the PCI bus from an external arbiter. Should be pulled high with a 10-KΩ resistor when not being utilized in the system. PCI_INTA_N Z Z O/D PCI interrupt: Used to request an interrupt. Should be pulled high with a 10-KΩ resistor when not being utilized in the system. PCI_CLKIN Z VI I PCI Clock: provides timing for all transactions on PCI. All PCI signals — except INTA#, INTB#, INTC#, and INTD# — are sampled on the rising edge of CLK and timing parameters are defined with respect to this edge. The PCI clock rate can operate at up to 66 MHz. Should be pulled low with a 10-KΩ resistor when not being utilized in the system.

Table 7. High-Speed, Serial Interface 0 with the transmitted data. Often known as a Frame Sync signal. Configured as an input upon reset. HSS_TXDATA0 Z Z O/D Transmit data out. Open Drain output. rising or falling edge of the transmit clock. signal. Configured as an input upon reset. an input or an output. The clock can be from 512 KHz to 8.192 MHz. Used to sample the received data. Configured as an input upon reset. Table 6. PCI Controller (Sheet 2 of 2) † For a legend of the Type codes, see Table 4 on page 30.

Table 8. High-Speed, Serial Interface 1 HSS_TXDATA1 Z Z O/D Transmit data out. Open Drain output. on the rising or falling edge of the transmit clock. to sample the received data. Configured as an input upon reset. † For a legend of the Type codes, see Table 4 on page 30. Table 9. MII Interfaces (Sheet 1 of 2) Externally supplied transmit clock.

• 25 MHz for 100-Mbps operation
• 2.5 MHz for 10 Mbps Should be pulled low through a 10-KΩ resistor when not being utilized in the system. ETH_TXDATA0[3:0] Z0 O Transmit data bus to PHY, asserted synchronously with respect to ETH_TXCLK0. ETH_TXEN0 Z0 O Indicates that the PHY is being presented with nibbles on the MII interface. Asserted synchronously, with respect to ETH_TXCLK0, at the first nibble of the preamble and remains asserted until all the nibbles of a frame are presented. ETH_RXCLK0 ZV II Externally supplied receive clock.
• 25 MHz for 100-Mbps operation
• 2.5 MHz for 10 Mbps Should be pulled low through a 10-KΩ resistor when not being utilized in the system. † For a legend of the Type codes, see Table 4 on page 30.

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• Should be pulled low through a 10-K Ω resistor when not being utilized in the system. ETH_RXDV0 ZV II Receive data valid, used to inform the MII interface that the Ethernet PHY is sending data. Should be pulled low through a 10-KΩ resistor when not being utilized in the system. ETH_COL0 ZV II Asserted by the PHY when a collision is detected by the PHY. Should be pulled low through a 10-KΩ resistor when not being utilized in the system. ETH_CRS0 ZV II Asserted by the PHY when the transmit medium or receive medium is active. De-asserted when both the transmit and receive medium are idle. Remains asserted throughout the duration of a collision condition. PHY asserts CRS asynchronously and de-asserts synchronously, with respect to ETH_RXCLK0. Should be pulled low through a 10-KΩ resistor when not being utilized in the system. ETH_MDIO Z Z I/O Management data output. Provides the write data to both PHY devices connected to each MII interface. Should be pulled low through a 10-KΩ resistor when not being utilized in the system. ETH_MDC ZZ O Management data clock. Management data interface clock is used to clock the MDIO signal as an output and sample the MDIO as an input. The ETH_MDC is an input on power up and can be configured to be an output through an Intel API as documented in the Intel ® IXP400 Software Programmer’s Guide. ETH_TXCLK1 ZV II Externally supplied transmit clock.
• 25 MHz for 100-Mbps operation
• 2.5 MHz for 10 Mbps Should be pulled low through a 10-KΩ resistor when not being utilized in the system. ETH_TXDATA1[3:0] Z0 O Transmit data bus to PHY, asserted synchronously with respect to ETH_TXCLK1. ETH_TXEN1 Z0 O Indicates that the PHY is being presented with nibbles on the MII interface. Asserted synchronously, with respect to ETH_TXCLK1, at the first nibble of the preamble, and remains asserted until all the nibbles of a frame are presented. ETH_RXCLK1 ZV II Externally supplied receive clock.
• 25 MHz for 100-Mbps operation
• 2.5 MHz for 10 Mbps Should be pulled low through a 10-KΩ resistor when not being utilized in the system. ETH_RXDATA1[3:0] ZV II Receive data bus from PHY, data sampled synchronously, with respect to ETH_RXCLK1.
• Should be pulled low through a 10-K Ω resistor when not being utilized in the system. ETH_RXDV1 ZV II Receive data valid, used to inform the MII interface that the Ethernet PHY is sending data. Should be pulled low through a 10-KΩ resistor when not being utilized in the system. ETH_COL1 ZV II Asserted by the PHY when a collision is detected by the PHY.
• Should be pulled low through a 10-K Ω resistor when not being utilized in the system. ETH_CRS1 ZV II Asserted by the PHY when the transmit medium or receive medium are active. De-asserted when both the transmit and receive medium are idle. Remains asserted throughout the duration of collision condition. PHY asserts CRS asynchronously and de-asserts synchronously with respect to ETH_RXCLK1. Should be pulled low through a 10-KΩ resistor when not being utilized in the system.

Table 9. MII Interfaces (Sheet 2 of 2) † For a legend of the Type codes, see Table 4 on page 30.

Table 10. UTOPIA-2 Interface (Sheet 1 of 2) being utilized in the system. selects which PHY is active in MPHY mode. the processor is ready to send data. Start of Cell. Also known as TX_SOC. valid byte of a transmitted cell. data from the processor to an ATM UTOPIA-Level-2-compliant PHY. MPHY mode to poll and select a single PHY at any given time. full cell cannot be received by the PHY. UTOPIA Receive clock input. Also known as UTP_RX_CLK. rising edge of the UTP_IP_CLK. being utilized in the system. PHY has an octet or cell available to be transferred to the processor. first valid byte of a transmitted cell. † For a legend of the Type codes, see Table 4 on page 30.

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UTOPIA input data. Also known as RX_DATA. UTOPIA-Level-2-compliant PHY. select a single PHY at any one given time. the processor is ready to accept data. the UTP_OP_FCO going to a logic 0 on the next clock cycle. Table 11. Expansion Bus Interface clock all expansion interface outputs. EX_ALE Z 0 O Address-latch enable used for multiplexed address/data bus accesses. Used in Intel and Motorola* multiplexed modes of operation. must be tied low in order for the device to operate in the desired mode. (EXP_MOT_DS_N) / TI*-mode data strobe (TI_HDS1_N). (EXPB_MOT_RNW) / TI mode read-not-write (TI_HR_W_N). External chip selects for expansion bus.

• Chip selects 0 through 7 can be configured to support Intel or Motorola bus cycles.
• Chip selects 4 through 7 can be configured to support TI HPI bus cycles. EX_DATA[15:0] Z 0 I/O Expansion-bus, bidirectional data EX_IOWAIT_N H H I Data ready/acknowledge from expansion-bus devices. Expansion-bus access is halted when an external device sets EX_IOWAIT_N to logic 0 and resume from the halted location once the external device sets EX_IOWAIT_N to logic 1. This signal affects accesses that use EX_CS_N[7:0] when the chip select is configured in Intel- or Motorola-mode of operation. Should be pulled high through a 10-KΩ resistor when not being utilized in the system. EX_RDY[3:0] H H I HPI interface ready signals. Can be configured to be active high or active low. These signals are used to halt accesses using Chip Selects 7 through 4 when the chip selects are configured to operate in HPI mode. There is one RDY signal per chip select. This signal only affects accesses that use EX_CS_N[7:4]. Should be pulled low though a 10-KΩ resistor when not being utilized in the system. † For a legend of the Type codes, see Table 4 on page 30.

Table 10. UTOPIA-2 Interface (Sheet 2 of 2) † For a legend of the Type codes, see Table 4 on page 30.

Table 12. UART Interfaces UART serial data input to High-Speed UART Pins. upon a reset operation. High-Speed Serial UART Pins. UART CLEAR-TO-SEND input to High-Speed UART Pins. a modem status input whose condition can be tested by the processor. the request to send signal to logic 1. upon a Reset operation. Console UART Pins. UART CLEAR-TO-SEND input to Console UART pins. a modem status input whose condition can be tested by the processor. the request to send signal to logic 1. † For a legend of the Type codes, see Table 4 on page 30. Table 13. USB Interface USB_DPOS Z Z I/O Positive signal of the differential USB receiver/driver. USB_DNEG Z Z I/O Negative signal of the differential USB receiver/driver. † For a legend of the Type codes, see Table 4 on page 30.

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Table 14. Oscillator Interface OSC_IN I 33.33-MHz, sinusoidal crystal input signal. Can be driven by an oscillator. † For a legend of the Type codes, see Table 4 on page 30. Table 15. GPIO Interface output. As an input, each signal may be configured a processor interrupt. Default after reset is to be configured as inputs. output. Default after reset is to be configured as inputs. various duty cycles. Configured as an input, upon reset. clock the expansion interface, after reset. † For a legend of the Type codes, see Table 4 on page 30. Table 16. JTAG Interface JTG_TMS H VI/PE I Test mode select for the IEEE 1149.1 JTAG interface. JTG_TDI H VI/PE I Input data for the IEEE 1149.1 JTAG interface. JTG_TDO Z VO O Output data for the IEEE 1149.1 JTAG interface. Used to reset the IEEE 1149.1 JTAG interface. and the processor may be locked. JTG_TCK Z VI I Used as the clock for the IEEE 1149.1 JTAG interface. † For a legend of the Type codes, see Table 4 on page 30.

Table 17. System Interface BYPASS_CLK Z VI I Used for test purposes only. Must be pulled high for normal operation. SCANTESTMODE_N H VI/PE I Used for test purposes only. Must be pulled high for normal operation. RESET_IN_N coming to an active state. input is a 1.3-V tolerant only. HIGHZ_N H VI/PE I Used for test purposes only. Must be pulled high for normal operation. strength is varied on PCI address, data and control signals. † For a legend of the Type codes, see Table 4 on page 30. Table 18. Power Interface VCC I 1.3-V power supply input pins used for the internal logic. VCCP I 3.3-V power supply input pins used for the peripheral (I/O) logic. VSS Ground power supply input pins used for both the 3.3-V and the 1.3-V power supplies. Ground input pins used for the peripheral (I/O) logic of the analog oscillator circuitry. Used in conjunction with the VCCOSCP pins. circuitry. Used in conjunction with the VCCOSC pins. Type codes, see Table 4 on page 30.

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4.0 Package and Pinout Information

extended-temperature applications.

4.1 Package Description

Figure 6. 492-Pin Lead PBGA Package

1. All measurements are in millimeters (mm).
2. The size of the land pad at the interposer side (1) is 0.81 mm.
3. The size of the solder resist at the interposer side (2) is 0.66 mm.

1.271.63 REF

3 Places

1.63 REF

22.00 REF

4 Places

Figure 7. Package Markings Table 19. Part Numbers (Sheet 1 of 2)

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Table 19. Part Numbers (Sheet 2 of 2)

4.2 Signal-Pin Descriptions

Table 20. Ball Map Assignment for the Intel ® IXP425 Network Processor (Sheet 1 of 7) requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.

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Table 20. Ball Map Assignment for the Intel ® IXP425 Network Processor (Sheet 2 of 7) requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.

Table 20. Ball Map Assignment for the Intel ® IXP425 Network Processor (Sheet 3 of 7) requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.

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Table 20. Ball Map Assignment for the Intel ® IXP425 Network Processor (Sheet 4 of 7) requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.

Table 20. Ball Map Assignment for the Intel ® IXP425 Network Processor (Sheet 5 of 7) requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.

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Table 20. Ball Map Assignment for the Intel ® IXP425 Network Processor (Sheet 6 of 7) requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.

Table 20. Ball Map Assignment for the Intel ® IXP425 Network Processor (Sheet 7 of 7) requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.

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Table 21. Ball Map Assignment for the Intel ® IXP422 Network Processor (Sheet 1 of 7) requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.

Table 21. Ball Map Assignment for the Intel ® IXP422 Network Processor (Sheet 2 of 7) requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.

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Table 21. Ball Map Assignment for the Intel ® IXP422 Network Processor (Sheet 3 of 7) requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.

Table 21. Ball Map Assignment for the Intel ® IXP422 Network Processor (Sheet 4 of 7) requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.

56 Datasheet

Table 21. Ball Map Assignment for the Intel ® IXP422 Network Processor (Sheet 5 of 7) requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.

Table 21. Ball Map Assignment for the Intel ® IXP422 Network Processor (Sheet 6 of 7) requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.

58 Datasheet

Table 21. Ball Map Assignment for the Intel ® IXP422 Network Processor (Sheet 7 of 7) requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.

Table 22. Ball Map Assignment for the Intel ® IXP421 Network Processor (Sheet 1 of 7) requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.

60 Datasheet

Table 22. Ball Map Assignment for the Intel ® IXP421 Network Processor (Sheet 2 of 7) requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.

Table 22. Ball Map Assignment for the Intel ® IXP421 Network Processor (Sheet 3 of 7) requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.

62 Datasheet

Table 22. Ball Map Assignment for the Intel ® IXP421 Network Processor (Sheet 4 of 7) requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.

Table 22. Ball Map Assignment for the Intel ® IXP421 Network Processor (Sheet 5 of 7) requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.

64 Datasheet

Table 22. Ball Map Assignment for the Intel ® IXP421 Network Processor (Sheet 6 of 7) requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.

Table 22. Ball Map Assignment for the Intel ® IXP421 Network Processor (Sheet 7 of 7) requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.

66 Datasheet

Table 23. Ball Map Assignment for the Intel ® IXP420 Network Processor requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.

requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.

68 Datasheet

requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.

requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.

70 Datasheet

requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.

requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.

72 Datasheet

requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.

Intel® IXP42X Product Line and IXC1100 Control Plane Processor Package and Pinout Information Datasheet 73

4.3 Package Thermal Specifications

The thermal characterization parameter “ΨJT” is proportional to the temperature difference between the top, center of the package and the junction temperature. This can be a useful value for verifying device temperatures in an actual environment. By measuring the package of the device, the junction temperature can be estimated, if the thermal characterization parameter has been measured under similar conditions. The use of ΨJT should not be confused with Θjc, which is the thermal resistance from the device junction to the external surface of the package or case nearest the die attachment — as the case is held at a constant temperature. The case temperature can then be monitored to make sure that the maximum junction temperature is not violated. Examples are given in the following sections. Note: For more information on ΨJT, refer to the EIA/JEDEC Standard 51-2, Section 4.

4.3.1 Commercial Temperature

“Commercial” temperature range is defined in terms of the ambient temperature range, which is specified as 0° C to 70° C. The maximum power (P) is 2.4 W and the maximum junction temperature (Tj) is 115 ° C. ΨJT for commercial temperature is 0.89° C/W. Using the preceding junction-temperature formula, the commercial temperature for a 266-MHz part — assuming a maximum power of 2 W — would be:

4.3.2 Extended Temperature

“Extended” temperature range is defined in terms of the ambient temperature range, which is specified as -40° C to 85° C. The maximum power (P) is 2.4 W and the maximum junction temperature (Tj) is 115° C. ΨJT for extended temperature is 0.32° C/W. Using the preceding junction-temperature formula, the extended temperature for a 533-MHz part — assuming a maximum power of 2.4 W — would be: Case temperature = Junction Temperature - (ΨJT * Power Dissipation) TJC = TJ - (ΨJT * Power Dissipation) TJC = 113.22° C TJC = 114.23° C

Intel® IXP42X Product Line and IXC1100 Control Plane Processor Electrical Specifications

74 Datasheet

5.0 Electrical Specifications

5.1 Absolute Maximum Ratings

Warning: Stressing the device beyond the “absolute maximum ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “operating conditions” is not recommended and extended exposure beyond the “operating conditions” may affect device reliability.

5.2 V CCPLL1, VCCPLL2, VCCOSCP, VCCOSC Pin Requirements

To reduce voltage-supply noise on the analog sections of the Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor, the phase-lock loop circuits (VCCPLL1, VCCPLL2) and oscillator circuit (VCCOSCP, VCCOSC) require isolated voltage supplies. The filter circuits for each supply are shown in the following sections.

5.2.1 V CCPLL1 Requirement

A parallel combination of a 10-nF capacitor — for bypass — and a 200-nF capacitor — for a first-order filter with a cut-off frequency below 30 MHz — must be connected to the V CCPLL1 pin of the Intel® IXP42X product line and IXC1100 control plane processors. The ground of both capacitors should be connected to the nearest VSS supply pin. Both capacitors should be located less than 0.5 inch away from the VCCPLL1 pin and the associated VSS pin. In order to achieve the 200-nF capacitance, a parallel combination of two 100-nF capacitors may be used as long as the capacitors are placed directly beside each other. Parameter Maximum Rating Ambient Air Temperature (Extended) -40º C to 85º C Ambient Air Temperature (Commercial) 0º C to 70º C Supply Voltage Core -0.3 V to 2.1V Supply Voltage I/O -0.3 V to 3.6V Supply Voltage Oscillator (V CCOSC) -0.3 V to 2.1V Supply Voltage Oscillator (VCCOSCP) -0.3 V to 3.6V Supply Voltage PLL (VCCPLL1) -0.3 V to 2.1V Supply Voltage PLL (VCCPLL2) -0.3 V to 2.1V Voltage On Any I/O Ball -0.3 V to 3.6V Storage Temperature -55 o C to 125o C

5.2.2 V CCPLL2 Requirement

of the IXP42X product line and IXC1100 control plane processors. used as long as the capacitors are placed directly beside each other.

5.2.3 V CCOSCP Requirement

AD10 and AF10. Ensure that both pins are connected as shown in Figure 10. Figure 8. V CCPLL1 Power Filtering Diagram Figure 9. V CCPLL2 Power Filtering Diagram

76 Datasheet

5.2.4 V CCOSC Requirement

VCCOSC pins of the IXP42X product line and IXC1100 control plane processors. should be located less than 0.5 inch away from the VCCOSC pin and the associated VSSOSC pin. used as long as the capacitors are placed directly beside each other. Figure 10. V CCOSCP Power Filtering Diagram Figure 11. V CCOSC Power Filtering Diagram

5.3 RCOMP Pin Requirements

Figure 12 shows the requirements for the RCOMP pin.

5.4 DC Specifications

5.4.1 Operating Conditions

Figure 12. RCOMP Pin External Resistor Requirements Table 24. Operating Conditions

78 Datasheet

5.4.2 PCI DC Parameters

1. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tri-state outputs.
2. These values are typical values seen by the manufacturing process and are not tested.
3. For additional information, see the PCI Local Bus Specification, Rev. 2.2.

5.4.3 USB DC Parameters

1. These values are typical values seen by the manufacturing process and are not tested.

Table 25. PCI DC Parameters Table 26. USB v1.1 DC Parameters

5.4.4 UTOPIA-2 DC Parameters

1. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tri-state outputs.
2. These values are typical values seen by the manufacturing process and are not tested.

5.4.5 MII DC Parameters

1. These values are typical values seen by the manufacturing process and are not tested.

Table 27. UTOPIA-2 DC Parameters Table 28. MII DC Parameters

80 Datasheet

5.4.6 MDIO DC Parameters

1. These values are typical values seen by the manufacturing process and are not tested.

5.4.7 SDRAM Bus DC Parameters

1. VIH overshoot: VIH (MAX) = VCCP + 2 V for a pulse width < 3 ns, and the pulse width cannot be greater than

one third of the cycle rate.

1. VIL undershoot: VIL (MIN) = -2 V for a pulse width < 3 ns cannot be exceeded.
2. These values are typical values seen by the manufacturing process and are not tested.

Table 29. MDIO DC Parameters Table 30. SDRAM Bus DC Parameters

5.4.8 Expansion Bus DC Parameters

1. Test conditions were a 70 pF load to ground.
2. These values are typical values seen by the manufacturing process and are not tested.

5.4.9 High-Speed, Serial Interface 0 DC Parameters

1. These values are typical values seen by the manufacturing process and are not tested.

5.4.10 High-Speed, Serial Interface 1 DC Parameters

1. These values are typical values seen by the manufacturing process and are not tested.

Table 31. Expansion Bus DC Parameters Table 32. High-Speed, Serial Interface 0 DC Parameters Table 33. High-Speed, Serial Interface 1 DC Parameters

82 Datasheet

5.4.11 High-Speed and Console UART DC Parameters

1. These values are typical values seen by the manufacturing process and are not tested.

Table 34. UART DC Parameters

5.4.12 GPIO DC Parameters

5.4.13 JTAG DC Parameters

1. These values are typical values seen by the manufacturing process and are not tested.

5.4.14 Reset DC Parameters

Table 35. GPIO DC Parameters Table 36. JTAG DC Parameters Table 37. PWRON_Reset _N DC Parameters CIN Input Capacitance 1 pF Simulated results.

84 Datasheet

5.5 AC Specifications

5.5.1 Clock Signal Timings

5.5.1.1 Processor Clock Timings

1. This value could be an oscillator input or a series resonant frequency from a crystal. If used as an oscillator

input, tie to the crystal input pin and leave the crystal output pin disconnected.

1. Use the component values recommended by the crystal manufacturer.
2. This parameter applies when driving the clock input with an oscillator.
3. The reference-clock input slope should not exceed more than 2.5 V/nS to ensure proper PLL operation

Table 38. Device Clock Timings (Oscillator Reference)

33.33 MHz 1, 4

Table 39. Device Clock Timings (Crystal Reference) (Sheet 1 of 2) processors crystal or oscillator.

1. This value could be an oscillator input or a series resonant frequency from a crystal. If used as an oscillator

input, tie to the crystal input pin and leave the crystal output pin disconnected.

1. Use the component values recommended by the crystal manufacturer.
2. This parameter applies when driving the clock input with an oscillator.
3. The reference-clock input slope should not exceed more than 2.5 V/nS to ensure proper PLL operation

1 Load capacitance pF 2

Table 39. Device Clock Timings (Crystal Reference) (Sheet 2 of 2) Figure 13. Typical Connection to a Crystal Figure 14. Typical Connection to an Oscillator

86 Datasheet

5.5.1.2 PCI Clock Timings

5.5.1.3 MII Clock Timings

5.5.1.4 UTOPIA-2 Clock Timings

1. The Utopia interface can operate at a minimum frequency greater than 0Hz

5.5.1.5 Expansion Bus Clock Timings

Table 40. PCI Clock Timings

33 MHZ 66 MHZ

Table 41. MII Clock Timings Table 42. UTOPIA-2 Clock Timings Table 43. Expansion Bus Clock Timings

5.5.2 Bus Signal Timings

The AC timing waveforms are shown in the following sections.

5.5.2.1 PCI

Figure 15. PCI Output Timing Figure 16. PCI Input Timing

88 Datasheet

1. See the timing measurement conditions.
2. Parts compliant to the 3.3 V signaling environment.
3. REQ# and GNT# are point-to-point signals and have different output valid delay and input setup times than
4. RST# is asserted and de-asserted asynchronously with respect to CLK.
5. All PCI outputs must be asynchronously driven to a tri-state value when RST# is active.
6. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at
7. Timing was tested with a 70-pF capacitor to ground.
8. For additional information, see the

PCI Local Bus Specification, Rev. 2.2.

5.5.2.2 USB Interface

product line and IXC1100 control plane processors’ USB v 1.1 interface cannot be line-powered. Table 44. PCI Bus Signal Timings

5.5.2.3 UTOPIA-2

1. Timing was tested with a 70-pF capacitor to ground.

Figure 17. UTOPIA-2 Input Timings Table 45. UTOPIA-2 Input Timings Values Input hold time after the rising edge of the clock. Figure 18. UTOPIA-2 Output Timings Table 46. UTOPIA-2 Output Timings Values UTP_OP_DATA[7:0], and UTP_OP_ADDR[3:0]. UTP_OP_DATA[7:0], and UTP_OP_ADDR[3:0].

90 Datasheet

5.5.2.4 MII

1. These values satisfy the MII specification requirement of 0 ns to 25 ns clock to output delay.
2. These values satisfy the MII specification requirement of 10-ns setup and hold time.
3. Timing tests were performed with a 70-pF capacitor to ground.

Figure 19. MII Output Timings Table 47. MII Output Timings Values Figure 20. MII Input Timings Table 48. MII Input Timings Values

5.5.2.5 MDIO

Figure 21. MDIO Output Timings NOTE: Processor is Sourcing MDIO. Figure 22. MDIO Input Timings

92 Datasheet

1. This parameter is not tested and is guaranteed by design.

5.5.2.6 SDRAM Bus

Table 49. MDIO Timings Values Figure 23. SDRAM Input Timings Table 50. SDRAM Input Timings Values Input hold time after the rising edge of the clock.

1. Timing test were performed with a 70-pF load to ground.

5.5.2.7 Expansion Bus

Figure 24. SDRAM Output Timings Table 51. SDRAM Output Timings Values SDM_DQ[31:0] (during a write operation). Figure 25. Intel Multiplexed Mode

94 Datasheet

1. The EX_ALE signal is extended form 1 to 4 cycles based on the programming of the T1 timing parameter.

The parameter Tale2addrhold is fixed at 1 cycle.

1. Setting the address phase parameter (T1) will adjust the duration that the address appears to the external device.
2. Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a data

strobe (read or write) to an external device.

1. Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears (read or

write) to an external device. Data will be available during this time as well.

1. Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects, address, and

data (during a write) will be held.

1. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
2. One cycle is the period of the Expansion Bus clock.
3. Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in
4. Timing tests were performed with a 70-pF capacitor to ground.

Table 52. Intel Multiplexed Mode Values Figure 26. Intel Simplex Mode

1. EX_ALE is not valid in simplex mode of operation.
2. Setting the address phase parameter (T1) will adjust the duration that the address appears to the external
3. Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a data

strobe (read or write) to an external device.

1. Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears (read or

write) to an external device. Data will be available during this time as well.

1. Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects, address, and

data (during a write) will be held.

1. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
2. One cycle is the period of the Expansion Bus clock.
3. Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in
4. Timing tests were performed with a 70-pF capacitor to ground.

Table 53. Intel Simplex Mode Values **Figure 27. Motorola* Multiplexed Mode**

96 Datasheet

1. The EX_ALE signal is extended form 1 to 4 cycles based on the programming of the T1 timing parameter.
2. Setting the address phase parameter (T1) will adjust the duration that the address appears to the external device.
3. Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a data

strobe (read or write) to an external device.

1. Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears (read or

write) to an external device. Data will be available during this time as well.

1. Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects, address, and

data (during a write) will be held.

1. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
2. One cycle is the period of the Expansion Bus clock.
3. Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in
4. Timing tests were performed with a 70-pF capacitor to ground.

**Table 54. Motorola* Multiplexed Mode Values**

**Figure 28. Motorola* Simplex Mode**

98 Datasheet

1. EX_ALE is not valid in simplex mode of operation.
2. Setting the address phase parameter (T1) will adjust the duration that the address appears to the external device.
3. Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a data

strobe (read or write) to an external device.

1. Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears (read or

write) to an external device. Data will be available during this time as well.

1. Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects, address, and

data (during a write) will be held.

1. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
2. One cycle is the period of the Expansion Bus clock.
3. Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in
4. Timing tests were performed with a 70-pF capacitor to ground.

**Table 55. Motorola* Simplex Mode Values**

Figure 29. HPI – 8 Mode Write Accesses Table 56. HPI Timing Symbol Description Table 57. HPI – 8 Mode Write Accesses Values

100 Datasheet

1. The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T clocks for

the address phase for at least one clock pulse after the HRDY is de-active.

1. The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T clocks
2. The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks
3. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
4. HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or T3
5. One cycle is the period of the Expansion Bus clock.
6. Timing tests were performed with a 70-pF capacitor to ground.
7. The Setup and Hold Timing Values are for all modes.

Table 58. Setup/Hold Timing Values

1. The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T clocks for

the address phase for at least one clock pulse after the HRDY is de-active.

1. The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T clocks
2. The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks
3. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
4. HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or T3
5. One cycle is the period of the Expansion Bus clock.
6. Timing tests were performed with a 70-pF capacitor to ground.

Table 59. HPI-16 Multiplexed Write Accesses Values Figure 30. HPI-16 Multiplex Write Mode

102 Datasheet

1. The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T clocks for

the address phase for at least one clock pulse after the HRDY is de-active.

1. The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T clocks
2. The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks
3. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
4. HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or T3
5. One cycle is the period of the Expansion Bus clock.
6. Timing tests were performed with a 70-pF capacitor to ground.

Table 60. HPI-16 Multiplex Read Accesses Values

Figure 31. HPI-16 Multiplex Read Mode

104 Datasheet

1. The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T clocks for

the address phase for at least one clock pulse after the HRDY is de-active.

1. The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T clocks
2. The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks
3. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
4. HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or T3
5. One cycle is the period of the Expansion Bus clock.
6. Timing tests were performed with a 70-pF capacitor to ground.

Table 61. HPI-16 Non-Multiplex Read Accesses Values Figure 32. HPI-16 Non-Multiplex Read Mode

1. The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T clocks for

the address phase for at least one clock pulse after the HRDY is de-active.

1. The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T clocks
2. The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks
3. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
4. HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or T3
5. One cycle is the period of the Expansion Bus clock.
6. Timing tests were performed with a 70-pF capacitor to ground.

Table 62. HPI-16 Non-Multiplexed Write Accesses Values

106 Datasheet

Figure 33. HPI-16 Non-Multiplex Write Mode

5.5.2.7.1 EX_IOWAIT_N

7 and is used as required by slow devices. parameter (T3) for the strobe phase. corresponding HRDY signal called EX_RDY . The polarity of the ready signal is programmable.

5.5.2.8 High-Speed, Serial Interfaces

Figure 34. High-Speed, Serial Timings

108 Datasheet

1. HSS_TXCLK and HSS_RXCLK may be coming from external independent sources or being driven by the

illustrative purposes and are not required to be synchronous.

1. Applicable when the HSS_RXFRAME and HSS_TXFRAME signals are being driven by an external source
2. The HSS_RXFRAME and HSS_TXFRAME can be configured to accept data on the rising or falling edge of

and HSS_TXFRAME and HSS_TXDATA signals are synchronous to the HSS_TXCLK.

1. Applicable when the HSS_RXFRAME and HSS_TXFRAME signals are being driven by the IXP42X product

line and IXC1100 control plane processors to an external source. Always applicable to HSS_TXDATA.

1. The HSS_TXCLK can be configured to be driven by an external source or be driven by the IXP42X product

accepted will be 50/50 + 20%.

1. Timing tests were performed with a 70-pF capacitor to ground and a 10-K

Table 63. High-Speed, Serial Timing Values

5.5.2.9 JTAG

1. Tests completed with a TBD pF load to ground on JTAG_TDO.
2. JTAG_TCK may be stopped indefinitely in either the low or high phase.

Figure 35. Boundary-Scan General Timings Figure 36. Boundary-Scan Reset Timings Table 64. Boundary-Scan Interface Timings Values

110 Datasheet

5.5.3 Reset Timings

Figure 37. Reset Timings

1. TRELEASE_PWRON_RST_N is the time required for the internal oscillator to reach stability. When an external

oscillator is being used in place of a crystal, the 500-ms delay is not required.

1. The expansion bus address is captured as a derivative of the RESET_IN_N signal going high. When a

active until PLL_LOCK is active.

1. PLL_LOCK is deasserted immediately when watchdog timer event occurs, or when RESET_IN_N is

watchdog reset is deasserted (internal to the chip). A ref clock time period is 1/CLKIN.

5.6 Power Sequence

line and IXC1100 control plane processors. Table 65. Reset Timings Table Parameters to drive the processors’ system clock. PWRON_RST_N signal is held low. for sampling configuration information. processors has been in normal operation.

112 Datasheet

5.7 I CC and Total Average Power

5.8 Ordering Information

For ordering information, please contact your local Intel sales representative. Figure 38. Power-up Sequence Timing Table 66. I CC and Total Average Power

400 MHz

533 MHz

1. Typical current ICC and ICCP are not tested. Typical currents were measured on the Intel®
2. Typical case power supply voltages V

specifications are tested and guaranteed.

1. The 400-MHz typical case core supply current is an approximation.