82562EP INTEL | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1.0 Introduction
- 1.1 Overview
- 1.2 References
- 1.3 Product Codes
- 2.1 LAN Connect Interface
- 2.2 Hardware Configuration
- 3.1 Signal Type Definitions
- 3.2 Twisted Pair Ethernet (TPE) Pins
- 3.3 External Bias Pins
- 3.4 Clock Pins
- 3.5 Platform LAN Connect Interface Pins
- 3.6 LED Pins
- 3.7 Miscellaneous Control Pins
- 3.8 Power and Ground Connections
- 4.0 Signal Terminations
- 4.1 Terminating Resistors
- 4.1.1 Termination Plane
- 4.1.2 Termination Plane Capacitance
- 5.1 Asynchronous Test Mode
- 5.2 Test Function Description
- 6.0 Electrical and Timing Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 DC Characteristics
- 6.2.1 X1 Clock DC Specifications
- 6.2.2 LAN Connect Interface DC Specifications
- 6.2.3 LED DC Specifications
- 7.0 Package and Pinout Information
- 7.1 Package Information
82562EP 10/100 Mbps Platform LAN Connect (PLC) Networking Silicon Datasheet Product Features 1 This device is lead-free. That is, lead has not been intentionally added, but lead may still exist as an impurity at <1000 ppm. The Material Declaration Data Sheet, which includes lead impurity levels and the concentration of other Restriction on Hazardous Substances (RoHS)- banned materials, is available at: ftp://download.intel.com/design/packtech/material_content_IC_Package.pdf#pagemode=bookmarks In addition, this device has been tested and conforms to the same parametric specifications as previous versions of the device. For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales representative. ■ IEEE 802.3 10BASE-T/100BASE-TX compliant physical layer interface ■ IEEE 802.3u Auto-Negotiation support ■ Digital Adaptive Equalization control ■ Link status interrupt capability ■ XOR tree mode support ■ 3-port LED support (speed, link and activity) ■ 10BASE-T auto-polarity correction ■ Alert on LAN functionality ■ Diagnostic loopback mode ■ 1:1 transmit transformer ratio support ■ Low power (less than 300 mW in active transmit mode) ■ Reduced power in “unplugged mode” (less than 50 mW) ■ Automatic detection of “unplugged mode” ■ 3.3 V device ■ Lead-free1 64-pin Plastic Ball Grid Array Package for both leaded and lead-free designs. (Devices that are lead-free are marked with a circled “e1” and have the product code prefix: PCxxxxxx). Revision 2.0 September 2005
Revision History
Revision Revision Date Description 1.0 August 2000 Initial release (Intel Secret). 1.4 May 2001 Finialized signal descriptions and pinouts. 1.5 October 2001 Changed document status to Intel Confidential - Controlled Access. 1.6 December 2003 Removed confidential status.
2.0 September 2005 Updated or new revision information includes:
- Lead-free information. Product codes. Bias reference resistor values (RBIAS 10 and RBIAS 100). Crystal input/output clock values. Signal termination section. Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or oth erwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel® products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 82562EP PLC may contain design defects or errors known as errata which may cause the product to deviate from published spec ifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © 2005, Intel Corporation * Other brands and names are the property of their respective owners.
82562EP — Networking Silicon iv Datasheet Figures Tables
Networking Silicon — 82562EP Datasheet 1
1.0 Introduction
1.1 Overview
The Intel® 82562EP is a highly-integrated Platform LAN Connect (PLC) device designed for 10 or 100 Mbps Ethernet systems. It is based on the IEEE 10BASE-T and 100BASE-TX standards. The IEEE 802.3u standard for 100BASE-TX defines networking over two pairs of Category 5 unshielded twisted pair cable or Type 1 shielded twisted pair cable. The 82562EP complies with the IEEE 802.3u Auto-Negotiation standard and the IEEE 802.3x Full Duplex Flow Control standard. The 82562EP also includes a PHY interface compliant to the current PLC interface.
1.2 References
IEEE 802.3 Standard for Local and Metropolitan Area Networks, Institute of Electrical and Electronics Engineers. LAN Connect Interface Specification. Intel Corporation. I/O Control Hub 2, 3, and 4 EEPROM Map and Programming Information. Intel Corporation. Programming information can be obtained through your local Intel representatives.
1.3 Product Codes
The product ordering code for a lead-free device is: PC82562EP. The product ordering code for a leaded device is: RC82562EP.
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with the IEEE 802.3 standard. Figure 1 shows a block diagram of the 82562EP architecture. Figure 1. 82562EP PLC Block Diagram
2.1 LAN Connect Interface
from a PLC in comparison to a standard MII PHY . Figure 2 shows how the 82562EP can be used in a 10/100 Mbps ICHx design. Figure 2. 82562EP PLC 10/100 Mbps Ethernet Solution
25 MHz
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2.2 Hardware Configuration
the different modes of operation. NOTE: Combinations not shown in Table 1 are reserved and should not be used. Table 1. 82562EP Hardware Configuration
Networking Silicon — 82562EP Datasheet 5 3.0 82562EP Signal Descriptions
3.1 Signal Type Definitions
3.2 Twisted Pair Ethernet (TPE) Pins
3.3 External Bias Pins
I Input Input pin to the 82562EP. O Output Output pin from the 82562EP. I/O Input/Output Multiplexed input and output pin to and from the 82562EP. MLT Multi-level analog I/O Multi-level analog pin used for input and output. B Bias Bias pin used for ground connection th rough a resistor or an external voltage reference. DPS Digital Power Supply Digital power or ground pin for the 82562EP. APS Analog Power Supply Analog power or ground pin for the 82562EP. Pin Name Pin Number Type Description TDP TDN MLT Transmit Differential Pair. The transmit differential pair sends serial bit streams to the unshielded twisted pair (UTP) cable. The differential pair is a two-level signal in 10BASE-T (Manchester) mode and a three-level signal in 100BASE-TX mode (MLT-3). These signals directly interface with the isolation transformer. RDP RDN MLT Receive Differential Pair. The receive differential pair receive the serial bit stream from an unshielded twisted pair (UTP) cable. The differential pair is a two-level signal in 10BASE-T mode (Manchester) or a three-level signal in 100BASE-TX mode (MLT-3). These signals directly interface with an isolation transformer. Pin Name Pin Number Type Description RBIAS10 F2 B Reference Bias Resistor (10 Mbps). This pin should be connected to a pull-down resistor.a a. Based on some board designs, RBIAS100 and RBIAS10 values may need to be increased/decreased to compensate for high/ low MDI transmit amplitude. See Section 4.0 for more information. RBIAS100 F1 B Reference Bias Resistor (100 Mbps). This pin should be connected to a pull-down resistor.a
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3.4 Clock Pins
3.5 Platform LAN Connect Interface Pins
X1 C2 I Crystal Input Clock. X1 and X2 can be driven by an external 25 MHz crystal of 30 PPM or better. Otherwise, X1 is driven by an external metal- oxide semiconductor (MOS) level 25 MHz oscillator when X2 is left floating. X2 C1 O Crystal Output Clock. X1 and X2 can be driven by an external 25 MHz crystal of 30 PPM or better. Pin Name Pin Number Type Description LAN_CLK A4 O LAN Connect Clock. The LAN Connect Clock is driven by the 82562EP on two frequencies depending on operation speed. When the 82562EP is in 100BASE-TX mode, LAN_CLK drives a 50 MHz clock. Otherwise, LAN_CLK drives a 5 MHz clock for 10BASE-T. The LAN_CLK does not stop during normal operation. LAN_RSTSYNC B3 I Reset/Synchronize. This is a multiplexed pin and is driven by the Media Access Control (MAC) layer device. Its functions are: Reset. When this pin is a sserted beyond one LAN Connect Clock period, the 82562EP uses this signal as Reset. To ensure the 82562EP is reset, this signal should remain active for at least 500 µs. Synchronize. When this pin is activated synchronously for only one LAN Connect Clock period, it is used to synchronize the MAC and PHY on PLC word boundaries. LAN_TXD[2:0] B1 I LAN Connect Transmit Data. The PLC transmit pins are used to transfer data from the MAC device to the 82562EP. These pins are used to move transmitted data and real time control and management data. They also transmit out of band control data from the MAC to the PHY. These pins should be fully synchronous to LAN_CLK. LAN_RXD[2:0] A5 O LAN Connect Receive Data. The PLC receive pins are used to transfer data from the 82562EP to the MAC device. These pins are used to move received data and real time control and management data. They also move out of band control data from the PHY to the MAC. These pins are synchronous to LAN_CLK.
Networking Silicon — 82562EP Datasheet 7
3.6 LED Pins
3.7 Miscellaneous Control Pins
LILED# O Link Integrity LED. The LED is active low and the Link Integrity LED pin indicates link status in either 10BASE-T or 100BASE-TX mode. If a link is present in either mode, the LILED# is asserted. ACTLED# O Activity LED. The LED is active low and the Activity LED signal indicates either receive or transmit activity. When no activity is present, the LED is off. The Activity LED will flicker when activity is present. T he flicker rate depends on the activity load. The individual address LED control bit in the ICH2 EEPROM (Word Ah, bit 4) can select the ACTLED# behavior. It controls the Activity LED (ACTLED) functionality in Wake on LAN (WOL) mode. 0b = In WOL mode, the ACTLED is activa ted by the transmission and reception of broadcast and individual address match packets. 1b = In WOL mode, the ACTLED is activa ted by the transmission and reception of individual address match packets only. This bit is configured by the OEM and is activated by a transmission and reception of individual address match packets. SPDLED# O Speed LED. The LED is active low and the Speed LED signal indicates the speed of operation, either 10 Mbps or 100 Mbps. The Speed LED is on during 100BASE-TX operation and off in 10BASE-T mode. Pin Name Type Description ADV10 I Advertise 10 Mbps Only. The this signal is asserted high, the 82562EP advertises only 10BASE-T technology during Auto-Negotiation processes in this state. Otherwise, the 82562EP advertises all of its technologies. Note: ADV10 has an internal pull-down resistor. ISOL_TCK I Test Clock. The Test Clock signal sets the device into asynchronous test mode in conjunction with the Test Input, Test Execute and Test Enable pins (refer to Table 1). In the manufacturing test mode, it acts as the test clock. Note: ISOL_TCK has an internal pull-down resistor. ISOL_TI I Test Input. The Test Input signal sets the device into asynchronous test mode in conjunction with the Test Clock, Test Execute and Test Enable pins (refer to Table 1). In the manufacturing test mode, it acts as the test data input pin. Note: ISOL_TI has an internal pull-down resistor. ISOL_TEX I Test Execute. The Test Execute signal sets the device into asynchronous test mode in conjunction with the Test Clock, Test Input, and Test Enable pins (refer to Table 1). In the manufacturing test mode, it places the command that was entered through the ISOL_TI pin in the instruction register. Note: ISOL_TEX has an internal pull-down resistor. TOUT O Test Output. The Test Output pin is used for Boundary XOR scan output. In the manufacturing test mode, it acts as the test output port. TESTEN I Test Enable. The Test Enable pin is used to enable test mode and should be tied to the pull-down resistor for normal operation.
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3.8 Power and Ground Connections
Pin Name Pin Number Type Description VCC VCCA VCCA2 VCCP VCCT A1, A8, E7, F7, F8 G1, H1 D2, E2 B4, B5 G4, G5, H4, H5 DPS Digital 3.3 V Power. These pins should be connected to the main digital power supply. VSS VSSA VSSA2 VSSP C3, C6, D3, D4, D5, D6, E3, E4, E5, E6, F3, F4, F5, F6 G2, H2 D1, E1 C4, C5 DPS Digital Ground. These pins should be connected to the main digital ground. VCCR G8, H8 APS Analog Power. These pins should be isolated from the main power using a resistor-capacitor (RC) filter. A ferrite bead may also be used in place of the resistor. VSSR G7, H7 APS Analog Ground. These pins should not be isolated from the main digital.
4.0 Signal Terminations
4.1 Terminating Resistors
connects to the MDI- (MDI negative) signal trace. Termination resistor values were recently increased from 49.9 Ω to 54.9 Ω to improve return loss. better meet the IEEE peak-to-peak center specification. +1025 mVpk for the positive peak. Figure 3. Termination Resistors Placement (Integrated Magnetics Solution)
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4.1.1 Termination Plane
Resistors are used to terminate noise from the unused inputs of both the RJ45 connector and the magnetics module to the termination plane. The netname “termplane” is provided as a guide to the termination plane. A termplane is a plane fabricated into the PCB substrate. This plane, which has no DC termination, acts like one-half of a capacitor that provides a path for the coupled noise.
4.1.2 Termination Plane Capacitance
It is recommended that the termination plane capacitance equal a minimum value of 1500 pF. This helps reduce the amount of crosstalk on the differential pairs (TDP and TDN and RDP and RDN) from the unused pairs of the RJ45. Pads may be placed for additional capacitance, which may be required if failure occurs during electrical fast transient testing. Note: This capacitor must be designed to tolerate 2 KV voltage injections to meet International Special Committee on Radio Interference (CISPR) Electrostatic Discharge (ESD) specifications.
device. The port provides the ability to perform basic production level testing.
5.1 Asynchronous Test Mode
5.2 Test Function Description
tests are described in the following sections. test output (TOUT) pin, are put into high-Z mode. These pins are driven to affect the tree’s output. Table 2. XOR Tree Chain Order
1 LAN_TXD2
2 LAN_TXD1
3 LAN_TXD0
4 LAN_RSTSYNC
6 LAN_CLK
10 ACTLED#
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11 SPDLED#
12 LILED#
6.0 Electrical and Timing Specifications
6.1 Absolute Maximum Ratings
conditions above those indicated in the operational sections of this specification is not implied.
6.2 DC Characteristics
6.2.1 X1 Clock DC Specifications
- This characteristic is only characterized, not tested. It is valid for digital pins only.
Table 3. General DC Specifications Table 4. X1 Clock DC Specifications
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6.2.2 LAN Connect Interf ace DC Specifications
- This characteristic is only characterized, not tested. It is valid for digital pins only.
6.2.3 LED DC Specifications
NOTES:Current is measured between the transmit di fferential pins (TDP and TDN) at 3.3 V.
- RL is the resistive load measured across the transmit differential pins, TDP and TDN.
Table 5. LAN Connect Interface DC Specifications Table 6. LED DC Specifications Table 7. 10BASE-T Transmitter
- The input differential resistance is measured across the receive differential pins, RDP and RDN.
NOTES:Current is measured between the transmit differential pins (TDP and TDN) at 3.3 V.
- RL is the resistive load measured across the transmit differential pins, TDP and TDN.
- The input differential resistance is measured across the receive differential pins, RDP and RDN.
Table 8. 10BASE-T Receiver
5 MHz ≤ f ≤ 10 MHz
Table 9. 100BASE-TX Transmitter Table 10. 100BASE-TX Receiver
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7.0 Package and Pinout Information
7.1 Package Information
Figure 4. Dimension Diagram for the 82562EP 64-pin PBGA (1 of 2)
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Figure 5. Dimension Diagram for the 82562EP 64-pin PBGA (2 of 2)
Table 11. 82562EP Pin Assignments
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Figure 6. 82562EP Pinout Diagram