28F640P3 INTEL | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 102
Technical content
Datasheet sections
- 1.0 Introduction
- 1.1 Nomenclature
- 1.2 Acronyms
- 1.3 Conventions
- 2.0 Functional Overview
- 3.0 Package Information
- 3.3 QUAD+ SCSP Packages
- 4.0 Ballout and Signal Descriptions
- 4.1 Signal Ballout
- 4.2 Signal Descriptions
- 4.3 SCSP Configurations
- 4.4 Memory Maps
- 5.0 Maximum Ratings and Operating Conditions
- 5.1 Absolute Maximum Ratings
- 5.2 Operating Conditions
- 6.0 Electrical Specifications
- 7.0 AC Characteristics
- 7.1 AC Test Conditions
- 7.2 Capacitance
- 7.3 AC Read Specifications
- 7.4 AC Write Specifications
- 7.5 Program and Erase Characteristics
- 8.0 Power and Reset Specifications
- 8.1 Power Up and Down
- 8.2 Reset Specifications
- 8.3 Power Supply Decoupling
- 9.0 Device Operations
- 9.1 Bus Operations
- 9.1.2 Writes
- 9.1.3 Output Disable
- 9.1.5 Reset
- 9.2 Device Commands
- 9.3 Command Definitions
Order Number: 306666, Revision: 001 April 2005 Intel StrataFlash® Embedded Memory (P30) 1-Gbit P30 Family Datasheet Product Features The Intel StrataFlash® Embedded Memory (P30) product is the latest generation of Intel StrataFlash® memory devices. Offered in 64-Mbit up through 1-Gbit densities, the P30 device brings reliable, two-bit-per-cell storage technology to the embedded flash market segment. Benefits include more density in less space, high-speed interface, lowest cost-per-bit NOR device, and support for code and data storage. Features include high-performance synchronous- burst read mode, fast asynchronous access times, low power, flexible security options, and three industry standard package choices. The P30 product family is manufactured using Intel ® 130 nm ETOX™ VIII process technology. ■ High performance — 85/88 ns initial access — 40 MHz with zero wait states, 20 ns clock-to- data output synchronous-burst read mode — 25 ns asynchronous-page read mode — 4-, 8-, 16-, and continuous-word burst mode — Buffered Enhanced Factory Programming (BEFP) at 5 µs/byte (Typ) — 1.8 V buffered programming at 7 µs/byte (Typ) ■ Architecture — Multi-Level Cell Technology: Highest Density at Lowest Cost — Asymmetrically-blocked architecture — Four 32-KByte parameter blocks: top or bottom configuration — 128-KByte main blocks ■ Voltage and Power —V CC (core) voltage: 1.7 V – 2.0 V —V CCQ (I/O) voltage: 1.7 V – 3.6 V — Standby current: 55 µA (Typ) for 256-Mbit — 4-Word synchronous read current: 13 mA (Typ) at 40 MHz ■ Quality and Reliability — Operating temperature: –40 °C to +85 °C
- 1-Gbit in SCSP is –30 °C to +85 °C — Minimum 100,000 erase cycles per block — ETOX™ VIII process technology (130 nm) ■ Security — One-Time Programmable Registers:
- 64 unique factory device identifier bits
- 64 user-programmable OTP bits
- Additional 2048 user-programmable OTP bits — Selectable OTP Space in Main Array:
- 4x32KB parameter blocks + 3x128KB main blocks (top or bottom configuration) — Absolute write protection: V PP = VSS — Power-transition erase/program lockout — Individual zero-latency block locking — Individual block lock-down ■ Software — 20 µs (Typ) program suspend — 20 µs (Typ) erase suspend —I n t e l® Flash Data Integrator optimized — Basic Command Set and Extended Command Set compatible — Common Flash Interface capable ■ Density and Packaging — 64/128/256-Mbit densities in 56-Lead TSOP package — 64/128/256/512-Mbit densities in 64-Ball Intel® Easy BGA package — 64/128/256/512-Mbit and 1-Gbit densities in Intel® QUAD+ SCSP — 16-bit wide data bus
April 2005 Intel StrataFlash ® Embedded Memory (P30) Datasheet
2 Order Number: 306666, Revision: 001
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY , RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY , OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not finalize a design with this information. StrataFlash® Embedded Memory (P30) Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © 2005, Intel Corporation * Other names and brands may be claimed as the property of others.
April 2005 Intel StrataFlash ® Embedded Memory (P30) Datasheet
4 Order Number: 306666, Revision: 001
Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 5
April 2005 Intel StrataFlash ® Embedded Memory (P30) Datasheet
6 Order Number: 306666, Revision: 001
Revision History
Revision Date Revision Description April 2005 -001 Initial Release
Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 7
1.0 Introduction
This document provides information about the Intel StrataFlash® Embedded Memory (P30) device and describes its features, operation, and specifications.
1.1 Nomenclature
1.2 Acronyms
1.8 V : VCC (core) voltage range of 1.7 V – 2.0 V 3.0 V : VCCQ (I/O) voltage range of 1.7 V – 3.6 V 9.0 V : VPP voltage range of 8.5 V – 9.5 V Block : A group of bits, bytes,1-Gbit P30 Family or words within the flash memory array that erase simultaneously when the Erase command is issued to the device. The 1-Gbit P30 Family has two block sizes: 32-KByte and 128-KByte. Main block : An array block that is usually used to store code and/or data. Main blocks are larger than parameter blocks. Parameter block : An array block that is usually used to store frequently changing data or small system parameters that traditionally would be stored in EEPROM. Top parameter device : A device with its parameter blocks located at the highest physical address of its memory map. Bottom parameter device : A device with its parameter blocks located at the lowest physical address of its memory map. BEFP : Buffer Enhanced Factory Programming CUI : Command User Interface MLC : Multi-Level Cell OTP : One-Time Programmable PLR : Protection Lock Register PR : Protection Register RCR : Read Configuration Register
April 2005 Intel StrataFlash ® Embedded Memory (P30) Datasheet
8 Order Number: 306666, Revision: 001
1.3 Conventions
RFU : Reserved for Future Use SR : Status Register WSM : Write State Machine VCC : Signal or voltage connection VCC : Signal or voltage level 0x : Hexadecimal number prefix 0b : Binary number prefix SR[4] : Denotes an individual register bit. A[15:0] : Denotes a group of similarly named signals, such as address or data bus. A5 : Denotes one element of a signal group membership, such as an individual address bit. Bit : Binary unit Byte : Eight bits Word : Two bytes, or sixteen bits Kbit : 1024 bits KByte : 1024 bytes KWord : 1024 words Mbit : 1,048,576 bits MByte : 1,048,576 bytes MWord : 1,048,576 words
Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 9
2.0 Functional Overview
This section provides an overview of the features and capabilities of the 1-Gbit P30 Family device. The P30 family provides density upgrades from 64-Mbit through 1-Gbit. This family of devices provides high performance at low voltage on a 16-bit data bus. Individually erasable memory blocks are sized for optimum code and data storage. Upon initial power up or return from reset, the device defaults to asynchronous page-mode read. Configuring the Read Configuration Register enables synchronous burst-mode reads. In synchronous burst mode, output data is synchronized with a user-supplied clock signal. A WAIT signal provides an easy CPU-to-flash memory synchronization. In addition to the enhanced architecture and interface, the device incorporates technology that enables fast factory program and erase operations. Designed for low-voltage systems, the 1-Gbit P30 Family supports read operations with V CC at 1.8 V , and erase and program operations with VPP at 1.8 V or 9.0 V. Buffered Enhanced Factory Programming (BEFP) provides the fastest flash array programming performance with VPP at 9.0 V , which increases factory throughput. With VPP at 1.8 V, VCC and VPP can be tied together for a simple, ultra low power design. In addition to voltage flexibility, a dedicated VPP connection provides complete data protection when V PP ≤ VPPLK. A Command User Interface (CUI) is the interface between the system processor and all internal operations of the device. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase and program. A Status Register indicates erase or program completion and any errors that may have occurred. An industry-standard command sequence invokes program and erase automation. Each erase operation erases one block. The Erase Suspend feature allows system software to pause an erase cycle to read or program data in another block. Program Suspend allows system software to pause programming to read other locations. Data is programmed in word increments (16 bits). The 1-Gbit P30 Family’s protection register allows unique flash device identification that can be used to increase system security. The individual Block Lock feature provides zero-latency block locking and unlocking. In addition, the P30 device also has four pre-defined spaces in the main array that can be configured as One-Time Programmable (OTP).
10 Order Number: 306666, Revision: 001
3.0 Package Information
Figure 1. TSOP Mechanical Specifications Table 1. TSOP Package Dimensions (Sheet 1 of 2)
Table 1. TSOP Package Dimensions (Sheet 2 of 2)
12 Order Number: 306666, Revision: 001
Figure 2. Easy BGA Mechanical Specifications Table 2. Easy BGA Package Dimensions
3.3 QUAD+ SCSP Packages
Figure 3. 64/128-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x10x1.2 mm)
14 Order Number: 306666, Revision: 001
Figure 4. 256-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x11x1.0 mm)
Figure 5. 512-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x11x1.2 mm)
16 Order Number: 306666, Revision: 001
Figure 6. 1-Gbit, 88-ball (80 active) QUAD+ SCSP Specifications (11x11x1.4 mm)
4.0 Ballout and Signal Descriptions
4.1 Signal Ballout
- A1 is the least significant address bit.
- A23 is valid for 128-Mbit densities and above; otherwise, it is a no connect (NC).
- A24 is valid for 256-Mbit densities and above; otherwise, it is a no connect (NC).
Figure 7. 56-Lead TSOP Pinout (64/128/256-Mbit)
18 Order Number: 306666, Revision: 001
- A1 is the least significant address bit.
- A23 is valid for 128-Mbit densities and above; otherwise, it is a no connect (NC).
- A24 is valid for 256-Mbit densities and above; otherwise, it is a no connect (NC).
- A25 is valid for 512-Mbit densities; otherwise, it is a no connect (NC).
Figure 8. 64-Ball Easy BGA Ballout (64/128/256/512-Mbit)
Figure 9. 88-Ball (80-Active Ball) QUAD+ SCSP Ballout
20 Order Number: 306666, Revision: 001
4.2 Signal Descriptions
This section has signal descriptions for the various P30 packages. Table 3. TSOP and Easy BGA Signal Descriptions (Sheet 1 of 2) See T able 5 on page 22 and Figure 10 on page 23 for 512-Mbit addressing. float when the CE# or OE# are deasserted. Data is internally latched during writes. the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first. WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through. WAIT outputs are placed in high-Z state. WARNING: All chip enables must be high when device is not in use. CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode. next valid CLK edge with ADV# low, whichever occurs first. WARNING: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS. cycles. OE# high places the data outputs and WAIT in High-Z. reset places the device in asynchronous read array mode. VOH when CE# and OE# are VIL. WAIT is high-Z if CE# or OE# is VIH.
- In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and valid data when deasserted.
- In asynchronous page mode, and all write modes, WAIT is deasserted. WE# Input WRITE ENABLE: Active low input. WE# controls writes to the device. Address and data are latched on the rising edge of WE#. WP# Input WRITE PROTECT: Active low input. WP# low enables the lock-down mechanism. Blocks in lock- down cannot be unlocked with the Unlock command. WP# high overrides the lock-down function enabling blocks to be erased or programmed using software commands. VPP Power/ Input Erase and Program Power: A valid voltage on this pin allows erasing or programming. Memory contents cannot be altered when V PP ≤ VPPLK. Block erase and program at invalid V PP voltages should not be attempted. Set VPP = VCC for in-system program and erase operations. T o accommodate resistor or diode drops from the system supply, the VIH level of VPP can be as low as VPPL min. VPP must remain above VPPL min to perform in-system flash modification. VPP may be 0 V during read operations. VPPH can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles. VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of this pin at 9 V may reduce block cycling capability. VCC Power Device Core Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited when VCC ≤ VLKO. Operations at invalid VCC voltages should not be attempted.
VCCQ Power Output Power Supply: Output-driver source voltage. VSS Power Ground: Connect to system ground. Do not float any VSS connection. should be treated in the same way as a Do Not Use (DU) signal. DU — Do Not Use: Do not connect to any other signal, or power supply; must be left floating. NC — No Connect: No internal connection; can be driven or floated. Table 3. TSOP and Easy BGA Signal Descriptions (Sheet 2 of 2) Table 4. QUAD+ SCSP Signal Descriptions (Sheet 1 of 2) float when the CE# or OE# are deasserted. Data is internally latched during writes. the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first. WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through. WAIT outputs are placed in high-Z state. See Table 6 on page 22 for CE# assignment definitions. WARNING: All chip enables must be high when device is not in use. CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode. next valid CLK edge with ADV# low, whichever occurs first. WARNING: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS. cycles. OE# high places the data outputs and WAIT in High-Z. F1-OE# and F2-OE# should be tied together for all densities. reset places the device in asynchronous read array mode. VOH when CE# and OE# are VIL. WAIT is high-Z if CE# or OE# is VIH.
- In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and valid data when deasserted.
- In asynchronous page mode, and all write modes, WAIT is deasserted. WE# Input WRITE ENABLE: Active low input. WE# controls writes to the device. Address and data are latched on the rising edge of WE#.
22 Order Number: 306666, Revision: 001
4.3 SCSP Configurations
enabling blocks to be erased or programmed using software commands. min to perform in-system flash modification. VPP may be 0 V during read operations. this pin at 9 V may reduce block cycling capability. VCC ≤ VLKO. Operations at invalid VCC voltages should not be attempted. VCCQ Power Output Power Supply: Output-driver source voltage. VSS Power Ground: Connect to system ground. Do not float any VSS connection. should be treated in the same way as a Do Not Use (DU) signal. DU — Do Not Use: Do not connect to any other signal, or power supply; must be left floating. NC — No Connect: No internal connection; can be driven or floated. Table 4. QUAD+ SCSP Signal Descriptions (Sheet 2 of 2) Table 5. Stacked Easy BGA Chip Select Logic Table 6. QUAD+ SCSP Chip Select Logic
24 Order Number: 306666, Revision: 001
4.4 Memory Maps
Operations” on page 61 for Programming Region information. Table 7. Discrete Top Parameter Memory Maps (all packages)
Table 8. Discrete Bottom Parameter Memory Maps (all packages)
26 Order Number: 306666, Revision: 001
Table 9. 512-Mbit Memory Map (Easy BGA and QUAD+ SCSP)
2 Flash Die #2
1 Flash Die #1 (Bottom
Note: Refer to 256-Mbit Memory Map ( Table 7 and T able 8) for Programming Region Information.
28 Order Number: 306666, Revision: 001
Table 10. 1-Gbit Memory Map (QUAD+ SCSP only)
4 Flash Die #4
3 Flash Die #3
1 Flash Die #1
Note: Refer to 256-Mbit Memory Map ( Table 7 and Table 8) for Programming Region Information.
Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 29
5.0 Maximum Ratings and Operating Conditions
5.1 Absolute Maximum Ratings
Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Parameter Maximum Rating Notes Temperature under bias –40 °C to +85 °C 1 Storage temperature –65 °C to +125 °C Voltage on any signal (except VCC, VPP) –0.5 V to +4.1 V 2 VPP voltage –0.2 V to +10 V 2,3,4 VCC voltage –0.2 V to +2.5 V 2 VCCQ voltage –0.2 V to +4.1 V 2 Output short circuit current 100 mA 5 Notes: 1. Temperature for 1-Gbit SCSP is –30 °C to +85 °C. 2. Voltages shown are specified with respect to V SS. Minimum DC voltage is –0.5 V on input/output signals and –0.2 V on VCC, VCCQ, and VPP. During transitions, this level may undershoot to –2.0 V for periods < 20 ns. Maximum DC voltage on V CC is VCC + 0.5 V, which, during transitions, may overshoot to VCC + 2.0 V for periods < 20 ns. Maximum DC voltage on input/output signals and V CCQ is VCCQ + 0.5 V, which, during transitions, may overshoot to V CCQ + 2.0 V for periods < 20 ns. 3. Maximum DC voltage on V PP may overshoot to +11.5 V for periods < 20 ns. any blocks for 1000 cycles maximum. 9.0 V program/erase voltage may reduce block cycling capability. 5. Output shorted for no more than one second. No more than one output shorted at a time.
30 Order Number: 306666, Revision: 001
5.2 Operating Conditions
the “Operating Conditions” may affect device reliability. Table 11. Operating Conditions
- Temperature for 1-Gbit SCSP is –30 °C to +85 °C.
- In typical operation, the VPP program voltage is V
6.0 Electrical Specifications
6.1 DC Current Characteristics
Table 12. DC Current Characteristics (Sheet 1 of 2)
32 Order Number: 306666, Revision: 001
6.2 DC Voltage Characteristics
- All currents are RMS unless noted. Typical values at typical V CC, TC = +25 °C.
- I CCS is the average current measured over any 5 ms time interval 5 µs after CE# is deasserted.
- Sampled, not 100% tested.
CC read + program current is the sum of V CC read and VCC program currents.
- V CC read + erase current is the sum of V CC read and VCC erase currents.
- I CCES is specified with the device deselected. If device is read while in erase suspend, current is I CCES plus ICCR.
- I CCW, ICCE measured over typical or max times specified in Section 7.5, “Program and Erase Characteristics” on
Table 13. DC Voltage Characteristics
- Synchronous read mode is not supported with TTL inputs.
IL can undershoot to –0.4 V and V IH can overshoot to VCCQ+ 0.4 V for durations of 20 ns or less.
- V PP ≤ VPPLK inhibits erase and program operations. Do not use V PPL and VPPH outside their valid ranges.
Table 12. DC Current Characteristics (Sheet 2 of 2)
7.0 AC Characteristics
7.1 AC Test Conditions
at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns. Worst case speed occurs at V CC = VCCMin.
- See the following table for component values.
- T est configuration component value for worst case speed conditions.
Figure 13. AC Input/Output Reference Waveform Figure 14. Transient Equivalent Testing Load Circuit Table 14. Test configuration component value for worst case speed conditions Figure 15. Clock Input AC Waveform
34 Order Number: 306666, Revision: 001
7.2 Capacitance
Table 15. Capacitance
- Capacitance values are for a single die; for 2-die and 4-die stacks multiple the above values by the number of die in the
- Sampled, not 100% tested.
- Silicon die capacitance only, add 1 pF for discrete packages.
7.3 AC Read Specifications
Table 16. AC Read Specifications for 64/128-Mbit Densities (Sheet 1 of 2)
36 Order Number: 306666, Revision: 001
- See Figure 13, “AC Input/Output Reference Waveform” on page 33 for timing measurements and max allowable input
- OE# may be delayed by up to t ELQV – tGLQV after CE#’s falling edge without impact to tELQV.
- Sampled, not 100% tested.
- Address hold in synchronous burst mode is t
CHAX or tVHAX, whichever timing specification is satisfied first.
- Applies only to subsequent synchronous reads.
- See your local Intel representative for designs requiring higher than 40 MHz synchronous operation.
Table 16. AC Read Specifications for 64/128-Mbit Densities (Sheet 2 of 2) Table 17. AC Read Specifications for 256/512-Mbit and 1-Gbit Densities (Sheet 1 of 2)
- See Figure 13, “AC Input/Output Reference Waveform” on page 33 for timing measurements and max allowable input
- OE# may be delayed by up to t ELQV – tGLQV after CE#’s falling edge without impact to tELQV.
- Sampled, not 100% tested.
- Address hold in synchronous burst mode is t
CHAX or tVHAX, whichever timing specification is satisfied first.
- Applies only to subsequent synchronous reads.
- See your local Intel representative for designs requiring higher than 40 MHz synchronous operation.
Table 17. AC Read Specifications for 256/512-Mbit and 1-Gbit Densities (Sheet 2 of 2)
38 Order Number: 306666, Revision: 001
Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0, Wait asserted low). Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0, Wait asserted low). Figure 16. Asynchronous Single-Word Read (ADV# Low) Figure 17. Asynchronous Single-Word Read (ADV# Latch)
40 Order Number: 306666, Revision: 001
- WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to
assert either during or one data cycle before valid data.
- At the end of Word Line; the delay incurred when a burst access crosses a 16-word boundary and the
starting address is not 4-word boundary aligned. Figure 20. Continuous Burst Read, showing an Output Delay Timing
initial latency and deasserted during valid data (RCR[10] = 0, Wait asserted low).
7.4 AC Write Specifications
Figure 21. Synchronous Burst-Mode Four-Word Read Timing Table 18. AC Write Specifications (Sheet 1 of 2)
42 Order Number: 306666, Revision: 001
- Write timing characteristics during erase suspend are the same as write-only operations.
- A write operation can be terminated with either CE# or WE#.
- Sampled, not 100% tested.
CE# or WE# high (whichever occurs first). Hence, t WLWH = tELEH = tWLEH = tELWH.
- Write pulse width high (t WHWL or tEHEL) is defined from CE# or WE# high (whichever occurs first) to
CE# or WE# low (whichever occurs last). Hence, t WHWL = tEHEL = tWHEL = tEHWL).
- t WHVH or tWHCH/L must be met when transitioning from a write cycle to a synchronous burst read.
- V PP and WP# should be at a valid level until erase or program success is determined.
- This specification is only applicable when transitioning from a write cycle to an asynchronous read.
See spec W19 and W20 for synchronous read.
- When doing a Read Status operation following any command that alters the Status Register, W14 is
- Add 10 ns if the write operations results in a RCR or block lock status change, for the subsequent
read operation to reflect this change.
- These specs are required only when the device is in a synchronous mode and clock is active during
Table 18. AC Write Specifications (Sheet 2 of 2) Figure 22. Write-to-Write Timing
44 Order Number: 306666, Revision: 001
ignored during write operation. Note: WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR[10]=0, Wait asserted low). Figure 25. Synchronous Read-to-Write Timing Figure 26. Write-to-Synchronous Read Timing
Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 45
7.5 Program and Erase Characteristics
Conventional Word Programming W200 t PROG/W Program Time Single word - 90 200 - 85 190 µs 1Single cell - 30 60 - 30 60 Buffered Programming W200 t PROG/W Program Time Single word - 90 200 - 85 190 µs 1W251 t BUFF 32-word buffer - 440 880 - 340 680 Buffered Enhanced Factory Programming W451 t BEFP/W Program Single word n/a n/a n/a - 10 - µs 1,2 W452 tBEFP/ Setup BEFP Setup n/a n/a n/a 5 - - 1 Erasing and Suspending W500 t ERS/PB Erase Time 32-KByte Parameter - 0.4 2.5 - 0.4 2.5 s 1W501 t ERS/MB 128-KByte Main - 1.2 4.0 - 1.0 4.0 W600 t SUSP/P Suspend Latency Program suspend - 20 25 - 20 25 µsW601 t SUSP/E Erase suspend - 20 25 - 20 25 Notes: 1. Typical values measured at T C = +25 °C and nominal voltages. Performance numbers are valid for all speed versions. Excludes system overhead. Sampled, but not 100% tested. 2. Averaged over entire device.
April 2005 Intel StrataFlash ® Embedded Memory (P30) Datasheet
46 Order Number: 306666, Revision: 001
8.0 Power and Reset Specifications
8.1 Power Up and Down
Power supply sequencing is not required if VCC, VCCQ, and VPP are connected together; If VCCQ and/or VPP are not connected to the VCC supply, then VCC should attain VCCMIN before applying VCCQ and VPP. Device inputs should not be driven before supply voltage equals VCCMIN. Power supply transitions should only occur when RST# is low. This protects the device from accidental programming or erasure during power transitions.
8.2 Reset Specifications
Asserting RST# during a system reset is important with automated program/erase devices because systems typically expect to read from flash memory when coming out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization may not occur. This is because the flash memory may be providing status information, instead of array data as expected. Connect RST# to the same active low reset signal used for CPU initialization. Also, because the device is disabled when RST# is asserted, it ignores its control inputs during power-up/down. Invalid bus conditions are masked, providing a level of memory protection. Num Symbol Parameter Min Max Unit Notes P1 t PLPH RST# pulse width low 100 - ns 1,2,3,4 P2 t PLRH RST# low to device reset during erase - 25 µs 1,3,4,7 RST# low to device reset during program - 25 1,3,4,7 P3 t VCCPH VCC Power valid to RST# de-assertion (high) 60 - 1,4,5,6 Notes: 1. These specifications are valid for all device versions (packages and speeds). 2. The device may reset if t PLPH is < tPLPH MIN, but this is not guaranteed. 3. Not applicable if RST# is tied to Vcc. 4. Sampled, but not 100% tested. 5. If RST# is tied to the V CC supply, device will not be ready until tVCCPH after VCC ≥ VCCMIN. 6. If RST# is tied to any supply/signal with V CCQ voltage levels, the RST# input voltage must not exceed VCC until VCC ≥ VCCMIN. 7. Reset completes within t PLPH if RST# is asserted while no erase or program operation is executing.
8.3 Power Supply Decoupling
produced when CE# and OE# are asserted and deasserted. voltage droop caused by PCB trace inductance. Figure 27. Reset Operation Waveforms
48 Order Number: 306666, Revision: 001
9.0 Device Operations
Machine (WSM) manages all block-erase and word-program algorithms. through which the flash device is controlled.
9.1 Bus Operations
low activates the outputs and gates selected data onto the I/O bus.
9.1.1 Reads
To perform a read operation, RST# and WE# must be deasserted while CE# and OE# are asserted. data-output control. When asserted, the addressed flash memory data is driven onto the I/O bus. Section 14.0, “Special Read States” on page 75 for details regarding the available read states. Table 19. Bus Operations Summary
- Refer to the Table 20, “Command Bus Cycles” on page 50 for valid DQ[15:0] during a write operation.
SS ± 0.2 V to meet the maximum specified power-down current.
Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 49
9.1.2 Writes
To perform a write operation, both CE# and WE# are asserted while RST# and OE# are deasserted. During a write operation, address and data are latched on the rising edge of WE# or CE#, whichever occurs first. Table 20, “Command Bus Cycles” on page 50 shows the bus cycle sequence for each of the supported device commands, while Table 21, “Command Codes and Definitions” on page 51 describes each command. See Section 7.0, “AC Characteristics” on page 33 for signal-timing details. Note: Write operations with invalid V CC and/or VPP voltages can produce spurious results and should not be attempted.
9.1.3 Output Disable
When OE# is deasserted, device outputs DQ[15:0] are disabled and placed in a high-impedance (High-Z) state, WAIT is also placed in High-Z.
9.1.4 Standby
When CE# is deasserted the device is deselected and placed in standby, substantially reducing power consumption. In standby, the data outputs are placed in High-Z, independent of the level placed on OE#. Standby current, I CCS, is the average current measured over any 5 ms time interval, 5 µs after CE# is deasserted. During standby, average current is measured over the same time interval 5 µs after CE# is deasserted. When the device is deselected (while CE# is deasserted) during a program or erase operation, it continues to consume active power until the program or erase operation is completed.
9.1.5 Reset
As with any automated device, it is important to assert RST# when the system is reset. When the system comes out of reset, the system processor attempts to read from the flash memory if it is the system boot device. If a CPU reset occurs with no flash memory reset, improper CPU initialization may occur because the flash memory may be providing status information rather than array data. Flash memory devices from Intel allow proper CPU initialization following a system reset through the use of the RST# input. RST# should be controlled by the same low-true reset signal that resets the system CPU. After initial power-up or reset, the device defaults to asynchronous Read Array, and the Status Register is set to 0x80. Asserting RST# de-energizes all internal circuits, and places the output drivers in High-Z. When RST# is asserted, the device shuts down the operation in progress, a process which takes a minimum amount of time to complete. When RST# has been deasserted, the device is reset to asynchronous Read Array state. Note: If RST# is asserted during a program or erase operation, the operation is terminated and the memory contents at the aborted location (for a program) or block (for an erase) are no longer valid, because the data may have been only partially written or erased. When returning from a reset (RST# deasserted), a minimum wait is required before the initial read access outputs valid data. Also, a minimum delay is required after a reset before a write cycle can be initiated. After this wake-up interval passes, normal operation is restored. See Section 7.0, “AC Characteristics” on page 33 for details about signal-timing.
50 Order Number: 306666, Revision: 001
9.2 Device Commands
appropriate suspend command. Table 20. Command Bus Cycles (Sheet 1 of 2)
9.3 Command Definitions
Valid device command codes and descriptions are shown in Table 21.
- First command cycle address should be the same as the operation’s target address.
IA = Identification code address offset. QA = CFI Query address offset. WA = Word address of memory location to be written. BA = Address within the block. PRA = Protection Register address. LRA = Lock Register address. RCD = Read Configuration Register data on A[15:0]. QD = Query data on DQ[15:0]. N = Word count of data to be loaded into the write buffer. PD = Protection Register data.
- The second cycle of the Buffered Program Command is the word count of the data to be loaded into the write buffer. This
- The confirm command (0xD0) is followed by the buffer data.
Table 20. Command Bus Cycles (Sheet 2 of 2) Table 21. Command Codes and Definitions (Sheet 1 of 2) 0xFF Read Array Places the device in Read Array mode. Array data is output on DQ[15:0]. Protection Register data on DQ[15:0]. Flash Interface information on DQ[7:0]. command is used to clear the SR error bits. command must be issued to read array data after programming has finished.
52 Order Number: 306666, Revision: 001
Program Setup Equivalent to the Word Program Setup command, 0x40. words onto the program buffer. algorithm, writing the data from the buffer to the flash memory array. and data, and prepares the device for BEFP mode. places the device in read status register mode. indicating a command sequence error. indicating a command sequence error. CUI latches the address and writes A[15:0] to the Read Configuration Register. read operations access array data. Table 21. Command Codes and Definitions (Sheet 2 of 2)
Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 53
10.0 Read Operations
The device supports two read modes: asynchronous page mode and synchronous burst mode. Asynchronous page mode is the default read mode after device power-up or a reset. The Read Configuration Register must be configured to enable synchronous burst reads of the flash memory array (see Section 10.3, “Read Configuration Register” on page 54). The device can be in any of four read states: Read Array, Read Identifier, Read Status or Read Query. Upon power-up, or after a reset, the device defaults to Read Array. To change the read state, the appropriate read command must be written to the device (see Section 9.2, “Device Commands” on page 50). See Section 14.0, “Special Read States” on page 75 for details regarding Read Status, Read ID, and CFI Query modes. The following sections describe read-mode operations in detail.
10.1 Asynchronous Page-Mode Read
Following a device power-up or reset, asynchronous page mode is the default read mode and the device is set to Read Array. However, to perform array reads after any other device operation (e.g. write operation), the Read Array command must be issued in order to read from the flash memory array. Note: Asynchronous page-mode reads can only be performed when Read Configuration Register bit RCR[15] is set (see Section 10.3, “Read Configuration Register” on page 54). To perform an asynchronous page-mode read, an address is driven onto the Address bus, and CE# and ADV# are asserted. WE# and RST# must already have been deasserted. WAIT is deasserted during asynchronous page mode. ADV# can be driven high to latch the address, or it must be held low throughout the read cycle. CLK is not used for asynchronous page-mode reads, and is ignored. If only asynchronous reads are to be performed, CLK should be tied to a valid V IH level, WAIT signal can be floated and ADV# must be tied to ground. Array data is driven onto DQ[15:0] after an initial access time t AV Q V delay. (see Section 7.0, “AC Characteristics” on page 33). In asynchronous page mode, four data words are “sensed” simultaneously from the flash memory array and loaded into an internal page buffer. The buffer word corresponding to the initial address on the Address bus is driven onto DQ[15:0] after the initial access delay. The lowest two address bits determine which word of the 4-word page is output from the data buffer at any given time.
10.2 Synchronous Burst-Mode Read
To perform a synchronous burst- read, an initial address is driven onto the Address bus, and CE# and ADV# are asserted. WE# and RST# must already have been deasserted. ADV# is asserted, and then deasserted to latch the address. Alternately, ADV# can remain asserted throughout the burst access, in which case the address is latched on the next valid CLK edge while ADV# is asserted. During synchronous array and non-array read modes, the first word is output from the data buffer on the next valid CLK edge after the initial access latency delay (see Section 10.3.2, “Latency Count” on page 55). Subsequent data is output on valid CLK edges following a minimum delay.
54 Order Number: 306666, Revision: 001
- Figure 19, “Synchronous Single-Word Array or Non-array Read Timing” on page 39
- Figure 20, “Continuous Burst Read, showing an Output Delay Timing” on page 40
- Figure 21, “Synchronous Burst-Mode Four-Word Read Timing” on page 41
10.3 Read Configuration Register
offset 0x05 (see Section 14.2, “Read Device Identifier” on page 76). The RCR is shown in Table 22. The following sections describe each RCR bit. Table 22. Read Configuration Register Description (Sheet 1 of 2)
15 Read Mode (RM) 0 = Synchronous burst-mode read
14 Reserved (R) Reserved bits should be cleared (0)
10 Wait Polarity (WP) 0 =WAIT signal is active low
9 Data Hold (DH) 0 =Data held for a 1-clock data cycle
8 Wait Delay (WD) 0 =WAIT deasserted with valid data
7 Burst Sequence (BS) 0 =Reserved
6 Clock Edge (CE) 0 = Falling edge
10.3.1 Read Mode
cleared, synchronous burst mode is selected.
10.3.2 Latency Count
word is to be driven onto DQ[15:0]. The input clock frequency is used to determine this value. Figure 28 shows the data output latency for the different settings of LC[2:0]. Refer to Table 23, “LC and Frequency Support” on page 56 for Latency Code Settings.
3 Burst Wrap (BW) 0 =Wrap; Burst accesses wrap within burst length set by BL[2:0]
data (WD = 1) combination is not supported. Table 22. Read Configuration Register Description (Sheet 2 of 2)
56 Order Number: 306666, Revision: 001
See Figure 29, “Example Latency Count Setting using Code 3. Figure 28. First-Access Latency Count Table 23. LC and Frequency Support
10.3.3 WAIT Polarity
The WAIT Polarity bit (WP), RCR[10] determines the asserted level (VOH or VOL) of WAIT. When WP is set, WAIT is asserted high (default). When WP is cleared, WAIT is asserted low.
10.3.3.1 WAIT Signal Function
(RCR[15]=0). The WAIT signal is only “deasserted” when data is valid on the bus. read query. The WAIT signal is also “deasserted” when data is valid on the bus. Page-Mode Read Timing” on page 39. Figure 29. Example Latency Count Setting using Code 3
58 Order Number: 306666, Revision: 001
10.3.4 Data Hold
Table 24. WAIT Functionality Table
- When OE# = V IH during writes, WAIT = High-Z
Figure 30. Data Hold Timing
2 CLK
1 CLK
10.3.5 WAIT Delay
WD is cleared, WAIT is deasserted during valid data.
10.3.6 Burst Sequence
effect of the Burst Wrap (BW) setting.
10.3.7 Clock Edge
edge is used at the start of a burst cycle, to output synchronous data, and to assert/deassert WAIT.
10.3.8 Burst Wrap
set, burst wrapping does not occur (default). When BW is cleared, burst wrapping occurs. Table 25. Burst Sequence Word Ordering
April 2005 Intel StrataFlash ® Embedded Memory (P30) Datasheet
60 Order Number: 306666, Revision: 001
boundary, the worst case output delay is one clock cycle less than the first access Latency Count. This delay can take place only once, and doesn’t occur if the burst sequence does not cross a device-row boundary. WAIT informs the system of this delay when it occurs.
10.3.9 Burst Length
The Burst Length bit (BL[2:0]) selects the linear burst length for all synchronous burst reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word, and continuous word. Continuous-burst accesses are linear only, and do not wrap within any word length boundaries (see Table 25, “Burst Sequence Word Ordering” on page 59). When a burst cycle begins, the device outputs synchronous burst data until it reaches the end of the “burstable” address space.
11.0 Programming Operations
the device. The following sections describe device programming in detail. WP# must be deasserted and the block must be unlocked before attempting to program the block. address ranges of each Programming Region per density. Execute in Place (XIP) is defined as the ability to execute code directly from the flash memory.
11.1 Word Programming
the specified VPPL min/max values (nominally 1.8 V). Table 26. Programming Regions per Device Code : Execution code ran out of the flash device on a continuous basis in the system. Data : Information periodically programmed into the flash device and read back (e.g. execution code shadowed and executed in RAM, pictures, log files, etc.).
April 2005 Intel StrataFlash ® Embedded Memory (P30) Datasheet
62 Order Number: 306666, Revision: 001
During programming, the Write State Machine (WSM) executes a sequence of internally-timed events that program the desired data bits at the addressed location, and verifies that the bits are sufficiently programmed. Programming the flash memory array changes “ones” to “zeros”. Memory array bits that are zeros can be changed to ones only by erasing the block (see Section 12.0, “Erase Operations” on page 67). The Status Register can be examined for programming progress and errors by reading at any address. The device remains in the Read Status Register state until another command is written to the device. Status Register bit SR[7] indicates the programming status while the sequence executes. Commands that can be issued to the device during programming are Program Suspend, Read Status Register, Read Device Identifier, CFI Query, and Read Array (this returns unknown data). When programming has finished, Status Register bit SR[4] (when set) indicates a programming failure. If SR[3] is set, the WSM could not perform the word programming operation because V PP was outside of its acceptable limits. If SR[1] is set, the word programming operation attempted to program a locked block, causing the operation to abort. Before issuing a new command, the Status Register contents should be examined and then cleared using the Clear Status Register command. Any valid command can follow, when word programming has completed.
11.1.1 Factory Word Programming
Factory word programming is similar to word programming in that it uses the same commands and programming algorithms. However, factory word programming enhances the programming performance with V PP = VPPH. This can enable faster programming times during OEM manufacturing processes. Factory word programming is not intended for extended use. See Section 5.2, “Operating Conditions” on page 30 for limitations when VPP = VPPH. Note: When VPP = VPPL, the device draws programming current from the V CC supply. If VPP is driven by a logic signal, VPPL must remain above VPPL MIN to program the device. When VPP = VPPH, the device draws programming current from the V PP supply. Figure 31, “Example VPP Supply Connections” on page 66 shows examples of device power supply configurations.
11.2 Buffered Programming
The device features a 32-word buffer to enable optimum programming performance. For Buffered Programming, data is first written to an on-chip write buffer. Then the buffer data is programmed into the flash memory array in buffer-size increments. This can improve system programming performance significantly over non-buffered programming. When the Buffered Programming Setup command is issued (see Section 9.2, “Device Commands” on page 50), Status Register information is updated and reflects the availability of the buffer. SR[7] indicates buffer availability: if set, the buffer is available; if cleared, the buffer is not available. To retry, issue the Buffered Programming Setup command again, and re-check SR[7]. When SR[7] is set, the buffer is ready for loading. (see Figure 42, “Buffer Program Flowchart” on page 87). On the next write, a word count is written to the device at the buffer address. This tells the device how many data words will be written to the buffer, up to the maximum size of the buffer.
Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 63 On the next write, a device start address is given along with the first data to be written to the flash memory array. Subsequent writes provide additional device addresses and data. All data addresses must lie within the start address plus the word count. Optimum programming performance and lower power usage are obtained by aligning the starting address at the beginning of a 32-word boundary (A[4:0] = 0x00). Crossing a 32-word boundary during programming will double the total programming time. After the last data is written to the buffer, the Buffered Programming Confirm command must be issued to the original block address. The WSM begins to program buffer contents to the flash memory array. If a command other than the Buffered Programming Confirm command is written to the device, a command sequence error occurs and Status Register bits SR[7,5,4] are set. If an error occurs while writing to the array, the device stops programming, and Status Register bits SR[7,4] are set, indicating a programming failure. When Buffered Programming has completed, additional buffer writes can be initiated by issuing another Buffered Programming Setup command and repeating the buffered program sequence. Buffered programming may be performed with V PP = VPPL or VPPH (see Section 5.2, “Operating Conditions” on page 30 for limitations when operating the device with VPP = VPPH). If an attempt is made to program past an erase-block boundary using the Buffered Program command, the device aborts the operation. This generates a command sequence error, and Status Register bits SR[5,4] are set. If Buffered programming is attempted while V PP is below VPPLK, Status Register bits SR[4,3] are set. If any errors are detected that have set Status Register bits, the Status Register should be cleared using the Clear Status Register command.
11.3 Buffered Enhanced Factory Programming
Buffered Enhanced Factory Programing (BEFP) speeds up Multi-Level Cell (MLC) flash programming. The enhanced programming algorithm used in BEFP eliminates traditional programming elements that drive up overhead in device programmer systems. BEFP consists of three phases: Setup, Program/Verify, and Exit (see Figure 43, “BEFP Flowchart” on page 88). It uses a write buffer to spread MLC program performance across 32 data words. Verification occurs in the same phase as programming to accurately program the flash memory cell to the correct bit state. A single two-cycle command sequence programs the entire block of data. This enhancement eliminates three write cycles per buffer: two commands and the word count for each set of 32 data words. Host programmer bus cycles fill the device’s write buffer followed by a status check. SR[0] indicates when data from the buffer has been programmed into sequential flash memory array locations. Following the buffer-to-flash array programming sequence, the Write State Machine (WSM) increments internal addressing to automatically select the next 32-word array boundary. This aspect of BEFP saves host programming equipment the address-bus setup overhead. With adequate continuity testing, programming equipment can rely on the WSM’s internal verification to ensure that the device has programmed properly. This eliminates the external post- program verification and its associated overhead.
April 2005 Intel StrataFlash ® Embedded Memory (P30) Datasheet
64 Order Number: 306666, Revision: 001
11.3.1 BEFP Requirements and Considerations
BEFP requirements:
- Case temperature: TC = 25 °C ± 5 °C
- VCC within specified operating range
- VPP driven to VPPH
- Target block unlocked before issuing the BEFP Setup and Confirm commands
- The first-word address (WA0) for the block to be programmed must be held constant from the setup phase through all data streaming into the target block, until transition to the exit phase is desired
- WA0 must align with the start of an array buffer boundary1 BEFP considerations:
- For optimum performance, cycling must be limited below 100 erase cycles per block 2
- BEFP programs one block at a time; all buffer data must fall within a single block 3
- BEFP cannot be suspended
- Programming to the flash memory array can occur only when the buffer is full 4 NOTES: 1. Word buffer boundaries in the array are determined by A[4:0] (0x00 through 0x1F). The alignment start point is A[4:0] = 0x00. 2. Some degradation in performance may occur if this limit is exceeded, but the internal algorithm continues to work properly. 3. If the internal address counter increments beyond the block's maximum address, addressing wraps around to the beginning of the block. 4. If the number of words is less than 32, remaining locations must be filled with 0xFFFF.
11.3.2 BEFP Setup Phase
After receiving the BEFP Setup and Confirm command sequence, Status Register bit SR[7] (Ready) is cleared, indicating that the WSM is busy with BEFP algorithm startup. A delay before checking SR[7] is required to allow the WSM enough time to perform all of its setups and checks (Block-Lock status, V PP level, etc.). If an error is detected, SR[4] is set and BEFP operation terminates. If the block was found to be locked, SR[1] is also set. SR[3] is set if the error occurred due to an incorrect V PP level. Note: Reading from the device after the BEFP Setup and Confirm command sequence outputs Status Register data. Do not issue the Read Status Register command; it will be interpreted as data to be loaded into the buffer.
11.3.3 BEFP Program/Verify Phase
After the BEFP Setup Phase has completed, the host programming system must check SR[7,0] to determine the availability of the write buffer for data streaming. SR[7] cleared indicates the device is busy and the BEFP program/verify phase is activated. SR[0] indicates the write buffer is available.
Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 65 Two basic sequences repeat in this phase: loading of the write buffer, followed by buffer data programming to the array. For BEFP, the count value for buffer loading is always the maximum buffer size of 32 words. During the buffer-loading sequence, data is stored to sequential buffer locations starting at address 0x00. Programming of the buffer contents to the flash memory array starts as soon as the buffer is full. If the number of words is less than 32, the remaining buffer locations must be filled with 0xFFFF. Caution: The buffer must be completely filled for programming to occur. Supplying an address outside of the current block's range during a buffer-fill sequence causes the algorithm to exit immediately. Any data previously loaded into the buffer during the fill cycle is not programmed into the array. The starting address for data entry must be buffer size aligned, if not the BEFP algorithm will be aborted and the program fails and (SR[4]) flag will be set. Data words from the write buffer are directed to sequential memory locations in the flash memory array; programming continues from where the previous buffer sequence ended. The host programming system must poll SR[0] to determine when the buffer program sequence completes. SR[0] cleared indicates that all buffer data has been transferred to the flash array; SR[0] set indicates that the buffer is not available yet for the next fill cycle. The host system may check full status for errors at any time, but it is only necessary on a block basis after BEFP exit. After the buffer fill cycle, no write cycles should be issued to the device until SR[0] = 0 and the device is ready for the next buffer fill. Note: Any spurious writes are ignored after a buffer fill operation and when internal program is proceeding. The host programming system continues the BEFP algorithm by providing the next group of data words to be written to the buffer. Alternatively, it can terminate this phase by changing the block address to one outside of the current block’s range. The Program/Verify phase concludes when the programmer writes to a different block address; data supplied must be 0xFFFF. Upon Program/Verify phase completion, the device enters the BEFP Exit phase.
11.3.4 BEFP Exit Phase
When SR[7] is set, the device has returned to normal operating conditions. A full status check should be performed at this time to ensure the entire block programmed successfully. When exiting the BEFP algorithm with a block address change, the read mode will not change. After BEFP exit, any valid command can be issued to the device.
11.4 Program Suspend
Issuing the Program Suspend command while programming suspends the programming operation. This allows data to be accessed from the device other than the one being programmed. The Program Suspend command can be issued to any device address. A program operation can be suspended to perform reads only. Additionally, a program operation that is running during an erase suspend can be suspended to perform a read operation (see Figure 41, “Program Suspend/Resume Flowchart” on page 86).
66 Order Number: 306666, Revision: 001
“Program and Erase Characteristics” on page 45. During a program suspend, deasserting CE# places the device in standby, reducing active current. suspend. If RST# is asserted, the device is reset.
11.5 Program Resume
(see Figure 41, “Program Suspend/Resume Flowchart” on page 86).
11.6 Program Protection
even if VPP is less than VPPLK. Figure 31. Example VPP Supply Connections
- Factory Programming with VPP = VPPH
- Complete write/Erase Protection when VPP ≤ VPPLK VCC VPP VCC VPP
- Low Voltage and Factory Programming
- Low-voltage Programming only
- Logic Control of Device Protection VCC VPP
- Low Voltage Programming Only
- Full Device Protection Unavailable VCC VPP ≤ 10K Ω VPP VCC VCC PROT # VCC VPP=VPPH VCC
Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 67
12.0 Erase Operations
Flash erasing is performed on a block basis. An entire block is erased each time an erase command sequence is issued, and only one block is erased at a time. When a block is erased, all bits within that block read as logical ones. The following sections describe block erase operations in detail.
12.1 Block Erase
Block erase operations are initiated by writing the Block Erase Setup command to the address of the block to be erased (see Section 9.2, “Device Commands” on page 50). Next, the Block Erase Confirm command is written to the address of the block to be erased. If the device is placed in standby (CE# deasserted) during an erase operation, the device completes the erase operation before entering standby.V PP must be above VPPLK and the block must be unlocked (see Figure 44, “Block Erase Flowchart” on page 89). During a block erase, the Write State Machine (WSM) executes a sequence of internally-timed events that conditions, erases, and verifies all bits within the block. Erasing the flash memory array changes “zeros” to “ones”. Memory array bits that are ones can be changed to zeros only by programming the block (see Section 11.0, “Programming Operations” on page 61). The Status Register can be examined for block erase progress and errors by reading any address. The device remains in the Read Status Register state until another command is written. SR[0] indicates whether the addressed block is erasing. Status Register bit SR[7] is set upon erase completion. Status Register bit SR[7] indicates block erase status while the sequence executes. When the erase operation has finished, Status Register bit SR[5] indicates an erase failure if set. SR[3] set would indicate that the WSM could not perform the erase operation because V PP was outside of its acceptable limits. SR[1] set indicates that the erase operation attempted to erase a locked block, causing the operation to abort. Before issuing a new command, the Status Register contents should be examined and then cleared using the Clear Status Register command. Any valid command can follow once the block erase operation has completed.
12.2 Erase Suspend
Issuing the Erase Suspend command while erasing suspends the block erase operation. This allows data to be accessed from memory locations other than the one being erased. The Erase Suspend command can be issued to any device address. A block erase operation can be suspended to perform a word or buffer program operation, or a read operation within any block except the block that is erase suspended (see Figure 41, “Program Suspend/Resume Flowchart” on page 86). When a block erase operation is executing, issuing the Erase Suspend command requests the WSM to suspend the erase algorithm at predetermined points. The device continues to output Status Register data after the Erase Suspend command is issued. Block erase is suspended when Status Register bits SR[7,6] are set. Suspend latency is specified in Section 7.5, “Program and Erase Characteristics” on page 45.
April 2005 Intel StrataFlash ® Embedded Memory (P30) Datasheet
68 Order Number: 306666, Revision: 001
To read data from the device (other than an erase-suspended block), the Read Array command must be issued. During Erase Suspend, a Program command can be issued to any block other than the erase-suspended block. Block erase cannot resume until program operations initiated during erase suspend complete. Read Array, Read Status Register, Read Device Identifier, CFI Query, and Erase Resume are valid commands during Erase Suspend. Additionally, Clear Status Register, Program, Program Suspend, Block Lock, Block Unlock, and Block Lock-Down are valid commands during Erase Suspend. During an erase suspend, deasserting CE# places the device in standby, reducing active current. V PP must remain at a valid level, and WP# must remain unchanged while in erase suspend. If RST# is asserted, the device is reset.
12.3 Erase Resume
The Erase Resume command instructs the device to continue erasing, and automatically clears status register bits SR[7,6]. This command can be written to any address. If status register error bits are set, the Status Register should be cleared before issuing the next instruction. RST# must remain deasserted (see Figure 41, “Program Suspend/Resume Flowchart” on page 86).
12.4 Erase Protection
When VPP = VIL, absolute hardware erase protection is provided for all device blocks. If V PP is below VPPLK, erase operations halt and SR[3] is set indicating a V PP-level error.
Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 69
13.0 Security Modes
The device features security modes used to protect the information stored in the flash memory array. The following sections describe each security mode in detail.
13.1 Block Locking
Individual instant block locking is used to protect user code and/or data within the flash memory array. All blocks power up in a locked state to protect array data from being altered during power transitions. Any block can be locked or unlocked with no latency. Locked blocks cannot be programmed or erased; they can only be read. Software-controlled security is implemented using the Block Lock and Block Unlock commands. Hardware-controlled security can be implemented using the Block Lock-Down command along with asserting WP#. Also, V PP data security can be used to inhibit program and erase operations (see Section 11.6, “Program Protection” on page 66 and Section 12.4, “Erase Protection” on page 68). The P30 device also offers four pre-defined areas in the main array that can be configured as One- Time Programmable (OTP) for the highest level of security. These include the four 32 KB parameter blocks together as one and the three adjacent 128 KB main blocks. This is available for top or bottom parameter devices.
13.1.1 Lock Block
To lock a block, issue the Lock Block Setup command. The next command must be the Lock Block command issued to the desired block’s address (see Section 9.2, “Device Commands” on page 50 and Figure 46, “Block Lock Operations Flowchart” on page 91). If the Set Read Configuration Register command is issued after the Block Lock Setup command, the device configures the RCR instead. Block lock and unlock operations are not affected by the voltage level on V PP. The block lock bits may be modified and/or read even if VPP is at or below VPPLK.
13.1.2 Unlock Block
The Unlock Block command is used to unlock blocks (see Section 9.2, “Device Commands” on page 50). Unlocked blocks can be read, programmed, and erased. Unlocked blocks return to a locked state when the device is reset or powered down. If a block is in a lock-down state, WP# must be deasserted before it can be unlocked (see Figure 32, “Block Locking State Diagram” on page 70).
13.1.3 Lock-Down Block
A locked or unlocked block can be locked-down by writing the Lock-Down Block command sequence (see Section 9.2, “Device Commands” on page 50). Blocks in a lock-down state cannot be programmed or erased; they can only be read. However, unlike locked blocks, their locked state cannot be changed by software commands alone. A locked-down block can only be unlocked by issuing the Unlock Block command with WP# deasserted. To return an unlocked block to locked-
70 Order Number: 306666, Revision: 001
13.1.4 Block Lock Status
DQ0 is the addressed block’s lock bit, while DQ1 is the addressed block’s lock-down bit.
13.1.5 Block Locking During Suspend
Figure 32. Block Locking State Diagram Notes: 1. [a,b,c] represents [WP#, DQ1, DQ0]. X = Don’t Care.
- DQ1 indicates Block Lock-Down status. DQ1 = ‘0’, Lock-Down has not been issued
to this block. DQ1 = ‘1’, Lock-Down has been issued to this block.
- DQ0 indicates block lock status. DQ0 = ‘0’, block is unlocked. DQ0 = ‘1’, block is
- Locked-down = Hardware + Software locked.
- [011] states should be tracked by system software to determine difference between
Hardware Locked and Locked-Down states.
masked by the command sequence error. page 78, which shows valid commands during an erase suspend.
13.2 Selectable One-Time Programmable Blocks
Please see your local Intel representative for details about the Selectable OTP implementation. Table 27. Selectable OTP Block Mapping the number of 256-Mbit dies in the stack and the placement of the parameter blocks.
April 2005 Intel StrataFlash ® Embedded Memory (P30) Datasheet
72 Order Number: 306666, Revision: 001
13.3 Protection Registers
The device contains 17 Protection Registers (PRs) that can be used to implement system security measures and/or device identification. Each Protection Register can be individually locked. The first 128-bit Protection Register is comprised of two 64-bit (8-word) segments. The lower 64- bit segment is pre-programmed at the Intel factor y with a unique 64-bit number. The other 64-bit segment, as well as the other sixteen 128-bit Protection Registers, are blank. Users can program these registers as needed. When programmed, users can then lock the Protection Register(s) to prevent additional bit programming (see Figure 33, “Protection Register Map” on page 73). The user-programmable Protection Registers contain one-time programmable (OTP) bits; when programmed, register bits cannot be erased. Each Protection Register can be accessed multiple times to program individual bits, as long as the register remains unlocked. Each Protection Register has an associated Lock Register bit. When a Lock Register bit is programmed, the associated Protection Register can only be read; it can no longer be programmed. Additionally, because the Lock Register bits themselves are OTP , when programmed, Lock Register bits cannot be erased. Therefore, when a Protection Register is locked, it cannot be unlocked.
13.3.1 Reading the Protection Registers
Information” on page 77 shows the address offsets of the Protection Registers and Lock Registers. Register data is read 16 bits at a time.
13.3.2 Programming the Protection Registers
Protection Register address (see Figure 33, “Protection Register Map” on page 73). Figure 33. Protection Register Map
April 2005 Intel StrataFlash ® Embedded Memory (P30) Datasheet
74 Order Number: 306666, Revision: 001
The device programs the 64-bit and 128-bit user-programmable Protection Register data 16 bits at a time (see Figure 47, “Protection Register Programming Flowchart” on page 92). Issuing the Program Protection Register command outside of the Protection Register’s address space causes a program error (SR[4] set). Attempting to program a locked Protection Register causes a program error (SR[4] set) and a lock error (SR[1] set).
13.3.3 Locking the Protection Registers
Each Protection Register can be locked by programming its respective lock bit in the Lock Register. To lock a Protection Register, program the corresponding bit in the Lock Register by issuing the Program Lock Register command, followed by the desired Lock Register data (see Section 9.2, “Device Commands” on page 50). The physical addresses of the Lock Registers are 0x80 for register 0 and 0x89 for register 1. These addresses are used when programming the lock registers (see Table 29, “Device Identifier Information” on page 77). Bit 0 of Lock Register 0 is already programmed at the factory, locking the lower, pre-programmed 64-bit region of the first 128-bit Protection Register containing the unique identification number of the device. Bit 1 of Lock Register 0 can be programmed by the user to lock the user-programmable, 64-bit region of the first 128-bit Protection Register. When programming Bit 1 of Lock Register 0, all other bits need to be left as ‘1’ such that the data programmed is 0xFFFD. Lock Register 1 controls the locking of the upper sixteen 128-bit Protection Registers. Each of the 16 bits of Lock Register 1 correspond to each of the upper sixteen 128-bit Protection Registers. Programming a bit in Lock Register 1 locks the corresponding 128-bit Protection Register. Caution: After being locked, the Protection Registers cannot be unlocked.
14.0 Special Read States
until the burst length requirements are satisfied.
- Figure 16, “Asynchronous Single-Word Read (ADV# Low)” on page 38
- Figure 17, “Asynchronous Single-Word Read (ADV# Latch)” on page 38
- Figure 19, “Synchronous Single-Word Array or Non-array Read Timing” on page 39
14.1 Read Status Register
The Status Register is read using single asynchronous-mode or synchronous burst mode reads. must be toggled to update status data. Table 28. Status Register Description (Sheet 1 of 2)
7 Device Write Status
0 = Device is busy; program or erase cycle in progress; SR[0] valid. 1 = Device is ready; SR[6:1] are valid.
6 Erase Suspend Status
0 = Erase suspend not in effect. 1 = Erase suspend in effect.
76 Order Number: 306666, Revision: 001
operation cannot be detected via the Status Register because it contains the previous error status.
14.1.1 Clear Status Register
ambiguity. A device reset also clears the Status Register.
14.2 Read Device Identifier
on page 77 show the address offsets and data values for this device. 5 Erase Status (ES) 0 = Erase successful. 1 = Erase fail or program sequence error when set with SR[4,7]. 4 Program Status (PS) 0 = Program successful. 3V PP Status (VPPS) 0 = VPP within acceptable limits during program or erase operation. 1 = VPP < VPPLK during program or erase operation.
2 Program Suspend Status
0 = Program suspend not in effect. 1 = Program suspend in effect.
1 Block-Locked Status
0 = Block not locked during program or erase. 1 = Block locked during program or erase; operation aborted.
0 BEFP Status (BWS)
= WSM is busy and buffer is available for loading. = WSM is busy and buffer is not available for loading. = WSM is not busy and buffer is available for loading. = Reserved for Future Use (RFU). Table 28. Status Register Description (Sheet 2 of 2)
14.3 CFI Query
offsets within the CFI database. Table 29. Device Identifier Information
- Block Is Unlocked DQ 0 = 0b0
- Block Is Locked DQ 0 = 0b1
- Block Is not Locked-Down DQ 1 = 0b0
- Block Is Locked-Down DQ 1 = 0b1 Configuration Register 0x05 Configuration Register Data Lock Register 0 0x80 PR-LK0 64-bit Factory-Programmed Protection Register 0x81–0x84 Factory Protection Register Data 64-bit User-Programmable Protection Register 0x85–0x88 User Protection Register Data Lock Register 1 0x89 Protection Register Data 128-bit User-Programmable Protection Registers 0x8A–0x109 PR-LK1 Notes: 1. BBA = Block Base Address.
Table 30. Device ID codes
78 Order Number: 306666, Revision: 001
until a new command changes it. The next WSM state does not depend on the partition’s output state. Figure 34. Write State Machine—Next State Table (Sheet 1 of 6)
Figure 35. Write State Machine—Next State Table (Sheet 2 of 6)
80 Order Number: 306666, Revision: 001
Figure 36. Write State Machine—Next State Table (Sheet 3 of 6)
Figure 37. Write State Machine—Next State Table (Sheet 4 of 6)
82 Order Number: 306666, Revision: 001
Figure 38. Write State Machine—Next State Table (Sheet 5 of 6)
- "Illegal commands" include commands outside of the allowed command set (allowed commands: 40H [pgm], 20H [erase],
- If a "Read Array" is attempted from a busy partition, the result will be invalid data. The ID and Query data are located at
different locations in the address map.
- 1st and 2nd cycles of "2 cycles write commands" must be given to the same partition address, or unexpected results will
- To protect memory contents against erroneous command sequences, there are specific instances in a multi-cycle
ignored because it is unclear whether the user intends to erase the block or resume the program operation. Figure 39. Write State Machine—Next State Table (Sheet 6 of 6)
April 2005 Intel StrataFlash ® Embedded Memory (P30) Datasheet
84 Order Number: 306666, Revision: 001
- The Clear Status command only clears the error bits in the status register if the device is not in the following modes: WSM running (Pgm Busy, Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, BEFP modes). 6. BEFP writes are only allowed when the status register bit #0 = 0, or else the data is ignored. 7. The "current state" is that of the "chip" and not of the "partition"; Each partition "remembers" which output (Array, ID/CFI or Status) it was last pointed to on the last instruction to the "chip", but the next state of the chip does not depend on where the partition's output mux is presently pointing to. 8. Confirm commands (Lock Block, Unlock Block, Lock-Down Block, Configuration Register) perform the operation and then move to the Ready State. 9. WA0 refers to the block address latched during the first write cycle of the current operation.
Figure 40. Word Program Flowchart Repeat for subsequent Word Program operations. after a sequence of program operations.
1 VPP Range
command clears the Status Register error bits.
86 Order Number: 306666, Revision: 001
Figure 41. Program Suspend/Resume Flowchart
Figure 42. Buffer Program Flowchart
- Word count value on D[7:0] is loaded into the word count
register. Count ranges for this device are N = 0x00 to 0x1F.
- The device outputs the Status Register when read.
- Write Buffer contents will be programmed at the issued word
- Align the start address on a Write Buffer boundary for
- The Buffered Programming Confirm command must be
loop that loaded the buffer data.
- The Status Register indicates an improper command
Clear Status Register command to clear error bits.
- The Status Register can be read from any address within
place the partition in the Read Array state.
88 Order Number: 306666, Revision: 001
Figure 43. BEFP Flowchart
- First-word address to be programmed within the target block must be aligned on a write -buffer boundary.
- Write-buffer contents are programmed sequentially to the flash array starting at the first word address (WSM internally incr ements addressing).
Write 0xFF to enter Read Array state.
Figure 44. Block Erase Flowchart Repeat for subsequent block erasures. or after a sequence of block erasures. Write 0xFF after the last operation to enter read array mode. Only the Clear Status Register command clears SR[1, 3, 4, 5]. attempting an erase retry or other error recovery.
0 Yes
Read None Status Register data.
90 Order Number: 306666, Revision: 001
Figure 45. Erase Suspend/Resume Flowchart Read None Status Register data.
Figure 46. Block Lock Operations Flowchart Confirm locking change on D[1,0].
92 Order Number: 306666, Revision: 001
Figure 47. Protection Register Programming Flowchart outside this space will return an error. Repeat for subsequent programming operations. after a sequence of program operations. Write 0xFF after the last operation to set Read Array state. Only the Clear Staus Register command clears SR[1, 3, 4]. attempting a program retry or other error recovery. Read None Status Register Data.
block erases, reads and otherwise control the flash device. The Query database allows system software to obtain information for controlling the flash device. This section describes the device’s CFI-compliant interface that allows access to Query data. devices, the Query table device starting address is a 10h, which is a word address for x16 devices. 7-0) and 00h in the high byte (DQ15-8). presented at the lower address, and the most significant data byte is presented at the higher address. shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode. Table 32. Example of Query Structure Output of x16- Devices Table 31. Summary of Query Structure Output as a Function of Device and Mode
94 Order Number: 306666, Revision: 001
Table 33. Query Structure
- Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as
a function of device bus width and mode.
- BA = Block Address beginning location (i.e., 08000h is block 1’s beginning location when the block size
- Offset 15 defines “P” which points to the Primary Intel-specific Extended Query Table.
Table 34. CFI Identification Table 35. System Interface Information Offset Length Description Add. Offset Length Description Add.
96 Order Number: 306666, Revision: 001
Table 36. Device Geometry Definition
- x = 0 means no erase blocking; the device erases in bulk
- x specifies the number of device regions with one or
more contiguous same-size erase blocks.
- Symmetrically blocked partitions have one blocking regionAddress 64-Mbit
Table 37. Primary Vendor-Specific Extended Query
98 Order Number: 306666, Revision: 001
Table 38. Protection Register Information Table 39. Burst Read Information pre-programmed and user-programmable. Following bytes are factory or user-programmable. Number of Protection register fields in JEDEC ID space. follow. 00h indicates no burst capability.
Table 40. Partition and Erase-block Region Information Number of device hardw are-partition regions w ithin the device. x = 0: a single hardw are partition device (no fields follow ). one or more contiguous erase block regions.
April 2005 Intel StrataFlash ® Embedded Memory (P30) Datasheet
100 Order Number: 306666, Revision: 001
Appendix D Additional Information Order/Document Number Document/Tool
290667 Intel StrataFlash ® Memory (J3) Datasheet
290737 Intel StrataFlash ® Synchronous Memory (K3/K18) Datasheet
290701 Intel ® Wireless Flash Memory (W18) Datasheet
290702 Intel ® Wireless Flash Memory (W30) Datasheet
252802 Intel ® Flash Memory Design for a Stacked Chip Scale Package (SCSP)
298161 Intel ® Flash Memory Chip Scale Package User’s Guide
253418 Intel ® Wireless Communications and Computing Package User's Guide
296514 Intel ® Small Outline Package Guide
297833 Intel ® Flash Data Integrator (FDI) User’s Guide
298136 Intel ® Persistent Storage Manager User Guide
300783 Using Intel® Flash Memory: Asynchronous Page Mode and Synchronous Burst Mode
306667 Migration Guide for Intel StrataFlash® Memory (J3) to Intel StrataFlash® Embedded
Memory (P30) Application Note 812
306668 Migration Guide for Spansion* S29GLxxxN to Intel StrataFlash® Embedded Memory
(P30) Application Note 813
306669 Migration Guide for Intel StrataFlash® Synchronous Memory (K3/K18) to Intel
StrataFlash® Embedded Memory (P30) Application Note 825 Notes: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.intel.com for technical documentation and tools. 3. For the most current information on Intel ® Flash Memory, visit our website at http://developer.intel.com/design/flash.
Figure 48. Decoder for Discrete Intel StrataFlash ® Embedded Memory (P30) Table 41. Valid Combinations for Discrete Products
102 Order Number: 306666, Revision: 001
Figure 49. Decoder for SCSP Intel StrataFlash ® Embedded Memory (P30) Table 42. Valid Combinations for Stacked Products