P87C51RC24

P87C51RC24 INTEL | Alldatasheet

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*Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. December 1995COPYRIGHT © INTEL CORPORATION, 1995 Order Number: 272659-002 8XC51RA/RB/RC CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER Commercial/Express 87C51RA/83C51RA/80C51RA/87C51RB/83C51RB/87C51RC/83C51RC *See Table 1 for Proliferation Options Y High Performance CHMOS EPROM/ ROM/CPU Y 24 MHz Operation Y 512 Bytes of On-Chip Data RAM Y Dedicated Hardware Watchdog Timer (One-Time Enabled with Reset-Out) Y Three 16-Bit Timer/Counters Y Programmable Clock Out Y Up/Down Timer/Counter Y Three Level Program Lock System Y 8K/16K/32K On-Chip Program Memory Y Improved Quick Pulse Programming Algorithm Y Boolean Processor Y 32 Programmable I/O Lines Y 6 Interrupt Sources Y Programmable Serial Channel with: Ð Framing Error Detection Ð Automatic Address Recognition Y TTL and CMOS Compatible Logic Levels Y 64K External Program Memory Space Y 64K External Data Memory Space Y MCSÉ 51 Compatible Instruction Set Y Power Saving Idle and Power Down Modes Y ONCE (On-Circuit Emulation) Mode Y Four-Level Interrupt Priority Y Extended Temperature Range b40§Ct o a85§C) MEMORY ORGANIZATION ROMless ROM EPROM ROM/EPROM RAM Device Device Version Bytes Bytes 80C51RA 83C51RA 87C51RA 8K 512 80C51RA 83C51RB 87C51RB 16K 512 80C51RA 83C51RC 87C51RC 32K 512 These devices can address up to 64 Kbytes of external program/data memory. The Intel 8XC51RA/8XC51RB/8XC51RC is a single-chip control-oriented microcontroller which is fabricated on Intel’s reliable CHMOS III-E technology. Being a member of the MCS 51 family of controllers, the 8XC51RA/8XC51RB/8XC51RC uses the same powerful instruction set, has the same architecture, and is pin- for-pin compatible with the existing MCS 51 family of products. The 8XC51RA/8XC51RB/8XC51RC is an enhanced version of the 8XC52/8XC54/8XC58. The added features make it an even more powerful microcon- troller for applications that require 512 bytes of on-chip data RAM and dedicated hardware WatchDog Timer with reset-out features. Throughout this document 8XC51RX will refer to the 8XC51RA, 8XC51RB and 8XC51RC unless information applies to a specific device. For a detailed description of 8XC51RA/RB/RC, refer to the 8XC51RA/RB/RC Hardware Description, order number 272668.

Table 1. Proliferations Options Figure 1. 8XC51RX Block Diagram

Figure 2. Pin Connections

VCC: Supply voltage. VSS: Circuit ground. VSS1: Secondary ground (not on DIP). Provided to reduce ground bounce and improve power supply by-passing. NOTE: This pin is not a substitute for the V SS pin (pin 22). (Connection not necessary for proper operation.) Port 0: Port 0 is an 8-bit, open drain, bidirectional I/O port. As an output port each pin can sink several LS TTL inputs. Port 0 pins that have 1’s written to them float, and in that state can be used as high-im- pedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory. In this application it uses strong inter- nal pullups when emitting 1’s, and can source and sink several LS TTL inputs. Port 0 also receives the code bytes during EPROM programming, and outputs the code bytes during program verification. External pullup resistors are re- quired during program verification. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can drive LS TTL inputs. Port 1 pins that have 1’s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current IL, on the data sheet) because of the internal pull- ups. In addition, Port 1 serves the functions of the follow- ing special features of the 8XC51RX: Port Pin Alternate Function P1.0 T2 (External Count Input to Timer/ Counter 2), Clock-Out P1.1 T2EX (Timer/Counter 2 Capture/ Reload Trigger and Direction Control) Port 1 receives the low-order address bytes during EPROM programming and verifying. Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can drive LS TTL inputs. Port 2 pins that have 1’s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current IL, on the data sheet) because of the internal pull- ups. Port 2 emits the high-order address byte during fetches from external Program Memory and during accesses to external Data Memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullups when emitting 1’s. Dur- ing accesses to external Data Memory that use 8-bit addresses (MOVX @Ri), Port 2 emits the contents of the P2 Special Function Register. Some Port 2 pins receive the high-order address bits during EPROM programming and program verifica- tion. Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can drive LS TTL inputs. Port 3 pins that have 1’s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current IL, on the data sheet) because of the pullups. Port 3 also serves the functions of various special features of the 8051 Family, as listed below: Port Pin Alternate Function P3.0 RXD (serial input port) P3.1 TXD (serial output port) P3.2 INT0 (external interrupt 0) P3.3 INT1 (external interrupt 1) P3.4 T0 (Timer 0 external input) P3.5 T1 (Timer 1 external input) P3.6 WR (external data memory write strobe) P3.7 RD (external data memory read strobe) RST: Reset I/O. A high on this pin for two machine cycles while the oscillator is running resets the de- vice. The port pins will be driven to their reset condi- tion when a minimum V IHI voltage is applied whether the oscillator is running or not. An internal pulldown resistor permits a power-on reset with only a capaci- tor connected to V CC. After a WatchDog Timer over- flow, this RST pin will drive an output high pulse at a minimum V OH2 for 96 x T OSC duration while the in- ternal reset signal is active. ALE: Address Latch Enable output pulse for latching the low byte of the address during accesses to ex-

Table 2. Status of the External Pins during Idle and Power Down ues until the Power Down mode is terminated. ternal interrupt can cause an exit from Power Down. the SFRs and on-chip RAM to retain their values. and stabilize (normally less than 10 ms). quence to WDTRST Special Function Register. While in the Idle mode the WDT continues to count. WDT stops counting and holds its current value. may be functionally impaired. Handbook Volume I, (Order No. 270645) and Application Note AP-252 (Embedded Applications Handbook, Order No.

2) Hold ALE low as RST is deactivated. operation is restored when a normal reset is applied. tended temperature range with or without burn-in. following guidelines in MIL-STD-883, Method 1015. prefixes are listed in Table 3. from their commercial temperature range limits. Table 3. Prefix Identification Contact distributor or local sales office to match EXPRESS prefix with proper device. P80C51RA indicates 80C51RA in a plastic package and specified for commercial temperature range, without burn-in. TS87C51RC indicates 87C51RC in a QFP package and specified for extended temperature range, without burn-in.

ABSOLUTE MAXIMUM RATINGS * Ambient Temperature Under Bias À b40§Ct o a85§C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b65§Ct o a150§C Voltage on EA/V PP Pin to V SS ÀÀÀÀÀÀÀ0V to a13.0V Voltage on Any Other Pin to V SS ÀÀb0.5V to a6.5V IOL Per I/O Pin ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ15 mA Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W (based on PACKAGE heat transfer limitations, not device power consumption) NOTICE: This data sheet contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest data sheet be- fore finalizing a design. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. OPERATING CONDITIONS Symbol Description Min Max Units TA Ambient Temperature Under Bias Commercial 0 a70 §C Express b40 a85 §C VCC Supply Voltage All Others 4.0 6.0 V 8XC51RX-24 4.5 5.5 V fOSC 0scillator Frequency 8XC51RX 3.5 12 MHz 8XC51RX-1 3.5 16 MHz 8XC51RX-20 3.5 20 MHz 8XC51RX-24 3.5 24 MHz DC CHARACTERISTICS (Over Operating Conditions) All parameter values apply to all devices unless otherwise indicated. Symbol Parameter Min Typ Max Unit Test Conditions(Note 4) VIL Input Low Voltage b0.5 0.2 V CCb0.1 V VIL1 Input Low Voltage EA 0 0.2 V CCb0.3 V VIH Input High Voltage 0.2 V CCa0.9 V CCa0.5 V (Except XTAL1, RST) VIH1 Input High Voltage 0.7 V CC VCCa0.5 V (XTAL1, RST) VOL Output Low Voltage (Note 5) 0.3 V I OL e 100 mA (Note 1) (Ports 1, 2 and 3) 0.45 V I OL e 1.6 mA (Note 1) 1.0 V I OL e 3.5 mA (Note 1) VOL1 Output Low Voltage (Note 5) 0.3 V I OL e 200 mA (Note 1) (Port 0, ALE, PSEN ) 0.45 V I OL e 3.2 mA (Note 1) 1.0 V I OL e 7.0 mA (Note 1) VOH Output High Voltage V CCb0.3 V I OH eb 10 mA (Ports 1, 2 and 3, ALE, PSEN ) VCCb0.7 V I OH eb 30 mA VCCb1.5 V I OH eb 60 mA

DC CHARACTERISTICS (Over Operating Conditions) (Continued) All parameter values apply to all devices unless otherwise indicated. Symbol Parameter Min Typ Max Unit Test Conditions(Note 4) VOH1 Output High Voltage V CCb0.3 V I OH eb 200 mA (Port 0 in External Bus Mode) VCCb0.7 V I OH eb 3.2 mA VCCb1.5 V I OH eb 7.0 mA VOH2 Output High Voltage 0.5 V CC VI OH eb 800 mA (RST) 0.75 V CC VI OH eb 300 mA

0.9 V CC VI OH eb 80 mA

IIL Logical 0 Input Current (Ports 1, 2 and 3) b50 mAV IN e 0.45V ILI Input leakage Current (Port 0) g10 mAV IN e VIL or V IH ITL Logical 1 to 0 Transition Current (Ports 1, 2 and 3) Commercial b675 mAV IN e 2V Express b775 mA RRST RST Pulldown Resistor 40 225 K X CIO Pin Capacitance 10 pF @1 MHz, 25 §C ICC Power Supply Current: (Note 3) Active Mode at 12 MHz (Figure 5) 15 30 mA at 16 MHz 38 mA at 20 MHz 47 mA at 24 MHz 56 mA Idle Mode at 12 MHz (Figure 5) 5 7.5 mA at 16 MHz 9.5 mA at 20 MHz 11.5 mA at 24 MHz 13.5 mA Power Down Mode 5 75 mA NOTES: 1. Capacitive loading on Ports 0 and 2 may cause noise pulses above 0.4V to be superimposed on the V OLs of ALE and Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change from 1 to 0. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8V. It may be desirable to qualify ALE or other signals with a Schmitt Triggers, or CMOS-level input logic. 2. Capacitive loading on Ports 0 and 2 cause the V OH on ALE and PSEN to drop below the 0.9 V CC specification when the address lines are stabilizing. 3. See Figures 6–9 for test conditions. Minimum V CC for Power Down is 2V. 4. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and 5V. 5. Under steady state (non-transient) conditions, I OL must be externally limited as follows: Maximum I OL per port pin: 10mA Maximum I OL per 8-bit portÐ Port 0: 26 mA Ports 1, 2 and 3: 15 mA Maximum total I OL for all output pins: 71 mA If I OL exceeds the test condition, V OL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.

EXPLANATION OF THE AC SYMBOLS Each timing symbol has 5 characters. The first char- acter is always a ‘T’ (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. A: Address C: Clock D: Input Data H: Logic level HIGH I: Instruction (program memory contents) L: Logic level LOW, or ALE P: PSEN Q: Output Data R: RD signal T: Time V: Valid W: WR signal X: No longer a valid logic level Z: Float For example, TAVLL e Time from Address Valid to ALE Low TLLPL e Time from ALE Low to PSEN Low AC CHARACTERISTICS (Over Operating Conditions, Load Capacitance for Port 0, ALE/PROG and PSEN e 100 pF, Load Capacitance for All Other Outputs e 80 pF) EXTERNAL MEMORY CHARACTERISTICS All parameter values apply to all devices unless otherwise indicated. In this table, 8XC51RX refers to 8XC51RX and 8XC51RX-1. 8XC51RX-24 refers to 8XC51RX-20 and 8XC51RX-24. Symbol Description

12 MHz 20 MHz 24 MHz Variable

UnitsOscillator Oscillator Oscillator Oscillator Min Max Min Max Min Max Min Max 1/TCLCL Oscillator Frequency 8XC51RX 3.5 12 MHz 8XC51RX-1 3.5 16 MHz 8XC51RX-20 3.5 20 MHz 8XC51RX-24 3.5 24 MHz TLHLL ALE Pulse Width 127 60 43 2 TCLCL b 40 ns TAVLL Address Valid to 43 10 12 TCLCL b 40 ns ALE Low TLLAX Address Hold After 53 20 12 TCLCL b 30 ns ALE Low TLLIV ALE Low to Valid Instruction In 8XC51RX 234 4 TCLCL b 100 ns 8XC51RX-24 125 91 4 TCLCL b 75 ns TLLPL ALE Low to PSEN 53 20 12 TCLCL b 30 ns Low TPLPH PSEN Pulse Width 205 105 80 3 TCLCL b 45 ns TPLIV PSEN Low to Valid Instruction In 8XC51RX 145 3 TCLCL b 105 ns 8XC51RX-24 60 35 3 TCLCL b 90 ns TPXIX Input Instruction 0 0 0 0 ns Hold After PSEN

EXTERNAL MEMORY CHARACTERISTICS (Continued) All parameter values apply to all devices unless otherwise indicated. Symbol Description UnitsOscillator Oscillator Oscillator Oscillator Min Max Min Max Min Max Min Max TPXIZ Input Instruction Float After PSEN 8XC51RX 59 TCLCL b25 ns 8XC51RX-24 30 21 TCLCL b20 ns TAVIV Address to Valid Instruction 312 145 103 5 TCLCL b105 ns In TPLAZ PSEN Low to Address Float 10 10 10 10 ns TRLRH RD Pulse Width 400 200 150 6 TCLCL b100 ns TWLWH WR Pulse Width 400 200 150 6 TCLCL b100 ns TRLDV RD Low to Valid Data In 8XC51RX 252 5 TCLCL b165 ns 8XC51RX-24 155 113 5 TCLCL b95 ns TRHDX Data Hold After RD 000 0 n s TRHDZ Data Float After RD 107 40 23 2 TCLCL b60 ns TLLDV ALE Low to Valid Data In 8XC51RX 517 8 TCLCL b150 ns 8XC51RX-24 310 243 8 TCLCL b90 ns TAVDV Address to Valid Data In 8XC51RX 585 9 TCLCL b165 ns 8XC51RX-24 360 285 9 TCLCL b90 ns TLLWL ALE Low to RD or WR Low 200 300 100 200 75 175 3 TCLCL b50 3 TCLCL a50 ns TAVWL Address Valid to WR Low 8XC51RX 203 4 TCLCL b130 ns 8XC51RX-24 110 77 4 TCLCL b90 ns TQVWX Data Valid before WR 8XC51RX 33 TCLCL b50 ns 8XC51RX-20 15 TCLCL b35 ns 8XC51RX-24 12 TCLCL b30 ns TWHQX Data Hold after WR 8XC51RX 33 TCLCL b50 ns 8XC51RX-20 10 TCLCL b40 ns 8XC51RX-24 7 TCLCL b30 ns TQVWH Data Valid to WR High 8XC51RX 433 7 TCLCL b150 ns 8XC51RX-24 280 222 7 TCLCL b70 ns TRLAZ RD Low to Address Float 0 0 0 0 ns TWHLH RD or WR High to ALE High 8XC51RX 43 123 10 90 TCLCL b40 TCLCL a40 ns 8XC51RX-24 12 71 TCLCL b30 TCLCL a30

EXTERNAL PROGRAM MEMORY READ CYCLE 272659–12 EXTERNAL DATA MEMORY READ CYCLE 272659–13 EXTERNAL DATA MEMORY WRITE CYCLE 272659–14

SERIAL PORT TIMING - SHIFT REGISTER MODE Test Conditions: Over Operating Conditions; Load Capacitance e 80 pF Symbol Parameter UnitsOscillator Oscillator Oscillator Oscillator Min Max Min Max Min Max Min Max TXLXL Serial Port Clock 1 0.600 0.500 12 TCLCL ms Cycle Time TQVXH Output Data 700 367 284 10 TCLCL b 133 ns Setup to Clock Rising Edge TXHQX Output Data Hold after Clock Rising Edge 8XC51RX 50 2 TCLCL b 117 ns 8XC51RX-24 50 34 2 TCLCL b 50 ns TXHDX Input Data Hold 0 0 0 0 ns After Clock Rising Edge TXHDV Clock Rising 700 367 284 10 TCLCL b 133 ns Edge to Input Data Valid SHIFT REGISTER MODE TIMING WAVEFORMS 272659–15

Symbol Parameter Min Max Units 1/TCLCL Oscillator Frequency 8XC51RX 3.5 12 MHz8XC51RX-1 3.5 16 8XC51RX-20 3.5 20 8XC51RX-24 3.5 24 TCHCX High Time 0.35 T OSC 0.65 T OSC ns TCLCX Low Time 0.35 T OSC 0.65 T OSC ns TCLCH Rise Time 8XC51RX 20 ns 8XC51RX-24 10 ns TCHCL Fall Time20 ns 8XC51RX 20 ns 8XC51RX-24 10 ns EXTERNAL CLOCK DRIVE WAVEFORM 272659–16 AC TESTING INPUT, OUTPUT WAVEFORMS 272659–17 AC Inputs during testing are driven at V CCb0.5V for a Logic ‘‘1’’ and 0.45V for a Logic ‘‘0’’. Timing measurements are made at V IH min for a Logic ‘‘1’’ and V IL max for a Logic ‘‘0’’. FLOAT WAVEFORMS 272659–18 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, and begins to float when a 100 mV change from the loaded V OH/VOL level occurs. IOL/IOH e g20 mA.

turned to a high (also refer to timing diagrams). DATA LINES: P0.0–P0.7 for D0–D7. Table 4. EPROM Programming Modes

The program lock system, when programmed, pro- tects the onboard program against software piracy. The 83C51RX has a one-level program lock system and a 64-byte encryption table. See line 2 of Table 5. If program protection is desired. the user submits the encryption table with their code. and both the lock-bit and encryption array are programmed by the factory. The encryption array is not available without the lock bit. For the lock bit to be programmed, the user must submit an encryption table. The 87C51RX has a 3-level program lock system and a 64-byte encryption array. Since this is an EPROM device, all locations are user-programma- ble. See Table 5. Encryption Array Within the EPROM array are 64 bytes of Encryption Array that are initially unprogrammed (all 1’s). Every time that a byte is addressed during a verify, 6 ad- dress lines are used to select a byte of the Encryp- tion Array. This byte is then exclusive-NOR’ed (XNOR) with the code byte, creating an Encryption Verify byte. The algorithm, with the array in the un- programmed state (all 1’s), will return the code in its original, unmodified form. For programming the En- cryption Array, refer to Table 4 (Programming the EPROM). When using the encryption array, one important fac- tor needs to be considered. If a code byte has the value 0FFH, verifying the byte will produce the en- cryption byte value. If a large block ( l64 bytes) of code is left unprogrammed, a verification routine will display the contents of the encryption array. For this reason all unused code bytes should be pro- grammed with some value other than 0FFH, and not all of them the same value. This will ensure maxi- mum program protection. Program Lock Bits The 87C51RX has 3 programmable lock bits that when programmed according to Table 5 will provide different levels of protection for the on-chip code and data. If any program lock bits were programmed, erasing the EPROM will not erase the program lock bits and programming of the EPROM is disabled. Reading the Signature Bytes The 8XC51RX has 3 signature bytes in locations 30H, 31H, and 60H. To read these bytes follow the procedure for EPROM verify, but activate the control lines provided in Table 4 for Read Signature Byte. Location Device Contents 30H All 89H 31H All 58H 60H 87C51RC C2H 87C51RB C1H 87C51RA C0H 83C51RC 42H/C2H 83C51RB 41H/C1H 83C51RA 40H/C0H Erasure Characteristics (Windowed Packages Only) Erasure of the EPROM begins to occur when the chip is exposed to light with wavelength shorter than approximately 4,000 Angstroms. Since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in room- level fluorescent lighting) could cause inadvertent erasure. If an application subjects the device to this type of exposure, it is suggested that an opaque la- bel be placed over the window. The recommended erasure procedure is exposure to ultraviolet light (at 2537 Angstroms) to an integrat- ed dose of at least 15 W-sec/cm 2. Exposing the EPROM to an ultraviolet lamp of 12,000 mW/cm2 rating for 30 minutes, at a distance of about 1 inch, should be sufficient. Erasure leaves all the EPROM Cells in a 1’s state.

Table 5. Program Lock Bits and the Features

2 P U U MOVC instructions executed from external program memory are disabled from

Reset, and further programming of the EPROM is disabled. 3 P P U Same as 2, also verify is disabled. 4 P P P Same as 3, also external execution is disabled. Any other combination of the lock bits is not defined.

EPROM PROGRAMMING AND VERIFICATION WAVEFORMS 272659–21 *5 pulses for the EPROM array, 25 pulses for the encryption table and lock bits. Thermal Impedance All thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will change depending on operating conditions and ap- plications. See the Intel Packaging Handbook (Order Number 240800) for a description of Intel’s thermal impedance test methodology. Package iJA iJC Device P4 5 §C/W 16 §C/W All N4 6 §C/W 16 §C/W All S8 7 §C/W 18 §C/W 51RA 96§C/W 24 §C/W 51RB 90§C/W 22 §C/W 51RC DATA SHEET REVISION HISTORY Data sheets are changed as new device information becomes available. Verify with your local Intel sales office that you have the latest version before finaliz- ing a design or ordering devices. The following differences exist between this data- sheet (272659-002) and the previous version (272659-001): 1. ADVANCE INFORMATION datasheet replaces PRODUCT PREVIEW datasheet. 2. I TL (Commercial) changed from b650 mAt o b675 mA. 3. I TL (Express) changed from b750 mAt o b775 mA. 4. 8XC51RX-24, V CC changed from 5V g20% to 5V g10%. 5. Remove all CERDIP package types (prefix D, TD, LD). INTEL CORPORATION, 2200 Mission College Blvd., Santa Clara, CA 95052; Tel. (408) 765-8080 INTEL CORPORATION (U.K.) Ltd., Swindon, United Kingdom; Tel. (0793) 696 000 INTEL JAPAN k.k., Ibaraki-ken; Tel. 029747-8511