P82C55A

82C55A INTEL | Alldatasheet

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Table 1. Pin Description buffer and an 8-bit data input latch. RD 56 I READ CONTROL: This input is low during CPU read operations.

00010 Port A - Data Bus

01010 Port B - Data Bus

10010 Port C - Data Bus

11010 Control Word - Data Bus

00100 Data Bus - Port A

01100 Data Bus - Port B

10100 Data Bus - Port C

11100 Data Bus - Control

PC0–3 14–17 16–19 I/O PORT C, PINS 0–3: Lower nibble of Port C. 24–28 bit data input buffer. VCC 26 29 SYSTEM POWER: a 5V Power Supply. ports are set to the input mode. buffer and an 8-bit data input latch.

82C55A FUNCTIONAL DESCRIPTION General The 82C55A is a programmable peripheral interface device designed for use in Intel microcomputer sys- tems. Its function is that of a general purpose I/O component to interface peripheral equipment to the microcomputer system bus. The functional configu- ration of the 82C55A is programmed by the system software so that normally no external logic is neces- sary to interface peripheral devices or structures. Data Bus Buffer This 3-state bidirectional 8-bit buffer is used to inter- face the 82C55A to the system data bus. Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control words and status information are also transferred through the data bus buffer. Read/Write and Control Logic The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to both of the Control Groups. Group A and Group B Controls The functional configuration of each port is pro- grammed by the systems software. In essence, the CPU ‘‘outputs’’ a control word to the 82C55A. The control word contains information such as ‘‘mode’’, ‘‘bit set’’, ‘‘bit reset’’, etc., that initializes the func- tional configuration of the 82C55A. Each of the Control blocks (Group A and Group B) accepts ‘‘commands’’ from the Read/Write Control Logic, receives ‘‘control words’’ from the internal data bus and issues the proper commands to its as- sociated ports. Control Grou p A - Port A and Port C upper (C7–C4) Control Group B - Port B and Port C lower (C3–C0) The control word register can be both written and read as shown in the address decode table in the pin descriptions. Figure 6 shows the control word format for both Read and Write operations. When the control word is read, bit D7 will always be a logic ‘‘1’’, as this implies control word mode information. Ports A, B, and C The 82C55A contains three 8-bit ports (A, B, and C). All can be configured in a wide variety of functional characteristics by the system software but each has its own special features or ‘‘personality’’ to further enhance the power and flexibility of the 82C55A. Port A. One 8-bit data output latch/buffer and one 8-bit input latch buffer. Both ‘‘pull-up’’ and ‘‘pull- down’’ bus hold devices are present on Port A. Port B. One 8-bit data input/output latch/buffer. Only ‘‘pull-up’’ bus hold devices are present on Port Port C. One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports A and B. Only ‘‘pull-up’’ bus hold devices are present on Port C. See Figure 4 for the bus-hold circuit configuration for Port A, B, and C.

Figure 7. Bit Set/Reset Format can be used as interrupt request inputs to the CPU. mode selection and device Reset.

Mode 0 (Basic Input/Output). This functional con- figuration provides simple input and output opera- tions for each of the three ports. No ‘‘handshaking’’ is required, data is simply written to or read from a specified port. Mode 0 Basic Functional Definitions: # Two 8-bit ports and two 4-bit ports. # Any port can be input or output. # Outputs are latched. # Inputs are not latched. # 16 different Input/Output configurations are pos- sible in this Mode. MODE 0 (BASIC INPUT) 231256–8 MODE 0 (BASIC OUTPUT) 231256–9

D4 D3 D1 D0 PORT A PORT C Ý PORT B PORT C (UPPER) (LOWER) 0 0 0 0 OUTPUT OUTPUT 0 OUTPUT OUTPUT 0 0 0 1 OUTPUT OUTPUT 1 OUTPUT INPUT 0 0 1 0 OUTPUT OUTPUT 2 INPUT OUTPUT 0 0 1 1 OUTPUT OUTPUT 3 INPUT INPUT 0 1 0 0 OUTPUT INPUT 4 OUTPUT OUTPUT 0 1 0 1 OUTPUT INPUT 5 OUTPUT INPUT 0 1 1 0 OUTPUT INPUT 6 INPUT OUTPUT 0 1 1 1 OUTPUT INPUT 7 INPUT INPUT 1 0 0 0 INPUT OUTPUT 8 OUTPUT OUTPUT 1 0 0 1 INPUT OUTPUT 9 OUTPUT INPUT 1 0 1 0 INPUT OUTPUT 10 INPUT OUTPUT 1 0 1 1 INPUT OUTPUT 11 INPUT INPUT 1 1 0 0 INPUT INPUT 12 OUTPUT OUTPUT 1 1 0 1 INPUT INPUT 13 OUTPUT INPUT 1 1 1 0 INPUT INPUT 14 INPUT OUTPUT 1 1 1 1 INPUT INPUT 15 INPUT INPUT MODE 0 Configurations 231256–10

MODE 0 Configurations (Continued) 231256–11

MODE 0 Configurations (Continued) 231256–12 Operating Modes MODE 1 (Strobed Input/Output). This functional configuration provides a means for transferring I/O data to or from a specified port in conjunction with strobes or ‘‘handshaking’’ signals. In mode 1, Port A and Port B use the lines on Port C to generate or accept these ‘‘handshaking’’ signals. Mode 1 Basic functional Definitions: # Two Groups (Group A and Group B). # Each group contains one 8-bit data port and one 4-bit control/data port. # The 8-bit data port can be either input or output Both inputs and outputs are latched. # The 4-bit port is used for control and status of the 8-bit data port.

Figure 12. Combinations of MODE 1 and enable/disable functions are also available. # Both inputs and outputs are latched. ). Controlled by bit set/reset of PC 6. INTE 2 (The INTE Flip-Flop Associated with IBF).

Figure 16. MODE (/4 Combinations

IN OUT IN OUT GROUP A ONLY PA0 IN OUT IN OUT Ý PA1 IN OUT IN OUT Ý PA2 IN OUT IN OUT Ý PA3 IN OUT IN OUT Ý PA4 IN OUT IN OUT Ý PA5 IN OUT IN OUT Ý PA6 IN OUT IN OUT Ý PA7 IN OUT IN OUT Ý PB0 IN OUT IN OUT Ð PB1 IN OUT IN OUT Ð PB2 IN OUT IN OUT Ð PB3 IN OUT IN OUT Ð MODE 0 PB4 IN OUT IN OUT Ð OR MODE 1 PB5 IN OUT IN OUT Ð ONLY PB6 IN OUT IN OUT Ð PB7 IN OUT IN OUT Ð PC0 IN OUT INTR B INTRB I/O PC1 IN OUT IBF B OBFB I/O PC2 IN OUT STB B ACKB I/O PC3 IN OUT INTR A INTRA INTRA PC4 IN OUT STB A I/O STB A PC5 IN OUT IBF A I/O IBF A PC6 IN OUT I/O ACK A ACKA PC7 IN OUT I/O OBF A OBFA Special Mode Combination Considerations There are several combinations of modes possible. For any combination, some or all of the Port C lines are used for control or status. The remaining bits are either inputs or outputs as defined by a ‘‘Set Mode’’ command. During a read of Port C, the state of all the Port C lines, except the ACK and STB lines, will be placed on the data bus. In place of the ACK and STB line states, flag status will appear on the data bus in the PC2, PC4, and PC6 bit positions as illustrated by Figure 18. Through a ‘‘Write Port C’’ command, only the Port C pins programmed as outputs in a Mode 0 group can be written. No other pins can be affected by a ‘‘Write Port C’’ command, nor can the interrupt enable flags be accessed. To write to any Port C output pro- grammed as an output in a Mode 1 group or to change an interrupt enable flag, the ‘‘Set/Reset Port C Bit’’ command must be used. With a ‘‘Set/Reset Port C Bit’’ command, any Port C line programmed as an output (including INTR, IBF and OBF ) can be written, or an interrupt enable flag can be either set or reset. Port C lines programmed as inputs, including ACK and STB lines, associated with Port C are not affected by a ‘‘Set/Reset Port C Bit’’ command. Writing to the corresponding Port C bit positions of the ACK and STB lines with the ‘‘Set/Reset Port C Bit’’ command will affect the Group A and Group B interrupt enable flags, as illus- trated in Figure 18. Current Drive Capability Any output on Port A, B or C can sink or source 2.5 mA. This feature allows the 82C55A to directly drive Darlington type drivers and high-voltage displays that require such sink or source current.

ABSOLUTE MAXIMUM RATINGS * Ambient Temperature Under BiasÀÀÀÀ0 §Ct o a 70§C Storage Temperature ÀÀÀÀÀÀÀÀÀ b 65§Ct o a 150§C Supply Voltage ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b 0.5 to a 8.0V Operating Voltage ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ a 4V to a 7V Voltage on any InputÀÀÀÀÀÀÀÀÀÀGND b2V to a 6.5V Voltage on any Output ÀÀGND b0.5V to V CC a 0.5V Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1 Watt NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. D.C. CHARACTERISTICS TA e 0§Ct o7 0 §C, V CC ea 5V g10%, GND e 0V (T A eb 40§Ct o a85§C for Extended Temperture) Symbol Parameter Min Max Units Test Conditions VIL Input Low Voltage b0.5 0.8 V VIH Input High Voltage 2.0 V CC V VOL Output Low Voltage 0.4 V I OL e 2.5 mA VOH Output High Voltage 3.0 V I OH eb 2.5 mA VCC b 0.4 V I OH eb 100 mA IIL Input Leakage Current g1 mAV IN e VCC to 0V (Note 1) IOFL Output Float Leakage Current g10 mAV IN e VCC to 0V (Note 2) IDAR Darlington Drive Current g2.5 (Note 4) mA Ports A, B, C Rext e 500X Vext e 1.7V IPHL Port Hold Low Leakage Current a50 a300 mAV OUT e 1.0V Port A only IPHH Port Hold High Leakage Current b50 b300 mAV OUT e 3.0V Ports A, B, C IPHLO Port Hold Low Overdrive Current b350 mAV OUT e 0.8V IPHHO Port Hold High Overdrive Current a350 mAV OUT e 3.0V ICC VCC Supply Current 10 mA (Note 3) ICCSB VCC Supply Current-Standby 10 mAV CC e 5.5V VIN e VCC or GND Port Conditions If I/P e Open/High O/P e Open Only With Data Bus e High/Low CS e High Reset e Low Pure Inputs e Low/High NOTES: 1. Pins A 1,A 0,C S ,W R ,R D , Reset. 2. Data Bus; Ports B, C. 3. Outputs open. 4. Limit output current to 4.0 mA.

TA e 25§C, V CC eGND e 0V Symbol Parameter Min Max Units Test Conditions CIN Input Capacitance 10 pF Unmeasured plns returned to GNDCI/O I/O Capacitance 20 pF fc e 1 MHz (5) NOTE: 5. Sampled not 100% tested. A.C. CHARACTERISTICS TA e 0§ to 70 §C, V CC ea 5V g10%, GND e 0V TA eb 40§Ct o a85§C for Extended Temperature BUS PARAMETERS READ CYCLE Symbol Parameter 82C55A-2 Units Test Min Max Conditions tAR Address Stable Before RD v 0n s tRA Address Hold Time After RD u 0n s tRR RD Pulse Width 150 ns tRD Data Delay from RD v 120 ns tDF RDuto Data Floating 10 75 ns tRV Recovery Time between RD /WR 200 ns WRITE CYCLE Symbol Parameter 82C55A-2 Units Test Min Max Conditions tAW Address Stable Before WR v 0n s tWA Address Hold Time After WR u 20 ns Port sA&B 20 ns Port C tWW WR Pulse Width 100 ns tDW Data Setup Time Before WR u 100 ns tWD Data Hold Time After WR u 30 ns Port sA&B 30 ns Port C

Symbol Parameter 82C55A-2 Units Test Min Max Conditions tWB WR e 1 to Output 350 ns tlR Peripheral Data Before RD 0n s tHR Peripheral Data After RD 0n s tAK ACK Pulse Width 200 ns tST STB Pulse Width 100 ns tPS Per. Data Before STB High 20 ns tPH Per. Data After STB High 50 ns tAD ACK e 0 to Output 175 ns tKD ACK e 1 to Output Float 20 250 ns tWOB WR e 1t oO B F e 0 150 ns tAOB ACK e 0t oO B F e 1 150 ns tSIB STB e 0t oI B F e 1 150 ns tRIB RD e 1t oI B F e 0 150 ns tRIT RD e 0 to INTR e 0 200 ns tSIT STB e 1 to INTR e 1 150 ns tAIT ACK e 1 to INTR e 1 150 ns tWIT WR e 0 to INTR e 0 200 ns see note 1 tRES Reset Pulse Width 500 ns see note 2 NOTE: 1. INTR u may occur as early as WR v. 2. Pulse width of initial Reset pulse after power on must be at least 50 mSec. Subsequent Reset pulses may be 500 ns minimum. The output Ports A, B, or C may glitch low during the reset pulse but all port pins will be held at a logic ‘‘one’’ level after the reset pulse.

MODE 0 (BASIC INPUT) 231256–22 MODE 0 (BASIC OUTPUT) 231256–23

WAVEFORMS (Continued) MODE 1 (STROBED INPUT) 231256–24 MODE 1 (STROBED OUTPUT) 231256–25

WAVEFORMS (Continued) MODE 2 (BIDIRECTIONAL) 231256–26 Note: Any sequence where WR occurs before ACK AND STB occurs before RD is permissible. (INTR e IBF # MASK # STB # RD a OBF # MASK # ACK # WR) WRITE TIMING 231256–27 READ TIMING 231256–28 A.C. TESTING INPUT, OUTPUT WAVEFORM 231256–29 A.C. Testing Inputs Are Driven At 2.4V For A Logic 1 And 0.45V For A Logic 0 Timing Measurements Are Made At 2.0V For A Logic 1 And 0.8 For A Logic 0. A.C. TESTING LOAD CIRCUIT 231256–30 *VEXT Is Set At Various Voltages During Testing To Guarantee The Specification. C L Includes Jig Capacitance.