P8291A

Intel Corporation

GPIB TALKER/LISTENER

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intel. 8291A Ne 8291A FEATURE iD to a listener role or vice-versa during a holdoff, AaPROVEMENTE: AN the “Holdoff on Source Handshake” has been eliminated. Only “Holdoff on Acceptor Hand- The 8291A is an improved design of the 8291 GPIB shake" Is available. Talker/Listener. Most of the functions are identical 8, The rsv local message is cleared automatically to the 8291, and the pin configuration is unchanged. upon exit from SPAS if (APRS:STRS:SPAS) oc- curred. The automatic resetting of the bit after the The 8291A offers the following improvements to the serial poll is complete simplities the service re- 8291: quest software. 1. EDlis active with the data as a ninth data bit rath- 9: The SPASC interrupt on the 6291 has been re- er than as @ control bit. This is to comply with placed by the SPC (Serial Poll Complete) interrupt some additions to the 1975 IEEE-488 Standard on the 8291A. SPC interrupt is set on exit trom incorporated in the 1978 Standard. Spas it APRRATRE:BPAE cooured, indicating 2. The BO interrupt is not asserted unt RFDis true. ghter tho B29IA receeston soning The ePace It the Controtier asserts ATN synchronously, the Interrupt was ambiguous because @ controller data is guaranteed to be transmitted, If the Con- could enter SPAS and exit SPAS generati troller asserts ATN asynchronously, the SH ‘ ng two (Source Handshake) will return t0 SIDS (Source Stars byte, The SPC Intornant aloo ormeeioe ra rile Statal, end the culput dete wil be cleered, CPUs cohwure by elerinetnn tre cnet ates Then, if is released while the 8291A is ad- the serial poll is half way done. dressed to talk, a new BO interrupt will be gener- ated. This change fixes 8291 problems which 10. The rt! Auxiliary Command in the 8291 has been caused data to be lost or repeated and a problem replaced by Set and Clear rt! Commands in the with the ROS bit (sometimes cannot be asserted 8291A. Using the new commands, the CPU has while talking). the flexibility to extend the length of local mode 3. LLOG and REMC interupts are setting flipflops @ leave Kas a short pulse as in the 8201. * rather than toggling flipflops in the interrupt back- —-11- A holdoff RFD on GET, SDC, and OCL feature up register. This ensures that the CPU knows that has been added to prevent additional bus activi- these state changes have occurred. The actual ty while the CPU is responding to any of these state can be determined by checking the LLO and commands. The feature is enabled by a new bit REM status bits in the upper nibble of the Inter- (B,) in the Auxiliary Register 8. rupt Status 2 Register. 12. On the 6291, BO could cease to occur upon IFT 4. DREQ is cleared by DACK (FID_+ WA). OREQ on going false it cpcured asynchronously. On tha 8291 wea Cleeloa oh ON OXON onion cn the 6291A. BO continues 10 occur after [FC has compatible with the 8089 I/O Processor. gone false even if it arrived asynchronously. 5. The INT bit in Interrupt Status 2 Register is dupli- 13. User's software can distinguish between the cated in bit 7 of the Address 0 Register. if soft- 8291 and the 6291A as follows: ware polling is used to check for an interrupt, INT @) pon (OOH to register 5) in ine Address ° Register should be poled rather b) RESET (02H to register 5) that no interrupts are lost dos to asynchoneus Cc) Read Interrupt Status 1 Register. If 8O inter- status reads and interrupts. Oe oe Se orice Ie the Se01. It BO is ; clear, it is . A

8 On oly bate ct ena marks This can be used to set a flag in the user's soft-

The 8291 did not assert EOI after this command ware which will permit special routines to be exe- for @ one byte message nor on two consecutive cuted for each device. It could be included as bytes. Pert of '& normal initialization procedure as the 7. To avoid confusion between holdott on DAV ver- ret step after a chip reset. sus RFD if a device is readdressed from a talker

Table 1. Pin Description (written into) with the execution of RD (WA). the register selected by RSp—RS2. written into the selected register. output or byte input in OMA mode; reset by DACK.

7 DMA ACKNOWLEDGE: When low, resets DREQ and selects

Must be high if DMA is not used. command or Trigger auxiliary command. EXTERNAL CLOCK: Input, used only for T, delay generator. May be any speed in 1-8 MHz range. 37 10 | NOT READY FOR DATA: GPIB handshake control line. DAC VO | NOT DATA ACCEPTED: GPIB handshake control lina. lines are to be interpreted.

Table 1. Pin Description (Continued) interface functions in a known quiescent state. sequence of events on the GPIB. addresses the device during a polling sequence. and NDAC tines (active acceptor handshake). TR2 EXTERNAL TRANSCEIVERS CONTROL LINE: Set to. expected input signal on the EOI line during parallel poll. [ Voc | 40 | PS. | POSITIVEPOWERSUPPLY:(5V + 10%). [_eno [20 | rs | cicurrGrounp poTeNTiAL. lines. Thus, the data is inverted once from Dp-D7 to DOs bio and non-inverting bus transceivers should be used.

1 CONTROLLER | __ GPIB

Figure 3. 8291A System Diagram

intel. 8291A send status. An 8291A implementation of the GPIB HE ae PURPOSE INTERFACE ofiors ‘the user three altemative addressing modes for which the device can be initialized for each appli- The General Purpose Interface Bus (GPIB) is de- Cation. The first of these modes allows for the de- fined in the IEEE Standard 488-1978 “Digital Inter- vice to have two separate primary addresses. The face for Programmable Instrumentation.” Although a Second mode allows the user to implement a single knowledge of this standard is assumed, Figure 4 _talker/listener with a two byte address (primary ad- provides the bus structure for quick reference. Also, dress + secondary address). The third mode again Tables 2 and 3 reference the interface state mne- _ allows for two distinct addresses but in this instance, monics and the interface messages respectively. they can each have a ten-bit address (5 low-order Modified state diagrams for the 8291A are present- _bits of each of two bytes). However, this mode re- ed in Appendix A. quires, that the secondary addresses be passed 1'0 e microprocessor for verificat . These three ad- dressing schemes are described in more detail in General Description the discussion of the Address Registers. The 8291A is a microprocessor-controlled device designed to interface microprocessors, @.9., 8048/49, 8051, 8080/85, 8086/88 to the GPIB. It implements all of the interface functions defined in Dever the IEEE-488 Standard except for the controller wire, PT function. If an implementation of the Standard’s won EHH] |] tH oaranus Controller is desired, it can be connected with an cote, FH 3 Intel® 8292 to form a complete interface. _— miu tt ‘The 8291A handles communication between a mi- ores eK croprocessor-controlled device and the GPIB. Its ca- ae FST] Pabilities include data transfer, handshake protocol, ie ——=-— talker/listener addressing procedures, device clear- waar fo bt PPh ty Sranaren ing and triggering, service request, and both serial (iL Ph CONTROL and parallel polling. in most procedures, it does not ceee a disturb the microprocessor unless a byte has arrived one apie 5 (input buffer full) or has to be sent out (output buffer TOustEN Ea |] empty). === ceyeaa === snrenrace The 8291A architecture includes 16 registers. Eight choy a of these registers may be written into by the micro- Dever O processor. The other eight registers may be read by omy anit =a the microprocessor. One each of these read and Fst, write registers is for direct data transfers. The rest of weacounes Pe 3 the write registers control the various features of the chip, while the rest of the read registers provide the for 8 microprocessor with a monitor of GPIB states, vari- ‘ous bus conditions, and device conditions. aro None GPIB Addressing am few Each device connected to the GPIB must have at fos least one address whereby the controller device in 205248-4 charge of the bus can configure it to talk, listen, or Figure 4. Interface Capabilities and Bus Structure 3-5

Table 2. IEEE 488 Interface State Mnemonics Table 3. IEEE 488 interface Message Reference List

intel. 82910 Table 3, IEEE 488 Intertace Message Reference List (Continued) tes(1) take control synchronously AH,C ton talk only T,TE REMOTE MESSAGES RECEIVED ATN Attention SH, AH, T, TE, L, LE, PP, C DAB Data Byte (Via L, LE) DAC Data Accepted SH DAV Data Valid AH DCL Device Clear oc END End (Via L, LE) GET Group Execute Trigger oT GTL Go to Local RL IDY Identity L.LE, PP 1FC Interface Clear T, TE, L, LE,C LLO Local Lockout RL MLA My Listen Address L, LE, RL, T, TE MSA My Secondary Address TE, LE, AL MTA My Talk Address 7, TE, LLE OSA Other Secondary Address TE 3 OTA Other Talk Address T.TE PCG Primary Command Group TE, LE, PP PPcte) Parallel Poll Configure PP [PPD]2) Parallel Poll Disable PP [PPE] Parallel Poll Enable PP . PPR) Parallel Poll Response N (via) PPU®) Parallel Poll Unconfigure PP REN Remote Enable RL RFD Ready for Data SH Ras Request Service (via L, LE) (soc) Select Device Clear oc SPD Serial Poll Disable T,TE SPE Serial Poll Enable T.TE sQR() Service Request (viaC) STB Status Byte (via L, LE) TCT or (TOT Take Control c UNL Unlisten LLe REMOTE MESSAGES SENT ATN Attentions c DAB Data Byte (Via T.TE) DAC Data Accepted AH DAV Data Valid SH DoL Device Clear (viac) ENO End (viaT) GET Group Execute Trigger (via C) GTL Go to Local (via C) DY Identity c IFC Interface Clear c LLo Local Lockout (via) MLA or [MLA] My Listen Address (via C) MSA or [MSA] My Secondary Address (viaC) MTA or [MTA] My Talk Address (viaC) OSA Other Secondary Address (viaC)

Table 3. IEEE 488 Intertace Message Reference List (Continued) 1, These messages are handled only by Intel's 8292.

Undefined commands which may be passed to the microprocessor.
All Controller messages must be sent via Intel’s 8292.

presented in Figure 5. A more detailed explanation —_has been processed. [Register | 5 | RO | WR | RSv-RS2| handshake while sending the byte out over the bus. ‘All Write Regist wait until BO is active before writing to the register. information in the Data-Out Register.

Figure 5. 8291A Registers receipt of an interrupt, the microprocessor must read how each of the interrupt bits is set. used to select the events that will cause the INT pin thus does not have a corresponding enable bit. be missed. cally reset after each byte is transferred.

Table 4. Interrupt Bits to the microprocessor for recognition. Set by DTAS A group execute trigger has occurred. TACS+(SWNS+SGNS) | _BO_| A byte should be output. 1, {n ton (talk-only) and ton (listen-only) modes, no ADSC interrupt is generated. The ERR bit is set to indicate the bus error condition detected on EOI. 8291A fires when the GET message is received. vice functions will return in DCAS. Typically this vention. The END interrupt bit may be used by the microproc- ignored in Mode 1.

intel. 82918 The CPT interrupt bit flags the occurrence of an un- between memory and the GPIB; DMAI (DMA in) en- defined command and of all secondary commands ables the DREQ (DMA request) pin of the 8291A to. following an undefined command. The Command be asserted upon the occurrence of Bi. Similarly, Pass Through feature is enabled by the BO bit of | DMAO (OMA out) enables the DREQ pin to be as- Auxiliary Register B. Any message not decoded by __serted upon the occurrence of BO. One might note the 6291A (not included in the state diagrams in Ap- that the DREQ pin may be used as a second inter- pendix B) becomes an undefined command. Note _rupt output pin, monitoring BI and/or BO and en- that any addressed command is automatically ig- abled by DMAI and DMAO. One should note that the nored when the 8291A is not addressed. DREQ pin is not affected by a read of the Interrupt Status 1 Register. It is reset whenever a byte is wrt. Undefined commands are read by the CPU from the _ten to the Data Out Register or read from the Data In Command Pass Through register of the 8291A. This Register. register reflects the logic levels present on the data lines at the time it is read. If the CPT feature is en- To ensure that an interrupt status bit will not be abled, the 8291A will hold off the handshake until cleared without being read, and will not remain un- this register is read. cleared after being read, the 8291A implements a special interrupt handling procedure. When an en- An especially useful feature of the 8291A is its ability abled interrupt bit is set in either of the Interrupt to generate interrupts from state transitions in the Status Registers, the input of the registers are interface functions. In particular, the lower 3 bits of blocked until the set bit is read and reset by the the Interrupt Status 2 Register, if enabled by.the cor- microprocessor. Thus, potential problems arise responding enable bits, will cause an interrupt upon when interrupt status changes while the register is changes in the following states as defined in the being blocked. However, the 8291A stores all now iy IEEE 488 Standard. interrupts in a temporary register and transfers them to the appropriate Interrupt Status Register after the Bit ADSC change in LIDS or TIDS or MJMN _ interrupt has been reset. This transfer takes place Bit 1 REMC change in LOCS or REMS only if the corresponding bits were read as zeroes. Bit 2 LLOC change in LWLS or RWLS The upper 4 bits of the Interrupt Status 2 Register Serial Poll Registers are available to the processor as status bits. Thus, if one of the bits 0-2 generates an interrupt indicating a stato change has taken place, he corresponding LS®_| SRas | ss | ss | s«] so | s2 | s1] status bit (bits 3-5) may be read to determine what SERIAL POLL STATUS (3R) the new state is. To determine the nature of a change in addressed status (bit 0) the Address [$8] rsv | S6| S5| $4] S3| S2| St | Status Register is available to be read. The SPC in- ‘SERIAL POLL MODE terrupt (bit 3 in Interrupt Status 2) is set upon exit @w) Cae tat the a eee gcaued which in The Serial Poll Mode Register determines the status serial poll status byte after the 8291A requested _ byte that the 8291A sends out on the GPIB data seine (asserted SUG) The SPC interust occurs lifes when it receives the SPE (Serial Poll Enable) . $ message. Bit 6 of this register is reserved for the rsv once after the controller reads the status byte it , ris reserved for the rv Service was requested. The convoler may readthe _Cequest svc) local message, Setng this bi to status byte later, and the byte will contain the last CaUSeS for * trom the e oll rena we status the 6291A’s CPU wrote to the Serial Poll tS need for attention from the controller-in-charge of Mode Register, but the SRQS bit will not be set and the GPIB. The other bits of this register are available no interrupt will be generated. Finally, bit 7 monitors £0 Sending status information over the GPIB. Some- d. Finally, bit 7 f time after the microprocessor initiates a request for the state of the 8291 INT pin. Logically, itis an OR p of all enabled interrupt status bits. One should note Service by setting bit 6, the controller of the GPIB Gf atl enabled interrupt status bis. sends the SPE message and then addresses the pt Status 2 Register dog 591, to talk. At this point, one byte of status is not generate interrupts, but are available only to be Point, one , ; returned by the 8291A via the Serial Poll Mode Fleg- read as status bits by the processor. Bit 7 in Interrupt Status 2 is duplicated in Address 0 Register, and the _'Ster. After the status byte is read by the controller, Status 2 is Cuplicated in Address 0 Register, rsv is automatically cleared by the 8291A and an polling for interrupts to , " avoid losing one of the interrupts in Interrupt Status SPC interrupt is generated. The CPU may request 2 Register. ‘service again by writing another byte to the Serial : Poll Mode Register with the rsv bit set. If the control- Bits 4 and 5 (MAI, DMAO) of the Interrupt Mask 2 Register are available to enable direct data transfers 3-11

intel. 8291 ee ler performs a serial poll when the rsv bit is clear, the To use Mode 2 addressing the primary address must last status byte written will be read, but the SRO line _be loaded into the Address 0 Register, and the Sec- will not be driven by the 8291A and the SRQS bit will ondary Address is placed in the Address 1 Register. be clear in the status byte. With both primary and secondary addresses residing on chip, the 8291A can handle all addressing se- The Serial Poll Status Register is available for read- quences without processor intervention. ing the status byte in the Serial Poll Mode Register. The processor may check the status of a request for © —In Mode 3, the 8291A handles addressing just as service by polling bit 6 of this register, which corre- _it does in Mode 1, except that each Major or Minor sponds to SRQS (Service Request State). When a —_ primary address must be followed by a secondary Serial Poll is conducted and the controller-in-charge address. All secondary addresses must be verified feads the status byte, the SRQS bit is cleared. The _by the microprocessor when Mode 3 is used. When ‘SRO line and the rsv bit are tied together. the 8291A is in TPAS or LPAS (talker/listener pri- mary addressed state), and it does not recognize the byte on the DIO lines, an APT interrupt is generated Address Registers (see section on Interrupt Registers) and the byte is available in the CPT (Command Pass-Through) Reg- [tn] ton Jeoi[ras[rpas[ ta] TA [MIMN] Stor Ae pant of te intorut series rorboe ae oe ADDRESS STATUS (4A) croprocessor must read the CPT Register and write ‘one of the following responses to the Auxiliary Mode [nr[oro[ovo[pos.o[aocalans [aozo]Aor] Ret ‘ADDRESS 0 (6R) : . oH inples a non-ai secondary address . implies a valid secondary address [x Jors Jou [Aos-t]an4-1]apa-s]ap2-[aD1-1] Setting the TO bit generates the local ton (talk-only) ‘ADDRESS 1 (7R) message and sets the 8291A to a talk-only mode. This mode allows the device to operate as a talker in [roftol oo [0 [0 JaowilAomo) siitrtace sytem wats carats ADDRESS MODE (4W) ; ; Setting the LO bit generates the local lon (listen- fars[ ot] ou] aps [ aba | aps | ab2 | AD? | only) message and sets the 6291A to a listen-only mode. This mode allows the device to operate as a ADDRESS 0/1 (6W) listener in an interface system without a controller. . The above bits may also be used by a controller-in- The Address Mode Register is used to select one of charge to set itself up for remote command or data the five modes of addressing available on the — communication, 8291A. It determines the way in which the 8291A uses the information in the Address 0 and Address 1 The mode of addressing implemented by the 8291A Registers. may be selected by writing one of the following —In Mode 1, the contents of the Address 0 Register Y'8S '0 the Address Mode Register. Constitute the “Major” talker/listener address while Register the Address 1 Register represents the “Minor” talk- Contents Mode er/listener address. In applications where only one 10000000 Enable talk only mode (ton) address is needed, the major talker/listener is used, 91900000 _Enable listen ‘only mode (lon) and the minor talker/listener should be disabled. 14000000 The 8291 may talk to itsalf Loading an address via the Address 0/1 Register 99000001 Mode 1, (Primary-Primary) into Address Registers 0 and 1 enables the major 99000010 Mode 2 (Primary Secondary) and minor talker/listener functions respectively. 00000011 Mode 3 (Primary/APT-Primary/APT) —In Mode 2 the 6291A recognizes two sequential The Address Status Register contains information address bytes: a primary followed by a secondary. used by the microprocessor to handle its own ad. Both address bytes must be received in order to en- dressing. This information includes status bits that able the device to talk or listen. In this manner, monitor the address state of each talker/listener, Mode 2 addressing implements the extended talker “ton” and “lon” flags which indicate the talk and and listener functions as defined in IEEE-488. listen only states, and an EO! bit which, when set, signifies that the END message came with the last data byte. LPAS and TPAS indicate that the listener 3-12

intel. 82914 or talker primary address has been received. The Mode 3, where secondary addresses are passed microprocessor can use these bits when the sec- through, must the processor intervene in the ad- ondary address is passed through to determine dressing sequence. whether the 8291A is addressed to talk or listen. The LA (listener addressed) bit will be set when the The Address 0 Register contains a copy of bit 7 of 8219A is in LACS (Listener Active State) orin LADS __the Interrupt Status 2 Register (INT). This is to be (Listener Addressed State). Similarly, the TA (Talker used when polling for interrupts. Software should Addressed bit) will be set to indicate TACS or TADS, __poll register 6 checking for INT (bit 7) to be set. but also to indicate SPAS (Serial Poll Active State). When INT is set, the Interrupt Status Register should The MJMN bit is used to determine whether the in- _be read to determine which interrupt was received formation in the other bits applies to the Major or Minor talker/listener. It is set to ‘'1” when the Minor talker/listener is addressed. It should be noted that © Command Pass Through Register only one talker/listener may be active at any one time. Thus, the MJMN bit will indicate which, if ei- [opteloPts|opraorrs|opr2|orTi|oPT9| ther, of the talker/listeners is addressed or active. [opr7|cere]cprs|cer«|crrs|cpra|cers|cpro ‘The Address 0/1 Register is used for specifying the COMMAND PASS THROUGH (SR) device’s addresses according to the format selected ister i may be loaded into the Address 0 and Address 1 the GPIB to the microprocessor. When the CPT fea- Registers by writing into the Address 0/1 Register. —_ ture is enabled (bit BO in Auxiliary Register B), any The ARS bit is used to select which of these regis: message not decoded by the 8291A becomes an aR} ters the other seven bits will be loaded into. The DT Undefined command. When Mode 3 addressing is and DL bits may be used to disable the talker of Used secondary addresses are also passed through listener function at the address signified by the other the CPT Movie, In either case, the 829A will five bits. When Mode 1 addressing is used and only hojd-off the handshake until the microprocessor ‘one primary address is desired, both the talker and reads this register and issues the VSCMD auxiliary the listener should be disabled at the Minor address. Command. ‘As an example of how the Address 0/1 Register The CPT and APT interrupts flag the availability of might be used, consider an example where two priv undefined commands and secondary addresses in mary addresses are needad in the device. The Major the CPT Register. The details of these interrupts are primary address will be selectable only as a talker —_gxpiained in the section on Interrupt Registers. and the Minor primary address will be selectable only as a listener. This configuration of the 8291A is an added feature of the 8291A is its ability to handle formed by the following sequence of writes by the undefined secondary commands cing unde. microprocessor. fined primaries. Thus, the number of available com- [Operation [6S] RO[WA] Data” [Rs,-R6q] mands for futuro IEEE-488 definition is increased;

7 Select adreest 30000001 one undefined primary command followad by a se-

Sle |"| scmoeemmeas be processed. The IEEE-488 Standard does not per- |2. Load major address mit users to define their own commands, but up- into Address 0 Register grades of the standard are thus provided for. with listener function disabled The recommended use of the 8291A’s undefined 3, Load minor address 11088888] 110 command capabilities is for a controller-configured into Addross 1 Register Parallel Poll. The PPC message is an undefined pri- wth talker function mary command typically followed by PPE, and unde- Sisabied, fined secondary command. For details on this proce- dure, refer to the section on Parallel Poll Protocol. At this point, the addresses AAAAA and BBBBB are stored in the Address 0 and Address 1 Registers respectively, and are available to be read by the mi. Auxillary Mode Register croprocessor. Thus, it is not necessary to store any address information elsewhere. Aiso, with the infor ENTZ{CNTifoNTo[coMa|coms|coma|com|comd mation stored in the Address 0 and Address 1 Reg- "AUX MODE (6) isters, processor intervention is not required to CNTO-2:CONTROL BITS recognize addressing by the controller. Only in COMO—4:COMMAND BITS 3-13

intel. 82010 The Auxiliary Mode Register contains a three-bit The 8291A is designed to power up in certain states control field and a five-bit command field. It is used __as specified in the IEEE-488 state diagrams. Thus, for several purposes on the 8291A: the following states are in effect in the power up 1. To load “hidden” auxiliary registers on the 8291. $1216" SIDS, AIDS, TIDS, LIDS, NPRS, LOCS, and 2. To issue commands from the microprocessor to . the 291A. The “0000” pon is an immediate execute command 3. To preset an internal counter used to generate —_ (a pon pulse). It is also used to release the “initial- T1, delay in the Source Handshake function, as ize” state generated by either an external reset defined in IEEE-488. pulse or the “0010” Chip Reset command. Table 5 summarizes how these tasks are performed 0010—Chip Reset (Initialize): This command has the with the Auxiliary Mode Register. Note that the three same effect as a pulse applied to the Reset pin. (Re- control bits determine how the five command bits __fer to the section on Reset Procedure.) are interpreted. Table 5 0011—Finish Handshake: This command finishes a handshake that was stopped because of a holdoff [code | on RFD. (Refer to Auxiliary Register A.) by this command. It has the same effect as a GET 000 | OCCCC |Execute auxiliary command CCCG command issued by the controller-in-charge of the 001 | ODDDD [Preset internal counter to GPIB, but does not cause a GET interrupt. match external cock 0101, 1101—Ciear/Set rtl: These commands corre- equency of ODDD MHz DODD binary representation spond to the local rti message as defined by the IEEE-488. Tho 8291A will go into local mode when a lof 1 to 8 MHz) Set rti Auxiliary Command is received if local lockout . | | DDDDD is not in effect. The 8291A will exit local mode after i i receiving a Clear rt! Auxiliary Command if the 8291A jauxilary register A is addressed to listen. DDDDD [Write DDDDD into lauxiliary register 8 0110—Send EOI: The EO! line of the 8291A may be asserted with this command. The command causes [Enable/disable parallel EOI to go true with the next byte transmitted. The JPoll either in response to remote | £0) line is then cleared upon completion of the messages (PPC followed by handshake for that byte. |PPE or PPD) or as a local lipe message. (Enable if U = 0, 0111, 1111—Non Valid/Valid Secondary Address or ldisable if U = 1.) Command (VSCMD): This command informs the 8291A that the secondary address received by the microprocessor was valid or invalid (0111 = invalid, AUXILIARY COMMANDS 1111 = valid). If Mode 3 addressing is used, the processor must field each extended address and re- Auxiliary commands are executed by the 8291A spond to it, or the GPIB will hang up. Note that the Whenever 0000CCCC is written into the Auxiliary COMS bit is the invalid/valid flag Mode Register, where CCCC is the 4-bit command code. The valid (1111) command is also used to tell the 8291A to continue from the command-pass-through- 0000—Immediate Execute pon: This command re- __state, or from RFD holdoff on GET, SDC or DCL. sets the 8291A to a power up state (local pon mes- sage as defined in IEEE-488). 1000—pon: This command puts the 8291A into the pon (power on) state and holds it there. it is similar The following conditions constitute the power up _to a Chip Reset except none of the Auxiliary Mode state: Registers are cleared. In this state, the 8291A does not participate in any bus activity. An Immediate Ex- 1. All talkers and listeners are disabled. ecute pon releases the 8291A from the pon state 2. No interrupt status bits are set. and permits the device to participate in the bus activ- ity again. 3-14

intel. 8291A ON 0001, 1001—Paralle! Poll Flag (local “ist” message): Thus, the shortest T; is achieved by setting Nr = 1 This Command sets (1001) or clears (0001) the par- using an 8 MHz clock with a 50% duty cycle clock allel poll flag. A “1” is sent over the assigned data (tsyno<63 ns): line (PRR = Parallel Poll Response true) only if the parallel poll flag matches the sense bit from the Ipe at . local message (or indirectly from the PPE message). THs) = 35g + 0.063 = 125.ns max. For a more complete description of the Parallel Poll f non Par- Teatres and procedures refer othe section OnPar~ — juyu any REGISTER A Auxiliary Register A is a “hidden” 5-bit register INTERNAL COUNTER which is used to enable some of the 8291A features. Whenever a 100 AgAgA2AsAq byte is written into the The internal counter determines the delay time al- Auxiliary Register, it is loaded with the data lowed for the setting of data on the DIO lines. This AgAgAgA1Ao, Setting the respective bits to “1” en- delay time is defined as T; in IEEE-488 and appears ables the following features. in the Source Handshake state diagram between the SDYS and STRS. As such, DAV is asserted T; after Ag—RFD Holdott on all Data: If the 8291A is listen- the DIO lines are driven, Consequently , T; is a ma- ing, FIED will not be sent true until the “finish hand- jor factor in determining the data transfer rate of the shake” auxiliary command is issued by the micro- 8291A over the GPIB (T, = TWADV2-TWRD15). —_ processor. The holdoff will be in effect for each data byte. When open-collector transceivers are used for con- nection to the GPIB, T; is defined by IEEE-488 to be Ay—RFD Holdoff on End: This feature enables the IK} 2 us. By writing OO10DDDD into the Auxiliary Mode —_holdotf on EO! or EOS (it enabled). However, no Register, the counter is preset to match a fc MHz _hold-off will be in effect on any other data bytes. clock input, where DDDD is the binary representa- tion of Ne [1<NF<8, Nr = (DDDD)2]. When Ne = Ag—End on EOS Received: Whenever the byte in fc, a2 us T; delay will be generated before each —_the Data In Register matches the byte in the EOS DAV asserted. Register, the END interrupt bit will be set in the Inter- . rupt Status 1 Register. 2Ne Tiqs) = FE + sync. 1SNF<8 ‘Ag—Output EO! on EOS Sent: Any occurrence of data in the Data Out Register matching the EOS teync is a synchronization error, greater than zero Register causes the EO! line to be sent true along and smaller than the larger of T clock high and T —_with the data. clock low. (For a 50% duty cycle clock, tgync is less than half the clock cycle). Ag—EOS Binary Compare: Setting this bit causes the EOS Register to function as a full 8-bit word. Ifit is necessary that T; be different from 2 us, Ne When it is not set, the EOS Register is a 7-bit word may be set to a value other than fc. In this manner, (for ASCII characters). data transfer rates may be programmed for a given system, In small systems, for example, where trans- If Ag = Ay = 1, @ special “continuous Acceptor fer rates exceeding GPIB specifications are re- Handshake cycling” mode is enabled. This mode quired, one may set Ne<fc and decrease Ty. should be used only in a controller system configura- tion, where both the 8291A and the 8292 are used. It When tri-state transceivers are used, IEEE-488 al- provides a continuous cycling through the Acceptor lows @ higher transfer rate (lower T;). Use of the Handshake state diagram, requiring no local mes- 8291A with such transceivers is enabled by setting sages from the microprocessor; the rdy local mes- By in Auxillary Register B. In this case, setting Ne = sage is automatically generated when in ANRS. As fe causes aT; delay of 2us to be generated for the such, the 8291A Acceptor Handshake serves as the first byte transmitted—all subsequent bytes willhave controller Acceptor Handshake. Thus, the controller a delay of 500 ns. cycles through the Acceptor Handshake without de- laying the data transfer in progress. When the tcs Ne local message is executed, the 8291A should be Ts (High Speed) us = 51° * "SNC taken out of the “continuous AH cycling” mode, the GPIB will hang up in ANRS, and a Bl interrupt will be generated to indicate that control may be taken. A 315

intel. 8291A simpler procedure may be used when a“‘tcsonend PARALLEL POLL PROT! of block” is executed; the 6291A may stay in “‘con- ‘OLL PROTOCOL tinuous AH cycling”. Upon the end of a block (EOlor Writing a 011USPPPy into the Auxiliary Mode Reg- EOS received), a holdotf is generated, the GPIB ister will enable (U = 0) or disable (U = 1) the hangs up in ANRS, and control may be taken. 8291A for a parallel poll. When U = 0, this com- ‘ mand is the “Ipe” (local poll enable) local message as defined in IEEE-488, The “‘S” bit is the sense in AUXILIARY REGISTER B which the 8291A is enabled; only if the Parallel Poll i is a “hidden” 4-bi Flag ("ist” local message) matches this bit will the Auxiliary Register B is a “hidden” 4-bit register which @ used to enable some of the features of the Palle! Poll Response, PPFiy, be, sont true (Re- 8291A, Whenever a 101 B48B2B;Bo is written into Sonse = S + ist). The bits F.aPaP1 specify which the Auxiiary Mode Register: iis’ icaded with the of the eight data lines PPR will be sent over. Thus, data 84898 58;By, Set tag tt respective bits to"1" nce the 8291A has been configured for Paralll enables the following features: Poll, whenever it senses both EO! and ATN true, it . will automatically compare its PP flag with the sense Bo—Enable Undefined Command Pass Through: Dit and send PPRw true or false according to the This feature allows any commands not recognized — COMParison. by the 82914 to be handled in software. If enabled, 7 . ; “pe” this feature will cause the 8291A to holdoff the __‘|f @,PP2* implementation is desired, the “Ipe” and handshake when an undefined command is re- __/St” local messages are all that are needed. Typi- ceived. The microprocessor must then read the Cally. the user will configure the 8291A for Parallel Command ftom the Command Pass Through Regis. Poll immediately after initialization. During normal ter and send the VSCMD auxiliary command. Until 2P8fation the microprocessor will set or clear the the VSCMD command is sent, the handshake hold- Parallel Poll Flag (ist) according to the device's need Off will be in otfoct for service. Consequently the 8291 will be set up to. give the proper response to IDY (EO! ® ATN) without B,—Send EO! in SPAS: This bit enables EO! tobe —_—“"8clly involving the microprocessor. sent with the status byte; EO! is sent true in Serial 7 - . ; If a PP1* implementation is desired, the undefined cong TNO State. Otherwise, EO! is sent false in Command features of the 8291A must be used. In : PP1, the 8291A is indirectly configured for Parallel i , Poll by the active controller on the GPIB. The se- are used, The data transfer rate is limited by T; de- _'M0tely is as follows: lay time generated in the Source Handshake func- 1. The PPC message is received and is loaded into tion, which is defined according to the type of trans- the Command Pass Through Register as an unde- ceivers used. When the “High Speed” feature is en- fined command. A CPT Interrupt is sent to the abled, T; = 2 microseconds is generated for the microprocessor; the handshake is automatically first byte transmitted after each true to false tran- held off. sition of ATN. For all subsequent bytes, T1 = 2. The microprocessor reads the CPT Register and 500 ns. Refer to the Internal Counter section for an sends VSCMD to the 8291A, releasing the hand- explanation of T; duration as a function of Bz and of shake. clock frequency. 3. Having recieved an undefined primary command, , - Setti , the 8291A is set up to receive an undefined sec- B3—Enable Active Low Interrupt: Setting this bit causes the polarity of the INT pin to be reversed, ondary command (the PPE or PPD message). providing an output signal compatible with Intel’s is massage is also received into the CPT Reg- MCS-48 Family, Interrupt ragistors are not attected ister, the handshake is held off, and the CPT inter- by this bit. rupt is generated. 4, The microprocessor reads the PPE or PPD mes- By—Enable RFD Holdoff on GET or DEC: Setting sage and writes the command into the Auxiliary this bit causes RFD to be held false until the Mode Register (bit 7 should be cleared first). Fi- “VSCMD" auxiliary command is written after GET, nally, the microprocessor sends VSCMD and the SDC, and DCL commands. This allows the device to handshake is released. hold off the bus until it has completed a clear or trigger similar to an unrecognized command. NOTE: *As defined in IEEE Standard 488. 3-16

intel. 82918 End of Sequence (EOS) Register 2. Set the desired initial conditions by writing into the d of Seq (EOS) Registe Interrupt Enable, Serial Poll Mode, Address Mode, Address 0/1, and EOS Registers. Auxiliary Regis- [ec7 [eos] ecsece[ rcs] eca]ect] eco] ters Aand B, and the intemal counter should also EOS REGISTER be initialized. 3. Send the “immediate execute pon” auxiliary com- The EOS Register and its features offer an alterna- mand to release the initialization state. tive to the “Send EO!” auxiliary command. A seven _4. if a PP2 Parallel Poll implementation is to be used or eight bit byte (ASCII or binary) may be placed in the “Ipe” local message may be sent, enabling the register to flag the end of a block or read. The the 8291A for a Parallel Poll Response on an as- type of EOS byte to be used is selected in Auxiliary signed line. (Refer to the section on Parallel Poll Register bit Ag. Protocol.) if the 8291A is a listener, and the "End on EOS Received” is enabled with bit Az, then an END inter- Using DMA rupt is generated in the Interrupt Status 1 Register whenever the byte in the Data-In Register matches The 8291A may be connected to the Intel® 8237 or the byte in the EOS Register. 8257 DMA Controllers or the 8089 I/O Processor for DMA operation. The 8237 will be used to refer to any If the 8291A is a talker, and the “Output EOI on EOS DMA controller. The DREQ pin of the 8291A re- Sent” is enabled with bit Ag, then the EOl line is sent quests a DMA byte transfer from the 8237. It is set true with the next byte whenever the contents of the by BO or BI flip flops, enabled by the DMAO and Data Out Register match the EOS register. DMA bits in the interrupt Enable 2 Register. Attor (aR} reading , the INT1 register BO and 81 interrupts will be cleared but not BO and BI in DREQ equation.) Reset Procedure The DACK pin is driven by the 8237 in response to The 8291A is reset to an initialization state either by the DMA request. When BACK is true (active low) it a pulse applied to its Reset pin, or by areset auxilia- sets CS = ASO = RS1 = RS2 = 0 such that the ty command (02H written into the Auxiliary Com- RD and WR signals sent by the 8237 refer to the mand Register). The following conditions are caused —_Data In and Data Out Registers. Also, the DMA re- by a reset pulse (or local reset command): quest line is reset by DACK (RD + WR). 1. A““pon” local message as defined by IEEE-488 is ; held true until the initialization state is released. DMA input sequence: 2. The Interrupt Status Registers are cleared (not in- 1. A data byte is accepted from the GPIB by the terrupt Enable Registers). 8291A. 3. Auxiliary Registers A and B are cleared. 2. A Bl interrupt is generated and DREQ is set. 4. The Serial Poll Mode Register is cleared. 3. ORCK and BD are jtiven by the & 8237, the con. ‘ents of the Data In Register are transferred to the 5. The Parallel Poll Flag is cleared. system bus, and DREG is reset.

6 The EOI bit in the Address Status Register is 4 The 8291A sends RFD true on the GPIB and pro-

cleares ceeds with the Acceptor Handshake protocol. 7. Ne in the Internal Counter is set to 8 MHz. This setting causes the longest possible T; delay tobe DMA output sequence: generated in the Source Handshake (16 ws for 1 1. 4 BO interrupt is generated (indicating that a byte iz clock). ; should be output) and DREQ is asserted. 8. The rdy local message is sent. 2. DACK and WR are driven by the 8237, a byte is The initialization state is released by an “imme- Ronuten ord OREO MCS ‘bus into the Data Out diate execute pon” command (00H written into the ‘ * Auxiliary Command Register). 3. The 8291A sends DAV true on the GPIB and pro- ceeds with the Source Handshake protocol The suggested initialization sequence is: 1 i It should be noted that each time the device is ad- Apply a reset pulse or send the reset auxiliary — Gressed (MTA + MLA + ton + lon), the Address command. Status Register should be read, and the 8237 should be initialized accordingly. (Refer to the 8237 or 8257 Data Sheets.) 3-17

intel. 8291A Polling the 8291A. 0 register. All relevant interrupt status bits must be enabled during initialization for them to affect the If polling is used to determine the 8291A's service INT status bit. The following flow chart illustrates the needs, the CPU must poll the INT bit in the address. recommended polling algorithm. ‘es JREGISTER "AND" WITH OFH STATUS 1 REGISTER ‘STATUS BITS SET . YES STATUS BITS SET 20824825 3-18

they must be demultiplexed first. case of 8080, any address lines may be used. If the complete IEEE-488 electrical specification.

1 DRC Tt

Figure 6. 8291A and 8293 System Configuration

Figure 7. 8291A, 8292, and 8293 System Configuration

intel. 8291A ON Start-Up Procedures The ADSC bit in the Interrupt Status 2 Register indi- i cates that the 8291A has been addressed or unad- The following section describes the steps needed to _dressed. The TA and LA bits in the Address Status initialize a typical 8291A system implementing a talk- Register indicate whether the 8291A is talker (TA = er/listener interface and an 8291A/8292 system im- _1), listener (LA = 1), both (TA = LA = 1) or unad- plementing a talker/listener/controlter interface. dressed (TA = LA = 0). If the 8291A is addressed to listen, the local CPU TALKER/LISTENER SYSTEM can read the Data-In Register whenever the Bl (Byte , in) interrupt occurs in the Interrupt Status 1 Register. Assume a general system configuration with the fol. if the END bit in the same register is also set, either lowing features: () Pollad system interface; (i) Mode E.G)or a data byte matching the pattern in the EOS 1 addressing; (ii) same address for talker andlisten- faite hae beon received. er; (iv) ASCII carriage return as the end-of-sequence ‘0! . eee Sauie: {¥) EO! sont true withthe lest byte; In the talker mode, the CPU writes data into the } (vi) 8 MHz clock. Byte-Out Register on BO (Byte Out) true. Initialization. Initialization is accomplished with the following steps: TALKER/LISTENER/CONTROLLER SYSTEM * rede: Register input or write 02H to the Auxilia- Combined with the Intel 8292, the 8291A executes a . ‘ ; complete IEEE-488-1978 controller function. The 2. Write OOH to the Interrupt Enable Registers 1 and 291A talks and listens via the data and handshake 2. This disables interrupt and DMA. lines (NRFD, NDAC and DAV). The 8292 controls [Ky 3. Write 01H to the Address Mode Register to select four of the five bus management lines (IFC, SRQ, Mode 1 addressing. KTN and REN). EOI, the fifth line, is shared. The 4. Write 28H to the Auxiliary Mode Register. This 291A drives and receives EO! when EOI is used as u an end-of-block indicator. The 8292 drives EOI loads 8H to the Auxiliary Register A matching the 7. ena-ol-meek im ire 8a S, 8 MHz clock input to the internal T1 delay counter long wi luring a parallel poll command. to generate the delay meeting the IEEE spec. Once again, assume a general system configuration 5. Write the talker/listener address to the Address with the foliowing features: (i) Polled system inter- 0/1 register. The three most significant bits are face; (i) 8292 as the system controller and control- z0r0. fer-in-charge; (ii) ASCII carriage return (ODH) as the 6. Write an ASCII carriage return (ODH) to the EOS —_EOS identifier; (iv) EOI sent with the last character; register. and, (v) an external buffer (8282) used to monitor 7. Write 84H to the Auxiliary Mode Register to allow ‘ne TCI line. FOI to be sent true when the EOS character IS initialization. in order to send a command across nt . the GPIB, the 8292 has to drive ATN, and the 8291A 8. Write OOH to the Auxiliary Mode Register. This has to drive the data lines. Both devices therefore writes the “Immediate Execute pon” message need initialization. and takes the 8291A from the initialization state into the idle state. The 82914 will remain idle until To initialize the 8292: the controller initiates some activity by driving 4. pulse the RESET input. The 8292 will initially drive TR tus. all outputs high. TCI, SPI, OBFI, IBFI and CLTH il then go low. The Interrupt Status, Interrupt Communication. The local CPU now polls the wa ‘ 8291A to determine which controller command has Mask, Error Flag, Error Mask and Timeout regis: eodieiarenny ters will be cleared. The interrupt counter will be : disabled and loaded with 255. The 8292 will then , monitor the status of the SYC pin. If high, the The controller addresses the 8291A by driving ATN, Fae eal tales IFC rue for at feast 106 sn placing MLA (My Listen Address) on the bus and . i; acing Mi \\dares compliance with the IEEE-488-1978 standard. It driving DAV. If the lower five bits of the MLA mes- aoa i tno ty eceerting ATH sage match the address programmed into the Ad- will then take control by asserting ATN. dress 0/1 register, the 8291A is addressed to listen. ‘eal ; SESS Oa Oa eee eect or sem To iitialze the 8291A, the following is necessary: the MTA message instead of MLA. 1. Write 00H to interrupt Enable registers 1 and 2. This disables interrupt and DMA. 3-21

intel. 8291A 2. With the 8292 as the controller-in-charge, it is im- _true unless the GTSB (Go To Standby) command is Possible to address the 8292 via the GPIB. There- _sent to the 8292. fore, the ton or lon modes of the 8291A must be used. To send commands, set the 8291A in the ATN has to be false in order to send data rather than ton mode by writing 80H to the Address Mode commands from the controller. To do this, the fol- Register. lowing steps are needed: 3. Write 26H to the Auxiliary Mode Register to match _—_1. Enable the TCI interrupt if not already enabled. the T1 data settling time to the 6 MHz clock input. 2. Wait for IBF (Input Buffer Full) in the 8292 inter- 4. Write an ASCII carriage return (ODH) to the EOS rupt Status Register to be reset. Register. 3. Write the GTSB (F6H) command to the 8292 5. Write 84H to the Auxiliary Mode Register in order Command Field Register. to enable “Output EO! on EOS sent” and thus 4 Read the 8 it for TCI to be true. send EOI with the last character. 4: Road the 8262 and wait for ve. ° 5. Write the ton (80H) and pon (00H) command to 6. Write 00H—Immediate Execute pon—to the Aux- the 8291A Address Mode Register and Auxiliary iliary Mode Register to put the 8291A in the idle Mode Registers respectively. state. 6. Wait for the BO interrupt to be set in the 8291A. Communication. Since the 8291A is in the ton _7. Write the data to the 8291A Data-Out Register. mode, a BO interrupt is generated as soon as the immediate Execute pon command is written. The —_Identically, the user could command the controller to CPU writes the command into the Data Out Regis- __ listen rather than talk. To do that, write lon (40H) ter, and repeats it on BO becoming true for as many —_ instead of ton into the Address Mode Register. Then commands as necessary. ATN remains continuously —_wait for BI rather than BO to go true. Read the data Ragister. 3-22

intel. 82010 ABSOLUTE MAXIMUM RATINGS cations are subject to change without notice. veh Respedt to Ground _osvie +7v ‘peraing Condons® te not sacormondee tod x. D.C. CHARACTERISTICS Vcc = 5V + 10%, Ta = 0°C to 70°C (Commercial) [Symbor[ Parameter | Min | Max [Unit] —TestConditions IM [pttow vonage] -08| oa [vd [vin [inputhighvotage | 2 [voc+os| v[ [Vor _[Outputtowvottege || 04s | Vv [ic = 2ma(emAtortAt pin) | [Vou [Outputtigh vonage | 24 | | Vion = —400 nA (— 150 wA for SRO pin) —ceomelg] eer V_| low = —50wA watiewe [| ofa [v= aves | [lor, | OutputLeakage Current | [#10 | uA |Vour=045V.voo [icc [VecSuppiyCurent | [120 [mal[m=oc A.C. CHARACTERISTICS Voc = 5V + 10%, Ta = 0°C to 70°C (Commercial) [‘Symbor [Parameter [| Min | Max | unit | TestConditions | [tan | Address Stabie BotoroREAD | 0 | [ ns | [tra | AddresstoiganorREAD [oo | [ ns [ [tea | READWan [tao | [ns | [tao | Address StabletoDatavaia [| 250 | ns | [tao | READtoDatavaia | | too | ns | [ taor | DataFloatatterREAD | o | 60 | me | [tow | Address StabloBetorowrre | 0 | | ns | [twa | AddressHowaterwaTE | o [| [| [ww | WATEwan | wo | [ms | ae Edge of WRITE 190 Lino [oa HoTine aterwATE [0 | [ef Powoae [ROL orWA woe) [|| we [toxoss | ADJ toValidData(Oo-07 | | 200 | ns_| BACK to J 0<t< 50ns | 9-23

intel. 82910 WAVEFORMS READ \\- tre =| tra ! t neab ata aus 208248-7 WRITE Sins, ww | wat prions WRITE i taw | —+| wo oara sus zos208-8 DMA onea toxRe RD or WR 205208-9 3-24

intel. 82918 ee A.C. TIMING MEASUREMENT POINTS AND LOAD CONDITIONS WNPUT/OUTPUT “ vevice BHDeR nest C= 150 0F 205248-10 = Ac. Toning: nuts re vn at 2.4 for a Logic" and 048 eg trang mansureents sre made at 20V for 8 2os248-11 eng 0 tre Lape GPIB TIMINGS() [Feorre@ | EoLwrart | 195 | ne | PRSSATN=oasv | FO woOvaid | 15 | _ne_| PPSSATN=o4sv | BitioTArd | 165 | _ns_| PPss.ATN=oasv | AND iNDACL | v85 [ns | tacsans | [tara LAMM L tora [155 | ns_[ Tasos [tarrea [AN wormed | 158 | ns_| Tacos DAVL toNDACT | 680 | ns | AWcacs NOACTtoDAVT | 380 [| ns | sHstAs RAFOTwOREGT | «00 [| ns | sw DAV wOREGT | 600 [ne | AHLACS.AIN24v | DAT ONOACL | 250 | ns | antacs DavTwoNAPoT | 950 | ns | AH,LACS.rdy = True ROL oNAFDT | 500 | ne | AMLACS [awaois | WAT tooiovad | 290 | me | sHTacsRS= ov | WAT wEOIvad | 350 | ne | sHtacs TWRDV2 WAT toDAV I 830 + teyno High Speed Transfers Enabled, Ne = fo, tsync = Ye*fo NOTES: 4. All GPIB timings are at the pins of the 8291A. 2. The last number in the symbol for any GPIB timing parameter is chosen according to the transition directions of the reference signals. The following table describes ‘the numbering scheme. [tet [+ | | te | 2 | [tet [3 | [tet [| [ Trova | 5 | [rrovauo | 6 | 3-25

intel. 82910 Consider the condition when the Not-Ready-For- MODIFIED STATE DIAGRAMS Data signal (pin 37) is active. Intel indicates this ac- Figure A-1 presents the interface function state dia- tive low signal with the symbol NRFD (Vout < VoL grams. It is derived from IEEE Std. state diagrams, —_for AH; Vin < Vi. for SH). The IEEE-488-1978 Stan- with the following changes: dard, in its state diagrams, indicates the active state A. The 8291A supports the complete set of IEEE- Of this signal (True condition) with NRFD. 488 interface functions except for the controller. __D. All remote multiline messages decoded are con- These include: SH1, AH1, TS, TES, L3, LE3, SR1, ditioned by ACDS. The multiplication by ACDS is RL1, PP1, DC1, DT1, and Co. not drawn to simplify the diagrams. B. Addressing modes included in T, L state dia- — E. The symbol grams. Note that in Mode 3, MSA, OSA are generated only x after secondary address validity check by the micro- processor (APT interrupt). 205248-12 C. In these modified state diagrams, the IEEE-488- indicates: 1978 convention of negative (low true) logic is 7 - followed. This should not be confused with the 1. When event X occurs, the function returns to Intel pin- and signal-naming convention based on state S. positive logic. Thus, while the state diagrams be- 2. X overrides any other transition condition in the low carry low true logic, the signals described function. elsewhere in this data sheet are consistent with Intel notation and are based on positive logic. Statement 2 simplifies the diagram, avoiding the ex- - plicit use of X to condition all transitions from S to other states. Level_| Logic | IGEE-488 | Intel | T DAV DAV F DAV DAV T NDAC NDAC F NDAC NDAC T NRFD NRFD F NRFD NRFD ony root on 80 IF TACS » NAF. | osu oy too--4 ia a Er AD AIN« FH (WITHIN ta) av Fi =TACS + SPAS 205248-13 Figure A-1. 8291A State Diagrams 3-26

intel. 8291A aro ‘DAT (NDAC ‘ ‘ NRFO a 3 t----4 i ecUR Une MORAL BOCA. Far) Toe Bzepcnciuc baw _ (-) (~) Bi 3 ENO IF 0) + €08) RECEIVED wAeD F2 = ATN + LAGS + LADS 20s248-14 F3 = ATN + rdy ‘T3' = 13 © CPT © APT tan TA MOO 1 ' ; + MSA- TPAS- MODE 1 TN: SPMS. (ove ! ' ' Loo en ‘S78 AND ROS AVAILABLE fost a RIN TAIN) (WITHIN 18) (WITHIN t2) AYN PMS EOVF DAB = EOS F4 = OTA + (OSA@ TPAS + MSA LPAS) © (205248-15, MODE 7 + MLA * MODE 1 Figure A-1. 8291A State Diagrams (Continued) 3-27

intel. 8291A ee ura (JX) CG. MTA sre Fe (WITHIN ta) 20524818 ace pron ROS IN STB ' \\ 1 sro! sroY | } w+ SPAS b----4 iv PRS cr) sas ROS IN STB 205248-17 Figure A-1. 8291A State Diagrams (Continued) 3-28

intel. 8291A ioue ft lon + MSA LPAS * 1 1 MODE 1 + MLA+ MODE 1 bee --d . (~) — X) UNL + MSA TRAS + ODE +MTA-MODE 1 IFC (WITHIN t4) AIN Ni (WITHIN t2 (WITHIN t2) (~~) Pca MTA 205248-18 ross 1 i bore _ 1 t F5- iti Lo---3 GrL- LADS rer CLO EN Lo uo (WITHIN ta) GTL LADS 208248-19 F5 = (MLA® MODE 1 + LPAS » MSA + MODE) Figure A-1. 8291A State Diagrams (Continued) 3-29

i ital. 8291A ro | pez ft Lee --d Ipe ipe ity ioy* WITHIN es) (WITHIN &s) 205248-20 *IDY = ATN © EO! rocco 1 1 1 oe ft i i “ 6 t----4 205248-21 Fo = DCL + SOC + LADS nen i] ! {oor id ' 1 GET: Laos t----4 ” GeT- Laos 5 20524822 Figure A-1. 8291A State Diagrams (Continued) 3-30

intel. 8291A Table B-1. IEEE 488 Time Values Ea Function (Applies to} | __peweroton | vate | i SH Settling Time for Multiline Messages > 2 ps ty LC, IC, SH, AH, T, L Response to ATN < 200ns T3 AH Interface Message Accept Time(3) > 0(4 ta T, TE, L, LE, C, CE Response to IFC or REN False < 100 ps ts PP Response to ATN + EO! < 200 ns Te c Parallel Poll Execution Time 22ps 7 c Controller Delay to Allow Current Talker > 500 ns to see ATN Message Te c Length of IFC or REN False > 100 ns To c Delay for EOS) = 1.5 ps) NOTES: 1. Time values specified by a lower case t indicate the maximum time allowed to make a state transition. Time values: specified by an upper case T indicate the minimum time that a function must remain in a state before exiting, 3 2. If three-state drivers are used on the DIO, DAV, and EOI lines, T; may be: 1, = 1100 ns. 2. Or > 700 ns if itis known that within the controller ATN is driven by a three-state driver. 3. Or > 500 ns for all subsequent bytes following the first sent after each false transition of ATN (the first byte must be sent in accordance with (1) or (2). 4, Or > 350 ns for all subsequent bytes following the first sent after each false transition of ATN under conditions specified in Section 5.2.3 and warning note. See IEEE Standard 488. 3. Time required for interface functions to accept, not necessarily respond to interface messages. 4. Implementation dependent 5. Delay required for EOI, NDAC, and NAFD signal lines to indicate valid states. 6. = 600 ns for three-state drivers. 3-31

intel. 82918 APPENDIX C THE THREE-WIRE HANDSHAKE aa rovunt rwnova . tS Figure C-1. 3-Wire Handshake Timing at 8291A - 3-32

Product Information

P8291A specifications and overview.

Summary

GPIB TALKER/LISTENER

Description

GPIB TALKER/LISTENER

Source title P8291A Datasheet(PDF) - Intel Corporation

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