P8095-90

Intel Corporation

MCS-96 809X-90, 839X-90

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MCS®-96 T-49 19 SF ’ . 809X-90, 839X-90 . m 839X: an 809X with 8 Kbytes of On- @ Pulse-Width Modulated Output Chip ROM mt 232 Byte Register File ms High Speed Pulee 1/0 @ Memory-to-Memory Architecture @ 10-Bit A/D Converter m Full Duplex Serial Port W 6.25 ps 16x 16 Multiply m Five 8-Bit 1/0 Ports m 6.25 ps 32/16 Divide mt Watchdog Timer ms 8 interrupt Sources m Four 16-Bit Software Timers The MCS®-96 family of 16-bit microcontrollers consists of many members, all of which are designed for high- ‘speed control functions. Members with the “~90" suffix are described in this data sheet. The CPU supports bit, byte, and word operations. 32-bit double-words are supported for a subset of the instruction set. With a 12 MHz input frequency the 6096 can do a 16-bit addition in 1.0 ws and a 16 x 16-bit muttiply of 32/16-bit divide in 6.25 1s. Instruction execution times average 1 to 2 18 in typical applications. Four high-speed trigger inputs are provided to record the times at which external events occur. Six high-speed pulse generator oulputs are provided to trigger external events at present times. The high-speed output unit can simultaneously perform timer functions. Up to four such 16-bit Software Timers can be in operation at once, An on-chip A/D Converter converts up to 4 (in the 48-pin version) or 8 (in the 68-pin version) analog input Channets to 10-bit digital values. This feature is only available on the 8096-90/6395-90 and 6097-90/8397-90. Also provided on-chip are a serial port, a watchdog timer, and a pulse-width modulated output signal, vowen reeauencr VAD AOR oOwN meremencs . | ees (eee peeeeiierie beierireed enemas eee 1 | ms | | | ri-- ==5 om) | (=) (SSP Loe, [wen 1] aia TT eS u \\ Le os 1 jponr’ ' ! ' [pa murnecanen | PORTO} =6PORT) Ont? o AAT FUNCTIONS 2700141 Figure 1, Block Diagram October 1087

648 Order Member; 2700 14-004

m@ 3c Pe mr without A/D, and with and without on-chip ROM. Figure 2. 48-Pin Package

Figure 4. Pin Grid Array

. it power is bpplied to the VPD pin.

are register mapped |/O control registers, also re- . Figure 5. Memory Map

itt 800%-00, 899%-00° PRELIMINARY a , T-49-19-16 The 839x carries 8 Kbytes of on-chip ROM, ocoupy- Internal clock, 90 each state time is 3 oscillator pert- . ing addresses 2000H through SFFFH. Instruction or ods. With @ 12 MHz clock, each state time requires dala fetches fram theee addresses access the on- 0,25 microseconds. chip ROM it the EA pin is externally held at a T-49-19-59 logieal 1, It the EA pin is at a logical 0 these address- @8 access off-chip memory. High Speed I/O Unit (HS10) A map for the MCS-96 product family is The HSI unit consists of the High Speed input Unit Shown in Figure & (HS), the'High Speed Output Unit (HSO), one coun- ter and one timer, “High Speed” denotes that the . The RALU (Register/ALU) section consists of a 17- units can perform functions related to the tmers bit ALU, the Program Status Word, the Program without CPU intervention. The HS! records times Counter, and several temporary registers. A key fea- when events occur and the HSO triggers events at ture of the 8006 Is that it does not use an accumula: preprogrammed times. tor. Rather, it operates directly on any register in the Register File. Being able to operate directly on data All actions within the HSIO unit are synchronized to In the Register File without having to move it into the timers. The two 16-bit timer/counter registers in and out of an acoumulator results in a significant the HSI0 unit are cleared on chip reset and can be Improvement in execution speed, programmed to generate an interrupt on overtiow. ‘The Timer 1 register is automatically incremented In addition to the normal arithmetic and logical func- every 6 state times (every 2.0 microseconds, with & tions, the MCS-96 instruction set provides the fol- 12 MHz clock). The Timer 2 register can be pro- lowing special features: grammed to count transitions on either the T2CLK pin or HSi.1 pin. It Is incremented on both positive 6.25 ys Multiply and Divide ‘and negative edges of the selected input line. in ad- Multipte Shift instructions dition to being cleared by rasat, Timer 2 can also be cleared in software or by signals from input pins 3 Operand Instructions T2RST or HS1.0, Neither of these timers Is required ‘ Normalize Instruction for the watchdog timer or the serial port. ‘Software Reset instruction : ‘The High Speed input (HSI) unit can detect tan- ‘All operations on the 8096 take place ina set num- _ sitions on arty of its 4 input fines. When one occurs it ber of “State Times.” The 8096 uses a three-phase records the time (from Timer 1) and which input lines ‘He TRIGOER OPTIONS "we puis wen q a [tom wares r Ls] = ae oS Haoaod } JUULIL [_voee_] [ns_srarus] (VERT ExlartH PORTE 7 Tearemon 270014-8 [_ici.rue | 27e014~19 © Pies meaiuvement with 2.0 pa00 resciitor: ¢ nee araifons trigger the recording of Be reference ‘Timer (16-88) and triggered inpat(s) [4.8% . Figure 6. High Speed Input Unit 6-52

08900 T-49-19-16

40 Le]

Figure 7. High Speed Output Unit level FIFO. The unit can be programmed to look for _as the input to the A/D Converter. of these events. Either Timer 1 or Timer 2 canbe 4 transition time.

INTEL CORP UP/PRPHLS L2€ 0 9 4826175 ooLazeo 5] . + - mM iritel 809X-90, 839X-90 PRELIMINARY a T-49-19-16 Ports 3 and 4 are bi-directional 1/O ports with open Pending register. The content of the Interrupt Mask ’ drain outputs. These pins are also used as the multi- register determines if a pending interrupt will be plexed address/data bus when accessing external serviced or not. if it is to be serviced, the CPU memory, in which case they have strong internal pushes the current program counter onto the stack pullups. The internal pullups are only used during —_and reloads.it with the vector corresponding to the external memory read or write cycles when the pins _dasired interrupt. The interrupt vectors are located in are outputting address or data bits. At any other addresses 2000H through 2011H, as shown in Fig- time, the internal pullups are disabled. ures. | pailues . T-49-19-59 Vector Location . Serial Port The serial port is compatible with the MCS®-51 fami- Byte) : ly (8051, 8031 otc.) serial port. It is full duplex, and Software 2011H | 2010H | Not Applicable réceive-buffered. There are 3 asynchronous modes —_| Extint 200FH | 200EH |7 (Highest) and 1 synchronous mode of operation for the serial | Serial Port 200DH] 200CH |6 port. The asynchronous modes allow for 8 or 9 bits —_| Software 200BH| 200AH |5 of data with even parity optionally inserted for one of Timers the data bits. Selective interrupts based on the 9th HSI.0 2009H | 2008H | 4 data bit are available to support interprocessor com- High Speed 2007H | 2006H |3 munication. Outputs HSI Data 2005H | 2004H |2 Baud rates in all modes are determined by an inde- Available pendent 16-bit on-chip baud rate generator. Either A/D Conversion | 2003H | 2002H | 1 the XTAL 1 pin or the T2CLK pin can be used as the Complete input to the baud rate generator. Tho maximum baud [Timer Overflow | 2001H | 2000H | 0 (Lowest) rate in the asynchronous mode is 187.5 KBaud. Figure 8. interrupt Vectors At the end of the terminal routine the RET instruction Pulse Width Modulator (PWM) -pops the program counter from the stack and execu- The PWM output shares a pin with port bit P2.6. tion continues where it let off. It is not necessary to When the PWM output is selected, this pin outputs a__store and replace registers during interrupt routines pulse train having a fixed period of 256 state times, 85 each routine can be set up to use a different sec- End a programmable width of O to 255 state times, _tion of the register file. This feature of the architec- The width is programmed by loading the desired val- ‘ure provides for very fast context switching. i 3, to the PWM Control Register. - 7 “, tue, In state times, to the ‘ontrol Register. While the 8096 has a single priority level in the . sense that any interrupt may be itself be interrupted, a priority structure exists for resolving simultaneous- A/D Converter ly pending interrupts, as indicated in Figure 8. Since The analog-to-digital converter is a 10-bit, succes- the interrupt pending and interrupt mask registers sive approximation converter. It has a fixed conver- can be manipulated in software, it is possible to dy- sion time of 168 state times, (42 microseconds with _amically alter the interrupt priorities to suit the us- a 12 MHz clock). The analog input must be in the —_&"S’ software. range of 0 to VREF (normally, VREF = 5V). This input can be selected from 8 analog input lines, . which connect to the same pins as Port 0. A conver: © Watchdog Timer i be initiated either by setti trol bit i a the A/D Command register, or by programming the The watchdog timer is a 16-bit counter which, once HSO unit to trigger the conversion at some specified Started, is incremented every state time. After 16 time. milliseconds, if not cleared, it will overflow, pulling down the RESET pin for two state times, causing the - system to be reinitialized. This feature is provided as . a means of graceful recovery from a software upset. Interrupts The counter must be cleared by the software before The 8096 has 20 interrupt sources which vector _ it overtlows, or else the system assumes an upset through 8 locations. A 0-to-1 transition from any of has occurred and activates RESET. the sources sets a corresponding bit in the Interrupt 6-54

INTEL, CORP UP/PRPHLS L2€ O ff 4826175 o0ba721 7a : intel 809X-90, 839X-80 - PRELIMINA PIN DESCRIPTION RESET T-49-19-59 Reset input to the chip. Input low for at least 2 state vcc times to reset the chip. The subsequent low-to-high / transition re-synchronizes CLKOUT and commenc- Main supply voltage (5V). es a 10-state-time sequence in which the PSW is cleared and a jump to address 2080H is executed. vss . Input high for normal operation. RESET has an inter- ‘nal pullup. \\ . Digital circuit ground (OV). . TEST vPD . Input low enables a factory test mode. The user RAM standby supply voltage (5V). This voltage must should tie this pin to VCC for normal operation. be present during normal operation. In a Power Down condition (Le., VCC drops to zero), if RESET is activated before VCC drops below spec and VPD = NMI. continues to be held within spec, the top 16 bytes in the Register File will retain their contents. RE: A positive transition clears the watchdog timer, and must be held low during the Power Down and should causes a vector to external memory location 0000H. not be brought high until VCC is within spec and the External memory from 00H through OFFH is re- oscillator has stablized. . served for Intel development systems. VREF . INST Reference voltage for the A/D converter (5V). VREF Output high during an external memory read indi- is also the supply voltage to the analog portion of cates the read is an instruction fetch. INST needs to . the A/D converter and the logic used to read Port 0 —_be latched on the falling edge of ALE. as digital input. EA ANGND Input for memory select (External Access). EA = 1 Reference ground for the A/D converter. Should be causes. memory accesses to locations 2000H held at nominally the same potential as VSS. through 3FFFH to be directed to on-chip ROM. EA = 0 causes accesses to these locations to be di- vi rected to off-chip memory. EA has an internal pull- BB down, 80 it goes to 0 unless driven to 1. EA is not ‘Substrate voltage from the on-chip back-bias gener- _'tched internally during RESET. ator. This pin should be connected to ANGND through a 0.01 yf capacitor (and not connected to ALE anything else). Address Latch Enable output. ALE is activated only XTAL1 during external memory accesses. It is used to latch , the address from the multiplexed address/data bus, Input of the oscillator inverter and of the internal and is placed in a low condition during reset. clock generator. RD XTAL2 - Read signal output to external memory. AD is acti- Output of the oscillator inverter. vated only during external memory reads, CLKOUT WR . Output of the internal clock generator. The frequen- Write signal output to external memory. WR is acti- cy of CLKOUT is % the oscillator frequency. Ithas a _yated only during external memory writes. 33% duty cycle. 6-55

"| 1 INTEL CORP UP/PRPHLS n2e o ff ya2uizs ooeazz2 9 a T-49-19-16 BHE Ports 3 and 4 : T-49-19-59 Bus High Enable signal output to external memory. _8-bit bi-directional I/O ports with open drain outputs. BHE = O’selects the bank of memory that is con- These pins are shared with the multiplexed address/ nected to the high byte of the data bus. A0 = 0 —_data bus which has strong internal pullups. selects the bank of memory that is connected to the tow byte of the data bust. Thus accesses to a 16-bit wide memory can be to the low byte only 0? =0, INSTRUCTION SET : BHE ~ 1), to the igh byte only (AO — 1. 8 = 0), Rs or to both bytes (AO = 0, = 0). BHEis activat- The 8096 instruction set makes use of six address- ed only when required during accesses to external —_ing modes as described below: memory. BHE can be ignored during read opera- - tions. This pin must be latched on the falling edge of | DIRECT—The operand is specified by an 8-bit ad- ALE, . . dress field in the instruction. The operand must be in the Register File or SFR space (locations 0000H READY through OOFFH). IMMEDIATE—The operand itself follows the op- The READY input Is used to lengthen external mem- ' ory bus cycles, for interfacing to slow or dynamic code in the instruction stream as immediate data. mamory, or for bus sharing, if the pin is high CPU _-The Immediate data can be either 8-bits or 16-bits as operation continues in a normal manner. If the pin is required by the opcode. oO A eee. nto a walt mode INDIRECT—An é-bit address field inthe instruction until the next negative transition in CLKOUT after gives the address of a word registar in the Register ALE occurs with HEADY high. The bus cyole canbe Fle which contains the 16-bit addrose of the oper- fengthened by up to 1 us. When the external memo- 44: The operand can be anywhere in memory. ty bus is not being used, READY has no effect. ; READY has a weak internal pullup, so it goos to1 INDIRECT WITH AUTO-INCREMENT—Samo as unless externally pulled low. Indirect, except that, after the operand is referenced, the word register that contains the operand’s: ad- dress is incremented by 1 if the operand is a byte, or HSI by 2 if the operand is a word. Inputs to High Speed Input Unit. Four HS! pins are INDEXED—The instruction contains an 8-bit_ad- them (HSI.2 and HSI.3) are shared with the HSO ment field. The 8-bit address field gives the address Unit. of a word register in the Register File which contains a 16-bit base address, The 8- or 16-bit displacement HsO field contains a signed displacement that will be added to the base address to produce the address Outputs from High Speed Output Unit. Six HSO pins _of the operand. The operand can be anywhere in and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit. The 8096 contains a Zero Register at word address 0000H (and which contains 0000H). This register is Porto available for performing comparisons and for use as Po! a base register in indexed addressing. This effective- 8-bit high impedance input-only port. These pins can ly provides direct addressing to all 64K of memory. . be used as digital inputs and/or as analog inputs to « In the 8096, the Stack Pointer is at word address the on-chip A/D converter. __ 0018H in the Register File. If the 8-bit address field . in an indexed instruction contains 18H, the Stack . Port 1 Pointer becomes the base register. This allows di- - 7 rect accessing of variables in the stack. 8-bit quasi-bidirectional I/O port. The following tables list the MCS-96 instructions, Port2 their opcodes, and execution times. : 8-bit multi-functional port. Six of its pins are shared with other functions in the 8096, the remaining 2 are quasi-bidirectional. 6-56

INTEL CORP UP/pRPHLS , . ¥2E 0 I vsee17s oova7e3 off inte! 809X-90, 899X-90 PRELIMINARY Sn T-49-19-16 Instruction Summary a ‘x T-49-19-59 [ mrwmone [er | onmaten ower Frere te Tarp ar St [appapos [2 [oeora sii» tet~ietri—T [app/apos | 3 [peste sid» itetetetrt[—T [appovappea|_a[poeo+are. itivlyty{r[—t | [supsusa|2 [p-o-a ixivitytei[r[—-t | [sussuss|s|o~s-A die iielte tet rt—] | [suscrsuscs | 2 [o<o-ato-1 | di[ei[ei[e[ri—| [ompomes [2 [o-A Sd [Ht oto tt Ley [sb eran pte = wnancor[—[—T=l2ptl=)2_| ——-[anoanos[9@ [peBada dt [ef ofof—[—y [ups if 2 [own dT (-f—-f=}—|-T [ror take re T= t= ff t d PUSHF SP < SP — 2;(SP) <~ PSW; poe eer LT tee fT a a [ar(ndrecy | 1 [poem Sd | — ||| JT feu [eres (ti t= [ie]: | PC < PC + 11-bit offset pen ereamer EET PC < PC + 16-bit offset . - [unc | 1 | uumpo=o0 —SS—Cd — | — |= J] [HT 5 | [set Pumps SCC [JJ] 8s | NOTES: 1. If the mnemonic ends in “B", a byte operation is performed, otherwise a word operation is done. Operands D, B, and A must conform to the alignment rules for the required operand type. D and B are locations in the registor file; A can be located anywhere in memory. 2.D, D + 2 are consecutive WORDS in memory; Dis DOUBLE-WORD aligned. . 3. D, D + 1 are consecutive BYTES in memory; D is WORD aligned. . ‘4, Changes a byte to a word. 5. Offset is a 2's complement number. 6-57

INTEL CORP UP/PRPHLS 12e o ff yaeei7s oovazey 2 ff | . he . IN { intel “oe 809X-90, 839X-90 - PRELIMINARY Fg g-1 9-16 Instruction Summary (Continued) S T-49-19-59 ceric [_wemonie | Ore LzTeTel var [one dT St [ umpz=o CSC J J —[ — J Ts | [uoe SST 1 | umptn=o SSC | ~~ — J — TJ's | fur, | 1 (| umptn=1 CT TPT J TAT ss [ued ti SumptNetorz=1 J | —[—[—f-J—T os | [und d| it ~*i| umptC=0oz=1 J | [Jf] Ts | fw Sd tsi umptveat TTP ss | [uv Sd St | umptveo Cd TTT is | a a Let npitvr = oscar T= =T=,=Pot=t [ust SSS St fumpst=1 Cd — | | Tf —T—J s [ust «| 1 ~‘|vumptst=o SCT | [J —[—J[ Ts] Liss} oT sin itspoctean= 1} = [== 1-1-1 bee] [ses [ane it specfeaen = 0 =} =T=|=}= T= Tee] DO + D0-1;ifD #Othen fore [eee tearm” ff ff [a] | [Decoecs | 1 [oe o-1 —C wT Tw TT TTT [Neqnecs | 1 |owo-0 |¥iel[yte[rl{—T | [wonncp | 1 [Oe +d C Pe Te Te tT [exe] 1 [Oe DO+1e Sin |~l~{fofol—|—T s | [NoTNOTa «| 1 | O+LogicaiNooy ss || fofol—[—| | [orcas | 1 [oro it sfofoto;—l-T | [sHu/sHie/sHLt | 2 [C+ msb—-————ib <0 |e] 2[el-| rt [—T 7 | [eunacnmsranma | 2 [ mab mb aao— mw SoTL fop ote | [sero | to [Cet TCS J JPR [oa S| oo |weo CE JJ TH [rst S| OPC eo CCP ToT oT of of 6 | a [eT entieAtrionpist' =) T=T=T=T=1=1=1 OO oc ee eee ee ee [sp S| 0 feces pc+e CUT [—f- PT -] Loma “2 [erste = 50 aie > |? to TTT 17 = gegen hl tt tt PG < (2010H) NOTES: ° 1. If the mnemonic ends in “B", a byte operation is performed, otherwise a word operation Is done. Operands D, B, and A must conform to the alignment rules for the required operand type. D and B are locations in the register file; A can be located anywhere in memory. 5. Offset is a 2's complement number. 6. Specified bit is one of the 2046 bits in the register file. 7. The “L” (Long) suffix indicates double-word operation. 8. Initiates a Reset by pulling RESET low. Software should re-initialize all the necessary registers with code starting at 2080H. 9. The assembler will not accept this mnemonic. 6-58

INTEL CORP UP /PRPHLS 12e 0 ff yaae17s aobazes 4 ff i intel 809X-90, 839X-90 PRELIMINARY T-49-19-16 i INDEXED 2 lg ; T-49-19-59 S 4 a] f=] on|s i} ie} japp [2 Jos[a] 4 Tos[a[ 5 [oo [3] on [3] m2 [or[at on [5] m2 | {app [3 [asfal os fasts} 6 [as [al m2 [at ens [a7 [5] m2 [ol ans | [a [a[ 4 fasfat 4 fae [a] on [3 m2 [a7 fat on [s[ az | jappp [3 [sa[a{ 5 [ssa s [se fal me [a] aa [57 [5] me [ol ens | : [appc [2 [aa[3| 4 [as[4{- 5 Tac[3{ on [3 [m2 [ar[a{ on [5] m2 | [appcs [2 [as[3| 4 [as{s| “4 [acls] on [3 [m2 [e7[a[ on [s| m2 | [sup [2 [os [s| 4 Joo fa] s [oats] ont [3] m2 [oa laf on [5] mz | [sus [3 fas{a{ 5 Ja [s{ 6 [aalat m2 [4[ ana [aps] m2 [ol ans | [susp [27s [3] 4 | {3sf 4 Prats] on [3{ m2 [re [4 on [5] az | (supp [3 [se fa] 5_[so[s] os [safa[ me [at ons [sp [5] m2 [ol] a3 | [suc [2 [asl3| 4 fasta[ os [aala[ on [3] m2 faslal on [5] ma | |susce | 2[es[3] 4 [asl3{ 4 [pals] on [3 m2 [eala[ on [5 | mz | [emp [2 [ee {3{ 4 [oo lal os [sala] on [3] m2 [en [ay on [s[ me | [emp [2 [os [3| 4 [oo [3] 4 [oats | ons [3] m2 [oe fal on [sf m2 | A OO OO A DO [Mucu [2 [oc {3 {25 [eo] 4| 26 [oe [3 | 2032 [3 | 203 [or [4 | 2732 | s [8033 | [Mutu [3 [aca | 26 [an] s| 27 [ae [4 | 28033 [4 [394 [ar [5 | 28733 [6 | 29734 | [MuuB | 2 [rc [s [17 [rm] 3] in [ve [3 | ie [3 | 2005 |r [4 | 9a [5 [20025 | [Mucus | 3 [sc[a] is [spa] ie [se [4 | 20s [4 | aire [sr [5 | 2005 | 6 | 21726 | jMur [3 [o[st 30 folel a [Is] sus7 [5 [3308 | @ [6] 3237 [7 [3308 | [Murs | 2 [fal 2 [ofa] 2 [o [a] 28 [a | 2429 | || 23/28 | 6 | 2429 | [piwy [2 [ec|3| 25 [eos] 26 [ee [3 {2032 [3 [2993 | ar [4 | 2ua2 [5 | 2933 | [piwus [2 [ec{s{ 17 [oo] 3] 17 |e [3 | 2026 [3 | airs | or [a | 204 [5 [2125 | [pie [2[o{s{ a [ofsl a [oe [4] 2s [4] 25n9 | o-]s | zane [| 2529 | 270014-9 NOTES: * Long indexed and Indirect + instructions have identical opcodes with Short indexed and Indirect modes, respectively. The second byte of instructions using any indirect or indexed addressing mode specifies the exact mode used. If the second byte Is even, use indirect or Short indexed. If it is odd, use Indirect+ or Long Indexed. In all cases the second byte of the instruction always specifies an even (word) location for the address referenced. . 1. Number of state times shown for internal/external operands. 2. The opcodes for signed multiply and divide are the opcodes for the unsigned functions with an “FE” appended as a ete times shown for 16-bit bus. 6-59

INTEL CORP UP/PRPHLS re o Mf seers oosszae s Bf : = 4 : intel 809X-90, 839X-80 PRELIMINARY SSS 9-16 | NORMAL [AUTOWNc| sHoRT | LONG | g T-49-19-59 w w wl | o wl lo | lelea| §e}eg| Sle) dale] 2g Fle] ey lel Bg a iJ BFYa| bE | Sia] BF fa] be fanD_[2foo[s] 4 Torls] s | 62 [3] om [3] m2 [ofa on [5] me | fand_ [3 [ao fats [arls[ 6 [a2 [at m2 [sf ana [ass] m2 [6] ens | faNDB [2 {7of3] 4 [ula{ 4 [2 3) on [3] m2 [asfal on [s| mz | lanpB | 3 [sofa[s [sifa[ ss [sz [af me [af ans [sa] s{ 72 fo] ans | for [2 feols{s Talat s [2 [3] ou [3] m2 [asla] ou [5] m2 | forB [2foofs{ 4 folat 4 | [at ou [3] m2 ]osfal on [s| m2 | [xor [2 {ela 4 [estat s | sofa] ou [af m2 [arts] on |s| mz | fxors_ [2fo[sl ¢ [os[a[ 4 [os [3] ou [3] m2 forfal ou [5] m2 | [ep 2Jaolsy 4 Taife{ 5 [ az[ay ou [37 m2 [as[s] on [5] me | lupe [2 {eols{ 4 [oils] 4 | e2ta{ ou [3{ m2 [esls| on |s| mz | jst [2 foofs} «4 [—[-[—Telstm [37 a2 [osla{ mi [s] en | [sta [2 feats] 4 [—|-| — Peefat mi [3 en forfat am Js] ez | juopse [2 {acl{3{ 4 [ep[s{ 4 [pels] ou [3{ m2 [erlal on [5] mz | juopze [2 fac{s] « [ao[a[ 4 | ae[s{ ou [3] m2 [arfs] on |s| mz | [push [ifce[2] es [oo[a] @ [cal2 [ims [2] 126 [op] s] ims [4] 126 | [por [1 fec{2 [12 [— [—)—— [ce [2 [ans [2] rane [or [3 [ane [4 | ians | jpuswr Tofmiit es | TTT TT TT TTT Tyr jporr fofmiit > T TT fT Tf Til Tyr TT [push [1 Tea[2[ 12 Too[s] 12 [cal2] iso [2] 1620 [ee] 3] iso [4] 16720 | jpusHr Tofra[if i [ [TPT TT Ty? err fy [por [ofmiifis [ TTF Tr Tr Trlr TT _i |MNEMONIC| OPCODE | BYTES | STATES [MNEMONIC | OPCODE| BYTES | STATES | fume fers seca fer || nem | [sp [amo [2 Ts scan faer® [| anew _| [pay es rer [ro SCd| St Cig | [rrap@ [ey | airs 270014-10 NoTES: 1. Number of state times shown for internal/external operands. 3. The assembler does not accept this mnemonic. 4. The least significant 3 bits of the opcode are concatenated with the following 8 bits to form an 11-bit, 2’s complement, offset for the relative call or jump. 5. State times for stack located internal/external. . 6-60

INTEL CORP UP/PRPHLS lee D I 4426175 0068728 T | intel 809X-90, 839X-90 PRELIMINARY —_— SS -49- 19-16 FUNCTIONAL DEVIATIONS . -HSI/HSO Section T-49-19-59 ; Functional deviations from the 80x and 839x on the 1. HSI Timing—An event occurring within 16 state 809x-90 and 839x-90. times of a prior event on the same HS! line may not be recorded. Additionally, an event occurring : . within 16 state times of a prior event on another CPU Section _ HSI line may be recorded with a time tag one ‘ : count garlier than expected. Events are defined 1, Indexed, 3 Operanid Multiply—The displacement as the ondition the line is set to trigger on. The portion of an indexed, three word multiply may not effective resolution is increased to 4 ys for such be in the range of 200H thru 17FFH inclusive. - ‘closely spaced events. ahs also applies to byte multiples that use 3 oper- > 4s) Divide by 8 Mode—If an event on a pin set to ands. look for every eighth transition occurs less than 2. Add or Subtract with carry—The zero flag is both 16 state times after an event on any other pin, ‘set and cleared by these instructions. Zero check- then the divide by 8 event will be recorded twice ing must be done after each operation. in the HS! FIFO. The time tag of the duplicate 3, EXT—This instruction never sets the N flag, and FIFO entry will be equal to that of the initial entry always sets the Z flag. The EXTB works correctly. plus one. The programmer's software should de- Check the flags before executing an EXT instruc- tect and discard the second entry. tion. Additionally, having more than two wait — 3, HSO Interrupts—Software timer interrupts cannot states during an EXT (extend word only) instruc- be generated by the HSO commands that reset tion may cause the instruction to give an incorrect Timer 2 or start an A to D conversion. result. "4, The first few instructions of an interrupt service 4. Read-Modify-Write on Interrupt Pending—A read- routine should check 10S1.7 and exit if the Hold- modify-write instruction on the interrupt pending . ing Register is not loaded. This will successfully register may cause interrupts that occur during clear unwanted events. . execution of the instruction to be missed. 5. READY line—The READY line should not be brought low during the execution of an instruction © Serlal Port Section that accesses HSI_TIME, SP_STAT or IOS1. It , should also not be brought.low for a data write _—_1- Serial Port Flags—Reading SP_STAT may not during the instruction immediately preceding one clear the TI or Al flag if that flag was set within of the above operations. Do not use wait states ‘wo state times prior to the read. In addition, the for program memory that holds these instructions. Parity error bit (RPE/AB8) may not be correct if it Also place a NOP between writes to slow memory is read within two state times after All is set. TIME, SP_STAT Hog BOresses © HSO—TIME, SP_STAT oF 1155 tho following code to replace ORB sp_image, - P. . The READY line also should not be brought low SP_STAT. for more than two state times when using the EXT —sp_REaD: {extend word) instruction. IDB TEMP, SP_STAT 6. Signed Divide—The V and VT flags may indicate ORB SP_INAGE, SP_STAT an overflow after a signed divide when no over- JBS TEMP,5,SP_READ ; if TI bit is set flow has occurred. 3 then read again 7. The sticky flag is not affected when a shift by zero ‘JBS TEMP,6,SP-READ ;.if RI bit is set .Is executed on an 8X9X-90. ANDB SPIMAGE,g7¥H then road again 8. The JBS and JBC instructions should not be used ee i REO/RPE directly on Port 2.1 or any pins of Port 0 if used as ORB SP_INAGE,TEMP ; load correct digital input. if it is necessary to test these pins, } RBB/RPE first LD ir ter, : ares thon test tno bat aan, 3 temporary resister, — 5 serial Port Mode O—The serial port is not tested in mode 0. The receive function in this mode does not work correctly. The receive function will not work unless the first bit shifted in is a one. 6-62

INTEL CORP UP/PRPHLS ize o ff 4a2u17s oons7e9 1 ff ; intel 200%-00, 999x-00 PRELIMIOARY a eeSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS T-49-19-16 T-49-19-59 3. Serial Port Baud Value—Loading the baud rata To write to Port 4, use the DCB operator to gener- Tegister with 8000H (maximum baud rate, internal ate the opcode sequence “OC3H, 001H, OFFH, clock) may cause an 11 millisecond delay (at 01FH, (temp)”, where the high byte of “temp” Fosc = 12 MHz) before the port is properly initial- contains the data for the port. Ports 3 and 4 will aed. After initialization the port works properly. in- not work as input ports. . clude a 44000 state time delay after writing Also, when writing to Ports 3 and 4, the address of 8000H to the Baud Rate Register. the port, (1FFEH, 1FFFH) will appear on the bus pins for 2 oscillator periods before the new data is Presented to the pins. Since normal bus contro! Standard I/O0.Section signals (ALE, RD, etc.) are suppressed during writes to these addresses, there is no way to latch Eee eee ocean Mode Only} Fo the data and prevent this address “glitch” to the drone hep iourd Rates toes praet Be outside world. If this presents a problem in an ap- tiie to Pod 3 oo" tee itch hee te plication, port reconstruction must be done at an- te to Port 3 use "ST temp, ‘ffeh", 8 other address as described in the MCS-96 Hard- low byte of “temp” contains the data for the port. ware Design Information Chapter. 6-63

INTEL CORP UP/PRPHLS L2E O | 4826175 0068730 af : intel 809X-90, 839X-90 PRELIMINARY T-49-19-16 . T-49-19-59 ABSOLUTE MAXIMUM RATINGS* “Notice: Stresses above those listed under “Abso- lute Maximum Ratings" may cause permanent dam- Voltage from Any Pin.to other conditions above those indicated in the opera- Veo OrANGND «oct oe<., =0.3V to +7.0v — “onal sections of this specification Is not implied. Ex- Ss netasteseseene 74 . iG abachae rating ‘ons for NOTICE: Specifications contained within the : following tables are subject to change. OPERATING-CONDITIONS : : . [symbor [= Parameter [Min [Max [Units | ‘Ainblont Temperature UnderSias | __0 | +70 | ¢ _| Digital Supply Voltage [450 [550 |v _| __ Analog Supply Voltage p45 [65 Tv | fosc | Oscillator Frequency | oT [Veo |_Power-Down Supply Volags | _460| 680] v __| NOTE: Vee should be connected to ANGND through a 0.01 yF capacitor. ANGND and Vgg should be nominally at the same ~ potential. - a : D.C. CHARACTERISTICS: [Symbot[ ____Parameter___| Min | Max | Unite] TeatCondiione | Input Low Voltage (Except RES [-oaf _+oe [v Jo [Vas | inputLowVoltage, RESET =f 03] 407 | v | | Input High Voltage (Except RESET, NMI,XTAL1)| 20 |Voc+os| v | _—is| Input High Voltage, RESET Rising [24 [Voct+os[ v [| SETFaling S| 241 [Vog+os] v fo | Input High Voltage, NMI, XTALY [24 |Voc+os| v [| [Vo. | OutputLowVoltage TT TV [iNotet) Output High Voltage [24 [|v [Wotea) | Disconnected and Power-Down liner | VacrSupplyCurent | TP mA | tu Input Leakage Current to all pins of HSI, £10 Vin = 0 to Veo. P3, P4, and to P2.1 - [ius TinputLsstagetoPono ‘|_| #3 | pA |Vw=Otoveo | [lj [inputHigh CurenttoEA | 400 A [Vy =2av | and to P2.6, P2.7 [ina | tnputLowGurenttoRESET | 3 | 2 | mA [Wy =045v | [we | input Low Current P2.2,P2.3,P24,READY [| {| -50_ | vA [Vu =045v___ | Pin Capacitance (Any Pin to Vs [| [10 | pF | frest = 1.0 MHz | NOTES: TXD, XD (in serial port mode 0), PWM, CLKOUT, ALE, BHE, RD, WR, and RESET and all pins of HSO and P3 and P4 when used as external memory bus (ADO-AD16). 2. low = 20 nA forall pine of Pl. for B26 and P27. lou = —200 wA for TXO, RXO fh sala port mode 0), PWM, CLKOUT, ALE, BHE, WR, and all pins of HSO and P3 and P4 when used as external memory bus (ADO-AD15). P3:and P4, when used as ports, have open-drain outputs. 6-64

INTEL CORP UP/PRPHLS L2E O | 4626175 0064731 T | intel , 809X-90, 839X-90 PRELIMINARY T-49-19-16 | A/D Converter operation is verified only on the Accuracy steeeteeeeeeneereeeaeree + £0,004 VREF section of these data sheets. Testing is done at 4 VREF = 5.120V. oo T-49-19-59 A.C. CHARACTERISTICS - (VCC, VPD = 4.5 to 5.5 Volts; Ta = 0°C to 70°C; fosc = 6.0 to 12.0 MHz) Test Conditions: Load Capacitance on Output Pins = 80 pF Oscillator Frequency = 12.00 MHz - TIMING REQUIREMENTS (Other system components must meet these specs.) [_“Symbot [" Parameter | Min [Max [units | | tovx | READYHoldafterCLkouTEdge [oo [Ts | | Tutyv | EndofALEtoREADYSetup | —Tose ‘(| atosc~eo | ins | | TLLYH | EndofALEtoREADYHigh | 2 Toso+40 "| 4Toso—c0t) | ns | TytyH | NonreadyTime | 000 =n | ravov | "Address ValidtoinputDetavaid [| | stoso-90 | ins | [_TRLDV |" AD/ActivetoInputDataVaid |_| Tosco [ns | TRXOx | DataHoldafterAD/inactve@ _ {| gf ns [“trxoz | AD/inactiveto input DataFloat@ [| Tose-20 [ns TIMING RESPONSES (MCS-96 parts meet these specs.) [—“symbor [Parameter Twin =] Max units | FXxTAL | OscillatorFrequency | 00 | 12.00 |_| |_Tosc | OscilatorPeiog | tt | tos STs | TOHCH | Oscillator HightoGLKOUTHigh® [| oT tao Tins | ToHoH | cikouTPeriog@ | aToso® | stosc® | ins | | tcc. | CLKOUTHighTime | Toso—20 | Toscx20 [ns | | Toh | CLKOUTLowtoALEHigh | 25 | go ns | | TiicH | ALELowtoGLKOUTHign | Tosc-20 | Tosc+40 | ns [ Tunut | ALEPulsewidth | Toso 25 | Tosc+15 [ns | [ TAVLL | Address SotuptoEndofale [| Tose—so_ [Tins | | TLtRL | End of ALEtORD/orWA/Actve [| Toso-20 | ns | | Titax | Address Hold AfterEndof ale | Tose-20 [| S| ns | twiwH | wa/Pulsowidth atoso-ag_ [ns | Towwx | OutputDataSetuptoendotwAy | 2tosc-eo | | ns | twxox | OutputDataHold AttorEndofwA/ | Toso-25_ | | ins | | TWxXtH | EndofWA/toNetALE | 2Toso—a0_ | Tn | TRLURH | RD/Pulsewisth | Toso—a9 [ns [_TRHLH | EndofAD/toNetale | Tosoma5_ | ns | NOTES: 1. If more than one wait state is desired, add STosc for each additional wait state. 2. This specification is not tested, but is verified by design analysis and/or derived from other tested parameters. 3. CLKOUT Is directly generated as a divide by 3 of the oscillator. The period will be STosc + 10 ns if Tosc is constant and the rise and fall times on XTAL 1 ara less than 10 ns. CLKOUT is not bonded out on 48-pin parts. . . 6-65

INTEL CORP UP/PRPHLS ize o Bf vaeei7s oonezae 1 : intel 809X-90, 839X-90 PRELIMINARY 7 —___ 49-19-16 WAVEFORM . _ T-49-19-59 1 ' ' 1 1 i. H H I reich ! . | cuxour Yo \\ : | Tene TCLLK . : ‘f Toure . neaov VY wo f ruck rome Tam ALE . =} — f= nuk ; PE mov Troe runt rw nou Wa s7001-8 Bus Signal Timings 6-66

Product Information

P8095-90 specifications and overview.

Summary

MCS-96 809X-90, 839X-90

Description

MCS-96 809X-90, 839X-90

Source title P8095-90 Datasheet(PDF) - Intel Corporation

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