P75N02LDG NIKOSEM | Alldatasheet

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Technical content

1 SEP-02-2004

N-Channel Logic Level Enhancement Mode Field Effect Transistor P75N02LDG TO-252 (DPAK) Lead-Free NIKO-SEM ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS SYMBOL LIMITS UNITS Gate-Source Voltage V GS ±20 V TC = 25 °C 75 Continuous Drain Current TC = 100 °C ID Pulsed Drain Current1 I DM 170 Avalanche Current I AR 60 A Avalanche Energy L = 0.1mH E AS 140 Repetitive Avalanche Energy2 L = 0.05mH E AR 5.6 mJ TC = 25 °C 60 Power Dissipation TC = 100 °C PD 32.75 W Operating Junction & Storage Temperature Range T j, Tstg -55 to 150 Lead Temperature (1/16” from case for 10 sec.) T L 275 THERMAL RESISTANCE RATINGS THERMAL RESISTANCE SYMBOL TYPICAL MAXIMUM UNITS Junction-to-Case RθJC 2.3 Junction-to-Ambient RθJA 62.5 Case-to-Heatsink RθCS 0.6 °C / W 1Pulse width limited by maximum junction temperature. 2Duty cycle ≤ 1％ ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted) LIMITS PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT STATIC Drain-Source Breakdown Voltage V (BR)DSS VGS = 0V, ID = 250µA 25 Gate Threshold Voltage V GS(th) VDS = VGS, ID = 250µA 1 1.5 3 V Gate-Body Leakage I GSS V DS = 0V, VGS = ±20V ±250 nA VDS = 20V, VGS = 0V 25 Zero Gate Voltage Drain Current I DSS VDS = 20V, VGS = 0V, TJ = 125 °C 250 µA 1. GATE 2. DRAIN 3. SOURCE PRODUCT SUMMARY V (BR)DSS R DS(ON) I D 25 5mΩ 75A G D S

2 SEP-02-2004

N-Channel Logic Level Enhancement Mode Field Effect Transistor P75N02LDG TO-252 (DPAK) Lead-Free NIKO-SEM On-State Drain Current1 I D(ON) V DS = 10V, VGS = 10V 70 A VGS = 10V, ID = 30A 5 7 Drain-Source On-State Resistance1 RDS(ON) VGS = 7V, ID = 24A 6 8 mΩ Forward Transconductance1 g fs V DS = 15V, ID = 30A 16 S DYNAMIC Input Capacitance C iss 5000 Output Capacitance C oss 1800 Reverse Transfer Capacitance C rss VGS = 0V, VDS = 15V, f = 1MHz 800 pF Total Gate Charge2 Q g 140 Gate-Source Charge2 Q gs 40 Gate-Drain Charge2 Q gd VDS = 0.5V(BR)DSS, VGS = 10V, ID = 35A 75 nC Turn-On Delay Time2 t d(on) 7 Rise Time2 t r VDS = 15V, RL = 1Ω 7 Turn-Off Delay Time2 t d(off) ID ≅ 30A, VGS = 10V, RGS = 2.5Ω 24 Fall Time2 t f 6 nS SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C) Continuous Current I S 75 Pulsed Current3 I SM 170 A Forward Voltage1 V SD I F = IS, VGS = 0V 1.3 V Reverse Recovery Time t rr 37 nS Peak Reverse Recovery Current I RM(REC) IF = IS, dlF/dt = 100A / µS 200 A Reverse Recovery Charge Q rr 0.043 µC 1Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2％. 2Independent of operating temperature. 3Pulse width limited by maximum junction temperature. REMARK: THE PRODUCT MARKED WITH “P75N02LDG”, DATE CODE or LOT # Orders for parts with Lead-Free plating can be placed using the PXXXXXXXG parts name.

3 SEP-02-2004

N-Channel Logic Level Enhancement Mode Field Effect Transistor P75N02LDG TO-252 (DPAK) Lead-Free NIKO-SEM TO-252 (DPAK) MECHANICAL DATA mm mm Dimension Min. Typ. Max. Dimension Min. Typ. Max. A 9.35 10.4 H 0.89 2.03 B 2.2 2.4 I 6.35 6.80 C 0.45 0.6 J 5.2 5.5 D 0.89 1.5 K 0.6 1 E 0.45 0.69 L 0.5 0.9 G 5.2 6.2 N G A H J I B C M L K D E F 13 2