P5C060-45

5C060 INTEL | Alldatasheet

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Technical content

22.2 MHz w/Feedback @ 100% Compatible with EP600

Figure 1. 5C060 Pin Configurations

The 5C060 can also be used as a direct, low-power chitecture of the device. Figure 2. 5C060 Global Architecture

intel ° 5C060 The 5CO60 PLD uses CMOS EPROM (floating gate) input or feedback paths available within the AND ar- cells as logic control elements instead of fuses. The ray. With these features, a wide variety of logic func- CMOS EPROM technology reduces power con- tions can be simultaneously implemented-alll on the sumption of PLDs to less than 20% of a comparable ‘same device. bipolar device without sacrificing speed perform- ance. In addition, Intel's advanced CMOS II-E EPROM process technology enables greater logic + =ARCHITECTURE DESCRIPTION densities to be achieved with superior speed and low-power performance over other comparable de- Externally, the 5CO60 has 4 dedicated data input vices. Intel's ELPDs add the benefits of “zero” pins, 16 I/O pins which may be configured for input, stand-by power not available on other programma- output, or bidirectional operations, and 2 synchro- ble logic devices. EPROM technology allows these nous clock inputs. The 5CO60 is contained in a devices to be 100% factory tested by programming _24-pin windowed package (0.3 inch wide) or 28-lead and erasing all the EPROM logic control elements. J-leaded chip carrier package, and contains 16 pro- grammable registers. The architecture of the 5C060 is based on the “Sum of Products” PLA (Programmable Logic Array) struc- The basic Macrocell architecture for the 5C060 is ture with a programmable AND array feeding into a shown in Figure 3. The 5CO60 has 16 of these Mac- fixed OR array. The device accommodates combina- _rocells (one for each I/O pin). The Macrocell is orga- 2 tional and sequential logic functions. A proprietary _nized in the familiar sum-of-products structure with a programmable |/O architecture provides individual © programmable AND array attached to a fixed OR selection of either combinatorial or registered output term. The inputs to the programmable AND array and feedback signals all with selectable polarity. originate from the true and complement signals from ‘each of the dedicated input pins and each of the I/O A feature unique to the 5C060 is the ability to individ- control blocks. The 40-input AND array of the 5CO60 ually program the output registers as a D-, T-, SR-, or feeds 160 AND gates (product terms) which are dis- JK-type Flip-Flop without sacrificing the utilization of tributed among the 16 available Macrocells within programmable AND logic. Additionally, each output that device. register can be individually clocked from any of the | 2-259

6 SS A SS |

Figure 3. 5CO60 Macrocell Architecture

The Macrocelis contain ten product terms total. Eight of the ten product terms (AND gates) are dedi, OUtPut Enable (OE)/Clock Selection cated for logic implementation. One product term on Two modes of operation are provided by the each Macrocell is used for RESET control to the OE/CLK Select Multiplexer as a part of each Macro- output register associated with the Macrocell. The cell. One mode provides for three-state butfering of final product term is used for OUTPUT ENABLE/ outputs while in the other mode, the outputs are al- Asynchronous Clock implementation. ways enabled. The operation of the OE/CLK Select Multiplexer sets the mode within a given Macrocell. Within the AND array, there is an EPROM connec- Therefore, the output mode can be selected individ- tion at every intersection of an input signal (true and —_ually on every output. Figure 4 illustrates the two complement) and a product term to a given Macro- modes of OE/CLK operation cell. Before programming an erased device, every EPROM connection is made at every intersection. But during the programming process, these connec- MODE 0: THREE-STATE BUFFERING tions are opened so that only the desired connec- tions remain. Therefore, the true or complement of Mode 0, the three-state output butter is controlled by a single product term originating from the AND any input signal can be connected to any product BY 8 Single product fer originating from the AND term. If both the true and complement connections 278Y- I ‘abled of any signal are lett intact a logical false results on _'® 8 logical true. Conversely, the output appears as the output of the AND gate. However, if both the true _high impedance when the product term is a logical °. 2 © false as shown in Table 1. In Mode 0, the Macrocell and complement connections are open, then a logic *{alse.as 8 fo 0, the Ms “don't care” results on the AND gate. Lastly, if all ip-Flop is connected to its associated synchronous ' clock (either CLK1 or CLK2 depending upon the the inputs of @ product term are programmed open, Mfacrocell's location within the device). Thus, the bd 8 logical true results on the output of the AND acrocell Flip-Flop may be clocked by its respective - synchronous clock but its output will not become The 5C060 has two dedicated clock inputs to pro- Valid until the output is enabled. vide synchronous clock signals to the internal regis- ters. Each of the clock signals controls half the total Table 1. Mode 0 Output Selection registers within the given device. For example, CLK1 Output Butter provides synchronous clocking to the registers in Macrocells inthe left half of the array wile CLK2 controls the registers associated with Macrocells in the right half of the array. The advanced I/O archi- tecture allows for any number of the registers to be synchronously clocked (from none to all). Both of — MODE 4: OUTPUT BUFFER ENABLED the dedicated clock inputs latch the data into a given register when triggered on a positive edge. In Mode 1, the Output Butter is always enabled. In addition, the Macrocell Flip-Flop is connected to the AND array. The Macrocell Flip-Flop may now be trig- MACROCELL ARCHITECTURE gered from an asynchronous clock signal generated SELECTION by the AND array logic to the OE/CLK multiplexable term. Mode 1 allows the Macrocell Flip-Flops to be The 5CO060 architecture provides each Macrocell individually clocked from any of the available signals with over 50 different possible I/O register configu- in the AND array. Since both true and complement rations. Each I/O pin can be configured for combina- values appear in the AND array, the Flip-Flop may torial or registered output (true or complement) with be clocked by any positive- or negative-going signals feedback. In addition, four different types of output at any input pin. Gated clock structures can be cre- ' registers can be implemented into every |/O pin ated since the Flip-Flop clock is created by a prod- without any additional logic requirements. The feed- uct term. back mechanism for each register back into the AND array can be programmed to provide for either registered feedback from the Macrocell or input Invert Select EPROM Bit feedback (treating the pin as an input). Another ad- vantage of the advanced I/O capability of the 5CO60 The Invert Select EPROM bit is used to invert the is the ability to individually clock each internal regis- product term input into the register. This applies to ter from asynchronous clock signals. all inputs including double inputs on the JK and SR registers | 2.261

170 PIN

Figure 4. Output Enable/Clock Configuration

REGISTER SELECTION When either a JK or SR register is configured, the eight product terms are shared among two OR The advanced I/O architecture of the 5CO60 allows gates (one for the J or S input and the other for four different register types along with combinatorial the K or R input). The allocation for these product output as illustrated in Figure 5a. The register types terms for each of the register inputs is optimized include a T, D, JK, or SR Flip-Flop and each Macro- by the PLDshell Plus software. cell 1/0 structure may be independently configured. In addition, all registers have an individual asynchro- nous RESET control from a dedicated product tem | OUTPUT/FEEDBACK derived in the AND array. When this dedicated prod- uct term is a logical one, the Macrocell register is | The Output Select Multiplexer allows for either regis- immediately cleared to a logical zero independent of ‘tered, combinatorial or no output. the register clock. The RESET function occurs auto- matically on power-up. The Feedback Select Multiplexer EPROM bit en- ables registered, 1/O (using the pin for bidirectional input or just input), or no feedback to the AND array. Output Register Confi: tp glster Configuration The Feedback Select is also important for building ‘The four different register types shown in Figure 5>- product terms with more than 8 products. The 8- 2 5e are described below. product product term of a Macrocell can be fed back into the AND array and combined with still more sig- D- or T-type Flip-Flops nals to create a much larger product term (of more than 8-inputs). In addition, if the feedback product When either a D- or T-type Flip-Flop is configured _term is not to be output, then the PLDshell Plus soft- as part of the I/O structure, all eight of the product _ware will reserve the associated Macrocell pin and terms into the Macrocell are ORed together and _ indicate it in the REPORT file. A reserved pin should fed into the register input. be left floating (no connect) when assembled onto a circuit board. JK or SR Registers Any I/O pin may be configured as a dedicated input by selecting no output and pin feedback through the: appropriate multiplexers. . 1/0 SELECTION [ourput/POLARITy | FEEDBACK | ‘Combinatorial/High | Pin, None Combinatorial/Low | Pin, None t ‘ { : A : i reioeace : . : Sater : ‘ H Hi : Hi Hi 200108-7 Figure Sa. Combinatorial 1/0 Configuration | 2-263

5060 intel. Erased-State Configuration FUNCTIONAL TESTING Prior to programming or after erasing, the I/O struc- Since the logical operation of the 5CO60 is ture is configured for combinatorial active low output —_controlled by EPROM elements, the device is com- with input (pin) feedback. pletely testable. Each programmable EPROM bit controlling the internal logic is tested using applica- tion-independent test program patterns. After test- ERASURE CHARACTERISTICS ing, the devices are erased before shipment to cus- tomers. No post-programming tests of the EPROM Erasure characteristics of the device are such that array are required. erasure begins to occur upon exposure to light with wavelengths shorter than approximately 4000A. It The testability and reliability of EPROM-based pro- should be noted that sunlight and certain types of grammable logic devices is an important feature flourescent lamps have wavelengths in the 3000A- over similar devices based on fuse technology. 40004. Data shows that constant exposure to room —_Fuse-based programmable logic devices require a level flourescent lighting could erase the typical de- user to perform post-programming tests to insure vice in approximately three years, while it would take proper programming. These tests must be done at approximately one week to cause erasure when ex- —_the device level because of the cummulative error Posed to direct sunlight. if the 5C060 is to be ex- effect. For example, a board containing ten devices Posed to these types of lighting conditions for ex- each possessing a 2% device fallout translates into tended periods of time, conductive opaque labels —_an 18% fallout at the board level (it should be noted should be placed over the device window to prevent that programming fallout of fuse-based programma- unintentional erasure. ble logic devices is typically 2% or higher). The recommended erasure procedure for the 5CO60 is exposure to shortwave ultraviolet light with a © DESIGN RECOMMENDATIONS wavelength of 2537A. The integrated dose (i.e., UV intensity x exposure time) for erasure should be a —_For proper operation, it is recommended that all in- minimum of fifteen (15) Wsec/cm?, The erasure put and output pins be constrained to the voltage time with this dosage is approximately 15 to 20 min- range GND < (Vin or Vout) < Voc. Unused inputs Utes using an ultraviolet lamp with a 12,000 zW/cm2 —_and I/Os should be tied to Voc or GND to minimize Power rating. The 5C060 should be placed within device power consumption. Reserved pins (as indi- ‘one inch of the lamp tubes during erasure. The maxi. _cated in the logic compiler REPORT file) should be mum integrated dose the 5C060 can be exposed to _eft floating (no connect) so that the pin can attain without damage is 7258 Wsec/em2 (1 week at the appropriate logic level. A power supply decou- 12,000 wW/cm2). Exposure to high intensity UV light pling capacitor of at least 0.2 4 F must be connected for longer periods may cause permanent damage to _ directly between Voc and GND pins of the device. the device. As with all CMOS devices, ESD handling procedures should be used with the 5C060 to prevent damage PROGRAMMING CHARACTERISTICS to the device during programming, assembly, and test. Initially, and after erasure, all the EPROM control bits of the 5CO60 are connected (in the “1” state). Each of the connected control bits are selectively DESIGN SECURITY disconnected by programming the EPROM celis into their “O” state. Programming voltage and waveform A single EPROM bit provides a programmable de- specifications are available by request from Intel to _sign security feature that controls the access to the support programming of the 5C060. data programmed into the device. If this bit is set, a proprietary design within the device cannot be cop- ied. This EPROM security bit enables a higher de- Intelligent Programming Algorithm gree of design security than fused-based devices ‘The 5C060 supports the intelligent Programming Al- gorithm which rapidly programs Intel ELPDs using an efficient and reliable method. The intelligent Pro- gramming Algorithm is particularly suited to the pro- duction programming environment. This method en- sures reliability as the incremental program margin of each bit is continually monitored to determine when the bit has been successfully programmed.

scoeo intel. Tools that support schematic capture and timing simulation for the 5CO60 are avaliable. Ploase refer. + ORDERING INFORMATION to the “Development Tools” section of the Program- Order Operating mable Logic Handbook. Code Range The 5C060 is also supported by third-party logic [osco6o-45 [cERDIP [Commercial compilers such as ABEL*, CUPL*, PLDesigner*, [pscoso-45 [PDIP | Log/IC*, etc. Programming support is provided by lpvcc_| third-party programmer companies such as Data PLoC 1/0, Logical Devices, STAG, etc, Please refer to the 23 |D5C060-55 [cerDIP | “Third-Party Support” lists in the Programmable Logic handbook for complete information and ven- [Pscososs [PDIP | dor contacts. N5C060-55 [45 | 22 | 26 [Fosc060.45|ceRDIP [industrial “Abel is a trademark of Data |/O, Corp. CUPL is a trademark of Logical Devices, inc. PLDesigner is a trademark of MINC, Inc. Log/IC is a trademark of ISDATA, Inc.

ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. [Symbol] Parameter__| Vottaget jee Me [me “WARNING: Stressing the device beyond the “Absolute ce < Maximum Ratings” may cause permanent damage. ia ‘Supply Voltaget? “Operating Conditions” is not recommended and ex- [vi [OCinpu votaget@7 |-05|vooros| V] ‘ended exposure beyond the “Oporatng Condions” [tug [Storage Tomperauxe |-e5| +150 [<0] 797 act devi rekebitty [ams [Ambien Temperature] —10] +65 | -0 | NOTES: 1. Voltages with respect to ground. ‘than 20 ns under no load conditions. 3. Under bias. Extended temperature versions are also available. RECOMMENDED OPERATING CONDITIONS y) [Symbol [Parameter [Min [Max] Unit ‘Supply Voltage [47s [525 TV Input Voltage [og [Vo | OutputVoitage Po Operating Temperature [OT #70 TC [ta | Input Rise Time [00s Lt) Input Fall Time [00 ns NOTE: 4. tp, te for CLK is 250 ns max. D.C. CHARACTERISTICS T, = 0°C to 70°C, Voc = 5.0V +5% [Symbol] Parameter [Conditions Min [Typ] Max _ [Unit] HIGH Level input Voltage | 20 [Voc + 08 HIGH Level Output Voltage [lo = —4.0 mA DC, Voc = Min. . faa{ | [vi LOW Level Output Voltage [Io = 4.0 mA DC, Voc = Min. [| [ o4 |v} [i __ Input Leakage Current Voc = Max., GND < Vin < Voc [| [ +100 [pal Output Leakage Curent [Von = Max..GNO <Vour <Voo |} | 2100 [ua] Output Short Circuit Current| Voc = Max., Vout = 0.5V | [2o{ 30 | maj Standby Current (Standby) [Voc = Max., Vin = Voc or GND [ [so] 100 | na] | 2-269

I D.C. CHARACTERISTICS Ty = 0°C to 70°C, Voc = 5.0V £5% (Continued) [Symboi[ Parameter [Conditions| Min | Typ | Max] Unit leo Power Supply Current Voc = Max., No Load, (Active) (Turbo Bit Off) | Vin = Voc or GND | Input Freq. = 1 MHz Device Prog. as 16-Bit Ctr. (See Ico vs. Freq. Graph.) : NOTES: 6. Io at CMOS levels (3.84V) = —2 mA. 7. Not more than 1 output should be tested at a time. Duration of that test must not exceed 1 second. 8. With Turbo Bit Off, device automatically enters ‘standby mode approximately 100 ns after last input transition. A.C. TESTING LOAD CIRCUIT A.C. TESTING INPUT, OUTPUT WAVEFORM wv 3.0 DEVICE | ‘To Test ° output SYSTEM 20019414 = AC. Testing: Inputs are Driven at 3.0 for a Logie “1” and OV for 290194-19 2 Logic "0". Timing Measurements are made at 2.0V for a Logic = 50 pF “'1" and 0.8V for a Logic "0" on inputs. Outputs are measured at £2 1.5V point. Device input rise and fall times. < 6 ns CAPACITANCE [‘symbo [Parameter | __CondWions | win | Typ | Mex [unt] A.C. CHARACTERISTICS T, = 0°C to 70°C, Voc = 5V +5%, Turbo Bit On(®) [__ bees To 5 s 0-55 Nratbe ’ EP600-3 EP600 Mode [ min | typ | Max | min | Typ | Max | [or [en [Comb ower [fo | | (| | ve poe | [woe [vo | comb.Ouipot | [as ||| s8 | +25 | ns | tor/O | Oupwtoisave | [| as | [| ss | +28 | ne | Asynch. Reset [QResot | | | «5 | | | s6 | +28 | ww | NOTES: 9. Typical Values are at Ta = 25°C, Voc = 5V, Active Mode. 10. tpzx and tpxz are measured at +0.5V from steady state voltage as driven by spec. output load. tpxz is measured with CL = Spr. 11, If device is operated with Turbo Bit Off (Non-Turbo Mode), and the device has been inactive for approx. 100 ns, increase time by amount shown. 2-270 |

SYNCHRONOUS CLOCK MODE A.C. CHARACTERISTIC Ta = 0°C to 70°C, Veg = 5.0V +5%, Turbo Bit On(9) ee ee 5C060-45 5C060-55 ‘oe EP600-3 EP600 Mode [wn [se [mx | [tye [a Max. Frequency (Pipelined) MHz (1/tgyu—No Feedback) font Max. Count Frequency 18.2 (1/tent—With Feedback) [tox [vosewwtimocix [| | | | | | +a fw | tont Register Output Feedback 45 +25 to Register Input—internal Path [tow [ecient fs [a | [tex —[eiktowrine fons [fats J ASYNCHRONOUS CLOCK MODE A.C. CHARACTERISTICS Ta = 0°C to 70°C, Voc = 5.0V +5%, Turbo Bit On(8) 5C060-45 5C060-55 Turbo EP600-3 EP600 Mode [ain [rye [ max wn [Te [wa | {ACNT Max. Count Frequency 18.2 (1/tacnt—With Feedback) tasu1 Input Setup Time to 10 +25 Asynch. Clock tasu2 1/0 Setup Time to 12 12 +25 Asynch. Clock Input or 1/O Hold After ns Asynch. Clock tacnT Register Output Feedback 45 +25 to Register Input—internal Path | 2-271

intel. SWITCHING WAVEFORMS COMBINATORIAL MODE , INPUT OR 1/0 INPUT R Yeo COMBINATORIAL OUTPUT | a (FROM REGISTER | HIGH IMPEDANCE TO OUTPUT) 3 STATE t— ox HIGH IMPEDANCE vaup ourpur ‘3=STATE tain ASYNICHRONOUSLY CLEAR OUTPUT (29019415 SYNCHRONOUS CLOCK MODE tox te CLK, CLK2 tsu-f—ty b teo (FROM REGISTER TO OUTPUT) VALID OUTPUT 200108-16 2-272 |

intel. so0ee SWITCHING WAVEFORMS (Continued) ASYNCHRONOUS CLOCK MODE ‘acH thou, asm si GD Gap Gap Gap usu a tan Le seo (now eaten y au oureut 9 5C060 5C060 Current in Relation to Frequency Current in Relation to Temperature 120 120 “AA ancosece! es EEE AH ed a bod 4euee weet icy o A a A 3 eLe = 1 = so Lee ae fore 3 offices | Bah *| § ot FSH po) 2o a ts Neo trbe co, a CEES

9 SCLCEET TT

tens (Mi) rene (©) Condiions:/T4 = 0°, Voc ~ 525 200104-18 Conditions: Veg = §:25V, TTL inputs 200108-19 5C060 Output Drive Current in Relation to Voltage 100 7 ff £ re ee ee F Pa an aN 3 set | TN or | a es es ep yy ots Yo Output Voitage (¥) Conditions: T, = 25°C 290194-20, | 2-273

scaen intel. SWITCHING WAVEFORMS (Continued) 5C060-45 tpp vs Capacitive Loading i i en Boom ee z ! : é i soor opr ope ver Cepectonce (290194-21 The 25c Wo Sov ‘One output switching: typical path 2-274 |