P5164SL

5164SL INTEL | Alldatasheet

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Technical content

Intel's 5164SL is a 8192-word by 8-bit CMOS static RAM fabricated using CMOS Silicon Gate process. mode that guarantees that data will remain valid at minimum Voc of 2.0V. Figure 1. Block Diagram

The 5164SL has three control inputs: Two Chip Se- puts. sition of CS;, low WE or high CS» and ends at the —_—_than single chip enable devices. Table 1. Mode Selection Truth Table

ABSOLUTE MAXIMUM RATINGS. NOTICE: This is a production data sheet. The specifi- Voltage on Any Pi cations are subject to change without notice. /oltage on Any Pin , 7 - “WARNING: Stressing the device beyond the “Absolute Relative to Ground (Vin, Vout) --.-.—9.3Vt07V — paximum Ratings” nay cause epsoute is “Operating Conditions” is not recommended and ex- Power Dissipation (Pp) «..+.s0secseerseeee OW oe ep entee are RECOMMENDED OPERATING CONDITIONS Voltage referenced to Vgg, Ta = 0°C to 70°C Suppyvotage | 45 | so | ss || | vss | Ground | oP OP InputHigh Votage | 22 | ~— | Vvoc+os | Vv | InputLowVottage | -os | — [| os | ov | NOTE: 1. During transitions, the inputs may undershoot to —3.5V for periods less than 20 ns. t CAPACITANCE Ty = 25°C, f = 1.0 MHz OuoikCpactance Waur= ov) | — |e | F _| NOTE: This parameter is sampled and not 100% tested, DC AND OPERATING CHARACTERISTICS . Recommended Operating Conditions unless otherwise noted [_Symbot | Parameter [min | typ* | Max | units | TestConditions | Operating Current CST = Vi. CS2 = Vin 1/0 Open, Voc = Max loce Dynamic Current 70 Toye = Min, Voc = Max 1/0 Open | tse | [ft fs | ma | GSI = Vinorcse = vil | [sto | | o2 | 2 [| ma | C8t2 Veo - o2v Standby rc | [na | Vin = Voc — 0.2V or Vin < 0.2V [sro | | o2 | 2 | ma | cse<Veo-o2v ef = [2 | 100 [na | Viv2 Veo = 02V orvin = 0.2 lu Input Load Current BA | Voc = Max Vin = GND to Voo lo Output Leakage HA | CST = Vin, CS2 = Vi Vout = Ground to Veo Outputtighvotage | 24 | — | — |v | ton=-1oma Ouputtowvotage | — | — [0a |v [im=aim | “Typ: Voc = SV, Ta = 25°C

DATA RETENTION ELECTRICAL CHARACTERISTICS Symbol | Parameter min | Typ | Max | Units | Test Conditions | Voor | VottagetorData Retention | 2 [ [ — [ov || Iccor Data Retention Current pA | CST 2 Voc — 0.2V, Voc = 3V Vin = Veo ~ 0.2V or Vin < 0.2V pA | CS2< 0.2V, Voc = 3V Vin 2 Voc — 0.2V or Vin < 0.2V tcpr Chip Deselect to Data Retention Time Lta___[ Operationecovery time | tact [ — | — [ons [| NOTES: 1. “tao = Read Cycle Time 2. Typ: Voc = 3V, Ta = 25°C DATA RETENTION WAVEFORM (No. 1) (CSi Controlled) DATA RETENTION MODE ' Yee tcor @S, BV 0.2V oy OY om 5 40570-3 DATA RETENTION WAVEFORM (No. 2) (CS2 Controlled) DATA RETENTION MODE Yoo tr es, ‘cor Vor= 2 Ve ie rns oe ooennnes C8) $0.2V

AC CHARACTERISTICS (READ CYCLE) Ta = 0°C to 70°C, Voc = 5V + 10% READ CYCLE smo | parame | ~ = toH Output Hold from ‘ Address Change toiz Chip Selection to. Output in Low Z* tonz Chip Deselection to Output in High Z* | toc | Outputnable access time [ss | Tins towz Output Enable to Output in Low Z tonz Output Disable to Output in High Z * _ *Timing parameters referenced to both GS1 and CS2.

TIMING DIAGRAMS (READ CYCLE) READ CYCLE 1(1,2,4) Sec Tent toe Dote Out KXXK bata vous > READ CYCLE 2(1.3, 4,6) ‘nest Sona teu out 240570-6 READ CYCLE 3(1,4,7) Sy a oa Cote Out 4056, READ CYCLE 4(1) Re deco ———— oe AAA ELYILTILILILLLL, tor ton: tou 3, (AMS cm VILAILILLELLLLL = A ese L777 \\ [| ANUANAAAAANIANAN vr oy Dote Out XK ota vais KX NOTES: 1. WE is high for READ cycle. 2. Device is continuously selected CST = Vy. and CS2 = Vin. 3. ones, valid prior to or coincident with oH transition low. 5. Transition is measured +500 mV from steady state. This parameter is sampled and not 100% tested. 6. CS2 is high. 7. CS1 is low.

AC CHARACTERISTICS (WRITE CYCLE) WRITE CYCLE | win [Max | we | Wiitecyctetime [too | Ts | ae End of Write Address Valid to End of Write [us| Aarne setdptine [| [we [wate Pus wean [ao [me [ “wa [ite Recovering [ss [me tow Data Valid to End of Write [er aoe ie] ' eee ‘Output in High Z tow Output Active from End of Write tonz Output Disable to Output in High Z TIMING DIAGRAMS (WRITE CYCLE) WRITE CYCLE 1(1) two: . Address CO) ‘wr (3) . ae &, AAAS LLILLVITLTLLL LL a |

082 WTTTTTLLXLLLT TLL LT F ANAANANAARAAY

‘wre (3) a n , we | WMA twuz (410) dots out AS) tow tow Dota In CX ota in voris RX XXXXXX 240570-8

TIMING DIAGRAMS (WRITE CYCLE) (Continued) WRITE CYCLE 2(1,6) two Aros C—O os, AAMAS ELLILILLLILLTT LLL

82 LILLILLLLLLLL LL NAAM

| twee (3) " ANNNNNANR: Dota out PIII K_X tow ton (9) bat (ssn vais RR 240870-10 ‘ NOTES: 1. WE must be high during address transitions. 2. A write occurs during the overlap (twp) of a low CS, a high CS, and a low WE. 3. tw is measured from the earl of CS or WE going high or CS going low to the end of write cycle. ‘4. During this period, 1/0 pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CS low transition or the CS high transition occurs simultaneously with the WE low transitions or after the WE transition, outputs remain in a high impedance state. 6. OE is continuously low (OE = Vi) 7. Dour is the same phase of write data of this write cycle. 8. Dy is the read data of next address. 9. 1S is low and CS is high during this period, /O pins aro in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured +500 mV from steady state. This parameter is sampled and not 100% tested. 11. tow is measured from the later of CS going low or CS going high to the end of write.