NH82801FBM

82801FB INTEL | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 786

Technical content

Datasheet sections

• 1 Introduction
• 1.2 Overview
• 2 Signal Description
• 2.1 Direct Media Interface (DMI) to Host Contro ller
• 2.2 PCI Express*
• 2.3 Link to LAN Connect
• 2.4 EEPROM Interface
• 2.5 Firmware Hub Interface
• 2.6 PCI Interface
• 2.7 Serial ATA Interface
• 2.8 IDE Interface
• 2.9 LPC Interface
• 2.10 Interrupt Interface
• 2.11 USB Interface
• 2.12 Power Management Interface
• 2.13 Processor Interface
• 2.14 SMBus Interface
• 2.15 System Management Interface
• 2.16 Real Time Clock Interface
• 2.17 Other Clocks
• 2.18 Miscellaneous Signals
• 2.19 AC ’97/Intel
• 2.20 General Purpose I/O
• 2.21 Power and Ground
• 2.22 Pin Straps
• 2.22.1 Functional Straps
• 2.22.2 External RTC Circuitry
• 2.22.3 Power Sequencing Requirements
• 2.22.3.1 V5REF / Vcc3_3 Sequencing Requ irements
• 2.22.3.4 Vcc1_5/V_Process or_IO Power Sequencing Requirements
• 3 Pin States
• 3.1 Integrated Pull-Ups and Pull-Downs
• 3.2 IDE Integrated Series Termination Resistor s
• 3.3 Output and I/O Signals Planes and States
• 3.4 Power Planes for Input Signals
• 4 System Clock Domains
• 5 Functional Description
• 5.1 PCI-to-PCI Bridge (D30:F0)
• 5.1.1 PCI Bus Interface
• 5.1.2 PCI Bridge As an Initiator
• 5.1.2.1 Memory Reads and Writes

Datasheet sections

• 4 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet
• 5.1.2.2 I/O Reads and Writes
• 5.1.2.3 Configuration Reads and Writes
• 5.1.2.4 Locked Cycles
• 5.1.2.5 Target / Master Aborts
• 5.1.2.6 Secondary Master Latency Timer
• 5.1.2.7 Dual Address Cycle (DAC)
• 5.1.2.8 Memory and I/O Decode to PCI
• 5.1.3 Parity Error Detection and Generation
• 5.1.4 PCIRST#
• 5.1.5 Peer Cycles
• 5.1.6 PCI-to-PCI Bridge Model
• 5.1.7 IDSEL to Device Number Mapping
• 5.1.8 Standard PCI Bus Configuration Mechani sm
• 5.2 PCI Express* Root Ports (D28:F0,F1,F2,F3)
• 5.2.1 Interrupt Generation
• 5.2.2 Power Management
• 5.2.2.1 S3/S4/S5 Support
• 5.2.2.2 Resuming from Suspended State
• 5.2.2.3 Device Initiated PM_PME Message
• 5.2.2.4 SMI/SCI Generation
• 5.2.3 SERR# Generation
• 5.2.4 Hot-Plug
• 5.2.4.1 Presence Detection
• 5.2.4.2 Message Generation
• 5.2.4.3 Attention Button Detection
• 5.2.4.4 SMI/SCI Generation
• 5.3 LAN Controller (B1:D8:F0)
• 5.3.1 LAN Controller PCI Bus Interface
• 5.3.1.1 Bus Slave Operation
• 5.3.1.2 CLKRUN# Signal (Mobile Only)
• 5.3.1.3 PCI Power Management
• 5.3.1.4 PCI Reset Signal
• 5.3.1.5 Wake-Up Events
• 5.3.1.6 Wake on LAN* (Preboot Wake-Up)
• 5.3.2 Serial EEPROM Interface
• 5.3.3 CSMA/CD Unit
• 5.3.3.1 Full Duplex
• 5.3.3.2 Flow Control
• 5.3.3.3 VLAN Support
• 5.3.4 Media Management Interface
• 5.3.5 TCO Functionality
• 5.3.5.1 Advanced TCO Mode
• 5.4 Alert Standard Format (ASF)
• 5.4.1 ASF Management Solution Features/Capabilities
• 5.4.2 ASF Hardware Support
• 5.4.2.2 EEPROM (256x16, 1 MHz)
• 5.4.2.3 Legacy Sensor SMBus Devices
• 5.4.2.4 Remote Control SMBus Devices
• 5.4.2.5 ASF Sensor SMBus Devices
• 5.4.3 ASF Software Support
• 5.5 LPC Bridge (w/ System an d Management Functions) (D31:F0)

Datasheet sections

• 5.5.1 LPC Interface
• 5.5.1.1 LPC Cycle Types
• 5.5.1.2 Start Field Definition
• 5.5.1.3 Cycle Type / Direction (CYCTYPE + DIR)
• 5.5.1.4 SIZE
• 5.5.1.5 SYNC
• 5.5.1.6 SYNC Time-Out
• 5.5.1.7 SYNC Error Indication
• 5.5.1.8 LFRAME# Usage
• 5.5.1.9 I/O Cycles
• 5.5.1.10 Bus Master Cycles
• 5.5.1.11 LPC Power Management
• 5.5.1.12 Configuration and Intel
• 5.6 DMA Operation (D31:F0)
• 5.6.1 Channel Priority
• 5.6.1.1 Fixed Priority
• 5.6.1.2 Rotating Priority
• 5.6.2 Address Compatibility Mode
• 5.6.3 Summary of DMA Transfer Sizes
• 5.6.3.1 Address Shifting When Programmed for 16-Bit
• 5.6.4 Autoinitialize
• 5.6.5 Software Commands
• 5.7 LPC DMA
• 5.7.1 Asserting DMA Requests
• 5.7.2 Abandoning DMA Requests
• 5.7.3 General Flow of DMA Transfers
• 5.7.4 Terminal Count
• 5.7.5 Verify Mode
• 5.7.6 DMA Request De-assertion
• 5.7.7 SYNC Field / LDRQ# Rules
• 5.8.1 Timer Programming
• 5.8.2 Reading from the Interval Timer
• 5.8.2.1 Simple Read
• 5.8.2.2 Counter Latch Command
• 5.8.2.3 Read Back Command
• 5.9.1 Interrupt Handling
• 5.9.1.1 Generating Interrupts
• 5.9.1.2 Acknowledging Interr upts
• 5.9.1.3 Hardware/Software Interrupt Sequence
• 5.9.2 Initialization Command Words (ICWx)
• 5.9.2.1 ICW1
• 5.9.2.2 ICW2
• 5.9.2.3 ICW3
• 5.9.2.4 ICW4
• 5.9.3 Operation Command Words (OCW)
• 5.9.4 Modes of Operation
• 5.9.4.1 Fully Nested Mode
• 5.9.4.2 Special Fully-Nested Mode
• 5.9.4.3 Automatic Rotation Mode (Equal Pr iority Devices)

Datasheet sections

• 6 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet
• 5.9.4.4 Specific Rotation Mode (Specific Priority)
• 5.9.4.5 Poll Mode
• 5.9.4.6 Cascade Mode
• 5.9.4.7 Edge and Level Triggered Mode
• 5.9.4.8 End of Interrupt (EOI) Operatio ns
• 5.9.4.9 Normal End of Interr upt
• 5.9.4.10 Automatic End of In terrupt Mode
• 5.9.5 Masking Interrupts
• 5.9.5.1 Masking on an Individual Interrupt Request
• 5.9.5.2 Special Mask Mode
• 5.9.6 Steering PCI Interrupts
• 5.10 Advanced Programmable Interrupt Controller
• 5.10.1 Interrupt Handling
• 5.10.2 Interrupt Mapping
• 5.10.3 PCI / PCI Express* Message-Based Inte rrupts
• 5.10.4 Front Side Bus Interrupt Delivery
• 5.10.4.1 Edge-Triggered Operation
• 5.10.4.2 Level-Triggered Operation
• 5.10.4.3 Registers Associated with Front Side Bus
• 5.10.4.4 Interrupt Message Format
• 5.11.1 Start Frame
• 5.11.2 Data Frames
• 5.11.3 Stop Frame
• 5.11.4 Specific Interrupts No t Supported via SERIRQ
• 5.11.5 Data Frame Format
• 5.12 Real Time Clock (D31:F0)
• 5.12.1 Update Cycles
• 5.12.3 Lockable RAM Ranges
• 5.12.4 Century Rollover
• 5.12.5 Clearing Battery-Backed RTC RAM
• 5.13 Processor Interface (D31:F0)
• 5.13.1 Processor Interface Signals
• 5.13.1.1 A20M# (Mask A20)
• 5.13.1.2 INIT# (Initialization)
• 5.13.1.3 FERR#/IGNNE# (Numeric Coprocessor Error /
• 5.13.1.4 NMI (Non-Maskable Interrupt)
• 5.13.1.5 Stop Clock Request and Processor Sleep
• 5.13.1.6 Processor Power Good (CPUPW RGOOD)
• 5.13.1.7 Deeper Sleep (DPSLP#) (Mobile Only)
• 5.13.2 Dual-Processor Issues (Desktop Only)
• 5.13.2.1 Signal Differences
• 5.13.2.2 Power Management
• 5.14 Power Management (D31:F0)
• 5.14.2 Intel
• 5.14.3 System Power Planes

Datasheet sections

• 5.14.4 SMI#/SCI Generation
• 5.14.4.1 PCI Express* SCI
• 5.14.4.2 PCI Express* Hot-Pl ug
• 5.14.5 Dynamic Processor Clock Control
• 5.14.5.1 Transition Rules among S0/Cx and Throttling States
• 5.14.5.2 Deferred C3/C4 (Mobile Only)
• 5.14.5.3 POPUP (Auto C3/C4 to C2) (Mobile Only)
• 5.14.5.4 POPDOWN (Auto C2 to C3/C4) (M obile Only)
• 5.14.6 Dynamic PCI Clock Contro l (Mobile Only)
• 5.14.6.1 Conditions for Checking the PC I Clock
• 5.14.6.2 Conditions for Maintaining the PCI Clock
• 5.14.6.3 Conditions for Stopping the PCI Clock
• 5.14.6.4 Conditions for Re-Starting the PCI Clock
• 5.14.6.5 LPC Devices and CLKRUN#
• 5.14.7 Sleep States
• 5.14.7.1 Sleep State Overview
• 5.14.7.2 Initiating Sleep State
• 5.14.7.3 Exiting Sleep States
• 5.14.7.4 PCI Express* WAKE # Signal and PME Event Message
• 5.14.7.5 Sx-G3-Sx, Ha ndling Power Failures
• 5.14.8 Thermal Management
• 5.14.8.1 THRM# Signal
• 5.14.8.2 Processor Initiated Passive Coo ling
• 5.14.8.3 THRM# Override Software Bit
• 5.14.8.4 Active Cooling
• 5.14.9 Event Input Signals and Their Usage
• 5.14.9.1 PWRBTN# (Power Bu tton)
• 5.14.9.2 RI# (Ring Indicator)
• 5.14.9.3 PME# (PCI Power Management Ev ent)
• 5.14.9.4 SYS_RESET# Signal
• 5.14.9.5 THRMTRIP# Signal
• 5.14.9.6 BMBUSY# (Mob ile Only)
• 5.14.10 ALT Access Mode
• 5.14.10.1 Write Only Registers with Read Paths in ALT Access Mode
• 5.14.10.2 PIC Reserved Bits
• 5.14.10.3 Read Only Registers with Write Paths in ALT Access Mode
• 5.14.11 System Power Supplies, Planes, and Signals
• 5.14.11.1 Power Plane Control with SLP_S3#, SLP_S4# and SLP_S5#
• 5.14.11.2 SLP_S4# and Suspend-To-RAM Sequencing
• 5.14.11.3 PWROK Signal
• 5.14.11.4 CPUPWRGD Signal
• 5.14.11.5 VRMPWRGD Signal
• 5.14.11.6 BATLOW# (Battery Low) (Mobile Only)
• 5.14.11.7 Controlling Leakage and Power Consumption
• 5.14.12 Clock Generators
• 5.14.12.1 Clock Control Signals from Intel
• 5.14.13 Legacy Power Management Theory of Operation
• 5.14.13.1 APM Power Management (Desktop Only)
• 5.14.13.2 Mobile APM Power Management (Mobile Only)
• 5.15 System Management (D31:F0)
• 5.15.1 Theory of Operation

Datasheet sections

• 8 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet
• 5.15.1.1 Detecting a System Lockup
• 5.15.1.2 Handling an Intruder
• 5.15.1.3 Detecting Im proper Firmware Hub Programming
• 5.15.2 Heartbeat and Event Reporting via SM Bus
• 5.16 IDE Controller (D31:F1)
• 5.16.1 PIO Transfers
• 5.16.1.1 PIO IDE Timing Modes
• 5.16.1.2 IORDY Masking
• 5.16.1.3 PIO 32-Bit IDE Data Port Acce sses
• 5.16.1.4 PIO IDE Data Port Prefetching and Posting
• 5.16.2 Bus Master Function
• 5.16.2.1 Physical Region Descriptor Format
• 5.16.2.2 Bus Master IDE Timings
• 5.16.2.3 Interrupts
• 5.16.2.4 Bus Master IDE Operation
• 5.16.2.5 Error Conditions
• 5.16.3 Ultra ATA/100/66/33 Protocol
• 5.16.3.1 Operation
• 5.16.4 Ultra ATA/33/66/100 Timing
• 5.16.5 ATA Swap Bay
• 5.16.6 SMI Trapping
• 5.17 SATA Host Controller (D31:F2)
• 5.17.1 Theory of Operation
• 5.17.1.1 Standard ATA Emulation
• 5.17.2 SATA Swap Bay Support
• 5.17.3 Intel
• 5.17.3.1 Intel ® Application Accelerator RAID Option ROM
• 5.17.4 Power Management Operation
• 5.17.4.1 Power State Mappings
• 5.17.4.2 Power State Transitions
• 5.17.4.3 SMI Trapping (APM)
• 5.17.5 SATA LED
• 5.17.6 AHCI Operation
• 5.18 High Precision Event Timers
• 5.18.1 Timer Accuracy
• 5.18.2 Interrupt Mapping
• 5.18.4 Enabling the Timers
• 5.18.5 Interrupt Levels
• 5.18.6 Handling Interrupts
• 5.18.7 Issues Related to 64-Bit Timers with 32-Bit Processors
• 5.19 USB UHCI Host Controllers (D29:F0, F1, F2, and F3)
• 5.19.1 Data Structures in Main Memory
• 5.19.2 Data Transfers to/from Main Memory
• 5.19.3 Data Encoding and Bit Stuffing
• 5.19.4 Bus Protocol
• 5.19.4.1 Bit Ordering
• 5.19.4.2 SYNC Field
• 5.19.4.3 Packet Field Formats
• 5.19.4.4 Address Fields

Datasheet sections

• 5.19.4.5 Frame Number Field
• 5.19.4.6 Data Field
• 5.19.4.7 Cyclic Redundancy Check (CRC)
• 5.19.5 Packet Formats
• 5.19.6 USB Interrupts
• 5.19.6.1 Transaction-Based Interrupts
• 5.19.6.2 Non-Transaction Based Interrupts
• 5.19.7 USB Power Management
• 5.19.8 USB Legacy Keyboard Op eration
• 5.20 USB EHCI Host Controller (D29:F7)
• 5.20.1 EHC Initialization
• 5.20.1.1 BIOS Initialization
• 5.20.1.2 Driver Initialization
• 5.20.1.3 EHC Resets
• 5.20.2 Data Structures in Ma in Memory
• 5.20.4 Data Encoding and Bit Stuffing
• 5.20.5 Packet Formats
• 5.20.7.1 Pause Feature
• 5.20.7.2 Suspend Feature
• 5.20.7.3 ACPI Device States
• 5.20.7.4 ACPI System States
• 5.20.7.5 Mobile Consideratio ns
• 5.20.8 Interaction with UHCI Ho st Controllers
• 5.20.8.1 Port-Routing Logic
• 5.20.8.2 Device Connects
• 5.20.8.3 Device Disconnects
• 5.20.8.4 Effect of Resets on Port-Routing Logic
• 5.20.10.1 Theory of Operation
• 5.21 SMBus Controller (D31:F3)
• 5.21.1 Host Controller
• 5.21.1.1 Command Protocols
• 5.21.2 Bus Arbitration
• 5.21.3 Bus Timing
• 5.21.3.1 Clock Stretching
• 5.21.3.2 Bus Time Out (Intel
• 5.21.4 Interrupts / SM I#
• 5.21.5 SMBALERT#
• 5.21.6 SMBus CRC Generation and Checking
• 5.21.7 SMBus Slave Interface
• 5.21.7.1 Format of Slave Write Cycle
• 5.21.7.2 Format of Read Command
• 5.21.7.3 Format of Host Notify Command
• 5.22 AC ’97 Controller (Audio D30:F2, Modem D30:F3)
• 5.22.1 PCI Power Management
• 5.22.2 AC-Link Overview

Datasheet sections

• 10 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet
• 5.22.2.1 Register Access
• 5.22.3 AC-Link Low Power Mode
• 5.22.3.1 External Wake Event
• 5.22.4 AC ’97 Cold Reset
• 5.22.5 AC ’97 Warm Reset
• 5.22.6 Hardware Assist to Determine ACZ_SD IN Used Per Codec
• 5.23 Intel® High Definition Audio (D27:F0)
• 5.23.1 Link Protocol Overview
• 5.23.1.1 Frame Composition
• 5.23.2 Link Reset
• 5.23.3 Link Power Management
• 6 Register and Memory Mapping
• 6.1 PCI Devices and Functions
• 6.3 I/O Map
• 6.3.1 Fixed I/O Address Ranges
• 6.3.2 Variable I/O Decode Ranges
• 6.4 Memory Map
• 6.4.1 Boot-Block Update Scheme
• 7 Chipset Configur ation Registers
• 7.1 Chipset Configuration Registers (Memory Space)
• 7.1.1 VCH—Virtual Channel Capability Header Register
• 7.1.2 VCAP1—Virtual Channel Capability #1 Re gister
• 7.1.3 VCAP2—Virtual Channel Capability #2 Re gister
• 7.1.4 PVC—Port Virtual Channel Control Register
• 7.1.5 PVS—Port Virtual Channe l Status Register
• 7.1.6 V0CAP—Virtual Channel 0 Resource Capability Register
• 7.1.7 V0CTL—Virtual Channel 0 Resource Co ntrol Register
• 7.1.8 V0STS—Virtual Channel 0 Resource St atus Register
• 7.1.9 RCTCL—Root Complex Topology Capabilitie s List Register
• 7.1.10 ESD—Element Self Description Register
• 7.1.11 ULD—Upstream Link Descriptor Register
• 7.1.12 ULBA—Upstream Link Base Address Register
• 7.1.13 RP1D—Root Port 1 Descriptor Register
• 7.1.14 RP1BA—Root Port 1 Base Address Register
• 7.1.15 RP2D—Root Port 2 Descriptor Register
• 7.1.16 RP2BA—Root Port 2 Base Address Register
• 7.1.17 RP3D—Root Port 3 Descriptor Register
• 7.1.18 RP3BA—Root Port 3 Base Address Register
• 7.1.19 RP4D—Root Port 4 Descriptor Register
• 7.1.20 RP4BA—Root Port 4 Base Address Register
• 7.1.21 HDD—Intel
• 7.1.22 HDBA—Intel ® High Definition Audio Base Address Register
• 7.1.23 ILCL—Internal Link Capabilities List Register
• 7.1.24 LCAP—Link Capabilities Register
• 7.1.25 LCTL—Link Control Register
• 7.1.26 LSTS—Link Status Register
• 7.1.27 CSIR5—Chipset Initialization Register

Datasheet sections

• 7.1.28 CSIR6—Chipset Initializat ion Register
• 7.1.29 BCR—Backbone Configuration Register
• 7.1.30 RPC—Root Port Configuration Register
• 7.1.31 CSIR7—Chipset Initializat ion Register
• 7.1.32 TRSR—Trap Status Register
• 7.1.33 TRCR—Trapped Cycle Register
• 7.1.34 TWDR—Trapped Write Data Register
• 7.1.35 IOTRn—I/O Trap Register (0:3)
• 7.1.36 DMC—DMI Miscellaneous Control Regist er (Mobile Only)
• 7.1.37 CSCR1—Chipset Configuration Register
• 7.1.38 CSCR2—Chipset Configuration Register
• 7.1.39 PLLMC—PLL Miscellaneous Control Regi ster (Mobile Only)
• 7.1.40 TCTL—TCO Configuration Register
• 7.1.41 D31IP—Device 31 Interrupt Pin Register
• 7.1.42 D30IP—Device 30 Interrupt Pin Register
• 7.1.43 D29IP—Device 29 Interrupt Pin Register
• 7.1.44 D28IP—Device 28 Interrupt Pin Register
• 7.1.45 D27IP—Device 27 Interrupt Pin Register
• 7.1.46 D31IR—Device 31 Interrupt Route Register
• 7.1.47 D30IR—Device 30 Interrupt Route Register
• 7.1.48 D29IR—Device 29 Interrupt Route Register
• 7.1.49 D28IR—Device 28 Interrupt Route Register
• 7.1.50 D27IR—Device 27 Interrupt Route Register
• 7.1.51 OIC—Other Interrupt Control Register
• 7.1.52 RC—RTC Configuration Register
• 7.1.53 HPTC—High Precision Timer Configuration Register
• 7.1.54 GCS—General Control and Status Register
• 7.1.55 BUC—Backed Up Control Register
• 7.1.56 FD—Function Disable Register
• 7.1.57 CG—Clock Gating
• 7.1.58 CSIR1—Chipset Initializat ion Register
• 7.1.59 CSIR2—Chipset Initializat ion Register
• 7.1.60 CSIR3—Chipset Initializat ion Register
• 7.1.61 CSIR4—Chipset Initializat ion Register
• 8 LAN Controller Registers (B1:D8:F0)
• 8.1 PCI Configuration Registers
• 8.1.1 VID—Vendor Identification Register
• 8.1.2 DID—Device Identification Register
• 8.1.3 PCICMD—PCI Command Register
• 8.1.4 PCISTS—PCI Status Register
• 8.1.5 RID—Revision Identification Register

Datasheet sections

• 12 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet
• 8.1.6 SCC—Sub Class Code Register
• 8.1.7 BCC—Base-Class Code Register
• 8.1.8 CLS—Cache Line Size Register
• 8.1.9 PMLT—Primary Master Latency Timer Register
• 8.1.10 HEADTYP—Header Type Register
• 8.1.11 CSR_MEM_BASE — CS R Memory-Mapped Base
• 8.1.12 CSR_IO_BASE — CSR I/O-Mapped Base Address Register
• 8.1.13 SVID — Subsystem Vendor Identification
• 8.1.14 SID — Subsystem Identification
• 8.1.15 CAP_PTR — Capabilities Pointer
• 8.1.16 INT_LN — Interrupt Line Register
• 8.1.17 INT_PN — Interrupt Pin Register
• 8.1.18 MIN_GNT — Mini mum Grant Register
• 8.1.19 MAX_LAT — Maximum Latency Register
• 8.1.20 CAP_ID — Capability I dentification Register
• 8.1.21 NXT_PTR — Next Item Pointer
• 8.1.22 PM_CAP — Power Management Capabilities
• 8.1.23 PMCSR — Power Management Control/
• 8.1.24 PCIDATA — PCI Power Management Data Register
• 8.2 LAN Control / Status Registers (CSR)
• 8.2.1 SCB_STA—System Control Block Status Word Register
• 8.2.2 SCB_CMD—System Control Block Command Word
• 8.2.3 SCB_GENPNT—System Cont rol Block General Pointer
• 8.2.4 PORT—PORT Interface Register
• 8.2.5 EEPROM_CNTL—EEPROM Control Register
• 8.2.6 MDI_CNTL—Management Data Interface (MDI) Control

Datasheet sections

• 8.2.7 REC_DMA_BC—Receive DM A Byte Count Register
• 8.2.8 EREC_INTR—Early Receive Interrupt Register
• 8.2.9 FLOW_CNTL—Flow Control Register
• 8.2.10 PMDR—Power Management Driver Register
• 8.2.11 GENCNTL—General Control Register
• 8.2.12 GENSTA—General Status Register
• 8.2.13 SMB_PCI—SMB via PCI Register
• 8.2.14 Statistical Counters
• 8.3 ASF Configuration Registers
• 8.3.1 ASF_RID—ASF Revision Identification Register
• 8.3.2 SMB_CNTL—SMBus Control Register
• 8.3.3 ASF_CNTL—ASF Control Register
• 8.3.4 ASF_CNTL_EN—ASF Co ntrol Enable Register
• 8.3.5 ENABLE—Enable Register
• 8.3.6 APM—APM Register
• 8.3.7 WTIM_CONF—Watchdog Time r Configuration Register
• 8.3.8 HEART_TIM—Heartb eat Timer Register
• 8.3.9 RETRAN_INT—Retransmission Interval Register
• 8.3.10 RETRAN_PCL—Retrans mission Packet Count Limit
• 8.3.11 ASF_WTIM1—ASF Watchdog Timer 1 Register
• 8.3.12 ASF_WTIM2—ASF Watchdog Timer 2 Register
• 8.3.13 PET_SEQ1—PET Sequence 1 Register
• 8.3.14 PET_SEQ2—PET Sequence 2 Register
• 8.3.15 STA—Status Register
• 8.3.16 FOR_ACT—Forced Actions Register
• 8.3.17 RMCP_SNUM—RMCP Se quence Number Register

Datasheet sections

• 14 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet
• 8.3.18 SP_MODE—Special Modes Register
• 8.3.19 INPOLL_TCONF—Inter-Poll Timer Configuration Register
• 8.3.20 PHIST_CLR—Poll Hi story Clear Register
• 8.3.21 PMSK1—Polling Mask 1 Register
• 8.3.22 PMSK2—Polling Mask 2 Register
• 8.3.23 PMSK3—Polling Mask 3 Register
• 8.3.24 PMSK4—Polling Mask 4 Register
• 8.3.25 PMSK5—Polling Mask 5 Register
• 8.3.26 PMSK6—Polling Mask 6 Register
• 8.3.27 PMSK7—Polling Mask 7 Register
• 8.3.28 PMSK8—Polling Mask 8 Register
• 9 PCI-to-PCI Bridge Registers (D30:F0)
• 9.1 PCI Configuration Registers (D30:F0)
• 9.1.1 VID— Vendor Identification Register (PCI-PCI—D30:F0)
• 9.1.2 DID— Device Identification Register (PCI-PCI—D30:F0)
• 9.1.3 PCICMD—PCI Command (PCI-PCI—D30:F 0)
• 9.1.4 PSTS—PCI Status Register (PCI-PCI—D30:F0)
• 9.1.5 RID—Revision Identification Register (PCI-PCI—D30:F0)
• 9.1.6 CC—Class Code Register (PCI-PCI—D30:F0)
• 9.1.7 PMLT—Primary Master Latency Timer Register
• 9.1.8 HEADTYP—Header Type Register (PCI-PCI—D30:F0)
• 9.1.9 BNUM—Bus Number Register (PCI-PCI—D30:F0)
• 9.1.10 SMLT—Secondary Master Latency Timer Register
• 9.1.11 IOBASE_LIMIT—I/O Base and Limit Register
• 9.1.12 SECSTS—Secondary Status Register (PCI-PCI—D30:F0)
• 9.1.13 MEMBASE_LIMIT—Memory Base and Limit Register
• 9.1.14 PREF_MEM_BASE_LIMIT— Prefetchable Memory Base
• 9.1.15 PMBU32—Prefetchable Memory Base Upper 32 Bits
• 9.1.16 PMLU32—Prefetchable Memory Limit Upper 32 Bits
• 9.1.17 CAPP—Capability List Pointer Register (PCI-PCI—D30:F0)
• 9.1.18 INTR—Interrupt Information Register (PCI-PCI—D30:F0)

Datasheet sections

• 9.1.19 BCTRL—Bridge Control Register (PCI-PCI—D30:F0)
• 9.1.20 SPDH—Secondary PCI Device Hiding Register
• 9.1.21 PDPR—PCI Decode Policy Register
• 9.1.22 DTC—Delayed Transac tion Control Register
• 9.1.23 BPS—Bridge Propri etary Status Register
• 9.1.24 BPC—Bridge Policy Configuration Register
• 9.1.25 SVCAP—Subsystem Vendor Capability Register
• 9.1.26 SVID—Subsystem Vendor IDs Register (PCI-PCI—D30:F0)
• 10 LPC Interface Bridge Registers (D31:F0)
• 10.1 PCI Configuration Registers (LPC I/F—D31: F0)
• 10.1.1 VID—Vendor Identification Register (LPC I/F—D31:F0)
• 10.1.2 DID—Device Identification Register (LPC I/F—D31:F0)
• 10.1.3 PCICMD—PCI COMMAND Register (LPC I/F—D31:F0)
• 10.1.4 PCISTS—PCI Status Register (LPC I/ F—D31:F0)
• 10.1.5 RID—Revision Identification Register (LPC I/F—D31:F0)
• 10.1.6 PI—Programming Interface Register (L PC I/F—D31:F0)
• 10.1.7 SCC—Sub Class Code Register (LPC I/ F—D31:F0)
• 10.1.8 BCC—Base Class Code Register (LPC I/F—D31:F0)
• 10.1.9 PLT—Primary Latency Ti mer Register (LPC I/F—D31:F0)
• 10.1.10 HEADTYP—Header Type Register (LPC I/F—D31:F0)
• 10.1.11 SS—Sub System Identifiers Register (LPC I/F—D31:F0)
• 10.1.12 PMBASE—ACPI Base Address Register (LPC I/F— D31:F0)
• 10.1.13 ACPI_CNTL—ACPI Control Register (L PC I/F — D31:F0)
• 10.1.14 GPIOBASE—GPIO Base Address Register (LPC I/F — D31:F0 )
• 10.1.15 GC—GPIO Control Register (LPC I/F — D31:F0)
• 10.1.16 PIRQ[n]_ROUT—PIRQ[A,B,C, D] Routing Control Register
• 10.1.17 SIRQ_CNTL—Serial IRQ Control Register
• 10.1.18 PIRQ[n]_ROUT—PIRQ[E,F,G, H] Routing Control Register
• 10.1.19 LPC_I/O_DEC—I/O Decode Ranges Register
• 10.1.20 LPC_EN—LPC I/F Enable s Register (LPC I/F—D31:F0)
• 10.1.21 GEN1_DEC—LPC I/F Generic Decode Range 1 Register
• 10.1.22 GEN2_DEC—LPC I/F Generic Decode Range 2 Register
• 10.1.23 FWH_SEL1—Firmware Hub Select 1 Register
• 10.1.24 FWH_SEL2—Firmware Hub Select 2 Register
• 10.1.25 FWH_DEC_EN1—Firmware Hub Decode Enable Register

Datasheet sections

• 16 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet
• 10.1.26 BIOS_CNTL—BIOS Control Register
• 10.1.27 RCBA—Root Complex Base Address Register
• 10.2 DMA I/O Registers (LPC I/F—D31:F0)
• 10.2.1 DMABASE_CA—DMA Base and Current Address
• 10.2.2 DMABASE_CC—DMA Ba se and Current Count Registers
• 10.2.3 DMAMEM_LP—DMA Memory Low Page Registers
• 10.2.4 DMACMD—DMA Command Register (LPC I/F—D31:F0)
• 10.2.5 DMASTA—DMA Status Register (LPC I/F—D31:F0)
• 10.2.6 DMA_WRSMSK—DMA Writ e Single Mask Register
• 10.2.7 DMACH_MODE—DMA Ch annel Mode Register
• 10.2.8 DMA Clear Byte Pointer Register (LPC I/F—D31:F0)
• 10.2.9 DMA Master Clear Regist er (LPC I/F—D31:F0)
• 10.2.10 DMA_CLMSK—DMA Clear Mask Register (LPC I/F—D31:F0)
• 10.2.11 DMA_WRMSK—DMA Write All Mask Register
• 10.3 Timer I/O Registers (LPC I/F—D31:F0)
• 10.3.1 TCW—Timer Control Word Register (L PC I/F—D31:F0)
• 10.3.2 SBYTE_FMT—Interval Timer Status Byte Format Register
• 10.3.3 Counter Access Ports Register (LPC I/ F—D31:F0)
• 10.4.1 Interrupt Controller I/O MAP (LPC I/F— D31:F0)
• 10.4.2 ICW1—Initialization Command Word 1 Register
• 10.4.3 ICW2—Initialization Command Word 2 Register
• 10.4.4 ICW3—Master Controlle r Initialization Command
• 10.4.5 ICW3—Slave Contro ller Initialization Command
• 10.4.6 ICW4—Initialization Command Word 4 Register
• 10.4.7 OCW1—Operational Control Word 1 (Interrupt Mask)
• 10.4.8 OCW2—Operational Control Word 2 Register
• 10.4.9 OCW3—Operational Control Word 3 Register
• 10.4.10 ELCR1—Master Controller Edge/Level Triggered Register
• 10.4.11 ELCR2—Slave Controller Edge/Level Triggered Register
• 10.5 Advanced Programmable Inte rrupt Controller (APIC)(D31:F0)
• 10.5.1 APIC Register Map (LPC I/F—D31:F0)

Datasheet sections

• 10.5.2 IND—Index Register (LPC I/F—D31:F0)
• 10.5.3 DAT—Data Register (LPC I/F—D31:F0)
• 10.5.4 EOIR—EOI Register (LPC I/F—D31:F0)
• 10.5.5 ID—Identification Register (LPC I/F—D 31:F0)
• 10.5.6 VER—Version Register (LPC I/F—D31:F0)
• 10.5.7 REDIR_TBL—Redirection Table (LPC I/F—D31:F0)
• 10.6 Real Time Clock Registers (LPC I/F—D31:F0 )
• 10.6.1 I/O Register Address Ma p (LPC I/F—D31:F0)
• 10.6.2 Indexed Registers (LPC I/F—D31:F0)
• 10.6.2.1 RTC_REGA—Register A (LPC I/F —D31:F0)
• 10.6.2.2 RTC_REGB—Register B (General Configuration)
• 10.6.2.3 RTC_REGC—Register C (Flag Register)
• 10.6.2.4 RTC_REGD—Register D (Flag Register)
• 10.7 Processor Interface Registers (LPC I/F—D3 1:F0)
• 10.7.1 NMI_SC—NMI Status and Control Register
• 10.7.2 NMI_EN—NMI Enable (a nd Real Time Clock Index)
• 10.7.3 PORT92—Fast A20 and Init Register (L PC I/F—D31:F0)
• 10.7.4 COPROC_ERR—Coprocessor Error Register
• 10.7.5 RST_CNT—Reset Co ntrol Register (LPC I/F—D31:F0)
• 10.8 Power Management Register s (PM—D31:F0)
• 10.8.1 Power Management PCI Configuration Registers
• 10.8.1.1 GEN_PMCON_1—General PM Configuration 1 Register
• 10.8.1.2 GEN_PMCON_2—General PM Configuration 2 Register
• 10.8.1.3 GEN_PMCON_3—General PM Configuration 3 Register
• 10.8.1.4 Cx-STATE_CNF—Cx State Configuration Register
• 10.8.1.5 C4-TIMING_CNT—C4 Timing Control Register
• 10.8.1.6 BM_BREAK_EN Register (PM—D 31:F0) (Mobile Only)
• 10.8.1.7 MSC_FUN—Miscellaneous Functionality Register
• 10.8.1.8 GPI_ROUT—GPI Ro uting Control Register
• 10.8.2 APM I/O Decode
• 10.8.2.1 APM_CNT—Advanced Power Management Control Port
• 10.8.2.2 APM_STS—Advanced Power Management Status Port
• 10.8.3 Power Management I/O Registers
• 10.8.3.1 PM1_STS—Powe r Management 1 Status Register
• 10.8.3.2 PM1_EN—Power M anagement 1 Enable Register
• 10.8.3.3 PM1_CNT—Power Management 1 C ontrol
• 10.8.3.4 PM1_TMR—Power Ma nagement 1 Timer Register

Datasheet sections

• 18 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet
• 10.8.3.5 PROC_CNT—Processo r Control Register
• 10.8.3.6 LV2 — Level 2 Register
• 10.8.3.7 LV3—Level 3 Regist er (Mobile Only)
• 10.8.3.8 LV4—Level 4 Regist er (Mobile Only)
• 10.8.3.9 PM2_CNT—Po wer Management 2 Control (Mobile Only)
• 10.8.3.10 GPE0_STS—Ge neral Purpose Event 0 Status Register
• 10.8.3.11 GPE0_EN—Gen eral Purpose Event 0 Enables Register
• 10.8.3.12 SMI_EN—SMI Control and Enable Register
• 10.8.3.13 SMI_STS—SMI Status Register
• 10.8.3.14 ALT_GP_SMI_EN—Alt ernate GPI SMI Enable Register
• 10.8.3.15 ALT_GP_SMI_STS—Al ternate GPI SMI Status Register
• 10.8.3.16 DEVACT_STS — Device Activity St atus Register
• 10.8.3.17 SS_CNT— Intel SpeedStep® Technology
• 10.8.3.18 C3_RES— C3 Residency Register (Mobile Only)
• 10.9 System Management TCO Regi sters (D31:F0)
• 10.9.1 TCO_RLD—TCO Timer Rel oad and Current Value Register
• 10.9.2 TCO_DAT_IN—TCO Data In Register
• 10.9.3 TCO_DAT_OUT—TCO Data Out Register
• 10.9.4 TCO1_STS—TCO1 Status Register
• 10.9.5 TCO2_STS—TCO2 Status Register
• 10.9.6 TCO1_CNT—TCO1 Control Register
• 10.9.7 TCO2_CNT—TCO2 Control Register
• 10.9.8 TCO_MESSAGE1 and TCO_ MESSAGE2 Registers
• 10.9.9 TCO_WDCNT—TCO Watchdog Control Re gister
• 10.9.10 SW_IRQ_GEN—Software IR Q Generation Register
• 10.9.11 TCO_TMR—TCO Timer In itial Value Register
• 10.10 General Purpose I/O Registers (D31:F0)
• 10.10.1 GPIO Register I/O Address Map
• 10.10.2 GPIO_USE_SEL—GPIO Use Select Register
• 10.10.3 GP_IO_SEL—GPIO Input/ Output Select Register
• 10.10.4 GP_LVL—GPIO Leve l for Input or Output Register
• 10.10.5 GPO_BLINK—GPO Blink Enable Regist er
• 10.10.6 GPI_INV—GPIO Signal Invert Register
• 10.10.7 GPIO_USE_SEL2—GPIO Us e Select 2 Register[63:32]
• 10.10.8 GP_IO_SEL2—GPIO Inpu t/Output Select 2 Register[63:32]
• 10.10.9 GP_LVL2—GPIO Level for Input or Output 2 Register[63:32]
• 11 IDE Controller Registers (D31:F1)
• 11.1 PCI Configuration Registers (IDE—D31:F1)
• 11.1.1 VID—Vendor Identificati on Register (IDE—D31:F1)
• 11.1.2 DID—Device Identification Register (IDE—D31:F1)
• 11.1.3 PCICMD—PCI Command Register (IDE —D31:F1)
• 11.1.4 PCISTS — PCI Status Register (IDE —D31:F1)
• 11.1.5 RID—Revision Identificati on Register (IDE—D31:F1)
• 11.1.6 PI—Programming Interface Register (IDE—D31:F1)
• 11.1.7 SCC—Sub Class Code Register (IDE—D 31:F1)
• 11.1.8 BCC—Base Class Code Register (IDE—D31:F1)
• 11.1.9 CLS—Cache Line Size Register (IDE—D 31:F1)
• 11.1.10 PMLT—Primary Master Latency Timer Register

Datasheet sections

• 11.1.11 PCMD_BAR—Primary Co mmand Block Base Address
• 11.1.12 PCNL_BAR—Primary Co ntrol Block Base Address
• 11.1.13 SCMD_BAR—Secondary Co mmand Block Base Address
• 11.1.14 SCNL_BAR—Secondary Control Block Base Address
• 11.1.15 BM_BASE — Bus Master Base Address Register
• 11.1.16 IDE_SVID — Subsystem Vendor Identification
• 11.1.17 IDE_SID — Subsystem Identification Register
• 11.1.18 INTR_LN—Interrupt Line Register (IDE—D31:F1)
• 11.1.19 INTR_PN—Interrupt Pin Register (I DE—D31:F1)
• 11.1.20 IDE_TIMP — IDE Primar y Timing Register (IDE—D31:F1)
• 11.1.21 IDE_TIMS — IDE Secondary Timing Register
• 11.1.22 SLV_IDETIM—Slave (Drive 1) IDE Timing Register
• 11.1.23 SDMA_CNT—Synchronous DMA Control Register
• 11.1.24 SDMA_TIM—Synchronous DMA Timing Register
• 11.1.25 IDE_CONFIG—IDE I/O Configuration Register
• 11.1.26 ATC—APM Trapping Control Register (IDE—D31:F1)
• 11.1.27 ATS—APM Trapping Status Register (IDE—D31:F1)
• 11.2 Bus Master IDE I/O Registers (IDE—D31:F1)
• 11.2.1 BMICP—Bus Master IDE Command Register
• 11.2.2 BMISP—Bus Master IDE Status Regist er (IDE—D31:F1)
• 11.2.3 BMIDP—Bus Master IDE De scriptor Table Pointer Register
• 12 SATA Controller Registers (D31:F2)
• 12.1 PCI Configuration Register s (SATA–D31:F2)
• 12.1.1 VID—Vendor Identificat ion Register (SATA—D31:F2)
• 12.1.2 DID—Device Identification Register (SATA—D31:F2)
• 12.1.3 PCICMD—PCI Command Register (SATA– D31:F2)
• 12.1.4 PCISTS — PCI Status Register (SATA– D31:F2)
• 12.1.5 RID—Revision Identification Register (SATA—D31:F2)
• 12.1.6 PI—Programming Interface Register (S ATA–D31:F2)
• 12.1.6.1 When Sub Class Code Register (D31:F2:Offset 0Ah) = 01h
• 12.1.6.2 When Sub Class Code Register (D31:F2:Offset 0Ah) = 04h
• 12.1.6.3 When Sub Class Code Register (D31:F2:Offset 0Ah) = 06h
• 12.1.7 SCC—Sub Class Code Regi ster (SATA–D31:F2)
• 12.1.8 BCC—Base Class Code Register
• 12.1.9 PMLT—Primary Master Latency Timer Register

Datasheet sections

• 20 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet
• 12.1.10 PCMD_BAR—Primary Co mmand Block Base Address
• 12.1.11 PCNL_BAR—Primary Contro l Block Base Address Register
• 12.1.12 SCMD_BAR—Secondary Command Block Base Address
• 12.1.13 SCNL_BAR—Secondary Control Block Base Address
• 12.1.14 BAR — Legacy Bus Master Base Address Register
• 12.1.15 ABAR — AHCI Ba se Address Register
• 12.1.15.1 Intel® ICH6 Only
• 12.1.15.2 Intel® ICH6R / ICH6-M Only
• 12.1.16 SVID—Subsystem Vendor Identification Register
• 12.1.17 SID—Subsystem Identification Regist er (SATA–D31:F2)
• 12.1.18 CAP—Capabilities Pointer Register (SAT A–D31:F2)
• 12.1.19 INT_LN—Inte rrupt Line Register (SATA–D31:F2)
• 12.1.20 INT_PN—Interrupt Pin Register (SATA– D31:F2)
• 12.1.21 IDE_TIM — IDE Timing Register (SAT A–D31:F2)
• 12.1.22 SIDETIM—Slave IDE Timing Register (SATA–D31:F2)
• 12.1.23 SDMA_CNT—Synchronous DMA Control Register
• 12.1.24 SDMA_TIM—Synchronous DMA Timing Register
• 12.1.25 IDE_CONFIG—IDE I/O Configuration Register
• 12.1.26 PID—PCI Power Manageme nt Capability Identification
• 12.1.27 PC—PCI Power Managem ent Capabilities Register
• 12.1.28 PMCS—PCI Power Management Control and Status
• 12.1.29 MAP—Address Map Regist er (SATA–D31:F2)
• 12.1.30 PCS—Port Control and Status Regist er (SATA–D31:F2)
• 12.1.31 SIR - SATA Initialization Register
• 12.1.32 SIRI—SATA Indexed Registers Index
• 12.1.33 STRD—SATA Indexed Register Data
• 12.1.34 STTT1—SATA Indexed Registers Index 00h
• 12.1.35 SIR18—SATA Indexed Registers Index 18h
• 12.1.36 STME—SATA Indexed Registers Index 1Ch
• 12.1.37 SIR28—SATA Indexed Registers Index 28h
• 12.1.38 STTT2—SATA Indexed Registers Index 74h
• 12.1.39 SIR84—SATA Indexed Registers Index 84h
• 12.1.40 ATC—APM Trapping Control Register (SATA–D31:F2)

Datasheet sections

• 12.1.41 ATS—APM Trapping Status Register (SATA–D31:F2)
• 12.1.42 SP—Scratch Pad Register (SATA–D31: F2)
• 12.1.43 BFCS—BIST FIS Control/ Status Register (SATA–D31:F2)
• 12.1.44 BFTD1—BIST FIS Transmit Data1 Regist er (SATA–D31:F2)
• 12.1.45 BFTD2—BIST FIS Transmit Data2 Regist er (SATA–D31:F2)
• 12.2 Bus Master IDE I/O Registers (D31:F2)
• 12.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F2)
• 12.2.2 BMIS[P,S]—Bus Master IDE Status Regi ster (D31:F2)
• 12.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer
• 12.3.1 AHCI Generic Host Control Registers (D31:F2)
• 12.3.1.1 CAP—Host Capabilities Register (D31:F2)
• 12.3.1.2 GHC—Global ICH6 Control Regist er (D31:F2)
• 12.3.1.3 IS—Interrupt Status Register (D31:F2)
• 12.3.1.4 PI—Ports Implemented Register (D31:F2)
• 12.3.1.5 VS—AHCI Version (D31:F2)
• 12.3.2 Port Registers (D31:F2)
• 12.3.2.1 PxCLB—Port [3 :0] Command List Base Address Register
• 12.3.2.2 PxCLBU—Port [3:0] Command List Base Address Upper
• 12.3.2.3 PxFB—Port [3:0] FI S Base Address Register (D31:F2)
• 12.3.2.4 PxFBU—Port [3:0] FI S Base Address Upper 32-Bits
• 12.3.2.5 PxIS—Port [3:0] Inte rrupt Status Register (D31:F2)
• 12.3.2.6 PxIE—Port [3:0] In terrupt Enable Register (D31:F2)
• 12.3.2.7 PxCMD—Port [3:0] Command Regi ster (D31:F2)
• 12.3.2.8 PxTFD—Port [3:0] Task File Data Register (D31:F2)
• 12.3.2.9 PxSIG—Port [3:0] Si gnature Register (D31:F2)
• 12.3.2.10 PxSSTS—Port [3:0] Serial ATA Status Register (D31:F2)
• 12.3.2.11 PxSCTL—Port [3:0] Serial ATA Control Register (D31:F2)
• 12.3.2.12 PxSERR—Port [3:0] Serial ATA Error Register (D31:F2)
• 12.3.2.13 PxSACT—Port [3:0] Serial ATA Active (D31:F2)
• 12.3.2.14 PxCI—Port [3:0] Command Issue Register (D31:F2)
• 13 UHCI Controllers Registers
• 13.1 PCI Configuration Registers
• 13.1.1 VID—Vendor Identification Register
• 13.1.2 DID—Device Identification Register
• 13.1.3 PCICMD—PCI Command Register (USB—D29:F0/F1/F2/F3)
• 13.1.4 PCISTS—PCI Status Register (USB—D2 9:F0/F1/F2/F3)
• 13.1.5 RID—Revision Identification Register
• 13.1.6 PI—Programming Interface Register
• 13.1.7 SCC—Sub Class Code Register
• 13.1.8 BCC—Base Class Code Register

Datasheet sections

• 22 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet
• 13.1.9 MLT—Master Latency Timer Register
• 13.1.10 HEADTYP—Header Type Register
• 13.1.11 BASE—Base Ad dress Register
• 13.1.12 SVID — Subsystem Vendo r Identification Register
• 13.1.13 SID — Subsystem Id entification Register
• 13.1.14 INT_LN—Interr upt Line Register
• 13.1.15 INT_PN—Interrupt Pin Register
• 13.1.16 USB_RELNUM—Serial Bus Release Number Register
• 13.1.17 USB_LEGKEY—USB Legacy Keyboard/Mouse Control
• 13.1.18 USB_RES—USB Resu me Enable Register
• 13.1.19 CWP—Core Well Policy Register
• 13.2 USB I/O Registers
• 13.2.1 USBCMD—USB Command Register
• 13.2.2 USBSTS—USB Status Regi ster
• 13.2.3 USBINTR—USB Interrupt Enable Register
• 13.2.4 FRNUM—Frame Number Re gister
• 13.2.5 FRBASEADD—Frame List Ba se Address Register
• 13.2.6 SOFMOD—Start of Frame Modify Regi ster
• 13.2.7 PORTSC[0,1]—Port Status and Control Register
• 14 EHCI Controller Registers (D29:F7)
• 14.1 USB EHCI Configuration Registers
• 14.1.1 VID—Vendor Iden tification Register
• 14.1.2 DID—Device Identification Register
• 14.1.3 PCICMD—PCI Command Register
• 14.1.4 PCISTS—PCI Status Register
• 14.1.5 RID—Revision Iden tification Register
• 14.1.6 PI—Programming Interface Register
• 14.1.7 SCC—Sub Class Code Register
• 14.1.8 BCC—Base Class Code Register
• 14.1.9 PMLT—Primary Master Latency Timer Register

Datasheet sections

• 14.1.10 MEM_BASE—Memory Ba se Address Register
• 14.1.11 SVID—USB EHCI Sub system Vendor ID Register
• 14.1.12 SID—USB EHCI Subsystem ID Register
• 14.1.13 CAP_PTR—Capabilit ies Pointer Register
• 14.1.14 INT_LN—Interrupt Line Register
• 14.1.15 INT_PN—Interr upt Pin Register
• 14.1.16 PWR_CAPID—PCI Powe r Management Capability ID
• 14.1.17 NXT_PTR1—Next Ite m Pointer #1 Register
• 14.1.18 PWR_CAP—Power Manage ment Capabilities Register
• 14.1.19 PWR_CNTL_STS—Power Management Control/Status
• 14.1.20 DEBUG_CAPID—Debug Po rt Capability ID Register
• 14.1.21 NXT_PTR2—Next Ite m Pointer #2 Register
• 14.1.22 DEBUG_BASE—Debug Port Base Offset Register
• 14.1.23 USB_RELNUM—USB Rele ase Number Register
• 14.1.24 FL_ADJ—Frame Length Adjustment Register
• 14.1.25 PWAKE_CAP—Port Wa ke Capability Register
• 14.1.26 LEG_EXT_CAP— USB EHCI Legacy Support Extended
• 14.1.27 LEG_EXT_CS— USB EHCI Legacy Support Extended
• 14.1.29 ACCESS_CNTL—Acces s Control Register
• 14.1.30 USB2IR—USB2 Init ialization Register
• 14.2 Memory-Mapped I/O Registers
• 14.2.1 Host Controller Capabilit y Registers
• 14.2.1.1 CAPLENGTH—Capability Register s Length Register
• 14.2.1.2 HCIVERSION—Host Contro ller Interface Version Number
• 14.2.1.3 HCSPARAMS—Host Co ntroller Structural Parameters
• 14.2.1.4 HCCPARAMS—Host Cont roller Capability Parameters
• 14.2.2 Host Controller Operatio nal Registers

Datasheet sections

• 24 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet
• 14.2.2.4 FRINDEX—Frame Index Register
• 14.2.2.5 CTRLDSSEGME NT—Control Data Structure Segment
• 14.2.2.6 PERIODICLISTBASE—Periodic Frame List Base Address
• 14.2.2.7 ASYNCLISTADDR—Current Asynchronous List Address
• 14.2.2.8 CONFIGFLAG—Configu re Flag Register
• 14.2.2.9 PORTSC—Port N Stat us and Control Register
• 14.2.3.1 CNTL_STS—Control/Status Regist er
• 14.2.3.2 USBPID—USB PIDs Re gister
• 14.2.3.3 DATABUF[7:0]—Data Buffer Bytes[7:0] Register
• 14.2.3.4 CONFIG—Configuration Register
• 15 SMBus Controller Registers (D31:F3)
• 15.1 PCI Configuration Registers (SMBus—D31:F3)
• 15.1.1 VID—Vendor Identifica tion Register (SMBus—D31:F3)
• 15.1.2 DID—Device Identification Register (SMBus—D31:F3)
• 15.1.3 PCICMD—PCI Command Register (SMB us—D31:F3)
• 15.1.4 PCISTS—PCI Status Register (SMBus—D31:F3)
• 15.1.5 RID—Revision Identification Register (SMBus—D31:F3)
• 15.1.6 PI—Programming Interface Register (SMBus—D31:F3)
• 15.1.7 SCC—Sub Class Code Register (SMB us—D31:F3)
• 15.1.8 BCC—Base Class Code Register (SMBus —D31:F3)
• 15.1.9 SMB_BASE—SMBus Ba se Address Register
• 15.1.10 SVID—Subsystem Vendor Identification Register
• 15.1.11 SID—Subsystem Identification Register
• 15.1.12 INT_LN—Inte rrupt Line Register (SMBus—D31:F 3)
• 15.1.13 INT_PN—Interrupt Pin Register (SMB us—D31:F3)
• 15.1.14 HOSTC—Host Configuration Register (SMBus—D31:F3)
• 15.2 SMBus I/O Registers
• 15.2.1 HST_STS—Host Status Register (SMBus—D31:F3)
• 15.2.2 HST_CNT—Host Control Register (S MBus—D31:F3)
• 15.2.3 HST_CMD—Host Command Register (SMBus—D31:F3)
• 15.2.4 XMIT_SLVA—Transmit Slave Address Register
• 15.2.5 HST_D0—Host Data 0 Register (SMB us—D31:F3)
• 15.2.6 HST_D1—Host Data 1 Register (SMB us—D31:F3)
• 15.2.7 Host_BLOCK_DB—Host Block Data Byte Register
• 15.2.8 PEC—Packet Error Check (PEC) Register
• 15.2.9 RCV_SLVA—Receive Slave Address Register
• 15.2.10 SLV_DATA—Receive Slav e Data Register (SMBus—D 31:F3)
• 15.2.11 AUX_STS—Auxiliary Status Register (SMBus—D31:F3)

Datasheet sections

• 15.2.12 AUX_CTL—Auxiliary Cont rol Register (SMBus—D31:F3)
• 15.2.13 SMLINK_PIN_CTL—SMLink Pin Control Register
• 15.2.14 SMBus_PIN_CTL—SMB us Pin Control Register
• 15.2.15 SLV_STS—Slave Status Register (S MBus—D31:F3)
• 15.2.16 SLV_CMD—Slave Comma nd Register (SMBus—D31:F3)
• 15.2.17 NOTIFY_DADDR—Notify Device Address Register
• 15.2.18 NOTIFY_DLOW—Notify Data Low Byte Register
• 15.2.19 NOTIFY_DHIGH—Notify Data High Byte Register
• 16 AC ’97 Audio Controlle r Registers (D30:F2)
• 16.1 AC ’97 Audio PCI Configuration Space
• 16.1.1 VID—Vendor Identificat ion Register (Audio—D30:F2)
• 16.1.2 DID—Device Identification Register (Audio—D30:F2)
• 16.1.3 PCICMD—PCI Command Register (Audio —D30:F2)
• 16.1.4 PCISTS—PCI Status Register (Audio —D30:F2)
• 16.1.5 RID—Revision Identification Register (Audio—D30:F2)
• 16.1.6 PI—Programming Interface Register (A udio—D30:F2)
• 16.1.7 SCC—Sub Class Code Register (Audio—D 30:F2)
• 16.1.8 BCC—Base Class Code Register (Audi o—D30:F2)
• 16.1.9 HEADTYP—Header Type Register (A udio—D30:F2)
• 16.1.10 NAMBAR—Native Audio Mixer Base Address Register
• 16.1.11 NABMBAR—Native Audio Bu s Mastering Base Address
• 16.1.12 MMBAR—Mixer Ba se Address Register (Audio—D3 0:F2)
• 16.1.13 MBBAR—Bus Master Base Address Register
• 16.1.14 SVID—Subsystem Vendor Identification Register
• 16.1.15 SID—Subsystem Identification Register (Audio—D30:F2)
• 16.1.16 CAP_PTR—Capabilities Po inter Register (Audio—D30:F2)
• 16.1.17 INT_LN—Interrupt Line Register (Aud io—D30:F2)
• 16.1.18 INT_PN—Interrup t Pin Register (Audio—D30:F2)
• 16.1.19 PCID—Programmable Codec Identification Register
• 16.1.20 CFG—Configuration Register (Audio—D 30:F2)
• 16.1.21 PID—PCI Power Manageme nt Capability Identification
• 16.1.22 PC—Power Management Capabilities Register
• 16.1.23 PCS—Power Management Control and Status Register
• 16.2 AC ’97 Audio I/O Space (D30:F2)

Datasheet sections

• 26 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet
• 16.2.8 GLOB_CNT—Global Contro l Register (Audio—D30:F2)
• 16.2.9 GLOB_STA—Global Status Register (Audio—D30:F2)
• 16.2.10 CAS—Codec Access Semaphore Register (Audio—D30:F2)
• 16.2.11 SDM—SDATA_IN Map Regi ster (Audio—D30:F2)
• 17 AC ’97 Modem Controller Registers (D30:F3)
• 17.1 AC ’97 Modem PCI Configuration Space (D30:F3)
• 17.1.1 VID—Vendor Identifica tion Register (Modem—D30:F3)
• 17.1.2 DID—Device Identification Register (Modem—D30:F3)
• 17.1.3 PCICMD—PCI Command Register (M odem—D30:F3)
• 17.1.4 PCISTS—PCI Status Register (Modem —D30:F3)
• 17.1.5 RID—Revision Identification Register (Modem—D30:F3)
• 17.1.6 PI—Programming Interface Register (Modem—D30:F3)
• 17.1.7 SCC—Sub Class Code Register (Mode m—D30:F3)
• 17.1.8 BCC—Base Class Code Register (Modem—D30:F3)
• 17.1.9 HEADTYP—Header Type Register (Modem—D30:F3)
• 17.1.10 MMBAR—Modem Mixer Base Address Register
• 17.1.11 MBAR—Modem Base Ad dress Register (Modem—D30 :F3)
• 17.1.12 SVID—Subsystem Vendor Identification Register
• 17.1.13 SID—Subsystem Identification Regist er (Modem—D30:F3)
• 17.1.14 CAP_PTR—Capabilities Po inter Register (Modem—D30:F3)
• 17.1.15 INT_LN—Inte rrupt Line Register (Modem—D30:F3 )
• 17.1.16 INT_PIN—Interrupt Pin Register (M odem—D30:F3)
• 17.1.17 PID—PCI Power Manageme nt Capability Identification
• 17.1.18 PC—Power Managemen t Capabilities Register
• 17.1.19 PCS—Power Management Control and Status Register
• 17.2 AC ’97 Modem I/O Space (D30:F3)
• 17.2.8 GLOB_CNT—Global Control Register (Modem—D30:F3)
• 17.2.9 GLOB_STA—Global Stat us Register (Modem—D30:F3)

Datasheet sections

• 17.2.10 CAS—Codec Access Semaphore Register
• 18 Intel ® High Definition Audio Controller Registers (D27:F0)
• 18.1 Intel ® High Definition Audio PCI Configuration Space
• 18.1.1 VID—Vendor Identification Register
• 18.1.2 DID—Device Identification Register
• 18.1.3 PCICMD—PCI Command Register
• 18.1.4 PCISTS—PCI Status Register
• 18.1.5 RID—Revision Identification Register
• 18.1.6 PI—Programming Interface Register
• 18.1.7 SCC—Sub Class Code Register
• 18.1.8 BCC—Base Class Code Register
• 18.1.9 CLS—Cache Line Size Register
• 18.1.10 LT—Latency Timer Register
• 18.1.11 HEADTYP—Header Type Register
• 18.1.12 HDBARL—Intel ® High Definition Audio Lower Base Address Register
• 18.1.13 HDBARU—Intel ® High Definition Audio Upper Base Address Register
• 18.1.14 SVID—Subsystem Vendor Identification Register
• 18.1.15 SID—Subsystem Identification Register
• 18.1.16 CAPPTR—Capabilities Poin ter Register (Audio—D30:F2 )
• 18.1.17 INTLN—Interrupt Line Register
• 18.1.18 INTPN—Interrupt Pin Register
• 18.1.19 HDCTL—Intel ® High Definition Audio Control Register
• 18.1.20 TCSEL—Traffic Cl ass Select Register
• 18.1.21 PID—PCI Power Manageme nt Capability ID Register
• 18.1.22 PC—Power Management Capabilities Register

Datasheet sections

• 28 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet
• 18.1.23 PCS—Power Management Control and Status Register
• 18.1.24 MID—MSI Cap ability ID Register
• 18.1.25 MMC—MSI Message Control Register
• 18.1.26 MMLA—MSI Message Lower Address Register
• 18.1.27 MMUA—MSI Message Upper Address Register
• 18.1.28 MMD—MSI Message Data Register
• 18.1.29 PXID—PCI Express* Capability ID Register
• 18.1.30 PXC—PCI Express* Capabilities Register
• 18.1.31 DEVCAP—Device Capabilities Register
• 18.1.32 DEVC—Device Control Register
• 18.1.33 DEVS—Device Status Register
• 18.1.34 VCCAP—Virtual Channel Enhanced Capability Header
• 18.1.35 PVCCAP1—Port VC Capability Register
• 18.1.36 PVCCAP2—Port VC Capability Register
• 18.1.37 PVCCTL—Port VC Control Register
• 18.1.38 PVCSTS—Port VC Status Register
• 18.1.39 VC0CAP—VC0 Resour ce Capability Register
• 18.1.40 VC0CTL—VC0 Resource Control Register
• 18.1.41 VC0STS—VC0 Reso urce Status Register
• 18.1.42 VCiCAP—VCi Resource Capability Register
• 18.1.43 VCiCTL—VCi Resour ce Control Register
• 18.1.44 VCiSTS—VCi Resour ce Status Register
• 18.1.45 RCCAP—Root Complex Link Declaration Enhanced
• 18.1.46 ESD—Element Self Description Register
• 18.1.47 L1DESC—Link 1 Description Register
• 18.1.48 L1ADDL—Link 1 Lower Address Register

Datasheet sections

• 18.1.49 L1ADDU—Link 1 Upper Address Register
• 18.2 Intel ® High Definition Audio Memory Mapped Configuration Registers
• 18.2.1 GCAP—Global Capabilities Register
• 18.2.2 VMIN—Minor Version Register
• 18.2.3 VMAJ—Major Version Register
• 18.2.4 OUTPAY—Output Payl oad Capability Register
• 18.2.5 INPAY—Input Payload Capability Register
• 18.2.6 GCTL—Global Control Register
• 18.2.7 WAKEEN—Wake Enable Register
• 18.2.8 STATESTS—State Change Status Register
• 18.2.9 GSTS—Global Status Register
• 18.2.10 INTCTL—Interrupt Control Register
• 18.2.11 INTSTS— Interrupt Status Register
• 18.2.12 WALCLK—Wall Clock Counter Register
• 18.2.13 SSYNC—Stream Sync hronization Register
• 18.2.14 CORBLBASE—CORB Lower Base Address Register
• 18.2.15 CORBUBASE—CORB Uppe r Base Address Register
• 18.2.16 CORBRP—CORB Wr ite Pointer Register
• 18.2.17 CORBRP—CORB Read Pointer Register
• 18.2.18 CORBCTL—CORB Control Register
• 18.2.19 CORBST—CORB Status Register
• 18.2.20 CORBSIZE—CORB Size Register
• 18.2.21 RIRBLBASE—RIRB Lowe r Base Address Register
• 18.2.22 RIRBUBASE—RIRB Upper Base Address Register
• 18.2.23 RIRBWP—RIRB Write Pointer Register
• 18.2.24 RINTCNT—Response In terrupt Count Register

Datasheet sections

• 30 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet
• 18.2.25 RIRBCTL—RIRB Control Register
• 18.2.26 RIRBSTS—RIRB Status Register
• 18.2.27 RIRBSIZE—RIRB Size Register
• 18.2.28 IC—Immediate Command Register
• 18.2.29 IR—Immediate Response Register
• 18.2.30 IRS—Immediate Command Status Register
• 18.2.31 DPLBASE—DMA Position Lowe r Base Address Register
• 18.2.32 DPUBASE—DMA Position Up per Base Address Register
• 18.2.33 SDCTL—Stream Descri ptor Control Register
• 18.2.34 SDSTS—Stream Descriptor Status Register
• 18.2.35 SDLPIB—Stream Descripto r Link Position in Buffer
• 18.2.36 SDCBL—Stream Descriptor Cy clic Buffer Length Register
• 18.2.37 SDLVI—Stream Descriptor Last Valid Index Register
• 18.2.38 SDFIFOW—Stream Descript or FIFO Watermark Register
• 18.2.39 SDFIFOS—Stream Descri ptor FIFO Size Register
• 18.2.40 SDFMT—Stream Descr iptor Format Register
• 18.2.41 SDBDPL—Stream Descriptor Buffer Descr iptor List Pointer Lower Base Address
• 18.2.42 SDBDPU—Stream Descriptor Buffer Descriptor List Pointer
• 19 PCI Express* Configuration Registers
• 19.1 PCI Express* Configuration Registers
• 19.1.1 VID—Vendor Iden tification Register
• 19.1.2 DID—Device Identification Register
• 19.1.3 PCICMD—PCI Command Register
• 19.1.4 PCISTS—PCI Status Register
• 19.1.5 RID—Revision Iden tification Register

Datasheet sections

• 19.1.6 PI—Programming Interface Register
• 19.1.7 SCC—Sub Class Code Register
• 19.1.8 BCC—Base Class Code Register
• 19.1.9 CLS—Cache Line Size Register
• 19.1.10 PLT—Primary Latency Timer Register
• 19.1.11 HEADTYP—Header Type Register
• 19.1.12 BNUM—Bus Nu mber Register
• 19.1.13 IOBL—I/O Base and Limit Register
• 19.1.14 SSTS—Secondar y Status Register
• 19.1.15 MBL—Memory Base and Limit Register
• 19.1.16 PMBL—Prefetchable Memory Base and Limit Register
• 19.1.17 PMBU32—Prefetchable Memory Base Upper 32 Bits
• 19.1.18 PMLU32—Prefetchable Memory Limit Upper 32 Bits
• 19.1.19 CAPP—Capabilities Li st Pointer Register
• 19.1.20 INTR—Interrupt Information Register
• 19.1.21 BCTRL—Bridge Control Register
• 19.1.22 CLIST—Capabilities List Register
• 19.1.23 XCAP—PCI Express* Capabilities Register
• 19.1.24 DCAP—Device Capabilities Register
• 19.1.25 DCTL—Device Control Register
• 19.1.26 DSTS—Device Status Register
• 19.1.27 LCAP—Link Capabilities Register
• 19.1.28 LCTL—Link Control Register
• 19.1.29 LSTS—Link Status Register
• 19.1.30 SLCAP—Slot Capabilities Register
• 19.1.31 SLCTL—Slot Control Register

Datasheet sections

• 32 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet
• 19.1.32 SLSTS—Slot Status Register
• 19.1.33 RCTL—Root Control Register
• 19.1.34 RSTS—Root Status Register
• 19.1.35 MID—Message Signaled In terrupt Identifiers Register
• 19.1.36 MC—Message Signaled Interrupt Message Control Register
• 19.1.37 MA—Message Signaled Interrupt Message Address
• 19.1.38 MD—Message Signaled Interrupt Message Data Register
• 19.1.39 SVCAP—Subsystem Vendor Capability Register
• 19.1.40 SVID—Subsystem Vendor Identification Register
• 19.1.41 PMCAP—Power Managem ent Capability Register
• 19.1.42 PMC—PCI Power Managem ent Capabilities Register
• 19.1.43 PMCS—PCI Power Management Control and Status
• 19.1.44 MPC—Miscellaneous Port Configuration Register
• 19.1.45 SMSCS—SMI/SCI Status Register
• 19.1.46 VCH—Virtual Channel Capability Header Register
• 19.1.47 VCAP2—Virtual Chan nel Capability 2 Register
• 19.1.48 PVC—Port Virtual Channel Control Register
• 19.1.49 PVS — Port Virtual Channel Status Register
• 19.1.50 V0CAP — Virtual Channel 0 Resource Capability Register
• 19.1.51 V0CTL — Virtual Channel 0 Resource Control Register
• 19.1.52 V0STS — Virtual Channel 0 Resource Status Register
• 19.1.53 UES — Uncorrectable Error Status Register
• 19.1.54 UEM — Uncorr ectable Error Mask
• 19.1.55 UEV — Uncorrecta ble Error Severity
• 19.1.56 CES — Correctable Error Status Register
• 19.1.57 CEM — Correctable Error Mask Register

Datasheet sections

• 19.1.58 AECC — Advanced Error Ca pabilities and Control Register
• 19.1.59 RES — Root Error Status Register
• 19.1.60 RCTCL — Root Complex To pology Capability List Register
• 19.1.61 ESD — Element Self Description Register
• 19.1.62 ULD — Upstream Link Description Register
• 19.1.63 ULBA — Upstream Link Base Address Register
• 19.1.64 PCIECR1 — PCI Expres s Configuration Register
• 19.1.65 PCIECR2 — PCI Expres s Configuration Register
• 20 High Precision Even t Timer Registers
• 20.1 Memory Mapped Registers
• 20.1.1 GCAP_ID—General Capabilities and Identification Register
• 20.1.2 GEN_CONF—General Conf iguration Register
• 20.1.3 GINTR_STA—Genera l Interrupt Status Register
• 20.1.4 MAIN_CNT—Main Counter Value Register
• 20.1.5 TIMn_CONF—Timer n Configuration and Capabilities Register
• 20.1.6 TIMn_COMP—Timer n Comp arator Value Register
• 21 Ballout Definition
• 22 Electrical Characteristics
• 22.1 Thermal Specifications
• 22.2 Absolute Maximum Ratings
• 22.3 DC Characteristics
• 22.4 AC Characteristics
• 22.5 Timing Diagrams
• 23 Package Information
• 24 Testability
• 24.1 XOR Chain Test Mode Description
• 24.1.1 XOR Chain Testability Algorithm Exampl e
• 24.2 XOR Chain Tables

Datasheet sections

• 34 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet
• 1 Desktop Configuration
• 2 Mobile Configuration

Datasheet sections

Datasheet sections

• 36 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

Datasheet sections

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• 38 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

Datasheet sections

Datasheet sections

• 40 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet
• 33 MHz

Datasheet sections

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• 42 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet For the Intel® 82801FB ICH6, 82801FR ICH6R and 82801FBM ICH6-M I/O Controller Hubs January 2005 Document Number: 301473-002

2 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY , OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® 82801FB ICH6, Intel® 82801FR ICH6R, and Intel® 82801FBM ICH6-M components may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I 2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM. Intel, Intel SpeedStep and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2004-2005, Intel Corporation

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 43 Introduction

1 Introduction

This document is intended for Original Equipment Manufacturers and BIOS vendors creating Intel® I/O Controller Hub 6 (ICH6) Family (ICH6, ICH6R, and ICH6-M) based products. This document is the datasheet for the following:

• Intel® 82801FB ICH6 (ICH6)
• Intel® 82801FR ICH6 RAID (ICH6R)
• Intel® 82801FBM ICH6 Mobile (ICH6-M) Note: Throughout this datasheet, ICH6 is used as a general ICH6 term and refers to the 82801FB ICH6, 82801FR ICH6R, and 82801FBM ICH6-M components, unless specifically noted otherwise. Note: Throughout this datasheet, the term “Desktop” refers to any implementation other than mobile, be it in a desktop, server, workstation, etc., unless specifically noted otherwise. The term “Mobile” refers to implementations using the Intel 82801FBM ICH6 Mobile (ICH6-M). This datasheet assumes a working knowledge of the vocabulary and principles of PCI Express*, USB, IDE, AHCI, SATA, Intel® High Definition Audio, AC ’97, SMBus, PCI, ACPI and LPC. Although some details of these features are described within this datasheet, refer to the individual industry specifications listed in Table 1-1 for the complete details. Table 1-1. Industry Specifications (Sheet 1 of 2) Specification Location PCI Express* Base Specification, Revision 1.0a http://www.pcisig.com/specifications Low Pin Count Interface Specification, Revision 1.1 (LPC) http://developer.intel.com/design/chipsets/ industry/lpc.htm Audio Codec ‘97 Component Specification, Version 2.3 (AC ’97) http://www.intel.com/labs/media/audio/ index.htm System Management Bus Specification, Version 2.0 (SMBus) http://www.smbus.org/specs/ PCI Local Bus Specification, Revision 2.3 (PCI) http://www.pcisig.com/specifications PCI Mobile Design Guide, Revision 1.1 http://www.pcisig.com/specifications PCI Power Management Specification, Revision 1.1 http://www.pcisig.com/specifications Universal Serial Bus Revision 2.0 Specification (USB) http://www.usb.org Advanced Configuration and Power Interface, Version 2.0 (ACPI) http://www.acpi.info/spec.htm Universal Host Controller Interface, Revision 1.1 (UHCI) http://developer.intel.com/design/USB/ UHCI11D.htm Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0 (EHCI) http://developer.intel.com/technology/usb/ ehcispec.htm Serial ATA Specification, Revision 1.0a http://www.serialata.org Serial ATA II: Extensions to Serial ATA 1.0, Revision 1.0 http://www.serialata.org

44 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

Chapter 1. Introduction Chapter 1 introduces the ICH6 and provides information on manual organization and gives a general overview of the ICH6. Chapter 2. Signal Description Chapter 2 provides a block diagram of the ICH6/ICH6-M and a detailed description of each signal. Signals are arranged according to interface and details are provided as to the drive characteristics (Input/Output, Open Drain, etc.) of all signals. Chapter 3. ICH6 Pin States Chapter 3 provides a complete list of signals, their associated power well, their logic level in each suspend state, and their logic level before and after reset. Chapter 4. System Clock Domains Chapter 4 provides a list of each clock domain associated with the ICH6 in an ICH6 based system. Chapter 5. Functional Description Chapter 5 provides a detailed description of the functions in the ICH6. All PCI buses, devices and functions in this document are abbreviated using the following nomenclature; Bus:Device:Function. This document abbreviates buses as B0 and B1, devices as D8, D27, D28, D29, D30 and D31 and functions as F0, F1, F2, F3, F4, F5, F6 and F7. For example Device 31 Function 0 is abbreviated as D31:F0, Bus 1 Device 8 Function 0 is abbreviated as B1:D8:F0. Generally, the bus number will not be used, and can be considered to be Bus 0. Note that the ICH6’s external PCI bus is typically Bus 1, but may be assigned a different number depending upon system configuration. Chapter 6. Register and Memory Mappings Chapter 6 provides an overview of the registers, fixed I/O ranges, variable I/O ranges and memory ranges decoded by the ICH6. Chapter 7. Chipset Configuration Registers Chapter 7 provides a detailed description of all registers and base functionality that is related to chipset configuration and not a specific interface (such as LPC, PCI, or PCI Express). It contains the root complex register block, which describes the behavior of the upstream internal link. Chapter 8. LAN Controller Registers Chapter 8 provides a detailed description of all registers that reside in the ICH6’s integrated LAN controller. The integrated LAN controller resides on the ICH6’s external PCI bus (typically Bus 1) at Device 8, Function 0 (B1:D8:F0). Chapter 9. PCI-to-PCI Bridge Registers Chapter 9 provides a detailed description of all registers that reside in the PCI-to-PCI bridge. This bridge resides at Device 30, Function 0 (D30:F0). Alert Standard Format Specification, Version 1.03 http://www.dmtf.org/standards/asf AT Attachment - 6 with Packet Interface (ATA/ATAPI - 6) http://T13.org (T13 1410D) IA-PC HPET (High Precision Event Timers) Specification, Revision 0.98a http://www.intel.com/labs/platcomp/hpet/ hpetspec.htm Table 1-1. Industry Specifications (Sheet 2 of 2) Specification Location

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 45 Introduction Chapter 10. LPC Bridge Registers Chapter 10 provides a detailed description of all registers that reside in the LPC bridge. This bridge resides at Device 31, Function 0 (D31:F0). This function contains registers for many different units within the ICH6 including DMA, Timers, Interrupts, Processor Interface, GPIO, Power Management, System Management and RTC. Chapter 11. IDE Controller Registers Chapter 11 provides a detailed description of all registers that reside in the IDE controller. This controller resides at Device 31, Function 1 (D31:F1). Chapter 12. SATA Controller Registers Chapter 12 provides a detailed description of all registers that reside in the SATA controller. This controller resides at Device 31, Function 2 (D31:F2). Chapter 13. UHCI Controller Registers Chapter 13 provides a detailed description of all registers that reside in the four UHCI host controllers. These controllers reside at Device 29, Functions 0, 1, 2, and 3 (D29:F0/F1/F2/F3). Chapter 14. EHCI Controller Registers Chapter 14 provides a detailed description of all registers that reside in the EHCI host controller. This controller resides at Device 29, Function 7 (D29:F7). Chapter 15. SMBus Controller Registers Chapter 15 provides a detailed description of all registers that reside in the SMBus controller. This controller resides at Device 31, Function 3 (D31:F3). Chapter 16. AC ’97 Audio Controller Registers Chapter 16 provides a detailed description of all registers that reside in the audio controller. This controller resides at Device 30, Function 2 (D30:F2). Note that this section of the EDS does not include the native audio mixer registers. Accesses to the mixer registers are forwarded over the AC-link to the codec where the registers reside. Chapter 17. AC ’97 Modem Controller Registers Chapter 17 provides a detailed description of all registers that reside in the modem controller. This controller resides at Device 30, Function 3 (D30:F3). Note that this section of the EDS does not include the modem mixer registers. Accesses to the mixer registers are forwarded over the AC-link to the codec where the registers reside. Chapter 18. Intel® High Definition Audio Controller Registers Chapter 18 provides a detailed description of all registers that reside in the Intel® High Definition Audio controller. This controller resides at Device 27, Function 0 (D27:F0). Chapter 19. PCI Express* Port Controller Registers Chapter 19 provides a detailed description of all registers that reside in the PCI Express controller. This controller resides at Device 28, Functions 0 to 3 (D30:F0-F3). Chapter 20. High Precision Event Timers Registers Chapter 20 provides a detailed description of all registers that reside in the multimedia timer memory mapped register space. Chapter 21. Ballout Definition Chapter 21 provides a table of each signal and its ball assignment in the 609-mBGA package. Chapter 22. Electrical Characteristics Chapter 22 provides all AC and DC characteristics including detailed timing diagrams.

46 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

Chapter 23. Package Information Chapter 23 provides drawings of the physical dimensions and characteristics of the 609-mBGA package. Chapter 24. Testability Chapter 24 provides detail about the implementation of test modes provided in the ICH6.

1.2 Overview

The ICH6 provides extensive I/O support. Functions and capabilities include:

• PCI Express* Base Specification, Revision 1.0a-compliant
• PCI Local Bus Specification, Revision 2.3-compliant with support for 33 MHz PCI operations (supports up to seven Req/Gnt pairs).
• ACPI Power Management Logic Support
• Enhanced DMA controller, interrupt controller, and timer functions
• Integrated Serial ATA host controller with independent DMA operation on four ports (ICH6/ICH6R only) or two ports (ICH6-M only) and AHCI support (ICH6R/ICH6-M only).
• Integrated IDE controller supports Ultra ATA100/66/33
• USB host interface with support for eight USB ports; four UHCI host controllers; one EHCI high-speed USB 2.0 Host controller
• Integrated LAN controller
• System Management Bus (SMBus) Specification, Version 2.0 with additional support for I2C devices
• Supports Audio Codec ’97, Revision 2.3 Specification (a.k.a., AC ’97 Component Specification, Revision 2.3) which provides a link for Audio and Telephony codecs (up to 7 channels)
• Supports Intel High Definition Audio
• Low Pin Count (LPC) interface
• Firmware Hub (FWH) interface support The ICH6 incorporates a variety of PCI functions that are divided into six logical devices (B0:D27, B0:D28, B0:D29, B0:D30, B0:D31 and B1:D8). D30 is the DMI-to-PCI bridge and the AC ’97 Audio and Modem controller functions, D31 contains the PCI-to-LPC bridge, IDE controller, SATA controller, and SMBus controller, D29 contains the four USB UHCI controllers and one USB EHCI controller, and D27 contains the PCI Express root ports. B1:D8 is the integrated LAN controller.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 47 Introduction The following sub-sections provide an overview of the ICH6 capabilities. Direct Media Interface (DMI) Direct Media Interface (DMI) is the chip-to-chip connection between the Memory Controller Hub / Graphics Memory Controller Hub ((G)MCH) and I/O Controller Hub 6 (ICH6). This high-speed interface integrates advanced priority-based servicing allowing for concurrent traffic and true isochronous transfer capabilities. Base functionality is completely software-transparent, permitting current and legacy software to operate normally. PCI Express* Interface The ICH6 provides 4 PCI Express root ports that are compliant to the PCI Express Base Specification, Revision 1.0a. The PCI Express root ports can be statically configured as four x1 ports or ganged together to form one x4 port (Enterprise applications only). Each Root Port supports 2.5 Gb/s bandwidth in each direction (5 Gb/s concurrent) and two virtual channels for full isochronous data support. Table 1-2. PCI Devices and Functions Bus:Device:Function Function Description Bus 0:Device 30:Function 0 PCI-to-PCI Bridge Bus 0:Device 30:Function 2 AC ’97 Audio Controller Bus 0:Device 30:Function 3 AC ’97 Modem Controller Bus 0:Device 31:Function 0 LPC Controller 1 NOTES: 1. The PCI-to-LPC bridge contains register s that control LPC, Power Management, System Management, GPIO, Processor Interface, RTC, Interrupts, Timers, and DMA. Bus 0:Device 31:Function 1 IDE Controller Bus 0:Device 31:Function 2 SATA Controller Bus 0:Device 31:Function 3 SMBus Controller Bus 0:Device 29:Function 0 USB UHCI Controller 1 Bus 0:Device 29:Function 1 USB UHCI Controller 2 Bus 0:Device 29:Function 2 USB UHCI Controller 3 Bus 0:Device 29:Function 3 USB UHCI Controller 4 Bus 0:Device 29:Function 7 USB 2.0 EHCI Controller Bus 0:Device 28:Function 0 PCI Express* Port 1 Bus 0:Device 28:Function 1 PCI Express Port 2 Bus 0:Device 28:Function 2 PCI Express Port 3 Bus 0:Device 28:Function 3 PCI Express Port 4 Bus 0:Device 27:Function 0 Intel High Definition Audio Controller Bus n:Device 8:Function 0 LAN Controller

48 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

Serial ATA (SATA) Controller The ICH6 has an integrated SATA host controller that supports independent DMA operation on four ports (desktop only) or two ports (mobile only) and supports data transfer rates of up to 1.5 Gb/s (150 MB/s). The SATA controller contains two modes of operation; a legacy mode using I/O space, and an AHCI mode using memory space (ICH6R/ICH6-M only). SATA and PATA can also be used in a combined function mode (where the SATA function is used with PATA). In this combined function mode, AHCI mode is not used. Software that uses legacy mode will not have AHCI capabilities. The ICH6 supports the Serial ATA Specification, Revision 1.0a. The ICH6 also supports several optional sections of the Serial ATA II: Extensions to Serial ATA 1.0 Specification, Revision 1.0 (AHCI support is required for some elements). AHCI (Intel® ICH6R/ICH6-M only) The ICH6R/ICH6-M provide hardware support for Advanced Host Controller Interface (AHCI), a new programming interface for SATA host controllers. Platforms supporting AHCI may take advantage of performance features such as no master/slave designation for SATA devices—each device is treated as a master—and hardware -assisted native command queuing. AHCI also provides usability enhancements (e.g., Hot-Plug). AHCI requires appropriate software support (e.g., an AHCI driver) and for some features, hardware support in the SATA device or additional platform hardware. PCI Interface The ICH6 PCI interface provides a 33 MHz, Revision 2.3 implementation. All PCI signals are 5 V tolerant, except PME#. The ICH6 integrates a PCI arbiter that supports up to seven external PCI bus masters in addition to the internal ICH6 requests. This allows for combinations of up to seven PCI down devices and PCI slots. IDE Interface (Bus Master Capability and Synchronous DMA Mode) The fast IDE interface supports up to two IDE devices providing an interface for IDE hard disks and ATAPI devices. Each IDE device can have independent timings. The IDE interface supports PIO IDE transfers up to 16 MB/sec and Ultra ATA transfers up 100 MB/sec. It does not consume any legacy DMA resources. The IDE interface integrates 16x32-bit buffers for optimal transfers. The ICH6’s IDE system contains a single, independent IDE signal channel that can be electrically isolated. There are integrated series resistors on the data and control lines (see Section 5.16 for details). Low Pin Count (LPC) Interface The ICH6 implements an LPC Interface as described in the LPC 1.1 specification. The Low Pin Count (LPC) bridge function of the ICH6 resides in PCI Device 31:Function 0. In addition to the LPC bridge interface function, D31:F0 contains other functional units including DMA, interrupt controllers, timers, power management, system management, GPIO, and RTC.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 49 Introduction Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller) The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-by-byte transfers, and channels 5–7 are hardwired to 16-bit, count-by-word transfers. Any two of the seven DMA channels can be programmed to support fast Type-F transfers. The ICH6 supports LPC DMA, which is similar to ISA DMA, through the ICH6’s DMA controller. LPC DMA is handled through the use of the LDRQ# lines from peripherals and special encoding on LAD[3:0] from the host. Single, Demand, Verify, and Increment modes are supported on the LPC interface. Channels 0–3 are 8-bit channels. Channels 5–7 are 16-bit channels. Channel 4 is reserved as a generic bus master request. The timer/counter block contains three counters that are equivalent in function to those found in one 82C54 programmable interval timer. These three counters are combined to provide the system timer function, and speaker tone. The 14.31818 MHz oscillator input provides the clock source for these three counters. The ICH6 provides an ISA-Compatible Programmable Interrupt Controller (PIC) that incorporates the functionality of two, 82C59 interrupt controllers. The two interrupt controllers are cascaded so that 14 external and two internal interrupts are possible. In addition, the ICH6 supports a serial interrupt scheme. All of the registers in these modules can be read and restored. This is required to save and restore system state after power has been removed and restored to the platform. Advanced Programmable Interrupt Controller (APIC) In addition to the standard ISA compatible Programmable Interrupt controller (PIC) described in the previous section, the ICH6 incorporates the Advanced Programmable Interrupt Controller (APIC). Universal Serial Bus (USB) Controller The ICH6 contains an Enhanced Host Controller Interface (EHCI) compliant host controller that supports USB high-speed signaling. High-speed USB 2.0 allows data transfers up to 480 Mb/s which is 40 times faster than full-speed USB. The ICH6 also contains four Universal Host Controller Interface (UHCI) controllers that support USB full-speed and low-speed signaling. The ICH6 supports eight USB 2.0 ports. All eight ports are high-speed, full-speed, and low-speed capable. ICH6’s port-routing logic determines whether a USB port is controlled by one of the UHCI controllers or by the EHCI controller. See Section 5.19 and Section 5.20 for details. LAN Controller The ICH6’s integrated LAN controller includes a 32-bit PCI controller that provides enhanced scatter-gather bus mastering capabilities and enables the LAN controller to perform high speed data transfers over the PCI bus. Its bus master capabilities enable the component to process high- level commands and perform multiple operations; this lowers processor utilization by off-loading communication tasks from the processor. Two large transmit and receive FIFOs of 3 KB each help prevent data underruns and overruns while waiting for bus accesses. This enables the integrated LAN controller to transmit data with minimum interframe spacing (IFS).

50 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

The LAN controller can operate in either full duplex or half duplex mode. In full duplex mode the LAN controller adheres with the IEEE 802.3x Flow Control specification. Half duplex performance is enhanced by a proprietary collision reduction mechanism. See Section 5.3 for details. Alert Standard Format (ASF) Management Controller ICH6 integrates an Alert Stand Format controller in addition to the integrated LAN controller, allowing interface system-monitoring devices to communicate through the integrated LAN controller to the network. This means remote manageability and system hardware monitoring are made possible using ASF. The ASF controller can collect and send various information from system components such as the processor, chipset, BIOS and sensors on the motherboard to a remote server running a management console. The controller can also be programmed to accept commands back from the management console and execute those commands on the local system. RTC The ICH6 contains a Motorola MC146818A-compatible real-time clock with 256 bytes of battery- backed RAM. The real-time clock performs two key functions: keeping track of the time of day and storing system data, even when the system is powered down. The RTC operates on a 32.768 KHz crystal and a 3 V battery. The RTC also supports two lockable memory ranges. By setting bits in the configuration space, two 8-byte ranges can be locked to read and write accesses. This prevents unauthorized reading of passwords or other system security information. The RTC also supports a date alarm that allows for scheduling a wake up event up to 30 days in advance, rather than just 24 hours in advance. GPIO Various general purpose inputs and outputs are provided for custom system design. The number of inputs and outputs varies depending on ICH6 configuration. Enhanced Power Management The ICH6’s power management functions include enhanced clock control and various low-power (suspend) states (e.g., Suspend-to-RAM and Suspend-to-Disk). A hardware-based thermal management circuit permits software-independent entrance to low-power states. The ICH6 contains full support for the Advanced Configuration and Power Interface (ACPI) Specification, Revision 2.0. Manageability The ICH6 integrates several functions designed to manage the system and lower the total cost of ownership (TCO) of the system. These system management functions are designed to report errors, diagnose the system, and recover from system lockups without the aid of an external microcontroller.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 51 Introduction

• TCO Timer. The ICH6’s integrated programmable TCO timer is used to detect system locks. The first expiration of the timer generates an SMI# that the system can use to recover from a software lock. The second expiration of the timer causes a system reset to recover from a hardware lock.
• Processor Present Indicator. The ICH6 looks for the processor to fetch the first instruction after reset. If the processor does not fetch the first instruction, the ICH6 will reboot the system.
• ECC Error Reporting. When detecting an ECC error, the host controller has the ability to send one of several messages to the ICH6. The host controller can instruct the ICH6 to generate either an SMI#, NMI, SERR#, or TCO interrupt.
• Function Disable. The ICH6 provides the ability to disable the following integrated functions: AC ’97 Modem, AC ’97 Audio, IDE, LAN, USB, LPC, Intel High Definition Audio, SATA, or SMBus. Once disabled, these functions no longer decode I/O, memory, or PCI configuration space. Also, no interrupts or power management events are generated from the disable functions.
• Intruder Detect. The ICH6 provides an input signal (INTRUDER#) that can be attached to a switch that is activated by the system case being opened. The ICH6 can be programmed to generate an SMI# or TCO interrupt due to an active INTRUDER# signal.
• SMBus 2.0. The ICH6 integrates an SMBus controller that provides an interface to manage peripherals (e.g., serial presence detection (SPD) and thermal sensors) with host notify capabilities. System Management Bus (SMBus 2.0) The ICH6 contains an SMBus Host interface that allows the processor to communicate with SMBus slaves. This interface is compatible with most I2C devices. Special I2C commands are implemented. The ICH6’s SMBus host controller provides a mechanism for the processor to initiate communications with SMBus peripherals (slaves). Also, the ICH6 supports slave functionality, including the Host Notify protocol. Hence, the host controller supports eight command protocols of the SMBus interface (see System Management Bus (SMBus) Specification, Version 2.0): Quick Command, Send Byte, Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block Read/Write, and Host Notify. ICH6’s SMBus also implements hardware-based Packet Error Checking for data robustness and the Address Resolution Protocol (ARP) to dynamically provide address to all SMBus devices. Intel High Definition Audio Controller The Intel High Definition Audio specification defines a digital interface that can be used to attach different types of codecs, such as audio and modem codecs. The ICH6 Intel High Definition Audio digital link shares pins with the AC-link. Concurrent operation of Intel High Definition Audio and AC ’97 functionality is not supported. The ICH6 Intel High Definition Audio controller supports up to 3 codecs. With the support of multi-channel audio stream, 32-bit sample depth, and sample rate up to 192 kHz, the Intel High Definition Audio controller provides audio quality that can deliver CE levels of audio experience. On the input side, the ICH6 adds support for an arrays of microphones.

52 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

The Intel High Definition Audio controller utilizes multi-purpose DMA engines, as opposed to dedicated DMA engines in AC ’97, to effectively manage the link bandwidth and support simultaneous independent streams on the link. The capability enables new exciting usage models with Intel High Definition Audio (e.g., listening to music while playing multi-player game on the internet.) The Intel High Definition Audio controller also supports isochronous data transfers allowing glitch-free audio to the system. Note: Users interested in providing feedback on the Intel High Definition Audio specification or planning to implement the Intel High Definition Audio specification into a future product will need to execute the Intel High Definition Audio Specification Developer’s Agreement. For more information, contact nextgenaudio@intel.com. AC ’97 2.3 Controller The ICH6 integrates an Audio Codec '97 Component Specification, Version 2.3 controller that can be used to attach an audio codec (AC), a modem codec (MC), an audio/modem codec (AMC) or a combination of ACs and a single MC. The ICH6 supports up to six channels of PCM audio output (full AC3 decode). For a complete surround-sound experience, six-channel audio consists of: front left, front right, back left, back right, center, and subwoofer. ICH6 has expanded support for up to three audio codecs on the AC-link. In addition, an AC '97 soft modem can be implemented with the use of a modem codec. Several system options exist when implementing AC '97. The ICH6-integrated AC '97 controller allows up to three external codecs to be connected to the ICH6. The system designer can provide AC '97 modem with a modem codec, or both audio and modem with up to two audio codecs with a modem codec.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 53 Signal Description

2 Signal Description

This chapter provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface. The “#” symbol at the end of the signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When “#” is not present, the signal is asserted when at the high voltage level. The following notations are used to describe the signal type: I Input Pin O Output Pin OD O Open Drain Output Pin. OD I Open Drain Input Pin. OD I/O Open Drain Input/Output Pin. OC O Open Collector Output Pin. I/O Bi-directional Input / Output Pin.

54 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

Figure 2-1. Intel® ICH6 Interface Signals Block Diagram (Desktop) THRM# THRMTRIP# SYS_RESET# RSMRST# MCH_SYNC# SLP_S3# SLP_S4# SLP_S5# PWROK PWRBTN# RI# WAKE# SUS_STAT# / LPCPD# SUSCLK LAN_RST# VRMPWRGD PLTRST# AD[31:0] C/BE[3:0]# DEVSEL# FRAME# IRDY# TRDY# STOP# PAR PERR# REQ[3:0]# REQ[4]# / GPI[40] REQ[5]# / GPI[1] REQ[6]# / GPI[0] GNT[3:0]# GNT[4]# / GPO[48] GNT[5]# / GPO[17] GNT[6]# / GPO[16] PCICLK PCIRST# PLOCK# SERR# PME# PCI Interface DCS1# DCS3# DA[2:0] DD[15:0] DDREQ DDACK# DIOR# (DWSTB / RDMARDY#) DIOW# (DSTOP) IORDY (DRSTB / WDMARDY#) IDE Interface Power Mgnt. Interrupt Interface A20M# CPUSLP# FERR# IGNNE# INIT# INIT3_3V# INTR NMI SMI# STPCLK# RCIN# A20GATE CPUPWRGD / GPO[49] Processor Interface USB SERIRQ PIRQ[D:A]# PIRQ[H:E]# / GPIO[5:2] IDEIRQ USBP[7:0]P USBP[7:0]N OC[3:0]# OC[4]# / GPI[9] OC[5]# / GPI[10] OC[6]# / GPI[14] OC[7]# / GPI[15] USBRBIAS# USBRBIAS RTCX1 RTCX2 CLK14 CLK48 SATA_CLKP, SATA_CLKN DMI_CLKP, DMI_CLKN RTC Clocks Misc. Signals INTVRMEN SPKR RTCRST# TP[4:0] General Purpose I/O GPIO[34:24] GPI[41:40, 15:0] EEPROM Interface EE_SHCLK EE_DIN EE_DOUT EE_CS INTRUDER# SMLINK[1:0] LINKALERT# DMI[3:0]TXP, DMI[3:0]TXN DMI[3:0]RXP, DMI[3:0]RXN DMI_ZCOMP DMI_IRCOMP Direct Media Interface LPC Interface SMBus Interface ACZ_RST# ACZ_SYNC ACZ_BIT_CLK ACZ_SDOUT ACZ_SDIN[2:0] AC '97/ Intel ® High Definition Audio Firmware Hub System Mgnt. FWH[3:0] / LAD[3:0] FWH[4] / LFRAME# LAD[3:0] / FWH[3:0] LFRAME# / FWH[4] LDRQ[0]# LDRQ[1]# / GPI[41] SMBDATA SMBCLK SMBALERT# / GPI[11] LAN_CLK LAN_RXD[2:0] LAN_TXD[2:0] LAN_RSTSYNC LAN Link SATA[3:0]TXP, SATA[3:0]TXN SATA[3:0]RXP, SATA[3:0]RXN SATARBIAS SATARBIAS# SATA[3:0]GP / GPI[31:29, 26] SATALED# Serial ATA Interface PCI Express* Interface PETp[4:1], PETn[4:1] PERp[4:1], PERn[4:1]

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 55 Signal Description Figure 2-2. Intel® ICH6-M Interface Signals Block Diagram (Mobile Only) THRM# THRMTRIP# SYS_RESET# RSMRST# MCH_SYNC# DPRSTP# SLP_S3# SLP_S4# SLP_S5# PWROK PWRBTN# RI# WAKE# SUS_STAT# / LPCPD# SUSCLK LAN_RST# VRMPWRGD BMBUSY# STP_PCI# STP_CPU# BATLOW# DPRSLPVR PLTRST# AD[31:0] C/BE[3:0]# DEVSEL# FRAME# IRDY# TRDY# STOP# PAR PERR# REQ[3:0]# REQ[4]# / GPI[40] REQ[5]# / GPI[1] REQ[6]# / GPI[0] GNT[3:0]# GNT[4]# / GPO[48] GNT[5]# / GPO[17] GNT[6]# / GPO[16] PCICLK PCIRST# PLOCK# SERR# PME# CLKRUN# PCI Interface DCS1# DCS3# DA[2:0] DD[15:0] DDREQ DDACK# DIOR# (DWSTB / RDMARDY#) DIOW# (DSTOP) IORDY (DRSTB / WDMARDY#) IDE Interface Power Mgnt. Interrupt Interface A20M# CPUSLP# FERR# IGNNE# INIT# INIT3_3# INTR NMI SMI# STPCLK# RCIN# A20GATE CPUPWRGD / GPO[49] DPSLP# Processor Interface USB SERIRQ PIRQ[D:A]# PIRQ[H:E]# / GPI[5:2] IDEIRQ USBP[7:0]P USBP[7:0]N OC[3:0]# OC[4]# / GPI[9] OC[5]# / GPI[10] OC[6]# / GPI[14] OC[7]# / GPI[15] USBRBIAS# USBRBIAS RTCX1 RTCX2 CLK14 CLK48 SATA_CLKP, SATA_CLKN DMI_CLKP, DMI_CLKN RTC Clocks Misc. Signals INTVRMEN SPKR RTCRST# TP[3] General Purpose I/O EEPROM Interface EE_SHCLK EE_DIN EE_DOUT EE_CS INTRUDER# SMLINK[1:0] LINKALERT# DMI[3:0]TXP, DMI[3:0]TXN DMI[3:0]RXP, DMI[3:0]RXN DMI_ZCOMP DMI_IRCOMP Direct Media Interface LPC Interface SMBus Interface ACZ_RST# ACZ_SYNC ACZ_BIT_CLK ACZ_SDOUT ACZ_SDIN[2:0] AC '97/ Intel® High Definition Audio Firmware Hub System Mgnt. FWH[3:0] / LAD[3:0] FWH[4] / LFRAME# LAD[3:0] / FWH[3:0] LFRAME# / FWH[4] LDRQ[0]# LDRQ[1]# / GPI[41] SMBDATA SMBCLK SMBALERT# / GPI[11] LAN_CLK LAN_RXD[2:0] LAN_TXD[2:0] LAN_RSTSYNC LAN Link SATA[2,0]TXP, SATA[2,0]TXN SATA[2,0]RXP, SATA[2,0]RXN SATARBIAS SATARBIAS# SATA[2,0]GP / GPI[30, 26] SATALED# Serial ATA Interface PCI Express* Interface PETp[4:1], PETn[4:1] PERp[4:1], PERn[4:1]

56 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

2.1 Direct Media Interface (DMI) to Host Controller

2.2 PCI Express*

Table 2-1. Direct Media Interface Signals Name Type Description DMI[0]TXP, DMI[0]TXN O Direct Media Interface Differential Transmit Pair 0 DMI[0]RXP, DMI[0]RXN I Direct Media Interface Differential Receive Pair 0 DMI[1]TXP, DMI[1]TXN O Direct Media Interface Differential Transmit Pair 1 DMI[1]RXP, DMI[1]RXN I Direct Media Interface Differential Receive Pair 1 DMI[2]TXP, DMI[2]TXN O Direct Media Interface Differential Transmit Pair 2 DMI[2]RXP, DMI[2]RXN I Direct Media Interface Differential Receive Pair 2 DMI[3]TXP, DMI[3]TXN O Direct Media Interface Differential Transmit Pair 3 DMI[3]RXP, DMI[3]RXN I Direct Media Interface Differential Receive Pair 3 DMI_ZCOMP I Impedance Compensation Input: Determines DMI input impedance. DMI_IRCOMP O Impedance/Current Compensation Output: Determines DMI output impedance and bias current. Table 2-2. PCI Express* Signals Name Type Description PETp[1], PETn[1] O PCI Express* Differential Transmit Pair 1 PERp[1], PERn[1] I PCI Express Differential Receive Pair 1 PETp[2], PETn[2] O PCI Express Differential Transmit Pair 2 PERp[2], PERn[2] I PCI Express Differential Receive Pair 2 PETp[3], PETn[3] O PCI Express Differential Transmit Pair 3 PERp[3], PERn[3] I PCI Express Differential Receive Pair 3 PETp[4], PETn[4] O PCI Express Differential Transmit Pair 4 PERp[4], PERn[4] I PCI Express Differential Receive Pair 4

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 57 Signal Description

2.3 Link to LAN Connect

2.4 EEPROM Interface

2.5 Firmware Hub Interface

Table 2-3. LAN Connect Interface Signals Name Type Description LAN_CLK I LAN I/F Clock: This signal is driven by the LAN Connect component. The frequency range is 5 MHz to 50 MHz. LAN_RXD[2:0] I Received Data: The LAN Connect component uses these signals to transfer data and control information to the integrated LAN controller. These signals have integrated weak pull-up resistors. LAN_TXD[2:0] O Transmit Data: The integrated LAN controller uses these signals to transfer data and control information to the LAN Connect component. LAN_RSTSYNC O LAN Reset/Sync: The LAN Connect component’s Reset and Sync signals are multiplexed onto this pin. Table 2-4. EEPROM Interface Signals Name Type Description EE_SHCLK O EEPROM Shift Clock: Serial shift clock output to the EEPROM. EE_DIN I EEPROM Data In: Transfers data from the EEPROM to the Intel® ICH6. This signal has an integrated pull-up resistor. EE_DOUT O EEPROM Data Out: Transfers data from the ICH6 to the EEPROM. EE_CS O EEPROM Chip Select: Chip select signal to the EEPROM. Table 2-5. Firmware Hub Interface Signals Name Type Description FWH[3:0] / LAD[3:0] I/O Firmware Hub Signals. These signals are multiplexed with the LPC address signals. FWH[4] / LFRAME# O Firmware Hub Signals. This signal is multiplexed with the LPC LFRAME# signal.

58 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

2.6 PCI Interface

Table 2-6. PCI Interface Signals (Sheet 1 of 3) Name Type Description AD[31:0] I/O PCI Address/Data: AD[31:0] is a multiplexed address and data bus. During the first clock of a transaction, AD[31:0] contain a physical address (32 bits). During subsequent clocks, AD[31:0] contain data. The Intel® ICH6 will drive all 0’s on AD[31:0] during the address phase of all PCI Special Cycles. C/BE[3:0]# I/O Bus Command and Byte Enables: The command and byte enable signals are multiplexed on the same PCI pins. During the address phase of a transaction, C/BE[3:0]# define the bus command. During the data phase C/BE[3:0]# define the Byte Enables. All command encodings not shown are reserved. The ICH6 does not decode reserved values, and therefore will not respond if a PCI master generates a cycle using one of the reserved values. DEVSEL# I/O Device Select: The ICH6 asserts DEVSEL# to claim a PCI transaction. As an output, the ICH6 asserts DEVSEL# when a PCI master peripheral attempts an access to an internal ICH6 address or an address destined DMI (main memory or graphics). As an input, DEVSEL# indicates the response to an ICH6-initiated transaction on the PCI bus. DEVSEL# is tri-stated from the leading edge of PLTRST#. DEVSEL# remains tri-stated by the ICH6 until driven by a target device. FRAME# I/O Cycle Frame: The current initiator drives FRAME# to indicate the beginning and duration of a PCI transaction. While the initiator asserts FRAME#, data transfers continue. When the initiator negates FRAME#, the transaction is in the final data phase. FRAME# is an input to the ICH6 when the ICH6 is the target, and FRAME# is an output from the ICH6 when the ICH6 is the initiator. FRAME# remains tri- stated by the ICH6 until driven by an initiator. IRDY# I/O Initiator Ready: IRDY# indicates the ICH6's ability, as an initiator, to complete the current data phase of the transaction. It is used in conjunction with TRDY#. A data phase is completed on any clock both IRDY# and TRDY# are sampled asserted. During a write, IRDY# indicates the ICH6 has valid data present on AD[31:0]. During a read, it indicates the ICH6 is prepared to latch data. IRDY# is an input to the ICH6 when the ICH6 is the target and an output from the ICH6 when the ICH6 is an initiator. IRDY# remains tri-stated by the ICH6 until driven by an initiator. C/BE[3:0]# Command Type 0000b Interrupt Acknowledge 0001b Special Cycle 0010b I/O Read 0011b I/O Write 0110b Memory Read 0111b Memory Write 1010b Configuration Read 1011b Configuration Write 1100b Memory Read Multiple 1110b Memory Read Line 1111b Memory Write and Invalidate

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 59 Signal Description TRDY# I/O Target Ready: TRDY# indicates the ICH6's ability as a target to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is completed when both TRDY# and IRDY# are sampled asserted. During a read, TRDY# indicates that the ICH6, as a target, has placed valid data on AD[31:0]. During a write, TRDY# indicates the ICH6, as a target is prepared to latch data. TRDY# is an input to the ICH6 when the ICH6 is the initiator and an output from the ICH6 when the ICH6 is a target. TRDY# is tri-stated from the leading edge of PLTRST#. TRDY# remains tri-stated by the ICH6 until driven by a target. STOP# I/O Stop: STOP# indicates that the ICH6, as a target, is requesting the initiator to stop the current transaction. STOP# causes the ICH6, as an initiator, to stop the current transaction. STOP# is an output when the ICH6 is a target and an input when the ICH6 is an initiator. PAR I/O Calculated/Checked Parity: PAR uses “even” parity calculated on 36 bits, AD[31:0] plus C/BE[3:0]#. “Even” parity means that the ICH6 counts the number of one within the 36 bits plus PAR and the sum is always even. The ICH6 always calculates PAR on 36 bits regardless of the valid byte enables. The ICH6 generates PAR for address and data phases and only guarantees PAR to be valid one PCI clock after the corresponding address or data phase. The ICH6 drives and tri- states PAR identically to the AD[31:0] lines except that the ICH6 delays PAR by exactly one PCI clock. PAR is an output during the address phase (delayed one clock) for all ICH6 initiated transactions. PAR is an output during the data phase (delayed one clock) when the ICH6 is the initiator of a PCI write transaction, and when it is the target of a read transaction. ICH6 checks parity when it is the target of a PCI write transaction. If a parity error is detected, the ICH6 will set the appropriate internal status bits, and has the option to generate an NMI# or SMI#. PERR# I/O Parity Error: An external PCI device drives PERR# when it receives data that has a parity error. The ICH6 drives PERR# when it detects a parity error. The ICH6 can either generate an NMI# or SMI# upon detecting a parity error (either detected internally or reported via the PERR# signal). REQ[0:3]# REQ[4]# / GPI[40] REQ[5]# / GPI[1] REQ[6]# / GPI[0] I PCI Requests: The ICH6 supports up to 7 masters on the PCI bus. The REQ[4]#, REQ[5]#, and REQ[6]# pins can instead be used as a GPI. GNT[0:3]# GNT[4]# / GPO[48] GNT[5]# / GPO[17]# GNT[6]# / GPO[16]# O PCI Grants: The ICH6 supports up to 7 masters on the PCI bus. The GNT[4]# pin can instead be used as a GPO. Pull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3 power rail. GNT[5]#/GPO[17] and GNT[6]#/GPO[17] both have an internal pull-up. NOTE: GNT[6] is sampled at the rising edge of PWROK as a functional strap. See Section 2.22.1 for more details. There is a weak, integrated pull-up resistor on the GNT[6] pin. PCICLK I PCI Clock: This is a 33 MHz clock. PCICLK provides timing for all transactions on the PCI Bus. NOTE: (Mobile Only) This clock does not stop based on STP_PCI# signal. PCI Clock only stops based on SLP_S3#. PCIRST# O PCI Reset: This is the Secondary PCI Bus reset signal. It is a logical OR of the primary interface PLTRST# signal and the state of the Secondary Bus Reset bit of the Bridge Control register (D30:F0:3Eh, bit 6). NOTE: PCIRST# is in the VccSus3_3 well. Table 2-6. PCI Interface Signals (Sheet 2 of 3) Name Type Description

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2.7 Serial ATA Interface

PLOCK# I/O PCI Lock: This signal indicates an exclusive bus operation and may require multiple transactions to complete. ICH6 asserts PLOCK# when it performs non- exclusive transactions on the PCI bus. PLOCK# is ignored when PCI masters are granted the bus in desktop configurations. Devices on the PCI bus (other than the ICH6) are not permitted to assert the PLOCK# signal in mobile configurations. SERR# OD I/O System Error: SERR# can be pulsed active by any PCI device that detects a system error condition. Upon sampling SERR# active, the ICH6 has the ability to generate an NMI, SMI#, or interrupt. PME# OD I PCI Power Management Event: PCI peripherals drive PME# to wake the system from low-power states S1–S5. PME# assertion can also be enabled to generate an SCI from the S0 state. In some cases the ICH6 may drive PME# active due to an internal wake event. The ICH6 will not drive PME# high, but it will be pulled up to VccSus3_3 by an internal pull-up resistor. CLKRUN# (Mobile Only) / GPIO[32] (Desktop Only) I/O PCI Clock Run: This signal is used to support PCI Clock Run protocol. It connects to PCI devices that need to request clock re-start, or prevention of clock stopping. NOTE: An external pull-up to Vcc3_3 is required. Table 2-7. Serial ATA Interface Signals (Sheet 1 of 2) Name Type Description SATA[0]TXP SATA[0]TXN O Serial ATA 0 Differential Transmit Pair: These are outbound high-speed differential signals to Port 0. SATA[0]RXP SATA[0]RXN I Serial ATA 0 Differential Receive Pair: These are inbound high-speed differential signals from Port 0. SATA[1]TXP SATA[1]TXN O Serial ATA 1 Differential Transmit Pair: These are outbound high-speed differential signals to Port 1. (Desktop Only) SATA[1]RXP SATA[1]RXN I Serial ATA 1 Differential Receive Pair: These are inbound high-speed differential signals from Port 1. (Desktop Only) SATA[2]TXP SATA[2]TXN O Serial ATA 2 Differential Transmit Pair: These are outbound high-speed differential signals to Port 2. SATA[2]RXP SATA[2]RXN I Serial ATA 2 Differential Receive Pair: These are inbound high-speed differential signals from Port 2. SATA[3]TXP SATA[3]TXN O Serial ATA 3 Differential Transmit Pair: These are outbound high-speed differential signals to Port 3. (Desktop Only) SATA[3]RXP SATA[3]RXN I Serial ATA 3 Differential Receive Pair: These are inbound high-speed differential signals from Port 3. (Desktop Only) SATARBIAS O Serial ATA Resistor Bias: These are analog connection points for an external resistor to ground. SATARBIAS# I Serial ATA Resistor Bias Complement: These are analog connection points for an external resistor to ground. Table 2-6. PCI Interface Signals (Sheet 3 of 3) Name Type Description

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2.8 IDE Interface

SATA[0]GP / GPI[26] I Serial ATA 0 General Purpose: This is an input pin that can be configured as an interlock switch corresponding to SATA Port 0. When used as an interlock switch status indication, this signal should be drive to 0 to indicate that the switch is closed and to 1 to indicate that the switch is open. If interlock switches are not required, this pin can be configured as GPI[26]. NOTE: All SATAxGP pins must be configured with the same function: as either SATAxGP pins or GPI pins. SATA[1]GP (Desktop Only) / GPI[29] I Serial ATA 1 General Purpose: Same function as SATA[0]GP, except for SATA Port 1. If interlock switches are not required, this pin can be configured as GPI[29]. SATA[2]GP / GPI[30] I Serial ATA 2 General Purpose: Same function as SATA[0]GP, except for SATA Port 2. If interlock switches are not required, this pin can be configured as GPI[30]. SATA[3]GP (Desktop Only) / GPI[31] I Serial ATA 3 General Purpose: Same function as SATA[0]GP, except for SATA Port 3. If interlock switches are not required, this pin can be configured as GPI[31]. SATALED# OC O Serial ATA LED: This is an open-collector output pin driven during SATA command activity. It is to be connected to external circuitry that can provide the current to drive a platform LED. When active, the LED is on. When tri-stated, the LED is off. An external pull-up resistor to Vcc3_3 is required. NOTE: An internal pull-up is enabled only during PLTRST# assertion. Table 2-8. IDE Interface Signals (Sheet 1 of 2) Name Type Description DCS1# O IDE Device Chip Selects for 100 Range: For ATA command register block. This output signal is connected to the corresponding signal on the IDE connector. DCS3# O IDE Device Chip Select for 300 Range: For ATA control register block. This output signal is connected to the corresponding signal on the IDE connector. DA[2:0] O IDE Device Address: These output signals are connected to the corresponding signals on the IDE connector. They are used to indicate which byte in either the ATA command block or control block is being addressed. DD[15:0] I/O IDE Device Data: These signals directly drive the corresponding signals on the IDE connector. There is a weak internal pull-down resistor on DD7. DDREQ I IDE Device DMA Request: This input signal is directly driven from the DRQ signal on the IDE connector. It is asserted by the IDE device to request a data transfer, and used in conjunction with the PCI bus master IDE function and are not associated with any AT compatible DMA channel. There is a weak internal pull- down resistor on this signal. DDACK# O IDE Device DMA Acknowledge: This signal directly drives the DAK# signal on the IDE connector. DDACK# is asserted by the Intel ® ICH6 to indicate to IDE DMA slave devices that a given data transfer cycle (assertion of DIOR# or DIOW#) is a DMA data transfer cycle. This signal is used in conjunction with the PCI bus master IDE function and are not associated with any AT-compatible DMA channel. Table 2-7. Serial ATA Interface Signals (Sheet 2 of 2) Name Type Description

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2.9 LPC Interface

DIOR# / (DWSTB / RDMARDY#) O Disk I/O Read (PIO and Non-Ultra DMA): This is the command to the IDE device that it may drive data onto the DD lines. Data is latched by the ICH6 on the de- assertion edge of DIOR#. The IDE device is selected either by the ATA register file chip selects (DCS1# or DCS3#) and the DA lines, or the IDE DMA acknowledge (DDAK#). Disk Write Strobe (Ultra DMA Writes to Disk): This is the data write strobe for writes to disk. When writing to disk, ICH6 drives valid data on rising and falling edges of DWSTB. Disk DMA Ready (Ultra DMA Reads from Disk): This is the DMA ready for reads from disk. When reading from disk, ICH6 de-asserts RDMARDY# to pause burst data transfers. DIOW# / (DSTOP) O Disk I/O Write (PIO and Non-Ultra DMA): This is the command to the IDE device that it may latch data from the DD lines. Data is latched by the IDE device on the de-assertion edge of DIOW#. The IDE device is selected either by the ATA register file chip selects (DCS1# or DCS3#) and the DA lines, or the IDE DMA acknowledge (DDAK#). Disk Stop (Ultra DMA): ICH6 asserts this signal to terminate a burst. IORDY / (DRSTB / WDMARDY#) I I/O Channel Ready (PIO): This signal will keep the strobe active (DIOR# on reads, DIOW# on writes) longer than the minimum width. It adds wait-states to PIO transfers. Disk Read Strobe (Ultra DMA Reads from Disk): When reading from disk, ICH6 latches data on rising and falling edges of this signal from the disk. Disk DMA Ready (Ultra DMA Writes to Disk): When writing to disk, this is de- asserted by the disk to pause burst data transfers. Table 2-9. LPC Interface Signals Name Type Description LAD[3:0] / FWH[3:0] I/O LPC Multiplexed Command, Address, Data: For LAD[3:0], internal pull-ups are provided. LFRAME# / FWH[4] O LPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort. LDRQ[0]# LDRQ[1]# / GPI[41] I LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used to request DMA or bus master access. These signals are typically connected to external Super I/O device. An internal pull-up resistor is provided on these signals. LDRQ[1]# may optionally be used as GPI. Table 2-8. IDE Interface Signals (Sheet 2 of 2) Name Type Description

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2.10 Interrupt Interface

Table 2-10. Interrupt Signals Name Type Description SERIRQ I/O Serial Interrupt Request: This pin implements the serial interrupt protocol. PIRQ[D:A]# OD I PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in the Interrupt Steering section. Each PIRQx# line has a separate Route Control register. In APIC mode, these signals are connected to the internal I/O APIC in the following fashion: PIRQA# is connected to IRQ16, PIRQB# to IRQ17, PIRQC# to IRQ18, and PIRQD# to IRQ19. This frees the legacy interrupts. PIRQ[H:E]# / GPI[5:2] OD I PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in the Interrupt Steering section. Each PIRQx# line has a separate Route Control register. In APIC mode, these signals are connected to the internal I/O APIC in the following fashion: PIRQE# is connected to IRQ20, PIRQF# to IRQ21, PIRQG# to IRQ22, and PIRQH# to IRQ23. This frees the legacy interrupts. If not needed for interrupts, these signals can be used as GPI. IDEIRQ I IDE Interrupt Request: This interrupt input is connected to the IDE drive.

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2.11 USB Interface

Table 2-11. USB Interface Signals Name Type Description USBP[0]P, USBP[0]N, USBP[1]P, USBP[1]N I/O Universal Serial Bus Port [1:0] Differential: These differential pairs are used to transmit Data/Address/Command signals for ports 0 and 1. These ports can be routed to UHCI controller #1 or the EHCI controller. NOTE: No external resistors are required on these signals. The ICH6 integrates 15 kΩ pull-downs and provides an output driver impedance of 45 Ω which requires no external series resistor USBP[2]P, USBP[2]N, USBP[3]P, USBP[3]N I/O Universal Serial Bus Port [3:2] Differential: These differential pairs are used to transmit data/address/command signals for ports 2 and 3. These ports can be routed to UHCI controller #2 or the EHCI controller. NOTE: No external resistors are required on these signals. The ICH6 integrates 15 kΩ pull-downs and provides an output driver impedance of 45 Ω which requires no external series resistor USBP[4]P, USBP[4]N, USBP[5]P, USBP[5]N I/O Universal Serial Bus Port [5:4] Differential: These differential pairs are used to transmit Data/Address/Command signals for ports 4 and 5. These ports can be routed to UHCI controller #3 or the EHCI controller. NOTE: No external resistors are required on these signals. The ICH6 integrates 15 kΩ pull-downs and provides an output driver impedance of 45 Ω which requires no external series resistor USBP[6]P, USBP[6]N, USBP[7]P, USBP[7]N I/O Universal Serial Bus Port [7:6] Differential: These differential pairs are used to transmit Data/Address/Command signals for ports 6 and 7. These ports can be routed to UHCI controller #4 or the EHCI controller. NOTE: No external resistors are required on these signals. The ICH6 integrates 15 kΩ pull-downs and provides an output driver impedance of 45 Ω which requires no external series resistor OC[3:0]# OC[4]# / GPI[9] OC[5]# / GPI[10] OC[6]# / GPI[14] OC[7]# / GPI[15] I Overcurrent Indicators: These signals set corresponding bits in the USB controllers to indicate that an overcurrent condition has occurred. OC[7:4]# may optionally be used as GPIs. NOTE: OC[7:0]# are not 5 V tolerant. USBRBIAS O USB Resistor Bias: Analog connection point for an external resistor. This signal is used to set transmit currents and internal load resistors. USBRBIAS# I USB Resistor Bias Complement: Analog connection point for an external resistor. This signal is used to set transmit currents and internal load resistors.

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2.12 Power Management Interface

Table 2-12. Power Management Interface Signals (Sheet 1 of 2) Name Type Description PLTRST# O Platform Reset: The ICH6 asserts PLTRST# to reset devices on the platform (e.g., SIO, FWH, LAN, (G)MCH, IDE, TPM, etc.). The ICH6 asserts PLTRST# during power-up and when S/W initiates a hard reset sequence through the Reset Control register (I/O Register CF9h). The ICH6 drives PLTRST# inactive a minimum of 1 ms after both PWROK and VRMPWRGD are driven high. The ICH6 drives PLTRST# active a minimum of 1 ms when initiated through the Reset Control register (I/O Register CF9h). NOTE: PLTRST# is in the VccSus3_3 well. THRM# I Thermal Alarm: Active low signal generated by external hardware to generate an SMI# or SCI. THRMTRIP# I Thermal Trip: When low, this signal indicates that a thermal trip from the processor occurred, and the ICH6 will immediately transition to a S5 state. The ICH6 will not wait for the processor stop grant cycle since the processor has overheated. SLP_S3# O S3 Sleep Control: SLP_S3# is for power plane control. This signal shuts off power to all non-critical systems when in S3 (Suspend To RAM), S4 (Suspend to Disk), or S5 (Soft Off) states. SLP_S4# O S4 Sleep Control: SLP_S4# is for power plane control. This signal shuts power to all non-critical systems when in the S4 (Suspend to Disk) or S5 (Soft Off) state. NOTE: This pin must be used to control the DRAM power to use the ICH6’s DRAM SLP_S5# O S5 Sleep Control: SLP_S5# is for power plane control. This signal is used to shut power off to all non-critical systems when in the S5 (Soft Off) states. PWROK I Power OK: When asserted, PWROK is an indication to the ICH6 that core power has been stable for at least 99 ms and PCICLK has been stable for at least 1 mS. An exception to this rule is if the system is in S3 HOT, in which PWROK may or may not stay asserted even though PCICLK may be inactive. PWROK can be driven asynchronously. When PWROK is negated, the ICH6 asserts PLTRST#. NOTE: PWROK must de-assert for a minimum of three RTC clock periods in order for the ICH6 to fully reset the power and properly generate the PLTRST# output PWRBTN# I Power Button: The Power Button will cause SMI# or SCI to indicate a system request to go to a sleep state. If the system is already in a sleep state, this signal will cause a wake event. If PWRBTN# is pressed for more than 4 seconds, this will cause an unconditional transition (power button override) to the S5 state. Override will occur even if the system is in the S1-S4 states. This signal has an internal pull- up resistor and has an internal 16 ms de-bounce on the input. RI# I Ring Indicate: This signal is an input from a modem. It can be enabled as a wake event, and this is preserved across power failures. SYS_RESET# I System Reset: This pin forces an internal reset after being debounced. The ICH6 will reset immediately if the SMBus is idle; otherwise, it will wait up to 25 ms ± 2 ms for the SMBus to idle before forcing a reset on the system. RSMRST# I Resume Well Reset: This signal is used for resetting the resume power plane logic.

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LAN_RST# I LAN Reset: When asserted, the internal LAN controller will be put into reset. This signal must be asserted for at least 10 ms after the resume well power (VccSus3_3 and VccSus1_5 in desktop and VccLAN3_3 and VccLAN1_5 in mobile) is valid. When de-asserted, this signal is an indication that the resume (LAN for mobile) well power is stable. NOTE: LAN_RST# must de-assert at some point to complete ICH6 power up sequencing. WAKE# I PCI Express* Wake Event: Sideband wake signal on PCI Express asserted by components requesting wakeup. MCH_SYNC# I MCH SYNC: This input is internally ANDed with the PWROK input. Desktop: Connected to the ICH_SYNC# output of (G)MCH. Mobile: Refer to the Platform Design Guide. SUS_STAT# / LPCPD# O Suspend Status: This signal is asserted by the ICH6 to indicate that the system will be entering a low power state soon. This can be monitored by devices with memory that need to switch from normal refresh to suspend refresh mode. It can also be used by other peripherals as an indication that they should isolate their outputs that may be going to powered-off planes. This signal is called LPCPD# on the LPC I/F. SUSCLK O Suspend Clock: This clock is an output of the RTC generator circuit to be used by other chips for refresh clock. VRMPWRGD I VRM Power Good: This should be connected to be the processor’s VRM Power Good signifying the VRM is stable. This signal is internally ANDed with the PWROK input. BMBUSY# (Mobile Only) / GPI[6] (Desktop Only) I Bus Master Busy: To support the C3 state. Indication that a bus master device is busy. When this signal is asserted, the BM_STS bit will be set. If this signal goes active in a C3 state, it is treated as a break event. NOTES: 1. This signal is internally synchronized using the PCICLK and a two-stage synchronizer. It does not need to meet any particular setup or hold time. 2. In desktop configurations, this signal is a GPI. STP_PCI# (Mobile Only) / GPO[18] (Desktop Only) O Stop PCI Clock: This signal is an output to the external clock generator for it to turn off the PCI clock. It is used to support PCI CLKRUN# protocol. If this functionality is not needed, this signal can be configured as a GPO. STP_CPU# (Mobile Only) / GPO[20] (Desktop Only) O Stop Processor Clock: This signal is an output to the external clock generator for it to turn off the processor clock. It is used to support the C3 state. If this functionality is not needed, this signal can be configured as a GPO. BATLOW# (Mobile Only) / TP[0] (Desktop Only) I Battery Low: This signal is an input from battery to indicate that there is insufficient power to boot the system. Assertion will prevent wake from S3–S5 state. This signal can also be enabled to cause an SMI# when asserted. DPRSLPVR (Mobile Only) / TP[1] (Desktop Only) O Deeper Sleep - Voltage Regulator: This signal is used to lower the voltage of VRM during the C4 state. When the signal is high, the voltage regulator outputs the lower “Deeper Sleep” voltage. When low (default), the voltage regulator outputs the higher “Normal” voltage. DPRSTP# (Mobile Only) / TP[4] (Desktop Only) O Deeper Sleep: This is a copy of the DPRSLPVR and it is active low. Table 2-12. Power Management Interface Signals (Sheet 2 of 2) Name Type Description

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 67 Signal Description

2.13 Processor Interface

Table 2-13. Processor Interface Signals (Sheet 1 of 2) Name Type Description A20M# O Mask A20: A20M# will go active based on either setting the appropriate bit in the Port 92h register, or based on the A20GATE input being active. CPUSLP# O Processor Sleep: This signal puts the processor into a state that saves substantial power compared to Stop-Grant state. However, during that time, no snoops occur. The Intel ® ICH6 can optionally assert the CPUSLP# signal when going to the S1 state, and will always assert it when going to C3 or C4. FERR# I Numeric Coprocessor Error: This signal is tied to the coprocessor error signal on the processor. FERR# is only used if the ICH6 coprocessor error reporting function is enabled in the OIC.CEN register (Chipset ConfigurationRegisters:Offset 31FFh: bit 1). If FERR# is asserted, the ICH6 generates an internal IRQ13 to its interrupt controller unit. It is also used to gate the IGNNE# signal to ensure that IGNNE# is not asserted to the processor unless FERR# is active. FERR# requires an external weak pull-up to ensure a high level when the coprocessor error function is disabled. NOTE: FERR# can be used in some states for notification by the processor of pending interrupt events. This functionality is independent of the OIC register bit setting. IGNNE# O Ignore Numeric Error: This signal is connected to the ignore error pin on the processor. IGNNE# is only used if the ICH6 coprocessor error reporting function is enabled in the OIC.CEN register (Chipset Configuration Registers:Offset 31FFh: bit 1). If FERR# is active, indicating a coprocessor error, a write to the Coprocessor Error register (I/O register F0h) causes the IGNNE# to be asserted. IGNNE# remains asserted until FERR# is negated. If FERR# is not asserted when the Coprocessor Error register is written, the IGNNE# signal is not asserted. INIT# O Initialization: INIT# is asserted by the ICH6 for 16 PCI clocks to reset the processor. ICH6 can be configured to support processor Built In Self Test (BIST). INIT3_3V# O Initialization 3.3 V: This is the identical 3.3 V copy of INIT# intended for the Firmware Hub. INTR O Processor Interrupt: INTR is asserted by the ICH6 to signal the processor that an interrupt request is pending and needs to be serviced. It is an asynchronous output and normally driven low. NMI O Non-Maskable Interrupt: NMI is used to force a non-Maskable interrupt to the processor. The ICH6 can generate an NMI when either SERR# is asserted or IOCHK# goes active via the SERIRQ# stream. The processor detects an NMI when it detects a rising edge on NMI. NMI is reset by setting the corresponding NMI source enable/disable bit in the NMI Status and Control register (I/O Register 61h). SMI# O System Management Interrupt: SMI# is an active low output synchronous to PCICLK. It is asserted by the ICH6 in response to one of many enabled hardware or software events. STPCLK# O Stop Clock Request: STPCLK# is an active low output synchronous to PCICLK. It is asserted by the ICH6 in response to one of many hardware or software events. When the processor samples STPCLK# asserted, it responds by stopping its internal clock. RCIN# I Keyboard Controller Reset CPU: The keyboard controller can generate INIT# to the processor. This saves the external OR gate with the ICH6’s other sources of INIT#. When the ICH6 detects the assertion of this signal, INIT# is generated for 16 PCI clocks. NOTE: The ICH6 will ignore RCIN# assertion during transitions to the S1, S3, S4, and S5 states.

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2.14 SMBus Interface

2.15 System Management Interface

A20 Gate: A20GATE is from the keyboard controller. The signal acts as an alternative method to force the A20M# signal active. It saves the external OR gate needed with various other chipsets. CPUPWRGD / GPO[49] OD O Processor Power Good: This signal should be connected to the processor’s PWRGOOD input to indicate when the processor power is valid. This is an open- drain output signal (external pull-up resistor required) that represents a logical AND of the ICH6’s PWROK and VRMPWRGD signals. This signal may optionally be configured as a GPO. DPSLP# (Mobile Only) / TP[2] (Desktop Only) O Deeper Sleep: DPSLP# is asserted by the ICH6 to the processor. When the signal is low, the processor enters the deep sleep state by gating off the processor Core Clock inside the processor. When the signal is high (default), the processor is not in the deep sleep state. Table 2-14. SM Bus Interface Signals Name Type Description SMBDATA OD I/O SMBus Data: External pull-up resistor is required. SMBCLK OD I/O SMBus Clock: External pull-up resistor is required. SMBALERT#/ GPI[11] I SMBus Alert: This signal is used to wake the system or generate SMI#. If not used for SMBALERT#, it can be used as a GPI. Table 2-15. System Management Interface Signals Name Type Description INTRUDER# I Intruder Detect: This signal can be set to disable system if box detected open. This signal’s status is readable, so it can be used like a GPI if the Intruder Detection is not needed. SMLINK[1:0] OD I/O System Management Link: SMBus link to optional external system management ASIC or LAN controller. External pull-ups are required. Note that SMLINK0 corresponds to an SMBus Clock signal, and SMLINK1 corresponds to an SMBus Data signal. LINKALERT# OD I/O SMLink Alert: Output of the integrated LAN and input to either the integrated ASF or an external management controller in order for the LAN’s SMLINK slave to be serviced. Table 2-13. Processor Interface Signals (Sheet 2 of 2) Name Type Description

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 69 Signal Description

2.16 Real Time Clock Interface

2.17 Other Clocks

2.18 Miscellaneous Signals

Table 2-16. Real Time Clock Interface Name Type Description RTCX1 Special Crystal Input 1: This signal is connected to the 32.768 kHz crystal. If no external crystal is used, then RTCX1 can be driven with the desired clock rate. RTCX2 Special Crystal Input 2: This signal is connected to the 32.768 kHz crystal. If no external crystal is used, then RTCX2 should be left floating. Table 2-17. Other Clocks Name Type Description CLK14 I Oscillator Clock: Used for 8254 timers. Runs at 14.31818 MHz. This clock is permitted to stop during S3 (or lower) states. CLK48 I 48 MHz Clock: Used to run the USB controller. Runs at 48.000 MHz. This clock is permitted to stop during S3 (or lower) states. SATA_CLKP SATA_CLKN I 100 MHz Differential Clock: These signals are used to run the SATA controller. Runs at 100 MHz. This clock is permitted to stop during S3 (or lower) states in desktop configurations or S1 (or lower) states. DMI_CLKP , DMI_CLKN I 100 MHz Differential Clock: These signals are used to run the Direct Media Interface. Runs at 100 MHz. Table 2-18. Miscellaneous Signals (Sheet 1 of 2) Name Type Description INTVRMEN I Internal Voltage Regulator Enable: This signal enables the internal 1.5 V Suspend regulator when connected to VccRTC. When connected to Vss, the internal regulator is disabled SPKR O Speaker: The SPKR signal is the output of counter 2 and is internally “ANDed” with Port 61h bit 1 to provide Speaker Data Enable. This signal drives an external speaker driver device, which in turn drives the system speaker. Upon PLTRST#, its output state is 0. NOTE: SPKR is sampled at the rising edge of PWROK as a functional strap. See Section 2.22.1 for more details. There is a weak integrated pull-down resistor on SPKR pin. RTCRST# I RTC Reset: When asserted, this signal resets register bits in the RTC well. NOTES: 1. Unless CMOS is being cleared (only to be done in the G3 power state), the RTCRST# input must always be high when all other RTC power planes are on. 2. In the case where the RTC battery is dead or missing on the platform, the RTCRST# pin must rise before the RSMRST# pin.

70 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

2.19 AC ’97/Intel ® High Definition Audio Link

NOTES: 1. Some signals have integrated pull-ups or pull-downs. Consult table in Section 3.1 for details. 2. Intel High Definition Audio mode is selected through D30:F1:40h, bit 0: AZ/AC97#. This bit selects the mode of the shared Intel High Definition Audio/AC ‘97 signals. When set to 0 AC ‘97 mode is selected. When set to 1 Intel High Definition Audio mode is selected. The bit defaults to 0 (AC ‘97 mode). TP[0] (Desktop Only) / BATLOW# (Mobile Only) I Test Point 0: This signal must have an external pull-up to VccSus3_3. TP[1] (Desktop Only) / DPRSLPVR# (Mobile Only) O Test Point 1: Route signal to a test point. TP[2] (Desktop Only) / DPSLP# (Mobile Only) O Test Point 2: Route signal to a test point. TP[3] I Test Point 3: Route signal to a test point. TP[4] (Desktop Only) / DPRSTP# (Mobile Only) O Test Point 4: Route signal to a test point. Table 2-19. AC ’97/Intel® High Definition Audio Link Signals Name Type Description ACZ_RST# O AC ’97/Intel High Definition Audio Reset: This signal is a master hardware reset to external codec(s). ACZ_SYNC O AC ’97/Intel High Definition Audio Sync: This signal is a 48 kHz fixed rate sample sync to the codec(s). Also used to encode the stream number. ACZ_BIT_CLK I/O AC ’97 Bit Clock Input: This signal is a 12.288 MHz serial data clock generated by the external codec(s). This signal has an integrated pull-down resistor (see Note below). Intel High Definition Audio Bit Clock Output: This signal is a 24.000 MHz serial data clock generated by the Intel High Definition Audio controller (the Intel® ICH6). This signal has an integrated pull-down resistor so that ACZ_BIT_CLK does not float when an Intel High Definition Audio codec (or no codec) is connected but the signals are temporarily configured as AC ’97. ACZ_SDOUT O AC ’97/Intel High Definition Audio Serial Data Out: This signal is a serial TDM data output to the codec(s). This serial output is double-pumped for a bit rate of

48 Mb/s for Intel

NOTE: ACZ_SDOUT is sampled at the rising edge of PWROK as a functional strap. See Section 2.22.1 for more details. There is a weak integrated pull-down resistor on the ACZ_SDOUT pin. ACZ_SDIN[2:0] I AC ’97/Intel High Definition Audio Serial Data In [2:0]: This signal is a serial TDM data inputs from the three codecs. The serial input is single-pumped for a bit rate of 24 Mb/s for Intel High Definition Audio. These signals have integrated pull- down resistors, which are always enabled. Table 2-18. Miscellaneous Signals (Sheet 2 of 2) Name Type Description

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 71 Signal Description

2.20 General Purpose I/O

Table 2-20. General Purpose I/O Signals1,2 (Sheet 1 of 2) Name Type Tolerance Power Well Description GPO[49] OD O V_CPU_IO Core This signal is fixed as output only and can instead be used as CPUPWRGD. GPO[48] O 3.3 V Core This signal is fixed as output only and can instead be used as GNT4#. GPIO[47:42] N/A N/A N/A This signal is not implemented. GPI[41] I 3.3 V Core This signal is fixed as input only and can be used instead as LDRQ1#. GPI[40] I5 V C o r e This signal is fixed as input only and can be used instead as REQ4#. GPIO[39:35] N/A N/A N/A This signal is not implemented. GPIO[34:33] I/O 3.3 V Core This signal can be input or output and is unmultiplexed GPIO[32] (Desktop Only) I/O 3.3 V Core This signal can be input or output. In mobile, this GPIO is not implemented and is used instead as CLKRUN#. GPI[31] I 3.3 V Core This signal is fixed as input only and can instead be used for SATA[3]GP. This signal is used only as GPI[31] in mobile. GPI[30] I 3.3 V Core This signal is fixed as input only and can instead be used for SATA[2]GP. GPI[29] I 3.3 V Core This signal is fixed as input only and can instead be used for SATA[1]GP. It is used only as GPI[29] in mobile. GPIO[28:27] I/O 3.3 V Resume This signal can be input or output and is unmultiplexed. GPI[26] I 3.3 V Core This signal is fixed as input only and can instead be used for SATA[0]GP. GPIO[25] I/O 3.3 V Resume This signal can be input or output and is unmultiplexed. It is a strap for internal Vcc2_5 regulator. See Section 2.22.1. GPIO[24] I/O 3.3 V Resume This signal can be input or output and is unmultiplexed. GPO[23] O 3.3 V Core This signal is fixed as output only. GPIO[22] N/A N/A N/A This signal is not Implemented GPO[21] O 3.3 V Core This signal is fixed as output only and is unmultiplexed GPO[20] (Desktop Only) O 3.3 V Core This signal is fixed as output only. In mobile, this GPO is not implemented and is used instead as STP_CPU#. GPO[19] O 3.3 V Core This signal is fixed as output only. NOTE: GPO[19] may be programmed to blink (controllable by GPO_BLINK (D31:F0:Offset GPIOBASE+18h:bit 19)).

72 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

NOTES: 1. All inputs are sticky. The status bit remains set as long as the input was asserted for two clocks. GPIs are sampled on PCI clocks in S0/S1 for desktop and S0 for mobile configurations. GPIs are sampled on RTC clocks in S3/S4/S5 for desktop and S1/S3/S4/S5 in mobile configurations. 2. Some GPIOs exist in the VccSus3_3 power plane. Care must be taken to make sure GPIO signals are not driven high into powered-down planes. Some ICH6 GPIOs may be connected to pins on devices that exist in the core well. If these GPIOs are outputs, there is a danger that a loss of core power (PWROK low) or a Power Button Override event will result in the Intel ICH6 driving a pin to a logic 1 to another device that is powered down. 3. GPI[15:0] can be configured to cause a SMI# or SCI. Note that a GPI can be routed to either an SMI# or an SCI, but not both. GPO[18] (Desktop Only) O 3.3 V Core This signal is fixed as output only. In mobile configurations this GPO is not implemented and is used instead as STP_PCI#. NOTE: GPO[18] will blink by default immediately after reset (controllable by GPO_BLINK (D31:F0:Offset GPIOBASE+18h:bit 18)). GPO[17] O 3.3 V Core This signal is fixed as output only and can be used instead as PCI GNT[5]#. GPO[16] O 3.3 V Core This signal is fixed as output only and can be used instead as PCI GNT[6]#. GPI[15:14] 3 I 3.3 V Resume This signal is fixed as input only and can be used instead as OC[7:6]# GPI[13]3 I 3.3 V Resume This signal is fixed as input only and is unmultiplexed. GPI[12]3 I 3.3 V Core This signal is fixed as input only and is unmultiplexed. GPI[11]3 I 3.3 V Resume This signal is fixed as input only and can be used instead as SMBALERT#. GPI[10:9]3 I 3.3 V Resume This signal is fixed as input only and can be used instead as OC[5:4]#. GPI[8]3 I 3.3 V Resume This signal is fixed as input only and is unmultiplexed. GPI[7]3 I 3.3 V Core This signal is fixed as input only and is unmultiplexed. GPI[6]3 (Desktop Only) I 3.3 V Core This signal is fixed as input only. In mobile this GPI is not implemented and is used instead as BMBUSY#. GPI[5:2]3 I5 V C o r e This signal is fixed as input only and can be used instead as PIRQ[H:E]#. GPI[1:0]3 I5 V C o r e This signal is fixed as input only and can be used instead as PCI REQ[6:5]#. Table 2-20. General Purpose I/O Signals1,2 (Sheet 2 of 2) Name Type Tolerance Power Well Description

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 73 Signal Description

2.21 Power and Ground

Table 2-21. Power and Ground Signals (Sheet 1 of 2) Name Description Vcc3_3 3.3 V supply for core well I/O buffers (22 pins). This power may be shut off in S3, S4, S5 or G3 states. Vcc1_5_A 1.5 V supply for core well logic, group A (52 pins). This power may be shut off in S3, S4, S5 or G3 states. Vcc1_5_B 1.5 V supply for core well logic, group B (45 pins). This power may be shut off in S3, S4, S5 or G3 states. Vcc2_5 2.5 V supply for internal logic (2 pins). This power may be shut off in S3, S4, S5 or G3 states. NOTE: This voltage may be generated internally (see Section 2.22.1 for strapping option). If generated internally, these pins should not be connected to an external supply. V5REF Reference for 5 V tolerance on core well inputs (2 pins). This power may be shut off in S3, S4, S5 or G3 states. VccSus3_3 3.3 V supply for resume well I/O buffers (20 pins). This power is not expected to be shut off unless the system is unplugged in desktop configurations or the main battery is removed or completely drained and AC power is not available in mobile configurations. VccSus1_5 1.5 V supply for resume well logic (3 pin). This power is not expected to be shut off unless the system is unplugged in desktop configurations or the main battery is removed or completely drained and AC power is not available in mobile configurations. This voltage may be generated internally (see Section 2.22.1 for strapping option). If generated internally, these pins should not be connected to an external supply. V5REF_Sus Reference for 5 V tolerance on resume well inputs (1 pin). This power is not expected to be shut off unless the system is unplugged in desktop configurations or the main battery is removed or completely drained and AC power is not available in mobile configurations. VccLAN3_3 (Mobile Only) 3.3 V supply for LAN Connect interface buffers (4 pins). This is a separate power plane that may or may not be powered in S3–S5 states depending upon the presence or absence of AC power and network connectivity. This plane must be on in S0 and S1. NOTE: In Desktop mode these signals are added to the VccSus3_3 group. VccLAN1_5 (Mobile Only) 1.5 V supply for LAN controller logic (2 pins). This is a separate power plane that may or may not be powered in S3–S5 states depending upon the presence or absence of AC power and network connectivity. This plane must be on in S0 and S1. NOTES: 1. This voltage will be generated internally if VccSus1_5 is generated internally (see Section 2.22.1 for strapping option). If generated internally, these pins should not be connected to an external supply. 2. In Desktop mode these signals are added to the VccSus1_5 group. VccRTC 3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well (1 pin). This power is not expected to be shut off unless the RTC battery is removed or completely drained. NOTE: Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low. Clearing CMOS in an ICH6-based platform can be done by using a jumper on RTCRST# or GPI. VccUSBPLL 1.5 V supply for core well logic (1 pin). This signal is used for the USB PLL. This power may be shut off in S3, S4, S5 or G3 states. Must be powered even if USB not used. VccDMIPLL 1.5 V supply for core well logic (1 pins). This signal is used for the DMI PLL. This power may be shut off in S3, S4, S5 or G3 states.

74 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

2.22 Pin Straps

2.22.1 Functional Straps

The following signals are used for static configuration. They are sampled at the rising edge of PWROK to select configurations (except as noted), and then revert later to their normal usage. To invoke the associated mode, the signal should be driven at least four PCI clocks prior to the time it is sampled. VccSATAPLL 1.5 V supply for core well logic (1 pins). This signal is used for the SATA PLL. This power may be shut off in S3, S4, S5 or G3 states. Must be powered even if SATA not used. V_CPU_IO Powered by the same supply as the processor I/O voltage (3 pins). This supply is used to drive the processor interface signals listed in Table 2-13. Vss Grounds (172 pins). Table 2-21. Power and Ground Signals (Sheet 2 of 2) Name Description Table 2-22. Functional Strap Definitions (Sheet 1 of 2) Signal Usage When Sampled Comment GNT[6]#/ GPO[16] Top-Block Swap Override Rising Edge of PWROK The signal has a weak internal pull-up. If the signal is sampled low, this indicates that the system is strapped to the “top-block swap” mode (ICH6 inverts A16 for all cycles targeting FWH BIOS space). The status of this strap is readable via the Top Swap bit (Chipset Configuration Registers:Offset 3414h:bit 0). Note that software will not be able to clear the Top-Swap bit until the system is rebooted without GNT6# being pulled down. LINKALERT# Reserved This signal requires an external pull-up resistor. SPKR No Reboot Rising Edge of PWROK The signal has a weak internal pull-down. If the signal is sampled high, this indicates that the system is strapped to the “No Reboot” mode (ICH6 will disable the TCO Timer system reboot feature). The status of this strap is readable via the NO REBOOT bit (Chipset Configuration Registers:Offset 3410h:bit 5). INTVRMEN Integrated VccSus1_5 VRM Enable/ Disable Always This signal enables integrated VccSus1_5 VRM when sampled high. GPIO[25] Integrated Vcc2_5 VRM Enable/ Disable Rising Edge of RSMRST# This signal enables integrated Vcc2_5 VRM when sampled low. This signal has a weak internal pull-up during RSMRST# and is disabled within 100 ms after RSMRST# de-asserts. EE_CS Reserved This signal has a weak internal pull-down. NOTE: This signal should not be pulled high.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 75 Signal Description NOTE: See Section 3.1for full details on pull-up/pull-down resistors. GNT[5]#/ GPO[17] Boot BIOS Destination Selection Rising Edge of PWROK Signal has a weak internal pull-up. Allows for select memory ranges to be forwarded out the PCI Interface as opposed to the Firmware Hub. When sampled high, destination is LPC. Also controllable via Boot BIOS Destination bit (Chipset Configuration Registers:Offset 3410h:bit 3). NOTE: This functionality intended for debug/testing only. EE_DOUT Reserved This signal has a weak internal pull-up. NOTE: This signal should not be pulled low. ACZ_SDOUT XOR Chain Entrance / PCI Express* Port Configu- ration bit 1 Rising Edge of PWROK Allows entrance to XOR Chain testing when TP[3] pulled low at rising edge of PWROK. See Chapter 24 for XOR Chain functionality information. When TP[3] not pulled low at rising edge of PWROK, sets bit 1 of RPC.PC (Chipset Configuration Registers:Offset 224h). See Section 7.1.30 for details. This signal has a weak internal pull-down. ACZ_SYNC PCI Express Port Configu- ration bit 0 Rising Edge of PWROK This signal has a weak internal pull-down. Sets bit 0 of RPC.PC (Chipset Configuration Registers:Offset 224h). See Section 7.1.30 for details. TP[1] (Desktop Only) / DPRSLPVR (Mobile Only) Reserved This signal has a weak internal pull-down. NOTE: This signal should not be pulled high. SATALED# Reserved This signal has a weak internal pull-up enabled only when PLTRST# is asserted. NOTE: This signal should not be pulled low. REQ[4:1]# XOR Chain Selection Rising Edge of PWROK See Chapter 24 for functionality information. TP[3] XOR Chain Entrance Rising Edge of PWROK See Chapter 24 for functionality information. This signal has a weak internal pull-up. NOTE: This signal should not be pulled low unless using XOR Chain testing. Table 2-22. Functional Strap Definitions (Sheet 2 of 2) Signal Usage When Sampled Comment

76 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

2.22.2 External RTC Circuitry

To reduce RTC well power consumption, the ICH6 implements an internal oscillator circuit that is sensitive to step voltage changes in VccRTC. Figure 2-3 shows an example schematic recommended to ensure correct operation of the ICH6 RTC. NOTE: C1 and C2 depend on crystal load.

2.22.3 Power Sequencing Requirements

2.22.3.1 V5REF / Vcc3_3 Se quencing Requirements

V5REF is the reference voltage for 5 V tolerance on inputs to the ICH6. V5REF must be powered up before Vcc3_3, or after Vcc3_3 within 0.7 V . Also, V5REF must power down after Vcc3_3, or before Vcc3_3 within 0.7 V . The rule must be followed in order to ensure the safety of the ICH6. If the rule is violated, internal diodes will attempt to draw power sufficient to damage the diodes from the Vcc3_3 rail. This rule also applies to V5REF_Sus and VccSus3_3. However, in most platforms, the VccSus3_3 rail is derived from the 5 VSB on the power supply through a voltage regulator and therefore, the VccSus3_3 rail will always come up after the VccSus5 rail. As a result, V5REF_Sus (which is derived directly from VccSus5) will always be powered up before VccSus3_3 and thus circuitry to satisfy the sequence requirement is not needed. However, in platforms that do not derive the VccSus3_3 rail from the VccSus5 rail, this rule must be observed in the platform design as described above. For platforms that use the integrated 1.5 V standby regulator, there are no power sequencing requirements for associated 3.3 V/1.5 V (standby or core) rails of the ICH6. For platforms that use an external 1.5 V standby regulator to power VccSus1_5 of the ICH6 (the internal voltage regulator is disabled), the platform must ensure that VccSus3_3 ramps up before VccSus1_5 or after VccSus1_5 within 0.7 V . VccSus1_5 must power down before VccSus3_3 or after VccSus3_3 within 0.7 V . Figure 2-3. Example External RTC Circuit 32.768 kHz Xtal 1.0 µF (20% tolerance) 15 pF (5% tolerance) VCCRTC RTCX2 RTCX1Vbatt 1 µF (20% tolerance) 1 KΩ VccSus3_3 15 pF (5% tolerance) 10 MΩ RTCRST# 20 KΩ Schottky Diodes

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 77 Signal Description VccLAN3_3 (mobile only) must power up before VccLAN1_5 (mobile only) or after VccLAN1_5 within 0.7 V . VccLAN1_5 must power down before VccLAN3_3 or after VccLAN3_3 within 0.7 V . For platforms that use the integrated 2.5 V regulator, there are no power sequencing requirements for associated 3.3 V/2.5 V rails of the ICH6. For platforms that use an external 2.5 V regulator to power Vcc2_5 of the ICH6 (the internal voltage regulator is disabled), the platform must ensure that Vcc3_3 must power up before Vcc2_5 or after Vcc2_5 within 0.7 V .

2.22.3.4 Vcc1_5/V_Processor_IO Power Sequencing Requirements

Vcc1_5 must power up before V_CPU_IO or after V_CPU_IO within 0.3 V . V_CPU_IO must power down before Vcc1_5 or after Vcc1_5 within 0.7 V . Note: Loaded from EEPROM. If EEPROM contains either 0000h or FFFFh in the device ID location, then 266Ch is used. Refer to the ICH6 EEPROM Map and Programming Guide for LAN Device IDs.

78 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 79 Pin States

3 Pin States

3.1 Integrated Pull-Ups and Pull-Downs

NOTES: 1. The pull-down resistors on ACZ_BIT_CLK (AC ‘97) and ACZ_RST# are enabled when either: - The LSO bit (bit 3) in the AC ’97 Global Control Register (D30:F2:2C) is set to 1, or - Both Function 2 and Function 3 of Device 30 are disabled. Otherwise, the integrated Pull-down resistor is disabled. 2. The AC ‘97/Intel High Definition Audio Link signals may either all be configured to be an AC-Link or an Intel High Definition Audio Link. Table 3-1. Integrated Pull-Up and Pull-Down Resistors Signal Resistor Type Nominal Value Notes ACZ_BIT_CLK, AC ‘97 Pull-down 20K 1, 2, 3 ACZ_RST#, AC ‘97 Pull-down 20K 1, 2, 4 ACZ_SDIN[2:0], AC ‘97 Pull-down 20K 2, 4 ACZ_SDOUT, AC ‘97 Pull-down 20K 2, 4, 5 ACZ_SYNC, AC ‘97 Pull-down 20K 2, 4, 5 ACZ_BIT_CLK, Intel High Definition Audio Pull-Down 20K 2, 6, 7 ACZ_RST#, Intel High Definition Audio None N/A 2 ACZ_SDIN[2:0], Intel High Definition Audio Pull-down 20K 2, 4 ACZ_SDOUT, Intel High Definition Audio Pull-down 20K 1, 2 ACZ_SYNC, Intel High Definition Audio Pull-down 20K 2, 4 DD[7] Pull-down 11.5K 8 DDREQ Pull-down 11.5K 8 DPRSLPVR / TP[1] Pull-down 20K 4, 9 EE_CS Pull-down 20K 10, 11 EE_DIN Pull-up 20K 10 EE_DOUT Pull-up 20K 10 GNT[3:0] Pull-up 20K 10, 12 GNT[4]# / GPO[48] Pull-up 20K 10, 12 GNT[5]# / GPO[17] Pull-up 20K 10 GNT[6]# / GPO[16] Pull-up 20K 10 GPIO[25] Pull-up 20K 10, 11 LAD[3:0]# / FHW[3:0]# Pull-up 20K 10 LAN_RXD[2:0] Pull-up 20K 13 LAN_CLK Pull-down 100K 14 LDRQ[0] Pull-up 20K 10 LDRQ[1] / GPI[41] Pull-up 20K 10 PME# Pull-up 20K 10 PWRBTN# Pull-up 20K 10 SATALED# Pull-up 15K 15 SPKR Pull-down 20K 4 TP[3] Pull-up 20K 16 USB[7:0] [P,N] Pull-down 15K 17

80 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

1. Simulation data shows that these resistor values can range from 10 kΩ to 20 kΩ. 4. Simulation data shows that these resistor values can range from 9 kΩ to 50 kΩ. 5. The pull-down resistors on ACZ_SYNC (AC ‘97) and ACZ_SDOUT (AC ‘97) are enabled during reset and also enabled when either: - The LSO bit (bit 3) in the AC ’97 Global Control Register (D30:F2:2C) is set to 1, or - Both Function 2 and Function 3 of Device 30 are disabled. Otherwise, the integrated Pull-down resistor is disabled. 6. Simulation data shows that these resistor values can range from 10 kΩ to 40 kΩ. 7. The pull-down on this signal (in Intel High Definition Audio mode) is only enabled when in S3COLD. 8. Simulation data shows that these resistor values can range from 5.7 kΩ to 28.3 kΩ. 9. The pull-up or pull-down on this signal is only enabled at boot/reset for strapping function. 10.Simulation data shows that these resistor values can range from 15 kΩ to 35 kΩ. 11.The pull-down on this signal is only enabled when LAN_RST# is asserted. 12.The internal pull-up is enabled only when the PCIRST# pin is driven low and the PWROK indication is high. 13.Simulation data shows that these resistor values can range from 15 kΩ to 30 kΩ. 14.Simulation data shows that these resistor values can range from 45 kΩ to 170 kΩ. 15.Simulation data shows that these resistor values can range from 10 kΩ to 20 kΩ. The internal pull-up is only enabled only during PLTRST# assertion. 16. Simulation data shows that these resistor values can range from 10 kΩ to 30 kΩ. 17.Simulation data shows that these resistor values can range from 14.25 kΩ to 24.8 kΩ

3.2 IDE Integrated Series Termination Resistors

Table 3-2 shows the ICH6 IDE signals that have integrated series termination resistors. NOTE: Simulation data indicates that the integrated series termination resistors are a nominal 33 Ω but can range from 21 Ω to 75 Ω.

3.3 Output and I/O Signals Planes and States

Table 3-3 and Table 3-4 shows the power plane associated with the output and I/O signals, as well as the state at various times. Within the table, the following terms are used: “High-Z” Tri-state. ICH6 not driving the signal high or low. “High” ICH6 is driving the signal to a logic 1 “Low” ICH6 is driving the signal to a logic 0 “Defined” Driven to a level that is defined by the function (will be high or low) “Undefined” ICH6 is driving the signa l, but the value is indeterminate. “Running” Clock is toggling or signal is transitioning because function not stopping “Off” The power plane is off, so ICH6 is not driving Note that the signal levels are the same in S4 and S5, except as noted. Table 3-2. IDE Series Termination Resistors Signal Integrated Series Termination Resistor Value DD[15:0], DIOW#, DIOR#, DREQ, DDACK#, IORDY, DA[2:0], DCS1#, DCS3#, IDEIRQ approximately 33 Ω (See Note)

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 81 Pin States Table 3-3. Power Plane and States for Output and I/O Signals for Desktop Configurations (Sheet 1 of 4) Signal Name Power Plane During PLTRST#1 / RSMRST#2 Immediately after PLTRST#1 / RSMRST#2 S1 S3 COLD

3 S4/S5

PCI Express* PETp[1], PETn[1] PETp[2], PETn[2] PETp[3], PETn[3] PETp[4], PETn[4] Vcc3_3 High High

4 Defined Off Off

AD[31:0] Vcc3_3 Low Undefined Defined Off Off C/BE[3:0]# Vcc3_3 Low Undefined Defined Off Off DEVSEL# Vcc3_3 High-Z High-Z High-Z Off Off FRAME# Vcc3_3 High-Z High-Z High-Z Off Off GNT[4:0]# Vcc3_3 High with Internal Pull- ups High High Off Off GNT[5]# Vcc3_3 High-Z with Internal Pull- up High High Off Off GNT[6]# Vcc3_3 High-Z with Internal Pull- up High High Off Off IRDY#, TRDY# Vcc3_3 High-Z High-Z High-Z Off Off PAR Vcc3_3 Low Undefined Defined Off Off PCIRST# VccSus3_3 Low High High Low Low PERR# Vcc3_3 High-Z High-Z High-Z Off Off PLOCK# Vcc3_3 High-Z High-Z High-Z Off Off STOP# Vcc3_3 High-Z High-Z High-Z Off Off LPC Interface LAD[3:0] / FWH[3:0] Vcc3_3 High High High Off Off LFRAME# / FWH[4] Vcc3_3 High High High Off Off LAN Connect and EEPROM Interface EE_CS VccSus3_3 Low Running Defined Defined Defined EE_DOUT VccSus3_3 High High Defined Defined Defined EE_SHCLK VccSus3_3 High-Z Running Defined Defined Defined LAN_RSTSYNC VccSus3_3 High Low Defined Defined Defined LAN_TXD[2:0] VccSus3_3 Low Low Defined Defined Defined

82 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

DA[2:0] Vcc3_3 Undefined Undefined Undefined Off Off DCS1#, DCS3# Vcc3_3 High High High Off Off DD[15:8], DD[6:0] Vcc3_3 High-Z High-Z High-Z Off Off DD[7] Vcc3_3 Low Low Low Off Off DDACK# Vcc3_3 High High High Off Off DIOR#, DIOW# Vcc3_3 High High High Off Off SATA Interface SATA[0]TXP, SATA[0]TXN SATA[1]TXP, SATA[1]TXN SATA[2]TXP, SATA[2]TXN SATA[3]TXP, SATA[3]TXN Vcc3_3 High-Z High-Z Defined Off Off SATALED# Vcc3_3 High-Z High-Z Defined Off Off SATARBIAS Vcc3_3 High-Z High-Z High-Z Off Off Interrupts PIRQ[A:H]# Vcc3_3 High-Z High-Z High-Z Off Off SERIRQ Vcc3_3 High-Z High-Z High-Z Off Off USB Interface USBP[7:0][P,N] VccSus3_3 Low Low Low Low Low USBRBIAS VccSus3_3 High-Z High-Z Defined Defined Defined Power Management PLTRST# VccSus3_3 Low High High Low Low SLP_S3# VccSus3_3 Low High High Low Low SLP_S4# VccSus3_3 Low High High High Low SLP_S5# VccSus3_3 Low High High High Low SUS_STAT# VccSus3_3 Low High High Low Low SUSCLK VccSus3_3 Low Running Table 3-3. Power Plane and States for Output and I/O Signals for Desktop Configurations (Sheet 2 of 4) Signal Name Power Plane During PLTRST#1 / RSMRST#2 Immediately after PLTRST#1 / RSMRST#2 S1 S3 COLD

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 83 Pin States Processor Interface A20M# V_CPU_IO Note 6 Note 6 High Off Off CPUPWRGD V_CPU_IO Note 7 High-Z High-Z Off Off CPUSLP# V_CPU_IO High High Defined Off Off IGNNE# V_CPU_IO Note 6 Note 6 High Off Off INIT# V_CPU_IO High High High Off Off INIT3_3V# Vcc3_3 High High High Off Off INTR V_CPU_IO Note 8 Note 8 Low Off Off NMI V_CPU_IO Note 8 Note 8 Low Off Off SMI# V_CPU_IO High High High Off Off STPCLK# V_CPU_IO High High Low Off Off SMBus Interface SMBCLK, SMBDATA VccSus3_3 High-Z High-Z Defined Defined Defined System Management Interface SMLINK[1:0] VccSus3_3 High-Z High-Z Defined Defined Defined LINKALERT# VccSus3_3 High-Z High-Z Defined Defined Defined Miscellaneous Signals SPKR Vcc3_3 High-Z with Internal Pull- down Low Defined Off Off AC ’97 Interface ACZ_RST# VccSus3_3 Low Low Cold Reset Bit (High) Low Low ACZ_SDOUT Vcc3_3 Low Running Low Off Off ACZ_SYNC Vcc3_3 Low Running Low Off Off Intel High Definition Audio Interface ACZ_RST# VccSus3_3 Low Low 9 Low Low Low ACZ_SDOUT Vcc3_3 High-Z with Internal Pull- down Running Low Off Off ACZ_SYNC Vcc3_3 High-Z with Internal Pull- down Running Low Off Off ACZ_BIT_CLK Vcc3_3 High-Z with Internal Pull- down Low9 Low Off Off Table 3-3. Power Plane and States for Output and I/O Signals for Desktop Configurations (Sheet 3 of 4) Signal Name Power Plane During PLTRST#1 / RSMRST#2 Immediately after PLTRST#1 / RSMRST#2 S1 S3 COLD

84 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

NOTES: 1. The states of Vcc3_3 signals are taken at the times During PLTRST# and Immediately after PLTRST#. 2. The states of VccSus3_3 signals are taken at the times During RSMRST# and Immediately after RSMRST#. 3. In S3HOT, signal states are platform implementation specific, as some external components and interfaces may be powered when the ICH6 is in the S3HOT state. 4. PETp/n[4:1] high until port is enabled by software. 5. SLP_S5# signals will be high in the S4 state. 6. ICH6 drives these signals Low before PWROK rising and High after the processor reset 7. CPUPWRGD is an open-drain output that represents a logical AND of the ICH6’s VRMPWRGD and PWROK signals, and thus will be driven low by ICH6 when either VRMPWRGD or PWROK are inactive. During boot, or during a hard reset with power cycling, CPUPWRGD will be expected to transition from low to High-Z. 8. ICH6 drives these signals Low before PWROK rising and Low after the processor reset. 9. Low until Intel High Definition Audio Controller Reset bit set (D27:F0:Offset HDBAR+08h:bit 0), at which time ACZ_RST# will be High and ACZ_BIT_CLK will be Running. 10.GPO[18] will toggle at a frequency of approximately 1 Hz when the ICH6 comes out of reset 11.GPIO[25] transitions from pulled high internally to actively driven following the de-assertion of the RSMRST# pin. Unmultiplexed GPIO Signals GPO[18] Vcc3_3 High Note 10 Defined Off Off GPO[21:19] Vcc3_3 High High Defined Off Off GPO[23] Vcc3_3 Low Low Defined Off Off GPIO[24] VccSus3_3 High High 11 Defined Defined Defined GPIO[25] VccSus3_3 High High Defined Defined Defined GPIO[28:27] VccSus3_3 High Hi gh Defined Defined Defined GPIO[34:32] Vcc3_3 High High Defined Off Off Table 3-3. Power Plane and States for Output and I/O Signals for Desktop Configurations (Sheet 4 of 4) Signal Name Power Plane During PLTRST#1 / RSMRST#2 Immediately after PLTRST#1 / RSMRST#2 S1 S3 COLD

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 85 Pin States Table 3-4. Power Plane and States for Output and I/O Signals for Mobile Configurations (Sheet 1 of 4) Signal Name Power Plane During PLTRST#6 / RSMRST#7 Immediately after PLTRST#6 / RSMRST#7 C3/C4 S1 S3 COLD

13 S4/S5

PCI Express* PETp[1], PETn[1] PETp[2], PETn[2] PETp[3], PETn[3] PETp[4], PETn[4] Vcc3_3 High High

12 Defined Defined Off Off

AD[31:0] Vcc3_3 Low Undefined Defined Defined Off Off C/BE[3:0]# Vcc3_3 Low Undefined Defined Defined Off Off CLKRUN# Vcc3_3 Low Low Defined Off Off DEVSEL# Vcc3_3 High-Z High-Z High-Z High-Z Off Off FRAME# Vcc3_3 High-Z High-Z High-Z High-Z Off Off GNT[4:0]# Vcc3_3 High with Internal Pull- ups High High High Off Off GNT[5]# Vcc3_3 High-Z with internal Pull- up High High High Off Off GNT[6]# Vcc3_3 High-Z with internal Pull- up High High High Off Off IRDY#, TRDY# Vcc3_3 High-Z High-Z High-Z High-Z Off Off PAR Vcc3_3 Low Undefined Defined Defined Off Off PCIRST# VccSus3_3 Low High High High Low Low PERR# Vcc3_3 High-Z High-Z High-Z High-Z Off Off PLOCK# Vcc3_3 High-Z High-Z High-Z High-Z Off Off STOP# Vcc3_3 High-Z High-Z High-Z High-Z Off Off LPC Interface LAD[3:0] / FWH[3:0] Vcc3_3 High High High High Off Off LFRAME# / FWH[4] Vcc3_3 High High High High Off Off

86 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

LAN Connect and EEPROM Interface EE_CS VccLAN3_3 Low Running Defined Defined Note 4 Note 4 EE_DOUT VccLAN3_3 High High Defined Defined Note 4 Note 4 EE_SHCLK VccLAN3_3 Low Running Defined Defined Note 4 Note 4 LAN_RSTSYNC VccLAN3_3 High Low Defined Defined Note 4 Note 4 LAN_TXD[2:0] VccLAN3_3 Low Low Defined Defined Note 4 Note 4 IDE Interface DA[2:0] Vcc3_3 Undefined Undefined Undefined Undefined Off Off DCS1#, DCS3# Vcc3_3 High High High High Off Off DD[15:8], DD[6:0] Vcc3_3 High-Z High-Z Defined High-Z Off Off DD[7] Vcc3_3 Low Low Defined Low Off Off DDACK# Vcc3_3 High High High High Off Off DIOR#, DIOW# Vcc3_3 High High High High Off Off SATA Interface SATA[0]TXP , SATA[0]TXN SATA[2]TXP , SATA[2]TXN Vcc3_3 High-Z High-Z Defined Defined Off Off SATALED# Vcc3_3 High-Z High-Z Defined Defined Off Off SATARBIAS Vcc3_3 High-Z High-Z Defined Defined Off Off Interrupts PIRQ[A:H]# Vcc3_3 High-Z High-Z Defined High-Z Off Off SERIRQ Vcc3_3 High-Z High-Z Running High-Z Off Off USB Interface USBP[7:0][P,N] VccSus3_3 Low Low Low Low Low Low USBRBIAS VccSus3_3 High-Z High-Z Defined Defined Defined Defined Power Management PLTRST# VccSus3_3 Low High High High Low Low SLP_S3# VccSus3_3 Low High High High Low Low SLP_S4# VccSus3_3 Low High High High High Low SLP_S5# VccSus3_3 Low High High High High Low STP_PCI# Vcc3_3 High High Defined High Low Low STP_CPU# Vcc3_3 High High Low High Low Low SUS_STAT# VccSus3_3 Low High High High Low Low DPRSLPVR Vcc3_3 Low Low Low/High 5 High Off Off Table 3-4. Power Plane and States for Output and I/O Signals for Mobile Configurations (Sheet 2 of 4) Signal Name Power Plane During PLTRST#6 / RSMRST#7 Immediately after PLTRST#6 / RSMRST#7 C3/C4 S1 S3 COLD

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 87 Pin States DPRSTP# Vcc3_3 High High Low/High 5 High Off Off SUSCLK VccSus3_3 Low Running Processor Interface A20M# V_CPU_IO See Note 1 See Note 1 Defined High Off Off CPUPWRGD Vcc3_3 See Note 3 High-Z High-Z High-Z Off Off CPUSLP# V_CPU_IO High High High Defined Off Off IGNNE# V_CPU_IO See Note 1 See Note 1 High High Off Off INIT# V_CPU_IO High High High High Off Off INIT3_3V# Vcc3_3 High High High High Off Off INTR V_CPU_IO See Note 8 See Note 8 Defined Low Off Off NMI V_CPU_IO See Note 8 See Note 8 Defined Low Off Off SMI# V_CPU_IO High High Defined High Off Off STPCLK# V_CPU_IO High High Low Low Off Off DPSLP# V_CPU_IO High High High/Low High Off Off SMBus Interface SMBCLK, SMBDATA VccSus3_3 High-Z High-Z Def ined Defined Defined Defined System Management Interface SMLINK[1:0] VccSus3_3 High-Z Hi gh-Z Defined Defined Defined Defined LINKALERT# VccSus3_3 High-Z High- Z Defined Defined Defined Defined Miscellaneous Signals SPKR Vcc3_3 High-Z with Internal Pull- down Low Defined Defined Off Off AC ’97 Interface ACZ_RST# VccSus3_3 Low Low High Cold Reset Bit (High) Low Low ACZ_SDOUT Vcc3_3 Low Running Running Low Off Off ACZ_SYNC Vcc3_3 Low Running Running Low Off Off Table 3-4. Power Plane and States for Output and I/O Signals for Mobile Configurations (Sheet 3 of 4) Signal Name Power Plane During PLTRST#6 / RSMRST#7 Immediately after PLTRST#6 / RSMRST#7 C3/C4 S1 S3 COLD

88 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

NOTES: 1. ICH6 drives these signals Low before PWROK rising and High after the processor reset. 2. GPIO[18] will toggle at a frequency of approximately 1 Hz when the ICH6 comes out of reset 3. CPUPWRGD is an open-drain output that represents a logical AND of the ICH6’s VRMPWRGD and PWROK signals, and thus will be driven low by ICH6 when either VRMPWRGD or PWROK are inactive. During boot, or during a hard reset with power cycling, CPUPWRGD will be expected to transition from low to High-Z. 4. LAN Connect and EEPROM signals will either be “Defined” or “Off” in S3-S5 states depending upon whether or not the LAN power planes are active. 5. The state of the DPRSLPVR and DPRSTP# signals in C4 are high if Deeper Sleep is enabled or low if it is disabled. 6. The states of Vcc3_3 signals are taken at the times during PLTRST# and Immediately after PLTRST#. 7. The states of VccSus3_3 signals are taken at the times during RSMRST# and Immediately after RSMRST#. 8. ICH6 drives these signals Low before PWROK rising and Low after the processor reset. 9. GPIO[25] transitions from pulled high internally to actively driven following the de-assertion of the RSMRST# pin. 10.SLP_S5# signals will be high in the S4 state. 11.Low until Intel High Definition Audio Controller Reset bit set (D27:F0:Offset HDBAR+08h:bit 0), at which time ACZ_RST# will be High and ACZ_BIT_CLK will be Running. 12.PETp/n[4:1] high until port is enabled by software. 13.In S3 HOT, signal states are platform implementation specific, as some external components and interfaces may be powered when the ICH6 is in the S3HOT state. Intel High Definition Audio Interface ACZ_RST# VccSus3_3 Low Low 11 High TBD Low Low ACZ_SDOUT Vcc3_3 High-Z with Internal Pull- down Running Running Low Off Off ACZ_SYNC Vcc3_3 High-Z with Internal Pull- down Running Running Low Off Off ACZ_BIT_CLK Vcc3_3 High-Z with Internal Pull- down Low11 Running Low Off Off Unmultiplexed GPIO Signals GPO[19] Vcc3_3 High High Defined Defined Off Off GPO[21] Vcc3_3 High High Defined Defined Off Off GPO[23] Vcc3_3 Low Low Defined Defined Off Off GPIO[24] VccSus3_3 High High Defined Defined Defined Defined GPIO[25] VccSus3_3 High High9 Defined Defined Defined Defined GPIO[28:27] VccSus3_3 High High De fined Defined Defined Defined GPIO[34:33] Vcc3_3 High Hi gh Defined Defined Off Off Table 3-4. Power Plane and States for Output and I/O Signals for Mobile Configurations (Sheet 4 of 4) Signal Name Power Plane During PLTRST#6 / RSMRST#7 Immediately after PLTRST#6 / RSMRST#7 C3/C4 S1 S3 COLD

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 89 Pin States

3.4 Power Planes for Input Signals

Table 3-5 and Table 3-6 shows the power plane associated with each input signal, as well as what device drives the signal at various times. Valid states include: High Low Static: Will be high or low, but will not change Driven: Will be high or low, and is allowed to change Running: For input clocks Table 3-5. Power Plane for Input Signals for Desktop Configurations (Sheet 1 of 3) Signal Name Power Well Driver During Reset S1 S3 COLD

1 S4/S5

A20GATE Vcc3_3 External Microcontroller Static Low Low ACZ_BIT_CLK (AC ‘97 Mode) Vcc3_3 AC ’97 Codec Low Low Low ACZ_SDIN[2:0] (AC ‘97 Mode) VccSus3_3 AC ’97 Codec Low Low Low ACZ_SDIN[2:0] (Intel High Definition Audio Mode) VccSus3_3 Intel High Definition Audio Codec Low Low Low CLK14 Vcc3_3 Clock Generator Running Low Low CLK48 Vcc3_3 Clock Generator Running Low Low DDREQ Vcc3_3 IDE Device Static Low Low DMI_CLKP, DMI_CLKN Vcc3_3 Clock Generator Running Low Low EE_DIN VccSus3_3 EEPROM Component Driven Driven Driven FERR# V_CPU_IO Processor Static Low Low GPI[6] Vcc3_3 External Device or External Pull-up/Pull-down Driven Off Off GPI[7] Vcc3_3 External Device or External Pull-up/Pull-down Driven Off Off GPI[8] VccSus3_3 External Device or External Pull-up/Pull-down Driven Driven Driven GPI[12] Vcc3_3 External Device or External Pull-up/Pull-down Driven Driven Driven GPI[13] VccSus3_3 External Device or External Pull-up/Pull-down Driven Driven Driven PERp[1], PERn[1] PERp[2], PERn[2] PERp[3], PERn[3] PERp[4], PERn[4] Vcc3_3 PCI Express* Device Driven Driven Driven

90 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

DMI[0]RXP, DMI[0]RXN DMI[1]RXP, DMI[1]RXN DMI[2]RXP, DMI[2]RXN DMI[3]RXP, DMI[3]RXN Vcc3_3 (G)MCH Driven Low Low IDEIRQ Vcc3_3 IDE Static Low Low INTRUDER# VccRTC External Switch Driven Driven Driven INTVRMEN VccRTC External Pull-up or Pull-down Driven Driven Driven IORDY Vcc3_3 IDE Device Static Low Low LAN_CLK VccSus3_3 LAN Connect Component Driven Driven Driven LAN_RST# VccSus3_3 External RC Circuit High High High LAN_RXD[2:0] VccSus3_3 LAN Connec t Component Driven Driven Driven LDRQ0# Vcc3_3 LPC Devices High Low Low LDRQ1# Vcc3_3 LPC Devices High Low Low MCH_SYNC# Vcc3_3 (G)MCH Driven Low Low OC[7:0]# VccSus3_3 External Pull-ups Driven Driven Driven PCICLK Vcc3_3 Clock Generator Running Low Low PME# VccSus3_3 Internal Pull-up Driven Driven Driven PWRBTN# VccSus3_3 Internal Pull-up Driven Driven Driven PWROK VccRTC System Power Supply Driven Low Low RCIN# Vcc3_3 External Microcontroller High Low Low REQ[6:0]# Vcc3_3 PCI Master Driven Low Low RI# VccSus3_3 Serial Port Buffer Driven Driven Driven RSMRST# VccRTC External RC Circuit High High High RTCRST# VccRTC External RC Circuit High High High SATA_CLKP, SATA_CLKN Vcc3_3 Clock Generator Running Low Low SATA[0]RXP, SATA[0]RXN SATA[1]RXP, SATA[1]RXN SATA[2]RXP, SATA[2]RXN SATA[3]RXP, SATA[3]RXN Vcc3_3 SATA Drive Driven Driven Driven SATARBIAS# Vcc3_3 External Pull-down Driven Driven Driven SATA[3:0]GP / GPI[31:29,26] Vcc3_3 External Device or External Pull-up/Pull-down Driven Driven Driven SERR# Vcc3_3 PCI Bus Peripherals High Low Low Table 3-5. Power Plane for Input Signals for Desktop Configurations (Sheet 2 of 3) Signal Name Power Well Driver During Reset S1 S3 COLD

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 91 Pin States NOTES: 1. In S3HOT, signal states are platform implementation specific, as some external components and interfaces may be powered when the ICH6 is in the S3HOT state. SMBALERT# VccSus3_3 External Pull-up Driven Driven Driven SYS_RESET# VccSus3_3 External Circuit Driven Driven Driven THRM# Vcc3_3 Thermal Sensor Driven Low Low THRMTRIP# V_CPU_IO Thermal Sensor Driven Low Low TP[0] VccSus3_3 External Pull-up High High High TP[3] VccSus3_3 Internal Pull-up High High High USBRBIAS# VccSus3_3 External Pull-down Driven Driven Driven VRMPWRGD Vcc3_3 Processor Voltage Regulator High Low Low WAKE# VccSus3_3 External Pull-up Driven Driven Driven Table 3-5. Power Plane for Input Signals for Desktop Configurations (Sheet 3 of 3) Signal Name Power Well Driver During Reset S1 S3 COLD Table 3-6. Power Plane for Input Signals for Mobile Configurations (Sheet 1 of 3) Signal Name Power Well Driver During Reset C3/C4 S1 S3 COLD A20GATE Vcc3_3 External Micr ocontroller Static Static Low Low ACZ_BIT_CLK (AC ‘97 mode) Vcc3_3 AC ’97 Codec Driven Low Low Low ACZ_SDIN[2:0] (AC ‘97 mode) VccSus3_3 AC ’97 Codec Driven Low Low Low ACZ_SDIN[2:0] (Intel High Definition Audio mode) VccSus3_3 Intel High Definition Audio Codec Driven Low Low Low BMBUSY# Vcc3_3 Graphics Component [(G)MCH] Driven High Low Low BATLOW# VccSus3_3 Power Supply High High High High CLK14 Vcc3_3 Clock Generator Running Running Low Low CLK48 Vcc3_3 Clock Generator Running Running Low Low DDREQ Vcc3_3 IDE Device Driven Static Low Low DMI_CLKP DMI_CLKN Vcc3_3 Clock Generator Running Running Low Low EE_DIN VccLAN3_3 EEPROM Component Driven Driven Note 2 Note 2 FERR# V_CPU_IO Processor Static Static Low Low GPI[7] Vcc3_3 External Device or External Pull-up/Pull-down Driven Driven Off Off GPI[8] VccSus3_3 External Device or External Pull-up/Pull-down Driven Driven Driven Driven GPI[12] Vcc3_3 External Device or External Pull-up/Pull-down Driven Driven Driven Driven

92 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

GPI[13] VccSus3_3 External Device or External Pull-up/Pull-down Driven Driven Driven Driven GPI[29] Vcc3_3 External Device or External Pull-up/Pull-down Driven Driven Driven Driven GPI[31] Vcc3_3 External Device or External Pull-up/Pull-down Driven Driven Driven Driven PERp[1], PERn[1] PERp[2], PERn[2] PERp[3], PERn[3] PERp[4], PERn[4] Vcc3_3 PCI Express* Device Driven Driven Driven Driven DMI[0]RXP, DMI[0]RXN DMI[1]RXP, DMI[1]RXN DMI[2]RXP, DMI[2]RXN DMI[3]RXP, DMI[3]RXN Vcc3_3 (G)MCH Driven Driven Low Low IDEIRQ Vcc3_3 IDE Driven Static Low Low INTRUDER# VccRTC External Swit ch Driven Driven Driven Driven INTVRMEN VccRTC External Pull-up or Pull- down Driven Driven Driven Driven IORDY Vcc3_3 IDE Device Static Static Low Low LAN_CLK VccLAN3_3 LAN Connect Component Driven Driven Note 2 Note 2 LAN_RST# VccSus3_3 Power Supply High High Static Static LAN_RXD[2:0] VccLAN3_3 LAN Connect Component Driven Driven Note 2 Note 2 LDRQ0# Vcc3_3 LPC Devices Driven High Low Low LDRQ1# Vcc3_3 LPC Devices Driven High Low Low MCH_SYNC# Vcc3_3 (G)MCH Driven Driven Low Low OC[7:0]# VccSus3_3 External Pull- ups Driven Driven Driven Driven PCICLK Vcc3_3 Clock Generator Running Running Low Low PME# VccSus3_3 Internal Pull-up Driven Driven Driven Driven PWRBTN# VccSus3_3 Internal Pull-up Driven Driven Driven Driven PWROK VccRTC System Power Supply Driven Driven Low Low RCIN# Vcc3_3 External Microcontroller High High Low Low REQ[6:0]# Vcc3_3 PCI Master Driven Driven Low Low RI# VccSus3_3 Serial Port Bu ffer Driven Driven Driven Driven RSMRST# VccRTC External RC Circuit High High High High RTCRST# VccRTC External RC Circuit High High High High Table 3-6. Power Plane for Input Signals for Mobile Configurations (Sheet 2 of 3) Signal Name Power Well Driver During Reset C3/C4 S1 S3 COLD

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 93 Pin States NOTES: 1. In S3HOT, signal states are platform implementation specific, as some some external components and interfaces may be powered when the ICH6 is in the S3HOT state. 2. LAN Connect and EEPROM signals will either be “Driven” or “Low” in S3–S5 states depending upon whether or not the LAN power planes are active. SATA_CLKP, SATA_CLKN Vcc3_3 Clock Generator Running Running Low Low SATA[0]RXP, SATA[0]RXN SATA[2]RXP, SATA[2]RXN Vcc3_3 SATA Drive Driven Driven Driven Driven SATARBIAS# Vcc3_3 External Pull -Down Driven Driven Driven Driven SATA[2,0]GP Vcc3_3 External Device or External Pull-up/Pull-down Driven Driven Driven Driven SERR# Vcc3_3 PCI Bus Peripherals Driven High Low Low SMBALERT# VccSus3_3 External Pull -up Driven Driven Driven Driven SYS_RESET# VccSus3_3 External Circ uit Driven Driven Driven Driven THRM# Vcc3_3 Thermal Sensor Driven Driven Low Low THRMTRIP# V_CPU_IO Thermal Sensor Driven Driven Low Low TP[3] VccSus3_3 Internal Pull-up High High High High USBRBIAS# VccSus3_3 External Pull -down Driven Driven Driven Driven VRMPWRGD Vcc3_3 Processor Voltage Regulator Driven Driven Low Low WAKE# VccSus3_3 External Pull-up Driven Driven Driven Driven Table 3-6. Power Plane for Input Signals for Mobile Configurations (Sheet 3 of 3) Signal Name Power Well Driver During Reset C3/C4 S1 S3 COLD

94 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 95 System Clock Domains

4 System Clock Domains

Table 4-1 shows the ICH6 and system clock domains. Figure 4-1 and Figure 4-2 shows the assumed connection of the various system components, including the clock generator in both desktop and mobile systems. For complete details of the system clocking solution, refer to the system’s clock generator component specification. Table 4-1. Intel® ICH6 and System Clock Domains Clock Domain Frequency Source Usage Intel® ICH6 SATA_CLKP, SATA_CLKN

100 MHz Main Clock

Generator Differential clock pair used for SATA. ICH6 DMI_CLKP, DMI_CLKN Generator Differential clock pair used for DMI. ICH6 PCICLK 33 MHz Main Clock Generator Free-running PCI Clock to Intel® ICH6. This clock remains on during S0 and S1 (in desktop) state, and is expected to be shut off during S3 or below in desktop configurations or S1 or below in mobile configurations. System PCI 33 MHz Main Clock Generator PCI Bus, LPC I/F. These only go to external PCI and LPC devices. Will stop based on CLKRUN# (and STP_PCI#) in mobile configurations. ICH6 CLK48 48.000 MHz Main Clock Generator Super I/O, USB controllers. Expected to be shut off during S3 or below in desktop configurations or S1 or below in mobile configurations. ICH6 CLK14 14.31818 MHz Main Clock Generator Used for ACPI timer and Multimedia Timers. Expected to be shut off during S3 or below in desktop configurations or S1 or below in mobile configurations. ICH6 ACZ_BIT_CLK 12.288 MHz AC ’97 Codec AC-link. Generated by AC ’97 Codec. Can be shut by codec in D3. Expected to be shut off during S3 or below in desktop configurations or S1 or below in mobile configurations. NOTE: For use only in AC ‘97 mode. LAN_CLK 5 to 50 MHz LAN Connect Component Generated by the LAN Connect component. Expected to be shut off during S3 or below in desktop configurations or S1 or below in mobile configurations.

96 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

Figure 4-1. Desktop Conceptual System Clock Diagram Intel® ICH6 PCI Clocks (33 MHz)Clock Gen.

14.31818 MHz

48.000 MHz

XTAL SUSCLK# (32 kHz) LAN Connect50 MHz AC ’97 Codec(s)12.288 MHz

33 MHz

100 MHz

Diff. Pair 1 to 6 Differential Clock Fan Out Device SATA 100 MHz Diff. Pair DMI 100 MHz Diff. Pair PCI Express Diff. Pairs High Definition Audio Codec(s)

24 MHz

Figure 4-2. Mobile Conceptual Clock Diagram Intel® ICH6-M 32 kHz XTAL SUSCLK# (32 kHz) STP_CPU# STP_PCI# PCI Clocks (33 MHz)Clock Gen.

48 MHz

100 MHz Diff. Pair 1 to 6 Differential Clock Fan Out Device SATA 100 MHz Diff. Pair DMI 100 MHz Diff. Pair PCI Express Diff. Pairs AC ’97 Codec(s)12.288 MHz Intel® HD Audio Codec(s)24 MHz

50 MHz

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 97 Functional Description

5 Functional Description

This chapter describes the functions and interfaces of the ICH6 Family.

5.1 PCI-to-PCI Bridge (D30:F0)

The PCI-to-PCI bridge resides in PCI Device 30, Function 0 on bus #0. This portion of the ICH6 implements the buffering and control logic between PCI and Direct Media Interface (DMI). The arbitration for the PCI bus is handled by this PCI device. The PCI decoder in this device must decode the ranges for the DMI. All register contents are lost when core well power is removed. Direct Media Interface (DMI) is the chip-to-chip connection between the Memory Controller Hub / Graphics and Memory Controller Hub ((G)MCH) and I/O Controller Hub 6 (ICH6). This high- speed interface integrates advanced priority-based servicing allowing for concurrent traffic and true isochronous transfer capabilities. Base functionality is completely software transparent permitting current and legacy software to operate normally. In order to provide for true isochronous transfers and configurable Quality of Service (QoS) transactions, the ICH6 supports two virtual channels on DMI: VC0 and VC1. These two channels provide a fixed arbitration scheme where VC1 is always the highest priority. VC0 is the default conduit of traffic for DMI and is always enabled. VC1 must be specifically enabled and configured at both ends of the DMI link (i.e., the ICH6 and (G)MCH). Configuration registers for DMI, virtual channel support, and DMI active state power management (ASPM) are in the RCRB space in the Chipset Configuration Registers (Section 7).

5.1.1 PCI Bus Interface

The ICH6 PCI interface provides a 33 MHz, PCI Local Bus Specification, Revision 2.3-compliant implementation. All PCI signals are 5 V tolerant (except PME#). The ICH6 integrates a PCI arbiter that supports up to seven external PCI bus masters in addition to the internal ICH6 requests.

5.1.2 PCI Bridge As an Initiator

The bridge initiates cycles on the PCI bus when granted by the PCI arbiter. The bridge generates the cycle types shown in Table 5-1. Table 5-1. PCI Bridge Initiator Cycle Types Command C/BE# Notes I/O Read/Write 2h/3h Non-posted Memory Read/Write 6h/7h Writes are posted Configuration Read/Write Ah/Bh Non-posted Special Cycles 1h Posted

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5.1.2.1 Memory Reads and Writes

The bridge bursts memory writes on PCI that are received as a single packet from DMI. The bridge will perform write combining if BPC.WCE (D30:F0:Offset 4Ch:bit 31) is set.

5.1.2.2 I/O Reads and Writes

The bridge generates single DW I/O read and write cycles. When the cycle completes on PCI bus, the bridge generates a corresponding completion on DMI. If the cycle is retried, the cycle is kept in the downbound queue and may be passed by a postable cycle.

5.1.2.3 Configuratio n Reads and Writes

The bridge generates single DW configuration read and write cycles. When the cycle completes on PCI bus, the bridge generates a corresponding completion. If the cycle is retried, the cycle is kept in the downbound queue and may be passed by a postable cycle.

5.1.2.4 Locked Cycles

The bridge propagates locks from DMI per the PCI specification. The PCI bridge implements bus lock, which means the arbiter will not grant to any agent except DMI while locked. If a locked read results in a target or master abort, the lock is not established (as per the PCI specification). Agents north of the ICH6 must not forward a subsequent locked read to the bridge if they see the first one finish with a failed completion.

5.1.2.5 Target / Master Aborts

When a cycle initiated by the bridge is master/target aborted, the bridge will not re-attempt the same cycle. For multiple DW cycles, the bridge increments the address and attempts the next DW of the transaction. For all non-postable cycles, a target abort response packet is returned for each DW that was master or target aborted on PCI. The bridge drops posted writes that abort.

5.1.2.6 Secondary Master Latency Timer

The bridge implements a Master Latency Timer via the SLT register which, upon expiration, causes the de-assertion of FRAME# at the next legal clock edge when there is another active request to use the PCI bus.

5.1.2.7 Dual Addr ess Cycle (DAC)

The bridge will issue full 64-bit dual address cycles for device memory-mapped registers above 4G B .

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 99 Functional Description

5.1.2.8 Memory and I/O Decode to PCI

The PCI bridge in the ICH6 is a subtractive decode agent, which follows the following rules when forwarding a cycle from DMI to the PCI interface:

• The PCI bridge will positively decode any memory I/O address within its window registers, assuming PCICMD.MSE (D30:F0:Offset 04h:bit 1) is set for memory windows and PCICMD.IOSE (D30:F0:Offset 04h:bit 0) is set for I/O windows.
• The PCI bridge will subtractively decode any 64-bit memory address not claimed by another agent, assuming PCICMD.MSE (D30:F0:Offset 04h:bit 1) is set.
• The PCI bridge will subtractively decode any 16-bit I/O address not claimed by another agent assuming PCICMD.IOSE (D30:F0:Offset 04h:bit 0) set
• If BCTRL.IE (D30:F0:Offset 3Eh:bit 2) is set, the PCI bridge will not positively forward from primary to secondary called out ranges in the I/O window per PCI specification (I/O transactions addressing the last 768 bytes in each, 1-KB block: offsets 100h to 3FFh). The PCI bridge will still take them subtractively assuming the above rules.
• If BCTRL.VGAE (D30:F0:Offset 3Eh:bit 3) is set, the PCI bridge will positively forward from primary to secondary I/O and memory ranges as called out in the PCI bridge specification, assuming the above rules are met.

5.1.3 Parity Error Det ection and Generation

PCI parity errors can be detected and reported. The following behavioral rules apply:

• When a parity error is detected on PCI, the bridge sets the SECSTS.DPE (D30:F0:Offset 1Eh:bit 15).
• If the bridge is a master and BCTRL.PERE (D30:F0:Offset 3Eh:bit 0) and one of the parity errors defined below is detected on PCI, then the bridge will set SECSTS.DPD (D30:F0:Offset 1Eh:bit 8) and will also generate an internal SERR#. — During a write cycle, the PERR# signal is active, or — A data parity error is detected while performing a read cycle
• If an address or command parity error is detected on PCI and PCICMD.SEE (D30:F0:Offset 04h:bit 8), BCTRL.PERE, and BCTRL.SEE (D30:F0:Offset 3Eh:bit 1) are all set, the bridge will set the PSTS.SSE (D30:F0:Offset 06h:bit 14) and generate an internal SERR#.
• If the PSTS.SSE is set because of an address parity error and the PCICMD.SEE is set, the bridge will generate an internal SERR#.
• When bad parity is detected from DMI, bad parity will be driven on all data the bridge.
• When an address parity error is detected on PCI, the PCI bridge will never claim the cycle. This is a slight deviation from the PCI bridge spec, which says that a cycle should be claimed if BCTRL.PERE is not set. However, DMI does not have a concept of address parity error, so claiming the cycle could result in the rest of the system seeing a bad transaction as a good transaction.

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5.1.4 PCIRST#

The PCIRST# pin is generated under two conditions:

• PLTRST# active
• BCTRL.SBR (D30:F0:Offset 3Eh:bit 6) set to 1 The PCIRST# pin is in the resume well. PCIRST# should be tied to PCI bus agents, but not other agents in the system.

5.1.5 Peer Cycles

The following peer cycles are supported: PCI Express to PCI Express Graphics (writes only), PCI to PCI Express Graphics (writes only) and PCI to PCI. Note: The ICH6’s AC ’97, IDE and USB controllers cannot perform peer-to-peer traffic.

5.1.6 PCI-to-PCI Bridge Model

From a software perspective, the ICH6 contains a PCI-to-PCI bridge. This bridge connects DMI to the PCI bus. By using the PCI-to-PCI bridge software model, the ICH6 can have its decode ranges programmed by existing plug-and-play software such that PCI ranges do not conflict with graphics aperture ranges in the Host controller.

5.1.7 IDSEL to Device Number Mapping

When addressing devices on the external PCI bus (with the PCI slots), the ICH6 asserts one address signal as an IDSEL. When accessing device 0, the ICH6 asserts AD16. When accessing Device 1, the ICH6 asserts AD17. This mapping continues all the way up to device 15 where the ICH6 asserts AD31. Note that the ICH6’s internal functions (AC ’97, Intel High Definition Audio, IDE, USB, SATA and PCI Bridge) are enumerated like they are off of a separate PCI bus (DMI) from the external PCI bus. The integrated LAN controller is Device 8 on the ICH6’s PCI bus, and hence it uses AD[24] for IDSEL.

5.1.8 Standard PCI Bus Configuration Mechanism

The PCI Bus defines a slot based “configuration space” that allows each device to contain up to eight functions with each function containing up to 256, 8-bit configuration registers. The PCI Local Bus Specification, Revision 2.3 defines two bus cycles to access the PCI configuration space: Configuration Read and Configuration Write. Memory and I/O spaces are supported directly by the processor. Configuration space is supported by a mapping mechanism implemented within the ICH6. The PCI Local Bus Specification, Revision 2.3 defines two mechanisms to access configuration space, Mechanism 1 and Mechanism 2. The ICH6 only supports Mechanism 1. Warning: Configuration writes to internal devices, when the devices are disabled, are illegal and may cause undefined results.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 101 Functional Description

5.2 PCI Express* Root Ports (D28:F0,F1,F2,F3)

PCI Express is the next generation high performance general input/output architecture. PCI Express is a high speed, low voltage, serial pathway for two devices to communicate simultaneously by implementing dual unidirectional paths between two devices. PCI Express has been defined to be 100-percent compatible with conventional PCI compliant operating systems and their corresponding bus enumeration and configuration software. All PCI Express hardware elements have been defined with a PCI-compatible configuration space representation. PCI Express replaces the device-based arbitration process of conventional PCI with flow-control - based link arbitration that allows data to pass up and down the link based upon traffic class priority. High priority is given to traffic classes that require guaranteed bandwidth such as isochronous transactions while room is simultaneously made for lower priority transactions to avoid bottlenecks. The ICH6 provides 4 (x1) PCI Express ports with each port supporting up to 5 Gb/s concurrent bandwidth (2.5 Gb/s in each direction). These all reside in device 28, and take function 0 – 3. Port 1 is function 0, port 2 is function 1, port 3 is function 2, and port 4 is function 3.

5.2.1 Interrupt Generation

The root port generates interrupts on behalf of Hot-Plug and power management events, when enabled. These interrupts can either be pin based, or can be MSIs, when enabled. When an interrupt is generated via the legacy pin, the pin is internally routed to the ICH6 interrupt controllers. The pin that is driven is based upon the setting of the chipset configuration registers. Specifically, the chipset configuration registers used are the D28IP (Base address + 310Ch) and D28IR (Base address + 3146h) registers. The following table summarizes interrupt behavior for MSI and wire-modes. In the table “bits” refers to the Hot-Plug and PME interrupt bits. Table 5-2. MSI vs. PCI IRQ Actions Interrupt Register Wire-Mode Action MSI Action All bits 0 Wire inactive No action One or more bits set to 1 Wire active Send message One or more bits set to 1, new bit gets set to 1 Wire active Send message One or more bits set to 1, software clears some (but not all) bits Wire active Send message One or more bits set to 1, software clears all bits Wire inactive No action Software clears one or more bits, and one or more bits are set on the same clock Wire active Send message

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5.2.2 Power Management

5.2.2.1 S3/S4/S5 Support

Software initiates the transition to S3/S4/S5 by performing an I/O write to the Power Management Control register in the ICH6. After the I/O write completion has been returned to the processor, each root port will send a PME_Turn_Off TLP (Transaction Layer Packet) message on it's downstream link. The device attached to the link will eventually respond with a PME_TO_Ack TLP message followed by sending a PM_Enter_L23 DLLP (Data Link Layer Packet) request to enter the L2/L3 Ready state. When all of the ICH6 root ports links are in the L2/L3 Ready state, the ICH6 power management control logic will proceed with the entry into S3/S4/S5. Prior to entering S3, software is required to put each device into D3 HOT. When a device is put into D3HOT it will initiate entry into a L1 link state by sending a PM_Enter_L1 DLLP. Thus under normal operating conditions when the root ports sends the PME_Turn_Off message the link will be in state L1. However, when the root port is instructed to send the PME_Turn_Off message, it will send it whether or not the link was in L1. Endpoints attached to ICH6 can make no assumptions about the state of the link prior to receiving a PME_Turn_Off message.

5.2.2.2 Resuming from Suspended State

The root port contains enough circuitry in the resume well to detect a wake event thru the WAKE# signal and to wake the system. When WAKE# is detected asserted, an internal signal is sent to the power management controller of the ICH6 to cause the system to wake up. This internal message is not logged in any register, nor is an interrupt/GPE generated due to it.

5.2.2.3 Device Initiated PM_PME Message

When the system has returned to a working state from a previous low power state, a device requesting service will send a PM_PME message continuously, until acknowledge by the root port. The root port will take different actions depending upon whether this is the first PM_PME has been received, or whether a previous message has been received but not yet serviced by the operating system. If this is the first message received (RSTS.PS - D28:F0/F1/F2/F3:Offset 60h:bit 16 is cleared), the root port will set RSTS.PS, and log the PME Requester ID into RSTS.RID (D28:F0/F1/F2/ F3:Offset 60h:bits 15:0). If an interrupt is enabled via RCTL.PIE (D28:F0/F1/F2/F3:Offset 5Ch:bit 3), an interrupt will be generated. This interrupt can be either a pin or an MSI if MSI is generation. If this is a subsequent message received (RSTS.PS is already set), the root port will set RSTS.PP (D28:F0/F1/F2/F3:Offset 60h:bit 17) and log the PME Requester ID from the message in a hidden register. No other action will be taken. When the first PME event is cleared by software clearing RSTS.PS, the root port will set RSTS.PS, clear RSTS.PP, and move the requester ID from the hidden register into RSTS.RID. If RCTL.PIE is set, generate an interrupt. If RCTL.PIE is not set, send over to the power management controller so that a GPE can be set. If messages have been logged (RSTS.PS is set), and RCTL.PIE is later written from a 0 to a 1, and interrupt must be generated. This last condition handles the case where the message was received prior to the operating system re-enabling interrupts after resuming from a low power state.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 103 Functional Description

5.2.2.4 SMI/SCI Generation

Interrupts for power management events are not supported on legacy operating systems. To support power management on non-PCI Express aware operating systems, PM events can be routed to generate SCI. To generate SCI, MPC.PMCE must be set. When set, a power management event will cause SMSCS.PMCS (D28:F0/F1/F2/F3:Offset DCh:bit 31) to be set. Additionally, BIOS workarounds for power management can be supported by setting MPC.PMME (D28:F0/F1/F2/F3:Offset D8h:bit 0). When this bit is set, power management events will set SMSCS.PMMS (D28:F0/F1/F2/F3:Offset DCh:bit 0), and SMI # will be generated. This bit will be set regardless of whether interrupts or SCI is enabled. The SMI# may occur concurrently with an interrupt or SCI.

5.2.3 SERR# Generation

SERR# may be generated via two paths; through PCI mechanisms involving bits in the PCI header, or through PCI Express mechanisms involving bits in the PCI Express capability structure.

5.2.4 Hot-Plug

Each root port implements a Hot-Plug controller which performs the following:

• Messages to turn on / off / blink LEDs
• Presence and attention button detection
• Interrupt generation The root port only allows Hot-Plug with modules (e.g., ExpressCard*). Edge-connector based Hot- Plug is not supported.

5.2.4.1 Presence Detection

When a module is plugged in and power is supplied, the physical layer will detect the presence of the device, and the root port sets SLSTS.PDS (D28:F0/F1/F2/F3:Offset 5Ah:bit 6) and SLSTS.PDC (D28:F0/F1/F2/F3:Offset 6h:bit 3). If SLCTL.PDE (D28:F0/F1/F2/F3:Offset 58h: bit 3) and SLCTL.HPE (D28:F0/F1/F2/F3:Offset 58h:bit 5) are both set, the root port will also generate an interrupt. Figure 5-1. Generation of SERR# to Platform PSTS.SSE SERR#PCICMD.SEE Secondary Parity Error Primary Parity Error Secondary SERR# Correctable SERR# Fatal SERR# Non-Fatal SERR# PCI PCI Express

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When a module is removed (via the physical layer detection), the root port clears SLSTS.PDS and sets SLSTS.PDC. If SLCTL.PDE and SLCTL.HPE are both set, the root port will also generate an interrupt.

5.2.4.2 Message Generation

When system software writes to SLCTL.AIC (D28:F0/F1/F2/F3:Offset 58h:bits 7:6) or SLCTL.PIC (D28:F0/F1/F2/F3:Offset 58h:bits 9:8), the root port will send a message down the link to change the state of LEDs on the module. Writes to these fields are non-postable cycles, and the resulting message is a postable cycle. When receiving one of these writes, the root port performs the following:

• Changes the state in the register
• Generates a completion into the upstream queue
• Formulates a message for the downstream port if the field is written to regardless of if the field changed
• Generates the message on the downstream port
• When the last message of a command is transmitted, sets SLSTS.CCE (D28:F0/F1/F2/ F3:Offset 58h:bit 4) to indicate the command has completed. If SLCTL.CCE and SLCTL.HPE (D28:F0/F1/F2/F3:Offset 58h:bit 5) are set, the root port generates an interrupt. The command completed register (SLSTS.CC) applies only to commands issued by software to control the Attention Indicator (SLCTL.AIC), Power Indicator (SLCTL.PIC), or Power Controller (SLCTL.PCC). However, writes to other parts of the Slot Control Register would invariably end up writing to the indicators and power controller fields. Hence, any write to the Slot Control Register is considered a command and if enabled, will result in a command complete interrupt. The only exception to this rule is a write to disable the command complete interrupt which will not result in a command complete interrupt. A single write to the Slot Control register is considered to be a single command, and hence receives a single command complete, even if the write affects more than one field in the Slot Control Register.

5.2.4.3 Attention Button Detection

When an attached device is ejected, an attention button could be pressed by the user. This attention button press will result in a the PCI Express message “Attention_Button_Pressed” from the device. Upon receiving this message, the root port will set SLSTS.ABP (D28:F0/F1/F2/F3:Offset 5Ah:bit 0). If SLCTL.ABE (D28:F0/F1/F2/F3:Offset 58h:bit 0) and SLCTL.HPE (D28:F0/F1/F2/F3:Offset 58h:bit 5) are set, the Hot-Plug controller will also generate an interrupt. The interrupt is generated on an edge-event. For example, if SLSTS.ABP is already set, a new interrupt will not be generated.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 105 Functional Description

5.2.4.4 SMI/SCI Generation

Interrupts for Hot-Plug events are not supported on legacy operating systems. To support Hot-Plug on non-PCI Express aware operating systems, Hot-Plug events can be routed to generate SCI. To generate SCI, MPC.HPCE (D28:F0/F1/F2/F3:Offset D8h:bit 30) must be set. When set, enabled Hot-Plug events will cause SMSCS.HPCS (D28:F0/F1/F2/F3:Offset DCh:bit 30) to be set. Additionally, BIOS workarounds for Hot-Plug can be supported by setting MPC.HPME (D28:F0/ F1/F2/F3:Offset D8h:bit 1). When this bit is set, Hot-Plug events can cause SMI status bits in SMSCS to be set. Supported Hot-Plug events and their corresponding SMSCS bit are:

• Command Completed – SMSCS.HPCCM (D28:F0/F1/F2/F3:Offset DCh:bit 3)
• Presence Detect Changed – SMSCS.HPPDM (D28:F0/F1/F2/F3:Offset DCh:bit 1)
• Attention Button Pressed – SMSCS.HPABM (D28:F0/F1/F2/F3:Offset DCh:bit 2) When any of these bits are set, SMI # will be generated. These bits are set regardless of whether interrupts or SCI is enabled for Hot-Plug events. The SMI# may occur concurrently with an interrupt or SCI.

5.3 LAN Controller (B1:D8:F0)

The ICH6’s integrated LAN controller includes a 32-bit PCI controller that provides enhanced scatter-gather bus mastering capabilities and enables the LAN controller to perform high-speed data transfers over the PCI bus. Its bus master capabilities enable the component to process high level commands and perform multiple operations; this lowers processor utilization by off-loading communication tasks from the processor. Two large transmit and receive FIFOs of 3 KB each, help prevent data underruns and overruns while waiting for bus accesses. This enables the integrated LAN controller to transmit data with minimum interframe spacing (IFS). The ICH6 integrated LAN controller can operate in either full-duplex or half-duplex mode. In full- duplex mode the LAN controller adheres with the IEEE 802.3x Flow Control Specification. Half duplex performance is enhanced by a proprietary collision reduction mechanism. The integrated LAN controller also includes an interface to a serial (4-pin) EEPROM. The EEPROM provides power-on initialization for hardware and software configuration parameters. From a software perspective, the integrated LAN controller appears to reside on the secondary side of the ICH6’s virtual PCI-to-PCI bridge (see Section 5.1.6). This is typically Bus 1, but may be assigned a different number, depending upon system configuration. The following summarizes the ICH6 LAN controller features:

• Compliance with Advanced Configuration and Power Interface and PCI Power Management standards
• Support for wake-up on interesting packets and link status change
• Support for remote power-up using Wake on LAN* (WOL) technology
• Deep power-down mode support
• Support of Wired for Management (WfM) Revision 2.0
• Backward compatible software with 82550, 82557, 82558 and 82559
• TCP/UDP checksum off load capabilities
• Support for Intel’s Adaptive Technology

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5.3.1 LAN Controller PCI Bus Interface

As a Fast Ethernet controller, the role of the ICH6 integrated LAN controller is to access transmitted data or deposit received data. The LAN controller, as a bus master device, initiates memory cycles via the PCI bus to fetch or deposit the required data. To perform these actions, the LAN controller is controlled and examined by the processor via its control and status structures and registers. Some of these control and status structures reside in the LAN controller and some reside in system memory. For access to the LAN controller’s Control/ Status Registers (CSR), the LAN controller acts as a slave (in other words, a target device). The LAN controller serves as a slave also while the processor accesses the EEPROM.

5.3.1.1 Bus Slave Operation

The ICH6 integrated LAN controller serves as a target device in one of the following cases:

• Processor accesses to the LAN controller System Control Block (SCB) Control/Status Registers (CSR)
• Processor accesses to the EEPROM through its CSR
• Processor accesses to the LAN controller PORT address via the CSR
• Processor accesses to the MDI control register in the CSR The size of the CSR memory space is 4 KB in the memory space and 64 bytes in the I/O space. The LAN controller treats accesses to these memory spaces differently. Control/Status Register (CSR) Accesses The integrated LAN controller supports zero wait-state single cycle memory or I/O mapped accesses to its CSR space. Separate BARs request 4 KB of memory space and 64 bytes of I/O space to accomplish this. Based on its needs, the software driver uses either memory or I/O mapping to access these registers. The LAN controller provides four valid KB of CSR space that include the following elements:
• System Control Block (SCB) registers
• PORT register
• EEPROM control register
• MDI control register
• Flow control registers In the case of accessing the Control/Status Registers, the processor is the initiator and the LAN controller is the target. Retry Premature Accesses The LAN controller responds with a Retry to any configuration cycle accessing the LAN controller before the completion of the automatic read of the EEPROM. The LAN controller may continue to Retry any configuration accesses until the EEPROM read is complete. The LAN controller does not enforce the rule that the retried master must attempt to access the same address again in order to complete any delayed transaction. Any master access to the LAN controller after the completion of the EEPROM read is honored.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 107 Functional Description Error Handling Data Parity Errors: The LAN controller checks for data parity errors while it is the target of the transaction. If an error was detected, the LAN controller always sets the Detected Parity Error bit in the PCI Configuration Status register, bit 15. The LAN controller also asserts PERR#, if the Parity Error Response bit is set (PCI Configuration Command register, bit 6). The LAN controller does not attempt to terminate a cycle in which a parity error was detected. This gives the initiator the option of recovery. Target-Disconnect: The LAN controller prematurely terminate a cycle in the following cases:

• After accesses to its CSR
• After accesses to the configuration space System Error: The LAN controller reports parity error during the address phase using the SERR# pin. If the SERR# Enable bit in the PCI Configuration Command register or the Parity Error Response bit are not set, the LAN controller only sets the Detected Parity Error bit (PCI Configuration Status register, bit 15). If SERR# Enable and Parity Error Response bits are both set, the LAN controller sets the Signaled System Error bit (PCI Configuration Status register, bit 14) as well as the Detected Parity Error bit and asserts SERR# for one clock. The LAN controller, when detecting system error, claims the cycle if it was the target of the transaction and continues the transaction as if the address was correct. Note: The LAN controller reports a system error for any error during an address phase, whether or not it is involved in the current transaction.

5.3.1.2 CLKRUN# Signal (Mobile Only)

The ICH6 receives a free-running 33 MHz clock. It does not stop based on the CLKRUN# signal and protocol. When the LAN controller runs cycles on the PCI bus, the ICH6 makes sure that the STP_PCI# signal is high indicating that the PCI clock will be running. This is to make sure that any PCI tracker does not get confused by transactions on the PCI bus with its PCI clock stopped.

5.3.1.3 PCI Power Management

Enhanced support for the power management standard, PCI Local Bus Specification, Revision 2.3, is provided in the ICH6 integrated LAN controller. The LAN controller supports a large set of wake-up packets and the capability to wake the system from a low power state on a link status change. The LAN controller enables the host system to be in a sleep state and remain virtually connected to the network. After a power management event or link status change is detected, the LAN controller wakes the host system. The sections below describe these events, the LAN controller power states, and estimated power consumption at each power state. The LAN controller contains power management registers for PCI, and implements four power states, D0 through D3, which vary from maximum power consumption at D0 to the minimum power consumption at D3. PCI transactions are only allowed in the D0 state, except for host accesses to the LAN controller’s PCI configuration registers. The D1 and D2 power management states enable intermediate power savings while providing the system wake-up capabilities. In the D3COLD state, the LAN controller can provide wake-up capabilities. Wake-up indications from the LAN controller are provided by the Power Management Event (PME#) signal.

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5.3.1.4 PCI Reset Signal

The PCIRST# signal may be activated in one of the following cases:

• During S3–S5 states
• Due to a CF9h reset If PME is enabled (in the PCI power management registers), PCIRST# assertion does not affect any PME related circuits (in other words, PCI power management registers and the wake-up packet would not be affected). While PCIRST# is active, the LAN controller ignores other PCI signals. The configuration of the LAN controller registers associated with ACPI wake events is not affected by PCIRST#. The integrated LAN controller uses the PCIRST# or the PWROK signal as an indication to ignore the PCI interface. Following the de-assertion of PCIRST#, the LAN controller PCI Configuration Space, MAC configuration, and memory structure are initialized while preserving the PME# signal and its context.

5.3.1.5 Wake-Up Events

There are two types of wake-up events: “Interesting” Packets and Link Status Change. These two events are detailed below. Note: If the Wake on LAN bit in the EEPROM is not set, wake-up events are supported only if the PME Enable bit in the Power Management Control/Status Register (PMCSR) is set. However, if the Wake on LAN bit in the EEPROM is set, and Wake on Magic Packet* or Wake on Link Status Change are enabled, the Power Management Enable bit is ignored with respect to these events. In the latter case, PME# would be asserted by these events. “Interesting” Packet Event In the power-down state, the LAN controller is capable of recognizing “interesting” packets. The LAN controller supports predefined and programmable packets that can be defined as any of the following:

• ARP Packets (with Multiple IP addresses)
• Direct Packets (with or without type qualification)
• Magic Packet
• Neighbor Discovery Multicast Address Packet (‘ARP’ in IPv6 environment)
• NetBIOS over TCP/IP (NBT) Query Packet (under IPv4)
• Internetwork Package Exchange* (IPX) Diagnostic Packet This allows the LAN controller to handle various packet types. In general, the LAN controller supports programmable filtering of any packet in the first 128 bytes.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 109 Functional Description When the LAN controller is in one of the low power states, it searches for a predefined pattern in the first 128 bytes of the incoming packets. The only exception is the Magic Packet, which is scanned for the entire frame. The LAN controller classifies the incoming packets as one of the following categories:

• No Match: The LAN controller discards the packet and continues to process the incoming packets.
• TCO Packet: The LAN controller implements perfect filtering of TCO packets. After a TCO packet is processed, the LAN controller is ready for the next incoming packet. TCO packets are treated as any other wake-up packet and may assert the PME# signal if configured to do so.
• Wake-up Packet: The LAN controller is capable of recognizing and storing the first 128 bytes of a wake-up packet. If a wake-up packet is larger than 128 bytes, its tail is discarded by the LAN controller. After the system is fully powered-up, software has the ability to determine the cause of the wake-up event via the PMDR and dump the stored data to the host memory. Magic Packets are an exception. The Magic Packets may cause a power management event and set an indication bit in the PMDR; however, it is not stored by the LAN controller for use by the system when it is woken up. Link Status Change Event The LAN controller link status indication circuit is capable of issuing a PME on a link status change from a valid link to an invalid link condition or vice versa. The LAN controller reports a PME link status event in all power states. If the Wake on LAN bit in the EEPROM is not set, the PME# signal is gated by the PME Enable bit in the PMCSR and the CSMA Configure command.

5.3.1.6 Wake on LAN* (Preboot Wake-Up)

The LAN controller enters Wake on LAN mode after reset if the Wake on LAN bit in the EEPROM is set. At this point, the LAN controller is in the D0u state. When the LAN controller is in Wake on LAN mode:

• The LAN controller scans incoming packets for a Magic Packet and asserts the PME# signal for 52 ms when a 1 is detected in Wake on LAN mode.
• The Activity LED changes its functionality to indicates that the received frame passed Individual Address (IA) filtering or broadcast filtering.
• The PCI Configuration registers are accessible to the host. The LAN controller switches from Wake on LAN mode to the D0a power state following a setup of the Memory or I/O Base Address Registers in the PCI Configuration space.

5.3.2 Serial EEPROM Interface

The serial EEPROM stores configuration data for the ICH6 integrated LAN controller and is a serial in/serial out device. The LAN controller supports a 64-register or 256-register size EEPROM and automatically detects the EEPROM’s size. The EEPROM should operate at a frequency of at least 1 MHz. All accesses, either read or write, are preceded by a command instruction to the device. The address field is six bits for a 64-register EEPROM or eight bits for a 256-register EEPROM. The end of the address field is indicated by a dummy 0 bit from the EEPROM, which indicates the entire address field has been transferred to the device. An EEPROM read instruction waveform is shown in Figure 5-2.

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The LAN controller performs an automatic read of seven words (0h, 1h, 2h, Ah, Bh, Ch, and Dh) of the EEPROM after the de-assertion of Reset.

5.3.3 CSMA/CD Unit

The ICH6 integrated LAN controller CSMA/CD unit implements both the IEEE 802.3 Ethernet 10 Mbps and IEEE 802.3u Fast Ethernet 100 Mbps standards. It performs all the CSMA/CD protocol functions (e.g., transmission, reception, collision handling, etc.). The LAN controller CSMA/CD unit interfaces to the 82562ET/EM/EZ/EX 10/100 Mbps Ethernet through the ICH6’s LAN Connect interface signals.

5.3.3.1 Full Duplex

When operating in full-duplex mode, the LAN controller can transmit and receive frames simultaneously. Transmission starts regardless of the state of the internal receive path. Reception starts when the platform LAN Connect component detects a valid frame on its receive differential pair. The ICH6 integrated LAN controller also supports the IEEE 802.3x flow control standard, when in full-duplex mode. The LAN controller operates in either half-duplex mode or full-duplex mode. For proper operation, both the LAN controller CSMA/CD module and the discrete platform LAN Connect component must be set to the same duplex mode. The CSMA duplex mode is set by the LAN Controller Configure command or forced by automatically tracking the mode in the platform LAN Connect component. Following reset, the CSMA defaults to automatically track the platform LAN Connect component duplex mode. The selection of duplex operation (full or half) and flow control is done in two levels: MAC and LAN Connect. Figure 5-2. 64-Word EEPROM Read Instruction Waveform A1A0 EE_CS EE_SHCLKK EE_DIN EE_DOUT A5 A4 A2 D15 D0 READ OP code A3 A1 A0

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 111 Functional Description

5.3.3.2 Flow Control

The LAN controller supports IEEE 802.3x frame-based flow control frames only in both full duplex and half duplex switched environments. The LAN controller flow control feature is not intended to be used in shared media environments. Flow control is optional in full-duplex mode and is selected through software configuration. There are three modes of flow control that can be selected: frame-based transmit flow control, frame- based receive flow control, and none.

5.3.3.3 VLAN Support

The LAN controller supports the IEEE 802.1 standard VLAN. All VLAN flows will be implemented by software. The LAN controller supports the reception of long frames, specifically frames longer than 1518 bytes, including the CRC, if software sets the Long Receive OK bit in the Configuration command. Otherwise, “long” frames are discarded.

5.3.4 Media Management Interface

The management interface allows the processor to control the platform LAN Connect component via a control register in the ICH6 integrated LAN controller. This allows the software driver to place the platform LAN Connect in specific modes (e.g., full duplex, loopback, power down, etc.) without the need for specific hardware pins to select the desired mode. This structure allows the LAN controller to query the platform LAN Connect component for status of the link. This register is the MDI Control Register and resides at offset 10h in the LAN controller CSR. The MDI registers reside within the platform LAN Connect component, and are described in detail in the platform LAN Connect component’s datasheet. The processor writes commands to this register and the LAN controller reads or writes the control/status parameters to the platform LAN Connect component through the MDI register.

5.3.5 TCO Functionality

The ICH6 integrated LAN controller supports management communication to reduce Total Cost of Ownership (TCO). The SMBus is used as an interface between the ASF controller and the integrated TCO host controller. There are two different types of TCO operation that are supported (only one supported at a time), they are 1) Integrated ASF Control or 2) external TCO controller support. The SMLink is a dedicated bus between the LAN controller and the integrated ASF controller (if enabled) or an external management controller. An EEPROM of 256 words is required to support the heartbeat command.

5.3.5.1 Advanced TCO Mode

The Advanced TCO functionalities through the SMLink are listed in Table 5-3.

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Note: For a complete description on various commands, see the Total Cost of Ownership (TCO) System Management Bus Interface Application Note (AP-430). Transmit Command during Normal Operation To serve a transmit request from the TCO controller, the ICH6 LAN controller first completes the current transmit DMA, sets the TCO request bit in the PMDR register (see Section 8.2), and then responds to the TCO controller’s transmit request. Following the completion of the TCO transmit DMA, the LAN controller increments the Transmit TCO statistic counter (described in Section 8.2.14). Following the completion of the transmit operation, the ICH6 increments the nominal transmit statistic counters, clears the TCO request bit in the PMDR register, and resumes its normal transmit flow. The receive flow is not affected during this entire period of time. Receive TCO The ICH6 LAN controller supports receive flow towards the TCO controller. The ICH6 can transfer only TCO packets, or all packets that passed MAC address filtering according to its configuration and mode of operation as detailed below. While configured to transfer only TCO packets, it supports Ethernet type II packets with optional VLAN tagging. Force TCO Mode: While the ICH6 is in the force TCO mode, it may receive packets (TCO or all) directly from the TCO controller. Receiving TCO packets and filtering level is controlled by the set Receive enable command from the TCO controller. Following a reception of a TCO packet, the ICH6 increments its nominal Receive statistic counters as well as the Receive TCO counter. Dx>0 Power State: While the ICH6 is in a powerdown state, it may receive TCO packets or all directly to the TCO controller. Receiving TCO packets is enabled by the set Receive enable command from the TCO controller. Although TCO packet might match one of the other wake up filters, once it is transferred to the TCO controller, no further matching is searched for and PME is not issued. While receive to TCO is not enabled, a TCO packet may cause a PME if configured to do so (setting TCO to 1 in the filter type). D0 Power State: At D0 power state, the ICH6 may transfer TCO packets to the TCO controller. At this state, TCO packets are posted first to the host memory, then read by the ICH6, and then posted back to the TCO controller. After the packet is posted to TCO, the receive memory structure (that is occupied by the TCO packet) is reclaimed. Other than providing the necessary receive resources, there is no required device driver intervention with this process. Eventually, the ICH6 increments the receive TCO static counter, clears the TCO request bit, and resumes normal control. Table 5-3. Advanced TCO Functionality Power State TCO Controller Functionality D0 nominal Transmit Set Receive TCO Packets Receive TCO Packets Read ICH6 status (PM & Link state) Force TCO Mode Dx (x>0) D0 functionality plus: Read PHY registers Force TCO Mode Dx functionality plus: Configuration commands Read/Write PHY registers

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 113 Functional Description Read ICH6 Status (PM and Link State) The TCO controller is capable of reading the ICH6 power state and link status. Following a status change, the ICH6 asserts LINKALERT# and then the TCO can read its new power state. Set Force TCO Mode The TCO controller put the ICH6 into the Force TCO mode. The ICH6 is set back to the nominal operation following a PCIRST#. Following the transition from nominal mode to a TCO mode, the ICH6 aborts transmission and reception and loses its memory structures. The TCO may configure the ICH6 before it starts transmission and reception if required. Warning: The Force TCO is a destructive command. It causes the ICH6 to lose its memory structures, and during the Force TCO mode the ICH6 ignores any PCI accesses. Therefore, it is highly recommended to use this command by the TCO controller at system emergency only.

5.4 Alert Standard Format (ASF)

The ASF controller collects information from various components in the system (including the processor, chipset, BIOS, and sensors on the motherboard) and sends this information via the LAN controller to a remote server running a management console. The controller also accepts commands back from the management console and drives the execution of those commands on the local system. The ASF controller is responsible for monitoring sensor devices and sending packets through the LAN controller SMBus (System Management Bus) interface. These ASF controller alerting capabilities include system health information (such as BIOS messages, POST alerts, operating system failure notifications, and heartbeat signals) to indicate the system is accessible to the server. Also included are environmental notification (e.g., thermal, voltage and fan alerts) that send proactive warnings that something is wrong with the hardware. The packets are used as Alert (S.O.S.) packets or as “heartbeat” status packets. In addition, asset security is provided by messages (e.g., “cover tamper” and “processor missing”) that notify of potential system break-ins and processor or memory theft. The ASF controller is also responsible for receiving and responding to RMCP (Remote Management and Control Protocol) packets. RMCP packets are used to perform various system APM commands (e.g., reset, power-up, power-cycle, and power-down). RMCP can also be used to ping the system to ensure that it is on the network and running correctly and for capability reporting. A major advantage of ASF is that it provides these services during the time that software is unable to do so (e.g., during a low-power state, during boot-up, or during an operating system hang) but are not precluded from running in the working state. The ASF controller communicates to the system and the LAN controller logic through the SMBus connections. The first SMBus connects to the host SMBus controller (within the ICH6) and any SMBus platform sensors. The SMBus host is accessible by the system software, including software running on the operating system and the BIOS. Note that the host side bus may require isolation if there are non-auxiliary devices that can pull down the bus when un-powered. The second SMBus connects to the LAN controller. This second SMBus is used to provide a transmit/receive network interface. The stimulus for causing the ASF controller to send packets can be either internal or external to the ASF controller. External stimuli are link status changes or polling data from SMBus sensor devices; internal events come from, among others, a set of timers or an event caused by software.

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The ASF controller provides three local configuration protocols via the host SMBus. The first one is the SMBus ARP interface that is used to identify the SMBus device and allow dynamic SMBus address assignment. The second protocol is the ASF controller command set that allows software to manage an ASF controller compliant interface for retrieving info, sending alerts, and controlling timers. ICH6 provides an input and an output EEPROM interface. The EEPROM contains the LAN controller configuration and the ASF controller configuration/packet information.

5.4.1 ASF Management Solu tion Features/Capabilities

• Alerting — Transmit SOS packets from S0–S5 states — System Health Heartbeats — SOS Hardware Events - System Boot Failure (Watchdog Expires on boot) - LAN Link Loss - Entity Presence (on ASF power-up) - SMBus Hung - Maximum of eight Legacy Sensors - Maximum of 128 ASF Sensor events — Watchdog Timer for operating system lockup/System Hang/Failure to Boot — General Push support for BIOS (POST messages)
• Remote Control — Presence Ping Response — Configurable Boot Options — Capabilities Reporting — Auto-ARP Support — System Remote Control - Power-Down - Power-Up - Power Cycle - System Reset — State-Based Security – Conditional Action on WatchDog Expire
• ASF Compliance — Compliant with the Alert Standard Format (ASF) Specification, Version 1.03 - PET Compliant Packets - RMCP - Legacy Sensor Polling - ASF Sensor Polling - Remote Control Sensor Support
• Advanced Features / Miscellaneous — SMBus 2.0 compliant — Optional reset extension logic (for use with a power-on reset)

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5.4.2 ASF Hardware Support

ASF requires additional hardware to make a complete solution. Note: If an ASF compatible device is externally connected and properly configured, the internal ICH6 ASF controller will be disabled. The external ASF device will have access to the SMBus controller. 5.4.2.1 82562EM/EX The 82562EM/EX Ethernet LAN controller is necessary. This LAN controller provides the means of transmitting and receiving data on the network, as well as adding the Ethernet CRC to the data from the ASF.

5.4.2.2 EEPROM (256x16, 1 MHz)

To support the ICH6 ASF solution, a larger, 256x16 1 MHz, EEPROM is necessary to configure defaults on reset and on hard power losses (software un-initiated). The ASF controller shares this EEPROM with the LAN controller and provides a pass through interface to achieve this. The ASF controller expects to have exclusive access to words 40h through F7h. The LAN controller can use the other EEPROM words. The ASF controller will default to safe defaults if the EEPROM is not present or not configured properly (both cause an invalid CRC).

5.4.2.3 Legacy Sensor SMBus Devices

The ASF controller is capable of monitoring up to eight sensor devices on the main SMBus. These sensors are expected to be compliant with the Legacy Sensor Characteristics defined in the Alert Standard Format (ASF) Specification, Version 1.03.

5.4.2.4 Remote Control SMBus Devices

The ASF controller is capable of causing remote control actions to Remote Control devices via SMBus. These remote control actions include Power-Up, Power-Down, Power-Cycle, and Reset. The ASF controller supports devices that conform to the Alert Standard Format (ASF) Specification, Version 1.03., Remote Control Devices.

5.4.2.5 ASF Sensor SMBus Devices

The ASF controller is capable of monitoring up to 128 ASF sensor devices on the main SMBus. However, ASF is restricted by the number of total events which may reduce the number of SMBus devices supported. The maximum number of events supported by ASF is 128. The ASF sensors are expected to operate as defined in the Alert Standard Format (ASF) Specification, Version 1.03.

5.4.3 ASF Software Support

ASF requires software support to make a complete solution. The following software is used as part of the complete solution.

• ASF Configuration driver / application
• Network Driver
• BIOS Support for SMBIOS, SMBus ARP, ACPI
• Sensor Configuration driver / application Note: Contact your Intel Field Representative for the Client ASF Software Development Kit (SDK) that includes additional documentation and a copy of the client ASF software drivers. Intel also provides an ASF Console SDK to add ASF support to a management console.

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5.5 LPC Bridge (w/ System and Management Functions)

(D31:F0) The LPC bridge function of the ICH6 resides in PCI Device 31:Function 0. In addition to the LPC bridge function, D31:F0 contains other functional units including DMA, Interrupt controllers, Timers, Power Management, System Management, GPIO, and RTC. In this chapter, registers and functions associated with other functional units (power management, GPIO, USB, IDE, etc.) are described in their respective sections.

5.5.1 LPC Interface

The ICH6 implements an LPC interface as described in the Low Pin Count Interface Specification, implements all of the signals that are shown as optional, but peripherals are not required to do so. Figure 5-3. LPC Interface Diagram LAD[3:0] Intel® ICH6 LPC Device LDRQ# (optional) LFRAME# PCI CLK PCI RST# PCI SERIRQ PCI PME# PCI Bus SUS_STAT# GPI LSMI# (optional) LPCPD# (optional)

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5.5.1.1 LPC Cycle Types

The ICH6 implements all of the cycle types described in the Low Pin Count Interface Specification, Revision 1.0. Table 5-4 shows the cycle types supported by the ICH6. NOTES: 1. For memory cycles below 16 MB that do not target enabled firmware hub ranges, the ICH6 performs standard LPC memory cycles. It only attempts 8-bit transfers. If the cycle appears on PCI as a 16-bit transfer, it appears as two consecutive 8-bit transfers on LPC. Likewise, if the cycle appears as a 32-bit transfer on PCI, it appears as four consecutive 8-bit transfers on LPC. If the cycle is not claimed by any peripheral, it is subsequently aborted, and the ICH6 returns a value of all 1s to the processor. This is done to maintain compatibility with ISA memory cycles where pull-up resistors would keep the bus high if no device responds. 2. Bus Master Read or Write cycles must be naturally aligned. For example, a 1-byte transfer can be to any address. However, the 2-byte transfer must be word-aligned (i.e., with an address where A0=0). A DWord transfer must be DWord-aligned (i.e., with an address where A1 and A0 are both 0).

5.5.1.2 Start Field Definition

NOTE: All other encodings are RESERVED. Table 5-4. LPC Cycle Types Supported Cycle Type Comment Memory Read Single: 1 byte only Memory Write Single: 1 byte only I/O Read 1 byte only. Intel® ICH6 breaks up 16- and 32-bit processor cycles into multiple 8-bit transfers. See Note 1 below. I/O Write 1 byte only. ICH6 breaks up 16- and 32-bit processor cycles into multiple 8-bit transfers. See Note 1 below. DMA Read Can be 1, or 2 bytes DMA Write Can be 1, or 2 bytes Bus Master Read Can be 1, 2, or 4 bytes. (See Note 2 below) Bus Master Write Can be 1, 2, or 4 bytes. (See Note 2 below) Table 5-5. Start Field Bit Definitions Bits[3:0] Encoding Definition

0000 Start of cycle for a generic target

0010 Grant for bus master 0

0011 Grant for bus master 1

1111 Stop/Abort: End of a cycle for a target.

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5.5.1.3 Cycle Type / Di rection (CYCTYPE + DIR)

The ICH6 always drives bit 0 of this field to 0. Peripherals running bus master cycles must also drive bit 0 to 0. Table 5-6 shows the valid bit encodings.

5.5.1.4 SIZE

Bits[3:2] are reserved. The ICH6 always drives them to 00. Peripherals running bus master cycles are also supposed to drive 00 for bits 3:2; however, the ICH6 ignores those bits. Bits[1:0] are encoded as listed in Table 5-7. Table 5-6. Cycle Type Bit Definitions Bits[3:2] Bit1 Definition 00 0 I/O Read 00 1 I/O Write 01 0 Memory Read 01 1 Memory Write 10 0 DMA Read 10 1 DMA Write 11 x Reserved. If a peripheral performing a bus master cycle generates this value, the Intel ® ICH6 aborts the cycle. Table 5-7. Transfer Size Bit Definition Bits[1:0] Size 00 8-bit transfer (1 byte) 01 16-bit transfer (2 bytes) 10 Reserved. The Intel® ICH6 never drives this combination. If a peripheral running a bus master cycle drives this combination, the ICH6 may abort the transfer. 11 32-bit transfer (4 bytes)

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 119 Functional Description

5.5.1.5 SYNC

Valid values for the SYNC field are shown in Table 5-8. NOTES: 1. All other combinations are RESERVED. 2. If the LPC controller receives any SYNC returned from the device other than short (0101), long wait (0110), or ready (0000) when running a FWH cycle, indeterminate results may occur. A FWH device is not allowed to assert an Error SYNC.

5.5.1.6 SYNC Time-Out

There are several error cases that can occur on the LPC interface. The ICH6 responds as defined in section 4.2.1.9 of the Low Pin Count Interface Specification, Revision 1.1 to the stimuli described therein. There may be other peripheral failure conditions; however, these are not handled by the ICH6.

5.5.1.7 SYNC Error Indication

The ICH6 responds as defined in section 4.2.1.10 of the Low Pin Count Interface Specification, Revision 1.1. Upon recognizing the SYNC field indicating an error, the ICH6 treats this as an SERR by reporting this into the Device 31 Error Reporting Logic.

5.5.1.8 LFRAME# Usage

The ICH6 follows the usage of LFRAME# as defined in the Low Pin Count Interface Specification, Revision 1.1. The ICH6 performs an abort for the following cases (possible failure cases):

• ICH6 starts a Memory, I/O, or DMA cycle, but no device drives a valid SYNC after four consecutive clocks.
• ICH6 starts a Memory, I/O, or DMA cycle, and the peripheral drives an invalid SYNC pattern.
• A peripheral drives an illegal address when performing bus master cycles.
• A peripheral drives an invalid value. Table 5-8. SYNC Bit Definition Bits[3:0]1,2 Indication 0000 Ready: SYNC achieved with no error. For DMA transfers, this also indicates DMA request de-assertion and no more transfers desired for that channel. 0101 Short Wait: Part indicating wait-states. For bus master cycles, the Intel® ICH6 does not use this encoding. Instead, the ICH6 uses the Long Wait encoding (see next encoding below). 0110 Long Wait: Part indicating wait-states, and many wait-states will be added. This encoding driven by the ICH6 for bus master cycles, rather than the Short Wait (0101). 1001 Ready More (Used only by peripheral for DMA cycle): SYNC achieved with no error and more DMA transfers desired to continue after this transfer. This value is valid only on DMA transfers and is not allowed for any other type of cycle. 1010 Error: Sync achieved with error. This is generally used to replace the SERR# or IOCHK# signal on the PCI/ISA bus. It indicates that the data is to be transferred, but there is a serious error in this transfer. For DMA transfers, this not only indicates an error, but also indicates DMA request de-assertion and no more transfers desired for that channel.

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5.5.1.9 I/O Cycles

For I/O cycles targeting registers specified in the ICH6’s decode ranges, the ICH6 performs I/O cycles as defined in the Low Pin Count Interface Specification, Revision 1.1. These are 8-bit transfers. If the processor attempts a 16-bit or 32-bit transfer, the ICH6 breaks the cycle up into multiple 8-bit transfers to consecutive I/O addresses. Note: If the cycle is not claimed by any peripheral (and subsequently aborted), the ICH6 returns a value of all 1s (FFh) to the processor. This is to maintain compatibility with ISA I/O cycles where pull-up resistors would keep the bus high if no device responds.

5.5.1.10 Bus Master Cycles

The ICH6 supports Bus Master cycles and requests (using LDRQ#) as defined in the Low Pin Count Interface Specification, Revision 1.1. The ICH6 has two LDRQ# inputs, and thus supports two separate bus master devices. It uses the associated START fields for Bus Master 0 (0010b) or Bus Master 1 (0011b). Note: The ICH6 does not support LPC Bus Masters performing I/O cycles. LPC Bus Masters should only perform memory read or memory write cycles.

5.5.1.11 LPC Power Management

CLKRUN# Protocol (Mobile Only) The CLKRUN# protocol is same as the PCI specification. Stopping the PCI clock stops the LPC clock. LPCPD# Protocol Same timings as for SUS_STAT#. Upon driving SUS_STAT# low, LPC peripherals drive LDRQ# low or tri-state it. ICH6 shuts off the LDRQ# input buffers. After driving SUS_STAT# active, the ICH6 drives LFRAME# low, and tri-states (or drive low) LAD[3:0]. Note: The Low Pin Count Interface Specification, Revision 1.1 defines the LPCPD# protocol where there is at least 30 µs from LPCPD# assertion to LRST# assertion. This specification explicitly states that this protocol only applies to entry/exit of low power states which does not include asynchronous reset events. The ICH6 asserts both SUS_STAT# (connects to LPCPD#) and PLTRST# (connects to LRST#) at the same time when the core logic is reset (via CF9h, PWROK, or SYS_RESET#, etc.). This is not inconsistent with the LPC LPCPD# protocol.

5.5.1.12 Configuration and Intel ® ICH6 Implications

To allow the I/O cycles and memory mapped cycles to go to the LPC interface, the ICH6 includes several decoders. During configuration, the ICH6 must be programmed with the same decode ranges as the peripheral. The decoders are programmed via the Device 31:Function 0 configuration space. Note: The ICH6 cannot accept PCI write cycles from PCI-to-PCI bridges or devices with similar characteristics (specifically those with a “Retry Read” feature which is enabled) to an LPC device if there is an outstanding LPC read cycle towards the same PCI device or bridge. These cycles are not part of normal system operation, but may be encountered as part of platform validation testing using custom test fixtures.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 121 Functional Description Bus Master Device Mapping and START Fields Bus Masters must have a unique START field. In the case of the ICH6 that supports two LPC bus masters, it drives 0010 for the START field for grants to bus master #0 (requested via LDRQ0#) and 0011 for grants to bus master #1 (requested via LDRQ1#.). Thus, no registers are needed to configure the START fields for a particular bus master.

5.6 DMA Operation (D31:F0)

The ICH6 supports LPC DMA using the ICH6’s DMA controller. The DMA controller has registers that are fixed in the lower 64 KB of I/O space. The DMA controller is configured using registers in the PCI configuration space. These registers allow configuration of the channels for use by LPC DMA. The DMA circuitry incorporates the functionality of two 82C37 DMA controllers with seven independently programmable channels (Figure 5-4). DMA controller 1 (DMA-1) corresponds to DMA channels 0–3 and DMA controller 2 (DMA-2) corresponds to channels 5–7. DMA channel 4 is used to cascade the two controllers and defaults to cascade mode in the DMA Channel Mode (DCM) Register. Channel 4 is not available for any other purpose. In addition to accepting requests from DMA slaves, the DMA controller also responds to requests that software initiates. Software may initiate a DMA service request by setting any bit in the DMA Channel Request Register to a 1. Each DMA channel is hardwired to the compatible settings for DMA device size: channels [3:0] are hardwired to 8-bit, count-by-bytes transfers, and channels [7:5] are hardwired to 16-bit, count-by-words (address shifted) transfers. ICH6 provides 24-bit addressing in compliance with the ISA-Compatible specification. Each channel includes a 16-bit ISA-Compatible Current Register which holds the 16 least-significant bits of the 24-bit address, an ISA-Compatible Page Register which contains the eight next most significant bits of address. The DMA controller also features refresh address generation, and autoinitialization following a DMA termination. Figure 5-4. Intel® ICH6 DMA Controller Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 DMA-1 DMA-2

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5.6.1 Channel Priority

For priority resolution, the DMA consists of two logical channel groups: channels 0–3 and channels 4–7. Each group may be in either fixed or rotate mode, as determined by the DMA Command Register. DMA I/O slaves normally assert their DREQ line to arbitrate for DMA service. However, a software request for DMA service can be presented through each channel's DMA Request Register. A software request is subject to the same prioritization as any hardware request. See the detailed register description for Request Register programming information in Section 10.2.

5.6.1.1 Fixed Priority

The initial fixed priority structure is as follows: The fixed priority ordering is 0, 1, 2, 3, 5, 6, and 7. In this scheme, channel 0 has the highest priority, and channel 7 has the lowest priority. Channels [3:0] of DMA-1 assume the priority position of channel 4 in DMA-2, thus taking priority over channels 5, 6, and 7.

5.6.1.2 Rotating Priority

Rotation allows for "fairness" in priority resolution. The priority chain rotates so that the last channel serviced is assigned the lowest priority in the channel group (0–3, 5–7). Channels 0–3 rotate as a group of 4. They are always placed between channel 5 and channel 7 in the priority list. Channel 5–7 rotate as part of a group of 4. That is, channels (5–7) form the first three positions in the rotation, while channel group (0–3) comprises the fourth position in the arbitration.

5.6.2 Address Compatibility Mode

When the DMA is operating, the addresses do not increment or decrement through the High and Low Page Registers. Therefore, if a 24-bit address is 01FFFFh and increments, the next address is 010000h, not 020000h. Similarly, if a 24-bit address is 020000h and decrements, the next address is 02FFFFh, not 01FFFFh. However, when the DMA is operating in 16-bit mode, the addresses still do not increment or decrement through the High and Low Page Registers but the page boundary is now 128 K. Therefore, if a 24-bit address is 01FFFEh and increments, the next address is 000000h, not 0100000h. Similarly, if a 24-bit address is 020000h and decrements, the next address is 03FFFEh, not 02FFFEh. This is compatible with the 82C37 and Page Register implementation used in the PC-AT. This mode is set after CPURST is valid. High priority Low priority 0, 1, 2, 3 5, 6, 7

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 123 Functional Description

5.6.3 Summary of DMA Transfer Sizes

Table 5-9 lists each of the DMA device transfer sizes. The column labeled “Current Byte/Word Count Register” indicates that the register contents represents either the number of bytes to transfer or the number of 16-bit words to transfer. The column labeled “Current Address Increment/ Decrement” indicates the number added to or taken from the Current Address register after each DMA transfer cycle. The DMA Channel Mode Register determines if the Current Address Register will be incremented or decremented.

5.6.3.1 Address Shifting When Programmed for 16-Bit

The ICH6 maintains compatibility with the implementation of the DMA in the PC AT that used the 82C37. The DMA shifts the addresses for transfers to/from a 16-bit device count-by-words. Note: The least significant bit of the Low Page Register is dropped in 16-bit shifted mode. When programming the Current Address Register (when the DMA channel is in this mode), the Current Address must be programmed to an even address with the address value shifted right by one bit. The address shifting is shown in Table 5-10. NOTE: The least significant bit of the Page Register is dropped in 16-bit shifted mode.

5.6.4 Autoinitialize

By programming a bit in the DMA Channel Mode Register, a channel may be set up as an autoinitialize channel. When a channel undergoes autoinitialization, the original values of the Current Page, Current Address and Current Byte/Word Count Registers are automatically restored from the Base Page, Address, and Byte/Word Count Registers of that channel following TC. The Base Registers are loaded simultaneously with the Current Registers by the microprocessor when the DMA channel is programmed and remain unchanged throughout the DMA service. The mask bit is not set when the channel is in autoinitialize. Following autoinitialize, the channel is ready to perform another DMA service, without processor intervention, as soon as a valid DREQ is detected. Table 5-9. DMA Transfer Size DMA Device Date Size And Word Count Current Byte/Word Count Register Current Address Increment/Decrement 8-Bit I/O, Count By Bytes Bytes 1 16-Bit I/O, Count By Words (Address Shifted) Words 1 Table 5-10. Address Shifting in 16-Bit I/O DMA Transfers Output Address 8-Bit I/O Programmed Address (Ch 0–3) 16-Bit I/O Programmed Address (Ch 5–7) (Shifted) A[16:1] A[23:17] A[16:1] A[23:17] A[15:0] A[23:17]

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5.6.5 Software Commands

There are three additional special software commands that the DMA controller can execute. The three software commands are:

• Clear Byte Pointer Flip-Flop
• Master Clear
• Clear Mask Register They do not depend on any specific bit pattern on the data bus.

5.7 LPC DMA

DMA on LPC is handled through the use of the LDRQ# lines from peripherals and special encodings on LAD[3:0] from the host. Single, Demand, Verify, and Increment modes are supported on the LPC interface. Channels 0–3 are 8 bit channels. Channels 5–7 are 16-bit channels. Channel 4 is reserved as a generic bus master request.

5.7.1 Asserting DMA Requests

Peripherals that need DMA service encode their requested channel number on the LDRQ# signal. To simplify the protocol, each peripheral on the LPC I/F has its own dedicated LDRQ# signal (they may not be shared between two separate peripherals). The ICH6 has two LDRQ# inputs, allowing at least two devices to support DMA or bus mastering. LDRQ# is synchronous with LCLK (PCI clock). As shown in Figure 5-5, the peripheral uses the following serial encoding sequence:

• Peripheral starts the sequence by asserting LDRQ# low (start bit). LDRQ# is high during idle conditions.
• The next three bits contain the encoded DMA channel number (MSB first).
• The next bit (ACT) indicates whether the request for the indicated DMA channel is active or inactive. The ACT bit is 1 (high) to indicate if it is active and 0 (low) if it is inactive. The case where ACT is low is rare, and is only used to indicate that a previous request for that channel is being abandoned.
• After the active/inactive indication, the LDRQ# signal must go high for at least 1 clock. After that one clock, LDRQ# signal can be brought low to the next encoding sequence. If another DMA channel also needs to request a transfer, another sequence can be sent on LDRQ#. For example, if an encoded request is sent for channel 2, and then channel 3 needs a transfer before the cycle for channel 2 is run on the interface, the peripheral can send the encoded request for channel 3. This allows multiple DMA agents behind an I/O device to request use of the LPC interface, and the I/O device does not need to self-arbitrate before sending the message. Figure 5-5. DMA Request Assertion through LDRQ# Start MSB LSB ACT Start LCLK LDRQ#

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 125 Functional Description

5.7.2 Abandoning DMA Requests

DMA Requests can be de-asserted in two fashions: on error conditions by sending an LDRQ# message with the ‘ACT’ bit set to 0, or normally through a SYNC field during the DMA transfer. This section describes boundary conditions where the DMA request needs to be removed prior to a data transfer. There may be some special cases where the peripheral desires to abandon a DMA transfer. The most likely case of this occurring is due to a floppy disk controller which has overrun or underrun its FIFO, or software stopping a device prematurely. In these cases, the peripheral wishes to stop further DMA activity. It may do so by sending an LDRQ# message with the ACT bit as 0. However, since the DMA request was seen by the ICH6, there is no guarantee that the cycle has not been granted and will shortly run on LPC. Therefore, peripherals must take into account that a DMA cycle may still occur. The peripheral can choose not to respond to this cycle, in which case the host will abort it, or it can choose to complete the cycle normally with any random data. This method of DMA de-assertion should be prevented whenever possible, to limit boundary conditions both on the ICH6 and the peripheral.

5.7.3 General Flow of DMA Transfers

Arbitration for DMA channels is performed through the 8237 within the host. Once the host has won arbitration on behalf of a DMA channel assigned to LPC, it asserts LFRAME# on the LPC I/F and begins the DMA transfer. The general flow for a basic DMA transfer is as follows: 1. ICH6 starts transfer by asserting 00 00b on LAD[3:0] with LFRAME# asserted. 2. ICH6 asserts ‘cycle type’ of DMA, direction based on DMA transfer direction. 3. ICH6 asserts channel number and, if applicable, terminal count. 4. ICH6 indicates the size of the transfer: 8 or 16 bits. 5. If a DMA read… — The ICH6 drives the first 8 bits of data and turns the bus around. — The peripheral acknowledges the data with a valid SYNC. — If a 16-bit transfer, the process is repeated for the next 8 bits. 6. If a DMA write… — The ICH6 turns the bus around and waits for data. — The peripheral indicates data ready th rough SYNC and transfers the first byte. — If a 16-bit transfer, the peripheral indicat es data ready and transfers the next byte. 7. The peripheral tu rns around the bus.

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5.7.4 Terminal Count

Terminal count is communicated through LAD[3] on the same clock that DMA channel is communicated on LAD[2:0]. This field is the CHANNEL field. Terminal count indicates the last byte of transfer, based upon the size of the transfer. For example, on an 8-bit transfer size (SIZE field is 00b), if the TC bit is set, then this is the last byte. On a 16-bit transfer (SIZE field is 01b), if the TC bit is set, then the second byte is the last byte. The peripheral, therefore, must internalize the TC bit when the CHANNEL field is communicated, and only signal TC when the last byte of that transfer size has been transferred.

5.7.5 Verify Mode

Verify mode is supported on the LPC interface. A verify transfer to the peripheral is similar to a DMA write, where the peripheral is transferring data to main memory. The indication from the host is the same as a DMA write, so the peripheral will be driving data onto the LPC interface. However, the host will not transfer this data into main memory.

5.7.6 DMA Request De-assertion

An end of transfer is communicated to the ICH6 through a special SYNC field transmitted by the peripheral. An LPC device must not attempt to signal the end of a transfer by de-asserting LDREQ#. If a DMA transfer is several bytes (e.g., a transfer from a demand mode device) the ICH6 needs to know when to de-assert the DMA request based on the data currently being transferred. The DMA agent uses a SYNC encoding on each byte of data being transferred, which indicates to the ICH6 whether this is the last byte of transfer or if more bytes are requested. To indicate the last byte of transfer, the peripheral uses a SYNC value of 0000b (ready with no error), or 1010b (ready with error). These encodings tell the ICH6 that this is the last piece of data transferred on a DMA read (ICH6 to peripheral), or the byte that follows is the last piece of data transferred on a DMA write (peripheral to ICH6). When the ICH6 sees one of these two encodings, it ends the DMA transfer after this byte and de- asserts the DMA request to the 8237. Therefore, if the ICH6 indicated a 16-bit transfer, the peripheral can end the transfer after one byte by indicating a SYNC value of 0000b or 1010b. The ICH6 does not attempt to transfer the second byte, and de-asserts the DMA request internally. If the peripheral indicates a 0000b or 1010b SYNC pattern on the last byte of the indicated size, then the ICH6 only de-asserts the DMA request to the 8237 since it does not need to end the transfer. If the peripheral wishes to keep the DMA request active, then it uses a SYNC value of 1001b (ready plus more data). This tells the 8237 that more data bytes are requested after the current byte has been transferred, so the ICH6 keeps the DMA request active to the 8237. Therefore, on an 8-bit transfer size, if the peripheral indicates a SYNC value of 1001b to the ICH6, the data will be transferred and the DMA request will remain active to the 8237. At a later time, the ICH6 will then come back with another START–CYCTYPE–CHANNEL–SIZE etc. combination to initiate another transfer to the peripheral.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 127 Functional Description The peripheral must not assume that the next START indication from the ICH6 is another grant to the peripheral if it had indicated a SYNC value of 1001b. On a single mode DMA device, the 8237 will re-arbitrate after every transfer. Only demand mode DMA devices can be guaranteed that they will receive the next START indication from the ICH6. Note: Indicating a 0000b or 1010b encoding on the SYNC field of an odd byte of a 16-bit channel (first byte of a 16 bit transfer) is an error condition. Note: The host stops the transfer on the LPC bus as indicated, fills the upper byte with random data on DMA writes (peripheral to memory), and indicates to the 8237 that the DMA transfer occurred, incrementing the 8237’s address and decrementing its byte count.

5.7.7 SYNC Field / LDRQ# Rules

Since DMA transfers on LPC are requested through an LDRQ# assertion message, and are ended through a SYNC field during the DMA transfer, the peripheral must obey the following rule when initiating back-to-back transfers from a DMA channel. The peripheral must not assert another message for eight LCLKs after a de-assertion is indicated through the SYNC field. This is needed to allow the 8237, that typically runs off a much slower internal clock, to see a message de-asserted before it is re-asserted so that it can arbitrate to the next agent. Under default operation, the host only performs 8-bit transfers on 8-bit channels and 16-bit transfers on 16-bit channels. The method by which this communication between host and peripheral through system BIOS is performed is beyond the scope of this specification. Since the LPC host and LPC peripheral are motherboard devices, no “plug-n-play” registry is required. The peripheral must not assume that the host is able to perform transfer sizes that are larger than the size allowed for the DMA channel, and be willing to accept a SIZE field that is smaller than what it may currently have buffered. To that end, it is recommended that future devices that may appear on the LPC bus, that require higher bandwidth than 8-bit or 16-bit DMA allow, do so with a bus mastering interface and not rely on the 8237.

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5.8 8254 Timers (D31:F0) The ICH6 contains three counters that have fixed uses. All registers and functions associated with the 8254 timers are in the core well. The 8254 unit is clocked by a 14.31818 MHz clock. Counter 0, System Timer This counter functions as the system timer by controlling the state of IRQ0 and is typically programmed for Mode 3 operation. The counter produces a square wave with a period equal to the product of the counter period (838 ns) and the initial count value. The counter loads the initial count value 1 counter period after software writes the count value to the counter I/O address. The counter initially asserts IRQ0 and decrements the count value by two each counter period. The counter negates IRQ0 when the count value reaches 0. It then reloads the initial count value and again decrements the initial count value by two each counter period. The counter then asserts IRQ0 when the count value reaches 0, reloads the initial count value, and repeats the cycle, alternately asserting and negating IRQ0. Counter 1, Refresh Request Signal This counter provides the refresh request signal and is typically programmed for Mode 2 operation and only impacts the period of the REF_TOGGLE bit in Port 61. The initial count value is loaded one counter period after being written to the counter I/O address. The REF_TOGGLE bit will have a square wave behavior (alternate between 0 and 1) and will toggle at a rate based on the value in the counter. Programming the counter to anything other than Mode 2 will result in undefined behavior for the REF_TOGGLE bit. Counter 2, Speaker Tone This counter provides the speaker tone and is typically programmed for Mode 3 operation. The counter provides a speaker frequency equal to the counter clock frequency (1.193 MHz) divided by the initial count value. The speaker must be enabled by a write to port 061h (see NMI Status and Control ports).

5.8.1 Timer Programming

The counter/timers are programmed as follows: 1. Write a control word to select a counter. 2. Write an initial count for that counter. 3. Load the least and/or most significant bytes (as required by Control Word bits 5, 4) of the 16-bit counter. 4. Repeat with other counters. Only two conventions need to be observed when programming the counters. First, for each counter, the control word must be written before the initial count is written. Second, the initial count must follow the count format specified in the control word (least significant byte only, most significant byte only, or least significant byte and then most significant byte). A new initial count may be written to a counter at any time without affecting the counter's programmed mode. Counting is affected as described in the mode definitions. The new count must follow the programmed count format.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 129 Functional Description If a counter is programmed to read/write two-byte counts, the following precaution applies: A program must not transfer control between writing the first and second byte to another routine which also writes into that same counter. Otherwise, the counter will be loaded with an incorrect count. The Control Word Register at port 43h controls the operation of all three counters. Several commands are available:

• Control Word Command. Specifies which counter to read or write, the operating mode, and the count format (binary or BCD).
• Counter Latch Command. Latches the current count so that it can be read by the system. The countdown process continues.
• Read Back Command. Reads the count value, programmed mode, the current state of the OUT pins, and the state of the Null Count Flag of the selected counter. Table 5-11 lists the six operating modes for the interval counters.

5.8.2 Reading from the Interval Timer

It is often desirable to read the value of a counter without disturbing the count in progress. There are three methods for reading the counters: a simple read operation, counter Latch command, and the Read-Back command. Each is explained below. With the simple read and counter latch command methods, the count must be read according to the programmed format; specifically, if the counter is programmed for two byte counts, two bytes must be read. The two bytes do not have to be read one right after the other. Read, write, or programming operations for other counters may be inserted between them. Table 5-11. Counter Operating Modes Mode Function Description 0 Out signal on end of count (=0) Output is 0. When count goes to 0, output goes to 1 and stays at 1 until counter is reprogrammed. 1 Hardware retriggerable one-shot Output is 0. When count goes to 0, output goes to 1 for one clock time. 2 Rate generator (divide by n counter) Output is 1. Output goes to 0 for one clock time, then back to 1 and counter is reloaded.

3 Square wave output

Output is 1. Output goes to 0 when counter rolls over, and counter is reloaded. Output goes to 1 when counter rolls over, and counter is reloaded, etc. 4 Software triggered strobe Output is 1. Output goes to 0 when count expires for one clock time. 5 Hardware triggered strobe Output is 1. Output goes to 0 when count expires for one clock time.

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5.8.2.1 Simple Read

The first method is to perform a simple read operation. The counter is selected through port 40h (counter 0), 41h (counter 1), or 42h (counter 2). Note: Performing a direct read from the counter does not return a determinate value, because the counting process is asynchronous to read operations. However, in the case of counter 2, the count can be stopped by writing to the GATE bit in port 61h.

5.8.2.2 Counter Latch Command

The Counter Latch command, written to port 43h, latches the count of a specific counter at the time the command is received. This command is used to ensure that the count read from the counter is accurate, particularly when reading a two-byte count. The count value is then read from each counter’s Count register as was programmed by the Control register. The count is held in the latch until it is read or the counter is reprogrammed. The count is then unlatched. This allows reading the contents of the counters on the fly without affecting counting in progress. Multiple Counter Latch Commands may be used to latch more than one counter. Counter Latch commands do not affect the programmed mode of the counter in any way. If a Counter is latched and then, some time later, latched again before the count is read, the second Counter Latch command is ignored. The count read is the count at the time the first Counter Latch command was issued.

5.8.2.3 Read Back Command

The Read Back command, written to port 43h, latches the count value, programmed mode, and current states of the OUT pin and Null Count flag of the selected counter or counters. The value of the counter and its status may then be read by I/O access to the counter address. The Read Back command may be used to latch multiple counter outputs at one time. This single command is functionally equivalent to several counter latch commands, one for each counter latched. Each counter's latched count is held until it is read or reprogrammed. Once read, a counter is unlatched. The other counters remain latched until they are read. If multiple count Read Back commands are issued to the same counter without reading the count, all but the first are ignored. The Read Back command may additionally be used to latch status information of selected counters. The status of a counter is accessed by a read from that counter's I/O port address. If multiple counter status latch operations are performed without reading the status, all but the first are ignored. Both count and status of the selected counters may be latched simultaneously. This is functionally the same as issuing two consecutive, separate Read Back commands. If multiple count and/or status Read Back commands are issued to the same counters without any intervening reads, all but the first are ignored. If both count and status of a counter are latched, the first read operation from that counter returns the latched status, regardless of which was latched first. The next one or two reads, depending on whether the counter is programmed for one or two type counts, returns the latched count. Subsequent reads return unlatched count.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 131 Functional Description 5.9 8259 Interrupt Controllers (PIC) (D31:F0) The ICH6 incorporates the functionality of two 8259 interrupt controllers that provide system interrupts for the ISA compatible interrupts. These interrupts are: system timer, keyboard controller, serial ports, parallel ports, floppy disk, IDE, mouse, and DMA channels. In addition, this interrupt controller can support the PCI based interrupts, by mapping the PCI interrupt onto the compatible ISA interrupt line. Each 8259 core supports eight interrupts, numbered 0–7. Table 5-12 shows how the cores are connected. The ICH6 cascades the slave controller onto the master controller through master controller interrupt input 2. This means there are only 15 possible interrupts for the ICH6 PIC. Interrupts can individually be programmed to be edge or level, except for IRQ0, IRQ2, IRQ8#, and IRQ13. Note: Active-low interrupt sources (e.g., the PIRQ#s) are inverted inside the ICH6. In the following descriptions of the 8259s, the interrupt levels are in reference to the signals at the internal interface of the 8259s, after the required inversions have occurred. Therefore, the term “high” indicates “active,” which means “low” on an originating PIRQ#. Table 5-12. Interrupt Controller Core Connections 8259 8259 Input Typical Interrupt Source Connected Pin / Function Master

0 Internal Internal Timer / Counter 0 output / HPET #0

1 Keyboard IRQ1 via SERIRQ

2 Internal Slave controller INTR output

3 Serial Port A IRQ3 via SERIRQ, PIRQ#

4 Serial Port B IRQ4 via SERIRQ, PIRQ#

5 Parallel Port / Generic IRQ5 via SERIRQ, PIRQ#

6 Floppy Disk IRQ6 via SERIRQ, PIRQ#

7 Parallel Port / Generic IRQ7 via SERIRQ, PIRQ#

0 Internal Real Time Clock Internal RTC / HPET #1

1 Generic IRQ9 via SERIRQ, SCI, TCO, or PIRQ#

2 Generic IRQ10 via SERIRQ, SCI, TCO, or PIRQ#

3 Generic IRQ11 via SERIRQ, SCI, TCO, or PIRQ#

4 PS/2 Mouse IRQ12 via SERIRQ, SCI, TCO, or PIRQ#

5 Internal

State Machine output based on processor FERR# assertion. May optionally be used for SCI or TCO interrupt if FERR# not needed.

6 IDE cable, SATA

IDEIRQ (legacy mode, non-combined or combined mapped as primary), SATA Primary (legacy mode), or via SERIRQ or PIRQ#

7 IDE cable, SATA

IDEIRQ (legacy mode — combined, mapped as secondary), SATA Secondary (legacy mode) or via SERIRQ or PIRQ#

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5.9.1 Interrupt Handling

5.9.1.1 Generating Interrupts

The PIC interrupt sequence involves three bits, from the IRR, ISR, and IMR, for each interrupt level. These bits are used to determine the interrupt vector returned, and status of any other pending interrupts. Table 5-13 defines the IRR, ISR, and IMR.

5.9.1.2 Acknowledging Interrupts

The processor generates an interrupt acknowledge cycle that is translated by the host bridge into a PCI Interrupt Acknowledge Cycle to the ICH6. The PIC translates this command into two internal INTA# pulses expected by the 8259 cores. The PIC uses the first internal INTA# pulse to freeze the state of the interrupts for priority resolution. On the second INTA# pulse, the master or slave sends the interrupt vector to the processor with the acknowledged interrupt code. This code is based upon bits [7:3] of the corresponding ICW2 register, combined with three bits representing the interrupt within that controller. Table 5-13. Interrupt Status Registers Bit Description IRR Interrupt Request Register. This bit is set on a low to high transition of the interrupt line in edge mode, and by an active high level in level mode. This bit is set whether or not the interrupt is masked. However, a masked interrupt will not generate INTR. ISR Interrupt Service Register. This bit is set, and the corresponding IRR bit cleared, when an interrupt acknowledge cycle is seen, and the vector returned is for that interrupt. IMR Interrupt Mask Register. This bit determines whether an interrupt is masked. Masked interrupts will not generate INTR. Table 5-14. Content of Interrupt Vector Byte Master, Slave Interrupt Bits [7:3] Bits [2:0] IRQ7,15 ICW2[7:3] 111 IRQ6,14 110 IRQ5,13 101 IRQ4,12 100 IRQ3,11 011 IRQ2,10 010 IRQ1,9 001 IRQ0,8 000

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 133 Functional Description

5.9.1.3 Hardware/Softwa re Interrupt Sequence

1. One or more of the Interrupt Request lines (IRQ) are raised high in edge mode, or seen high in level mode, setting the corresponding IRR bit. 2. The PIC sends INTR active to the processor if an asserted interrupt is not masked. 3. The processor acknowledges the INTR and respond s with an interrupt acknowledge cycle. The cycle is translated into a PCI interrupt acknowledge cycle by the host bridge. This command is broadcast over PCI by the ICH6. 4. Upon observing its own interrupt acknowledge cycle on PCI, the ICH6 converts it into the two cycles that the internal 8259 pair can respond to. Each cycle appears as an interrupt acknowledge pulse on the internal INTA# pin of the cascaded interrupt controllers. 5. Upon receiving the first internally generated INTA# pulse, the highest priority ISR bit is set and the corresponding IRR bit is reset. On the trailing edge of the first pulse, a slave identification code is broadcast by the master to the slave on a private, internal three bit wide bus. The slave controller uses these bits to determine if it must respond with an interrupt vector during the second INTA# pulse. 6. Upon receiving the second inte rnally generated INTA# pulse, the PIC returns the interrupt vector. If no interrupt request is present because the request was too short in duration, the PIC returns vector 7 from the master controller. 7. This completes the interrupt cycle. In AEOI mode the ISR bit is reset at the end of the second INTA# pulse. Otherwise, the ISR bit remains set until an appropriate EOI command is issued at the end of the interrupt subroutine.

5.9.2 Initialization Command Words (ICWx)

Before operation can begin, each 8259 must be initialized. In the ICH6, this is a four byte sequence. The four initialization command words are referred to by their acronyms: ICW1, ICW2, ICW3, and ICW4. The base address for each 8259 initialization command word is a fixed location in the I/O memory space: 20h for the master controller, and A0h for the slave controller.

5.9.2.1 ICW1

An I/O write to the master or slave controller base address with data bit 4 equal to 1 is interpreted as a write to ICW1. Upon sensing this write, the ICH6 PIC expects three more byte writes to 21h for the master controller, or A1h for the slave controller, to complete the ICW sequence. A write to ICW1 starts the initialization sequence during which the following automatically occur: 1. Following initialization, an interrupt request (I RQ) input must make a low-to-high transition to generate an interrupt. 2. The Interrupt Mask Register is cleared. 3. IRQ7 input is assigned priority 7. 4. The slave mode address is set to 7. 5. Special mask mode is cleared and Status Read is set to IRR.

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5.9.2.2 ICW2

The second write in the sequence (ICW2) is programmed to provide bits [7:3] of the interrupt vector that will be released during an interrupt acknowledge. A different base is selected for each interrupt controller.

5.9.2.3 ICW3

The third write in the sequence (ICW3) has a different meaning for each controller.

• For the master controller, ICW3 is used to indicate which IRQ input line is used to cascade the slave controller. Within the ICH6, IRQ2 is used. Therefore, bit 2 of ICW3 on the master controller is set to a 1, and the other bits are set to 0s.
• For the slave controller, ICW3 is the slave identification code used during an interrupt acknowledge cycle. On interrupt acknowledge cycles, the master controller broadcasts a code to the slave controller if the cascaded interrupt won arbitration on the master controller. The slave controller compares this identification code to the value stored in its ICW3, and if it matches, the slave controller assumes responsibility for broadcasting the interrupt vector.

5.9.2.4 ICW4

The final write in the sequence (ICW4) must be programmed for both controllers. At the very least, bit 0 must be set to a 1 to indicate that the controllers are operating in an Intel Architecture-based system.

5.9.3 Operation Command Words (OCW)

These command words reprogram the Interrupt controller to operate in various interrupt modes.

• OCW1 masks and unmasks interrupt lines.
• OCW2 controls the rotation of interrupt priorities when in rotating priority mode, and controls the EOI function.
• OCW3 is sets up ISR/IRR reads, enables/disables the special mask mode (SMM), and enables/ disables polled interrupt mode.

5.9.4 Modes of Operation

5.9.4.1 Fully Nested Mode

In this mode, interrupt requests are ordered in priority from 0 through 7, with 0 being the highest. When an interrupt is acknowledged, the highest priority request is determined and its vector placed on the bus. Additionally, the ISR for the interrupt is set. This ISR bit remains set until: the processor issues an EOI command immediately before returning from the service routine; or if in AEOI mode, on the trailing edge of the second INTA#. While the ISR bit is set, all further interrupts of the same or lower priority are inhibited, while higher levels generate another interrupt. Interrupt priorities can be changed in the rotating priority mode.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 135 Functional Description

5.9.4.2 Special Fully-Nested Mode

This mode is used in the case of a system where cascading is used, and the priority has to be conserved within each slave. In this case, the special fully-nested mode is programmed to the master controller. This mode is similar to the fully-nested mode with the following exceptions:

• When an interrupt request from a certain slave is in service, this slave is not locked out from the master's priority logic and further interrupt requests from higher priority interrupts within the slave are recognized by the master and initiate interrupts to the processor. In the normal- nested mode, a slave is masked out when its request is in service.
• When exiting the Interrupt Service routine, software has to check whether the interrupt serviced was the only one from that slave. This is done by sending a Non-Specific EOI command to the slave and then reading its ISR. If it is 0, a non-specific EOI can also be sent to the master.

5.9.4.3 Automatic Rotation Mo de (Equal Priority Devices)

In some applications, there are a number of interrupting devices of equal priority. Automatic rotation mode provides for a sequential 8-way rotation. In this mode, a device receives the lowest priority after being serviced. In the worst case, a device requesting an interrupt has to wait until each of seven other devices are serviced at most once. There are two ways to accomplish automatic rotation using OCW2; the Rotation on Non-Specific EOI Command (R=1, SL=0, EOI=1) and the rotate in automatic EOI mode which is set by (R=1, SL=0, EOI=0).

5.9.4.4 Specific Rotation Mo de (Specific Priority)

Software can change interrupt priorities by programming the bottom priority. For example, if IRQ5 is programmed as the bottom priority device, then IRQ6 is the highest priority device. The Set Priority Command is issued in OCW2 to accomplish this, where: R=1, SL=1, and LO–L2 is the binary priority level code of the bottom priority device. In this mode, internal status is updated by software control during OCW2. However, it is independent of the EOI command. Priority changes can be executed during an EOI command by using the Rotate on Specific EOI Command in OCW2 (R=1, SL=1, EOI=1 and LO–L2=IRQ level to receive bottom priority.

5.9.4.5 Poll Mode

Poll mode can be used to conserve space in the interrupt vector table. Multiple interrupts that can be serviced by one interrupt service routine do not need separate vectors if the service routine uses the poll command. Poll mode can also be used to expand the number of interrupts. The polling interrupt service routine can call the appropriate service routine, instead of providing the interrupt vectors in the vector table. In this mode, the INTR output is not used and the microprocessor internal Interrupt Enable flip-flop is reset, disabling its interrupt input. Service to devices is achieved by software using a Poll command. The Poll command is issued by setting P=1 in OCW3. The PIC treats its next I/O read as an interrupt acknowledge, sets the appropriate ISR bit if there is a request, and reads the priority level. Interrupts are frozen from the OCW3 write to the I/O read. The byte returned during the I/O read contains a 1 in bit 7 if there is an interrupt, and the binary code of the highest priority level in bits 2:0.

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5.9.4.6 Cascade Mode

The PIC in the ICH6 has one master 8259 and one slave 8259 cascaded onto the master through IRQ2. This configuration can handle up to 15 separate priority levels. The master controls the slaves through a three bit internal bus. In the ICH6, when the master drives 010b on this bus, the slave controller takes responsibility for returning the interrupt vector. An EOI command must be issued twice: once for the master and once for the slave.

5.9.4.7 Edge and Level Triggered Mode

In ISA systems this mode is programmed using bit 3 in ICW1, which sets level or edge for the entire controller. In the ICH6, this bit is disabled and a new register for edge and level triggered mode selection, per interrupt input, is included. This is the Edge/Level control Registers ELCR1 and ELCR2. If an ELCR bit is 0, an interrupt request will be recognized by a low-to-high transition on the corresponding IRQ input. The IRQ input can remain high without generating another interrupt. If an ELCR bit is 1, an interrupt request will be recognized by a high level on the corresponding IRQ input and there is no need for an edge detection. The interrupt request must be removed before the EOI command is issued to prevent a second interrupt from occurring. In both the edge and level triggered modes, the IRQ inputs must remain active until after the falling edge of the first internal INTA#. If the IRQ input goes inactive before this time, a default IRQ7 vector is returned.

5.9.4.8 End of Interrupt (EOI) Operations

An EOI can occur in one of two fashions: by a command word write issued to the PIC before returning from a service routine, the EOI command; or automatically when AEOI bit in ICW4 is set to 1.

5.9.4.9 Normal End of Interrupt

In normal EOI, software writes an EOI command before leaving the interrupt service routine to mark the interrupt as completed. There are two forms of EOI commands: Specific and Non-Specific. When a Non-Specific EOI command is issued, the PIC clears the highest ISR bit of those that are set to 1. Non-Specific EOI is the normal mode of operation of the PIC within the ICH6, as the interrupt being serviced currently is the interrupt entered with the interrupt acknowledge. When the PIC is operated in modes that preserve the fully nested structure, software can determine which ISR bit to clear by issuing a Specific EOI. An ISR bit that is masked is not cleared by a Non-Specific EOI if the PIC is in the special mask mode. An EOI command must be issued for both the master and slave controller.

5.9.4.10 Automatic End of Interrupt Mode

In this mode, the PIC automatically performs a Non-Specific EOI operation at the trailing edge of the last interrupt acknowledge pulse. From a system standpoint, this mode should be used only when a nested multi-level interrupt structure is not required within a single PIC. The AEOI mode can only be used in the master controller and not the slave controller.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 137 Functional Description

5.9.5 Masking Interrupts

5.9.5.1 Masking on an Indi vidual Interrupt Request

Each interrupt request can be masked individually by the Interrupt Mask Register (IMR). This register is programmed through OCW1. Each bit in the IMR masks one interrupt channel. Masking IRQ2 on the master controller masks all requests for service from the slave controller.

5.9.5.2 Special Mask Mode

Some applications may require an interrupt service routine to dynamically alter the system priority structure during its execution under software control. For example, the routine may wish to inhibit lower priority requests for a portion of its execution but enable some of them for another portion. The special mask mode enables all interrupts not masked by a bit set in the Mask register. Normally, when an interrupt service routine acknowledges an interrupt without issuing an EOI to clear the ISR bit, the interrupt controller inhibits all lower priority requests. In the special mask mode, any interrupts may be selectively enabled by loading the Mask Register with the appropriate pattern. The special mask mode is set by OCW3 where: SSMM=1, SMM=1, and cleared where SSMM=1, SMM=0.

5.9.6 Steering PCI Interrupts

The ICH6 can be programmed to allow PIRQA#-PIRQH# to be internally routed to interrupts 3–7, 9–12, 14 or 15. The assignment is programmable through the through the PIRQx Route Control registers, located at 60–63h and 68–6Bh in Device 31:Function 0. One or more PIRQx# lines can be routed to the same IRQx input. If interrupt steering is not required, the Route registers can be programmed to disable steering. The PIRQx# lines are defined as active low, level sensitive to allow multiple interrupts on a PCI board to share a single line across the connector. When a PIRQx# is routed to specified IRQ line, software must change the IRQ's corresponding ELCR bit to level sensitive mode. The ICH6 internally inverts the PIRQx# line to send an active high level to the PIC. When a PCI interrupt is routed onto the PIC, the selected IRQ can no longer be used by an active high device (through SERIRQ). However, active low interrupts can share their interrupt with PCI interrupts. Internal sources of the PIRQs, including SCI and TCO interrupts, cause the external PIRQ to be asserted. The ICH6 receives the PIRQ input, like all of the other external sources, and routes it accordingly.

138 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

5.10 Advanced Programmable Interrupt Controller

(APIC) (D31:F0) In addition to the standard ISA-compatible PIC described in the previous chapter, the ICH6 incorporates the APIC. While the standard interrupt controller is intended for use in a uni-processor system, APIC can be used in either a uni-processor or multi-processor system.

5.10.1 Interrupt Handling

The I/O APIC handles interrupts very differently than the 8259. Briefly, these differences are:

• Method of Interrupt Transmission. The I/O APIC transmits interrupts through memory writes on the normal datapath to the processor, and interrupts are handled without the need for the processor to run an interrupt acknowledge cycle.
• Interrupt Priority. The priority of interrupts in the I/O APIC is independent of the interrupt number. For example, interrupt 10 can be given a higher priority than interrupt 3.
• More Interrupts. The I/O APIC in the ICH6 supports a total of 24 interrupts.
• Multiple Interrupt Controllers. The I/O APIC architecture allows for multiple I/O APIC devices in the system with their own interrupt vectors.

5.10.2 Interrupt Mapping

The I/O APIC within the ICH6 supports 24 APIC interrupts. Each interrupt has its own unique vector assigned by software. The interrupt vectors are mapped as follows, and match “Config 6” of the Multi-Processor Specification. Table 5-15. APIC Interrupt Mapping (Sheet 1 of 2) IRQ # Via SERIRQ Direct from Pin Via PCI Message Internal Modules

0 No No No Cascade from 8259 #1

2 No No No 8254 Counter 0, HPET #0 (legacy mode)

8 No No No RTC, HPET #1 (legacy mode)

9 Yes No Yes Option for SCI, TCO

10 Yes No Yes Option for SCI, TCO

11 Yes No Yes HPET #2, Option for SCI, TCO

12 Yes No Yes

13 No No No FERR# logic

14 Yes Yes

1 Yes IDEIRQ (legacy mode, non-combined or combined

mapped as primary), SATA Primary (legacy mode)

15 Yes Yes Yes IDEIRQ (legacy mode — combined, mapped as

secondary), SATA Secondary (legacy mode)

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 139 Functional Description NOTES: 1. IDEIRQ can only be driven directly from the pin when in legacy IDE mode. 2. When programming the polarity of internal interrupt sources on the APIC, interrupts 0 through 15 receive active-high internal interrupt sources, while interrupts 16 through 23 receive active-low internal interrupt sources. 3. If IRQ 11 is used for HPET #2, software should ensure IRQ 11 is not shared with any other devices to guarantee the proper operation of HPET #2. ICH6 hardware does not prevent sharing of IRQ 11.

5.10.3 PCI / PCI Express* Message-Based Interrupts

When external devices through PCI / PCI Express wish to generate an interrupt, they will send the message defined in the PCI Express* Base Specification, Revision 1.0a for generating INTA# - INTD#. These will be translated internal assertions/de-assertions of INTA# - INTD#.

5.10.4 Front Side Bus Interrupt Delivery

For processors that support Front Side Bus (FSB) interrupt delivery, the ICH6 requires that the I/O APIC deliver interrupt messages to the processor in a parallel manner, rather than using the I/O APIC serial scheme. This is done by the ICH6 writing (via DMI) to a memory location that is snooped by the processor(s). The processor(s) snoop the cycle to know which interrupt goes active. The following sequence is used: 1. When the ICH6 detects an interrupt event (active edge for edge-triggered mode or a change for level-triggered mode), it sets or resets the internal IRR bit associated with that interrupt. 2. Internally, the ICH6 requests to use the bus in a way that automatically flushes upstream buffers. This can be internally implemented similar to a DMA device request. 3. The ICH6 then delivers the message by perfor ming a write cycle to the appropriate address with the appropriate data. The address and data formats are described below in Section 5.10.4.4. Note: FSB Interrupt Delivery compatibility with processor clock control depends on the processor, not the ICH6.

16 PIRQA# PIRQA#

Yes Internal devices are routable; see Section 7.1.41 thru Section 7.1.50.

17 PIRQB# PIRQB#

18 PIRQC# PIRQC#

19 PIRQD# PIRQD#

20 N/A PIRQE#

Option for SCI, TCO, HPET #0,1,2. Other internal devices are routable; see Section 7.1.41 thru Section 7.1.50.

21 N/A PIRQF#

22 N/A PIRQG#

23 N/A PIRQH#

Table 5-15. APIC Interrupt Mapping (Sheet 2 of 2) IRQ # Via SERIRQ Direct from Pin Via PCI Message Internal Modules

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5.10.4.1 Edge-Triggered Operation

In this case, the “Assert Message” is sent when there is an inactive-to-active edge on the interrupt.

5.10.4.2 Level-Triggered Operation

In this case, the “Assert Message” is sent when there is an inactive-to-active edge on the interrupt. If after the EOI the interrupt is still active, then another “Assert Message” is sent to indicate that the interrupt is still active.

5.10.4.3 Registers Associat ed with Front Side Bus

Capabilities Indication: The capability to support Front Side Bus interrupt delivery is indicated via ACPI configuration techniques. This involves the BIOS creating a data structure that gets reported to the ACPI configuration software.

5.10.4.4 Interrupt Message Format

The ICH6 writes the message to PCI (and to the Host controller) as a 32-bit memory write cycle. It uses the formats shown in Table 5-16 and Table 5-17 for the address and data. The local APIC (in the processor) has a delivery mode option to interpret Front Side Bus messages as a SMI in which case the processor treats the incoming interrupt as a SMI instead of as an interrupt. This does not mean that the ICH6 has any way to have a SMI source from ICH6 power management logic cause the I/O APIC to send an SMI message (there is no way to do this). The ICH6’s I/O APIC can only send interrupts due to interrupts which do not include SMI, NMI or INIT. This means that in IA32/IA64 based platforms, Front Side Bus interrupt message format delivery modes 010 (SMI/PMI), 100 (NMI), and 101 (INIT) as indicated in this section, must not be used and is not supported. Only the hardware pin connection is supported by ICH6. Table 5-16. Interrupt Message Address Format Bit Description 31:20 Will always be FEEh 19:12 Destination ID: This is the same as bits 63:56 of the I/O Redirection Table entry for the interrupt associated with this message. 11:4 Extended Destination ID: This is the same as bits 55:48 of the I/O Redirection Table entry for the interrupt associated with this message. Redirection Hint: This bit is used by the processor host bridge to allow the interrupt message to be redirected. 0 = The message will be delivered to the agent (processor) listed in bits 19:12. 1 = The message will be delivered to an agent with a lower interrupt priority This can be derived from bits 10:8 in the Data Field (see below). The Redirection Hint bit will be a 1 if bits 10:8 in the delivery mode field associated with corresponding interrupt are encoded as 001 (Lowest Priority). Otherwise, the Redirection Hint bit will be 0 Destination Mode: This bit is used only the Redirection Hint bit is set to 1. If the Redirection Hint bit and the Destination Mode bit are both set to 1, then the logical destination mode is used, and the redirection is limited only to those processors that are part of the logical group as based on the logical ID. 1:0 Will always be 00.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 141 Functional Description

5.11 Serial Interrupt (D31:F0)

The ICH6 supports a serial IRQ scheme. This allows a single signal to be used to report interrupt requests. The signal used to transmit this information is shared between the host, the ICH6, and all peripherals that support serial interrupts. The signal line, SERIRQ, is synchronous to PCI clock, and follows the sustained tri-state protocol that is used by all PCI signals. This means that if a device has driven SERIRQ low, it will first drive it high synchronous to PCI clock and release it the following PCI clock. The serial IRQ protocol defines this sustained tri-state signaling in the following fashion:

• S – Sample Phase. Signal driven low
• R – Recovery Phase. Signal driven high
• T – Turn-around Phase. Signal released The ICH6 supports a message for 21 serial interrupts. These represent the 15 ISA interrupts (IRQ0–1, 2–15), the four PCI interrupts, and the control signals SMI# and IOCHK#. The serial IRQ protocol does not support the additional APIC interrupts (20–23). Note: When the IDE controller is enabled or the SATA controller is configured for legacy IDE mode, IRQ14 and IRQ15 are are expected to behave as ISA legacy interrupts, which cannot be shared, i.e. through the Serial Interrupt pin. If IRQ14/IRQ15 are shared with the Serial Interrupt pin then abnormal system behavior may occur. For example, IRQ14/IRQ15 may not be detected by the ICH6’s interrupt controller. Table 5-17. Interrupt Message Data Format Bit Description 31:16 Will always be 0000h. 15 Trigger Mode: 1 = Level, 0 = Edge. Same as the corresponding bit in the I/O Redirection Table for that interrupt. 14 Delivery Status: 1 = Assert, 0 = De-assert. Only Assert messages are sent. This bit is always 1. 13:12 Will always be 00 11 Destination Mode: 1 = Logical. 0 = Physical. Same as the corresponding bit in the I/O Redirection Table for that interrupt. 10:8 Delivery Mode: This is the same as the corresponding bits in the I/O Redirection Table for that interrupt. 000 = Fixed 100 = NMI 001 = Lowest Priority 101 = INIT 010 = SMI/PMI 110 = Reserved 011 = Reserved 111 = ExtINT 7:0 Vector: This is the same as the corresponding bits in the I/O Redirection Table for that interrupt.

142 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

5.11.1 Start Frame

The serial IRQ protocol has two modes of operation which affect the start frame. These two modes are: Continuous, where the ICH6 is solely responsible for generating the start frame; and Quiet, where a serial IRQ peripheral is responsible for beginning the start frame. The mode that must first be entered when enabling the serial IRQ protocol is continuous mode. In this mode, the ICH6 asserts the start frame. This start frame is 4, 6, or 8 PCI clocks wide based upon the Serial IRQ Control Register, bits 1:0 at 64h in Device 31:Function 0 configuration space. This is a polling mode. When the serial IRQ stream enters quiet mode (signaled in the Stop Frame), the SERIRQ line remains inactive and pulled up between the Stop and Start Frame until a peripheral drives the SERIRQ signal low. The ICH6 senses the line low and continues to drive it low for the remainder of the Start Frame. Since the first PCI clock of the start frame was driven by the peripheral in this mode, the ICH6 drives the SERIRQ line low for 1 PCI clock less than in continuous mode. This mode of operation allows for a quiet, and therefore lower power, operation.

5.11.2 Data Frames

Once the Start frame has been initiated, all of the SERIRQ peripherals must start counting frames based on the rising edge of SERIRQ. Each of the IRQ/DATA frames has exactly 3 phases of 1 clock each:

• Sample Phase. During this phase, the SERIRQ device drives SERIRQ low if the corresponding interrupt signal is low. If the corresponding interrupt is high, then the SERIRQ devices tri-state the SERIRQ signal. The SERIRQ line remains high due to pull-up resistors (there is no internal pull-up resistor on this signal, an external pull-up resistor is required). A low level during the IRQ0–1 and IRQ2–15 frames indicates that an active-high ISA interrupt is not being requested, but a low level during the PCI INT[A:D], SMI#, and IOCHK# frame indicates that an active-low interrupt is being requested.
• Recovery Phase. During this phase, the device drives the SERIRQ line high if in the Sample Phase it was driven low. If it was not driven in the sample phase, it is tri-stated in this phase.
• Turn-around Phase. The device tri-states the SERIRQ line

5.11.3 Stop Frame

After all data frames, a Stop Frame is driven by the ICH6. The SERIRQ signal is driven low by the ICH6 for 2 or 3 PCI clocks. The number of clocks is determined by the SERIRQ configuration register. The number of clocks determines the next mode: Table 5-18. Stop Frame Explanation Stop Frame Width Next Mode 2 PCI clocks Quiet Mode. Any SERIRQ device may initiate a Start Frame 3 PCI clocks Continuous Mode. Only the host (Intel® ICH6) may initiate a Start Frame

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 143 Functional Description

5.11.4 Specific Interrupts Not Supported via SERIRQ

There are three interrupts seen through the serial stream that are not supported by the ICH6. These interrupts are generated internally, and are not sharable with other devices within the system. These interrupts are:

• IRQ0. Heartbeat interrupt generated off of the internal 8254 counter 0.
• IRQ8#. RTC interrupt can only be generated internally.
• IRQ13. Floating point error interrupt generated off of the processor assertion of FERR#. The ICH6 ignores the state of these interrupts in the serial stream, and does not adjust their level based on the level seen in the serial stream.

5.11.5 Data Frame Format

Table 5-19 shows the format of the data frames. For the PCI interrupts (A–D), the output from the ICH6 is ANDed with the PCI input signal. This way, the interrupt can be signaled via both the PCI interrupt input signal and via the SERIRQ signal (they are shared). Table 5-19. Data Frame Format Data Frame # Interrupt Clocks Past Start Frame Comment 1 IRQ0 2 Ignored. IRQ0 can only be generated via the internal 8524 2I R Q 1 5 3 SMI# 8 Causes SMI# if low. Will set the SERIRQ_SMI_STS bit. 4I R Q 3 1 1 5I R Q 4 1 4 6I R Q 5 1 7 7I R Q 6 2 0 8I R Q 7 2 3 9 IRQ8 26 Ignored. IRQ8# can only be generated internally.

10 IRQ9 29

11 IRQ10 32

12 IRQ11 35

13 IRQ12 38

14 IRQ13 41 Ignored. IRQ13 can only be generated from FERR#

15 IRQ14 44 Not attached to PATA or SATA logic

16 IRQ15 47 Not attached to PATA or SATA logic

17 IOCHCK# 50 Same as ISA IOCHCK# going active.

18 PCI INTA# 53 Drive PIRQA#

19 PCI INTB# 56 Drive PIRQB#

20 PCI INTC# 59 Drive PIRQC#

21 PCI INTD# 62 Drive PIRQD#

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5.12 Real Time Clock (D31:F0)

The Real Time Clock (RTC) module provides a battery backed-up date and time keeping device with two banks of static RAM with 128 bytes each, although the first bank has 114 bytes for general purpose usage. Three interrupt features are available: time of day alarm with once a second to once a month range, periodic rates of 122 µs to 500 ms, and end of update cycle notification. Seconds, minutes, hours, days, day of week, month, and year are counted. Daylight savings compensation is available. The hour is represented in twelve or twenty-four hour format, and data can be represented in BCD or binary format. The design is functionally compatible with the Motorola MS146818B. The time keeping comes from a 32.768 kHz oscillating source, which is divided to achieve an update every second. The lower 14 bytes on the lower RAM block has very specific functions. The first ten are for time and date information. The next four (0Ah to 0Dh) are registers, which configure and report RTC functions. The time and calendar data should match the data mode (BCD or binary) and hour mode (12 or 24 hour) as selected in register B. It is up to the programmer to make sure that data stored in these locations is within the reasonable values ranges and represents a possible date and time. The exception to these ranges is to store a value of C0–FFh in the Alarm bytes to indicate a don’t care situation. All Alarm conditions must match to trigger an Alarm Flag, which could trigger an Alarm Interrupt if enabled. The SET bit must be 1 while programming these locations to avoid clashes with an update cycle. Access to time and date information is done through the RAM locations. If a RAM read from the ten time and date bytes is attempted during an update cycle, the value read do not necessarily represent the true contents of those locations. Any RAM writes under the same conditions are ignored. Note: The leap year determination for adding a 29th day to February does not take into account the end-of-the-century exceptions. The logic simply assumes that all years divisible by 4 are leap years. According to the Royal Observatory Greenwich, years that are divisible by 100 are typically not leap years. In every fourth century (years divisible by 400, like 2000), the 100-year-exception is over-ridden and a leap-year occurs. Note that the year 2100 will be the first time in which the current RTC implementation would incorrectly calculate the leap-year. The ICH6 does not implement month/year alarms.

5.12.1 Update Cycles

An update cycle occurs once a second, if the SET bit of register B is not asserted and the divide chain is properly configured. During this procedure, the stored time and date are incremented, overflow is checked, a matching alarm condition is checked, and the time and date are rewritten to the RAM locations. The update cycle will start at least 488 µs after the UIP bit of register A is asserted, and the entire cycle does not take more than 1984 µs to complete. The time and date RAM locations (0–9) are disconnected from the external bus during this time. To avoid update and data corruption conditions, external RAM access to these locations can safely occur at two times. When a updated-ended interrupt is detected, almost 999 ms is available to read and write the valid time and date data. If the UIP bit of Register A is detected to be low, there is at least 488 µs before the update cycle begins. Warning: The overflow conditions for leap years and daylight savings adjustments are based on more than one date or time item. To ensure proper operation when adjusting the time, the new time and data values should be set at least two seconds before one of these conditions (leap year, daylight savings time adjustments) occurs.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 145 Functional Description

5.12.2 Interrupts

The real-time clock interrupt is internally routed within the ICH6 both to the I/O APIC and the 8259. It is mapped to interrupt vector 8. This interrupt does not leave the ICH6, nor is it shared with any other interrupt. IRQ8# from the SERIRQ stream is ignored. However, the High Performance Event Timers can also be mapped to IRQ8#; in this case, the RTC interrupt is blocked.

5.12.3 Lockable RAM Ranges

The RTC’s battery-backed RAM supports two 8-byte ranges that can be locked via the configuration space. If the locking bits are set, the corresponding range in the RAM will not be readable or writable. A write cycle to those locations will have no effect. A read cycle to those locations will not return the location’s actual value (resultant value is undefined). Once a range is locked, the range can be unlocked only by a hard reset, which will invoke the BIOS and allow it to relock the RAM range.

5.12.4 Century Rollover

The ICH6 detects a rollover when the Year byte (RTC I/O space, index offset 09h) transitions from 99 to 00. Upon detecting the rollover, the ICH6 sets the NEWCENTURY_STS bit (TCOBASE + 04h, bit 7). If the system is in an S0 state, this causes an SMI#. The SMI# handler can update registers in the RTC RAM that are associated with century value. If the system is in a sleep state (S1 –S5) when the century rollover occurs, the ICH6 also sets the NEWCENTURY_STS bit, but no SMI# is generated. When the system resumes from the sleep state, BIOS should check the NEWCENTURY_STS bit and update the century value in the RTC RAM.

5.12.5 Clearing Battery-Backed RTC RAM

Clearing CMOS RAM in an ICH6-based platform can be done by using a jumper on RTCRST# or GPI. Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low. Using RTCRST# to clear CMOS A jumper on RTCRST# can be used to clear CMOS values, as well as reset to default, the state of those configuration bits that reside in the RTC power well. When the RTCRST# is strapped to ground, the RTC_PWR_STS bit (D31:F0:A4h bit 2) will be set and those configuration bits in the RTC power well will be set to their default state. BIOS can monitor the state of this bit, and manually clear the RTC CMOS array once the system is booted. The normal position would cause RTCRST# to be pulled up through a weak pull-up resistor. Table 5-20 shows which bits are set to their default state when RTCRST# is asserted. This RTCRST# jumper technique allows the jumper to be moved and then replaced—a ll while the system is powered off. Then, once booted, the RTC_PWR_STS can be detected in the set state.

146 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

Table 5-20. Configuration Bits Reset by RTCRST# Assertion Bit Name Register Location Bit(s) Default State Alarm Interrupt Enable (AIE) Register B (General Configuration) (RTC_REGB) I/O space (RTC Index + 0Bh) 5 X Alarm Flag (AF) Register C (Flag Register) (RTC_REGC) I/O space (RTC Index + 0Ch) 5 X SWSMI_RATE_SEL General PM Configuration 3 Register GEN_PMCON_3 D31:F0:A4h 7:6 0 SLP_S4# Minimum Assertion Width General PM Configuration 3 Register GEN_PMCON_3 D31:F0:A4h 5:4 0 SLP_S4# Assertion Stretch Enable General PM Configuration 3 Register GEN_PMCON_3 D31:F0:A4h 3 0 RTC Power Status (RTC_PWR_STS) General PM Configuration 3 Register GEN_PMCON_3 D31:F0:A4h 2 0 Power Failure (PWR_FLR) General PM Configuration 3 Register (GEN_PMCON_3) D31:F0:A4h 1 0 AFTERG3_EN General PM Configuration 3 Register GEN_PMCON_3 D31:F0:A4h 0 0 Power Button Override Status (PRBTNOR_STS) Power Management 1 Status Register (PM1_STS) PMBase + 00h 11 0 RTC Event Enable (RTC_EN) Power Management 1 Enable Register (PM1_EN) PMBase + 02h 10 0 Sleep Type (SLP_TYP) Power Management 1 Control (PM1_CNT) PMBase + 04h 12:10 0 PME_EN General Purpose Event

0 Enables Register

(GPE0_EN) PMBase + 2Ch 11 0 BATLOW_EN General Purpose Event (GPE0_EN) PMBase + 2Ch 10 0 RI_EN General Purpose Event (GPE0_EN) PMBase + 2Ch 8 0 NEWCENTURY_STS TCO1 Status Register (TCO1_STS) TCOBase + 04h 7 0 Intruder Detect (INTRD_DET) TCO2 Status Register (TCO2_STS) TCOBase + 06h 0 0 Top Swap (TS) Backed Up Control Register (BUC) Chipset Configuration Registers:Offset 3414h 0X PATA Reset State (PRS) (Mobile Only) Backed Up Control Register (BUC) Chipset Configuration Registers:Offset 3414h 11

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 147 Functional Description Using a GPI to Clear CMOS A jumper on a GPI can also be used to clear CMOS values. BIOS would detect the setting of this GPI on system boot-up, and manually clear the CMOS array. Note: The GPI strap technique to clear CMOS requires multiple steps to implement. The system is booted with the jumper in new position, then powered back down. The jumper is replaced back to the normal position, then the system is rebooted again. Warning: Clearing CMOS, using a jumper on VccRTC, must not be implemented.

5.13 Processor Interface (D31:F0)

The ICH6 interfaces to the processor with a variety of signals

• Standard Outputs to processor: A20M#, SMI#, NMI, INIT#, INTR, STPCLK#, IGNNE#, CPUSLP#, CPUPWRGD
• Standard Input from processor: FERR#
• Intel SpeedStep® technology output to processor: CPUPWRGOOD (In mobile configurations) Most ICH6 outputs to the processor use standard buffers. The ICH6 has separate V_CPU_IO signals that are pulled up at the system level to the processor voltage, and thus determines VOH for the outputs to the processor.

5.13.1 Processor Interface Signals

This section describes each of the signals that interface between the ICH6 and the processor(s). Note that the behavior of some signals may vary during processor reset, as the signals are used for frequency strapping.

5.13.1.1 A20M# (Mask A20)

The A20M# signal is active (low) when both of the following conditions are true:

• The ALT_A20_GATE bit (Bit 1 of PORT92 register) is a 0
• The A20GATE input signal is a 0 The A20GATE input signal is expected to be generated by the external microcontroller (KBC).

5.13.1.2 INIT# (I nitialization)

The INIT# signal is active (driven low) based on any one of several events described in Table 5-21. When any of these events occur, INIT# is driven low for 16 PCI clocks, then driven high. Note: The 16-clock counter for INIT# assertion halts while STPCLK# is active. Therefore, if INIT# is supposed to go active while STPCLK# is asserted, it actually goes active after STPCLK# goes inactive. This section refers to INIT#, but applies to two signals: INIT# and INIT3_3V#, as INIT3_3V# is functionally identical to INIT#, but signaling at 3.3 V .

148 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

5.13.1.3 FERR#/IGNNE# (Numer ic Coprocessor Error /

Ignore Numeric Error) The ICH6 supports the coprocessor error function with the FERR#/IGNNE# pins. The function is enabled via the COPROC_ERR_EN bit (Chipset Configuration Registers:Offset 31FFh:bit 1). FERR# is tied directly to the Coprocessor Error signal of the processor. If FERR# is driven active by the processor, IRQ13 goes active (internally). When it detects a write to the COPROC_ERR register (I/O Register F0h), the ICH6 negates the internal IRQ13 and drives IGNNE# active. IGNNE# remains active until FERR# is driven inactive. IGNNE# is never driven active unless FERR# is active. If COPROC_ERR_EN is not set, the assertion of FERR# will not generate an internal IRQ13, nor will the write to F0h generate IGNNE#. Table 5-21. INIT# Going Active Cause of INIT# Going Active Comment Shutdown special cycle from processor. PORT92 write, where INIT_NOW (bit 0) transitions from a 0 to a 1. PORTCF9 write, where SYS_RST (bit 1) was a 0 and RST_CPU (bit 2) transitions from 0 to 1. RCIN# input signal goes low. RCIN# is expected to be driven by the external microcontroller (KBC). 0 to 1 transition on RCIN# must occur before the Intel ICH6 will arm INIT# to be generated again. NOTE: RCIN# signal is expected to be high during S3HOT and low during S3COLD, S4, and S5 states. Transition on the RCIN# signal in those states (or the transition to those states) may not necessarily cause the INIT# signal to be generated to the processor. Processor BIST To enter BIST, software sets CPU_BIST_EN bit and then does a full processor reset using the CF9 register. Figure 5-6. Coprocessor Error Timing Diagram FERR# Internal IRQ13 I/O Write to F0h IGNNE#

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 149 Functional Description

5.13.1.4 NMI (Non-Maskable Interrupt)

Non-Maskable Interrupts (NMIs) can be generated by several sources, as described in Table 5-22.

5.13.1.5 Stop Clock Request and Processor Sleep

(STPCLK# and CPUSLP#) The ICH6 power management logic controls these active-low signals. Refer to Section 5.14 for more information on the functionality of these signals.

5.13.1.6 Processor Power Good (CPUPWRGOOD)

This signal is connected to the processor’s PWRGOOD input. In mobile configurations to allow for Intel SpeedStep technology support, this signal is kept high during an Intel SpeedStep technology state transition to prevent loss of processor context. This is an open-drain output signal (external pull-up resistor required) that represents a logical AND of the ICH6’s PWROK and VRMPWRGD signals.

5.13.1.7 Deeper Sleep (D PSLP#) (Mobile Only)

This active-low signal controls the internal gating of the processor’s core clock. This signal asserts before and de-asserts after the STP_CPU# signal to effectively stop the processor’s clock (internally) in the states in which STP_CPU# can be used to stop the processor’s clock externally.

5.13.2 Dual-Processor Is sues (Desktop Only)

5.13.2.1 Signal Differences

In dual-processor designs, some of the processor signals are unused or used differently than for uniprocessor designs. Table 5-22. NMI Sources Cause of NMI Comment SERR# goes active (either internally, externally via SERR# signal, or via message from (G)MCH) Can instead be routed to generate an SCI, through the NMI2SCI_EN bit (Device 31:Function 0, TCO Base + 08h, bit 11). IOCHK# goes active via SERIRQ# stream (ISA system Error) Can instead be routed to generate an SCI, through the NMI2SCI_EN bit (Device 31:Function 0, TCO Base + 08h, bit 11). Table 5-23. DP Signal Differences Signal Difference A20M# / A20GATE Generally not used, but still supported by Intel ® ICH6. STPCLK# Used for S1 State as well as preparation for entry to S3–S5 Also allows for THERM# based throttling (not via ACPI control methods). Should be connected to both processors. FERR# / IGNNE# Generally not used, but still supported by ICH6.

150 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

5.13.2.2 Power Management

For multiple-processor (or multiple-core) configurations in which more than one Stop Grant cycle may be generated, the (G)MCH is expected to count Stop Grant cycles and only pass the last one through to the ICH6. This prevents the ICH6 from getting out of sync with the processor on multiple STPCLK# assertions. Because the S1 state will have the STPCLK# signal active, the STPCLK# signal can be connected to both processors. However, for ACPI implementations, the BIOS must indicate that the ICH6 only supports the C1 state for dual-processor designs. In going to the S1 state for desktop, multiple Stop-Grant cycles will be generated by the processors. The Intel ICH6 also has the option to assert the processor’s SLP# signal (CPUSLP#). It is assumed that prior to setting the SLP_EN bit that causes the transition to the S1 state, the processors will not be executing code that is likely to delay the Stop-Grant cycles. In going to the S3, S4, or S5 states, the system will appear to pass through the S1 state; thus, STPCLK# and SLP# are also used. During the S3, S4, and S5 states, both processors will lose power. Upon exit from those states, the processors will have their power restored.

5.14 Power Management (D31:F0)

5.14.1 Features

• Support for Advanced Configuration and Power Interface, Version 2.0 (ACPI) providing power and thermal management — ACPI 24-Bit Timer — Software initiated throttling of processor performance for Thermal and Power Reduction — Hardware Override to throttle proce ssor performance if system too hot — SCI and SMI# Generation
• PCI PME# signal for Wake Up from Low-Power states
• System Clock Control — (Mobile Only) ACPI C2 state: Stop Grant (using STPCLK# signal) halts processor’s instruction stream — (Mobile Only) ACPI C3 State: Ability to halt processor clock (but not memory clock) — (Mobile Only) ACPI C4 State: Ability to lower processor voltage. — (Mobile Only) CLKRUN# Protocol for PCI Clock Starting/Stopping
• System Sleep State Control — ACPI S1 state: Stop Grant (using STPCLK# signal) halts processor’s instruction stream (only STPCLK# active, and CPUSLP# optional) — ACPI S3 state — Suspend to RAM (STR) — ACPI S4 state — Suspend-to-Disk (STD) — ACPI G2/S5 state — Soft Off (SOFF) — Power Failure Detection and Recovery
• Streamlined Legacy Power Management for APM-Based Systems

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 151 Functional Description

5.14.2 Intel ® ICH6 and System Power States

Table 5-24 shows the power states defined for ICH6-based platforms. The state names generally match the corresponding ACPI states. Table 5-25 shows the transitions rules among the various states. Note that transitions among the various states may appear to temporarily transition through intermediate states. For example, in going from S0 to S1, it may appear to pass through the G0/S0/C2 states. These intermediate transitions and states are not listed in the table. Table 5-24. General Power States for Systems Using Intel® ICH6 State/ Substates Legacy Name / Description G0/S0/C0 Full On: Processor operating. Individual devices may be shut down to save power. The different processor operating levels are defined by Cx states, as shown in Table 5-25. Within the C0 state, the Intel® ICH6 can throttle the processor using the STPCLK# signal to reduce power consumption. The throttling can be initiated by software or by the operating system or BIOS. G0/S0/C1 Auto-Halt: Processor has executed an AutoHalt instruction and is not executing code. The processor snoops the bus and maintains cache coherency. G0/S0/C2 (Mobile Only) Stop-Grant: The STPCLK# signal goes active to the processor. The processor performs a Stop-Grant cycle, halts its instruction stream, and remains in that state until the STPCLK# signal goes inactive. In the Stop-Grant state, the processor snoops the bus and maintains cache coherency. G0/S0/C3 (Mobile Only) Stop-Clock: The STPCLK# signal goes active to the processor. The processor performs a Stop-Grant cycle, halts its instruction stream. ICH6 then asserts DPSLP# followed by STP_CPU#, which forces the clock generator to stop the processor clock. This is also used for Intel SpeedStep ® technology support. Accesses to memory (by graphics, PCI, or internal units) is not permitted while in a C3 state. G0/S0/C4 (Mobile Only) Stop-Clock with Lower Processor Voltage: This closely resembles the G0/S0/C3 state. However, after the ICH6 has asserted STP_CPU#, it then lowers the voltage to the processor. This reduces the leakage on the processor. Prior to exiting the C4 state, the ICH6 increases the voltage to the processor. G1/S1 Stop-Grant: Similar to G0/S0/C2 state. ICH6 also has the option to assert the CPUSLP# signal to further reduce processor power consumption. NOTE: The behavior for this state is slightly different when supporting iA64 processors. G1/S3 Suspend-To-RAM (STR): The system context is maintained in system DRAM, but power is shut off to non-critical circuits. Memory is retained, and refreshes continue. All clocks stop except RTC clock. G1/S4 Suspend-To-Disk (STD): The context of the system is maintained on the disk. All power is then shut off to the system except for the logic required to resume. G2/S5 Soft Off (SOFF): System context is not maintained. All power is shut off except for the logic required to restart. A full boot is required when waking. Mechanical OFF (MOFF): System context not maintained. All power is shut off except for the RTC. No “Wake” events are possible, because the system does not have any power. This state occurs if the user removes the batteries, turns off a mechanical switch, or if the system power supply is at a level that is insufficient to power the “waking” logic. When system power returns, transition will depends on the state just prior to the entry to G3 and the AFTERG3 bit in the GEN_PMCON3 register (D31:F0, offset A4). Refer to Table 5-32 for more details.

152 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

NOTES: 1. Transitions from the S1–S5 or G3 states to the S0 state are deferred until BATLOW# is inactive in mobile configurations. 2. Some wake events can be preserved through power failure. Table 5-25. State Transition Rules for Intel® ICH6 Present State Transition Trigger Next State G0/S0/C0

• Processor halt instruction
• Level 2 Read
• Level 3 Read (Mobile Only)
• Level 4 Read (Mobile Only)
• SLP_EN bit set
• Power Button Override
• Mechanical Off/Power Failure
• G 0 / S 0 / C 1
• G 0 / S 0 / C 2
• G0/S0/C2, G0/S0/C3 or G0/S0/C4 - depending on C4onC3_EN bit (D31:F0:Offset A0h:bit 7) and BM_STS_ZERO_EN bit (D31:F0:Offset A9h :bit 2) (Mobile Only)
• G1/Sx or G2/S5 state
• G 2 / S 5
• G 3 G0/S0/C1
• Any Enabled Break Event
• STPCLK# goes active
• Power Button Override
• Power Failure
• G 0 / S 0 / C 0
• G 0 / S 0 / C 2
• G 2 / S 5
• G 3 G0/S0/C2 (Mobile Only)
• Any Enabled Break Event
• Power Button Override
• Power Failure
• Previously in C3/C4 and bus masters idle
• G 0 / S 0 / C 0
• G 2 / S 5
• G 3
• C3 or C4 - depending on PDME bit (D31:F0: Offset A9h: bit 4) G0/S0/C3 (Mobile Only)
• Any Enabled Break Event
• Any Bus Master Event
• Power Button Override
• Power Failure
• Previously in C4 and bus masters idle
• G 0 / S 0 / C 0
• G0/S0/C2 - if PUME bit (D31:F0: Offset A9h: bit 3) is set, else G0/S0/C0
• G 2 / S 5
• G 3
• C4 - depending on PDME bit (D31:F0: Offset A9h: bit 4 G0/S0/C4 (Mobile Only)
• Any Enabled Break Event
• Any Bus Master Event
• Power Button Override
• Power Failure
• G 0 / S 0 / C 0
• G0/S0/C2 - if PUME bit (D31:F0: Offset A9h: bit 3) is set, else G0/S0/C0
• G 2 / S 5
• G 3 G1/S1, G1/S3, or G1/S4
• Any Enabled Wake Event
• Power Button Override
• Power Failure
• G0/S0/C0
• G 2 / S 5
• G 3 G2/S5 • Any Enabled Wake Event
• Power Failure
• G 0 / S 0 / C 01
• G 3
• Power Returns • Optional to go to S0/C0 (reboot) or G2/S5 (stay off until power button pressed or other wake event). 1,2

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 153 Functional Description

5.14.3 System Power Planes

The system has several independent power planes, as described in Table 5-26. Note that when a particular power plane is shut off, it should go to a 0 V level. s

5.14.4 SMI#/SCI Generation

On any SMI# event taking place, ICH6 asserts SMI# to the processor, which causes it to enter SMM space. SMI# remains active until the EOS bit is set. When the EOS bit is set, SMI# goes inactive for a minimum of 4 PCICLK. If another SMI event occurs, SMI# is driven active again. The SCI is a level-mode interrupt that is typically handled by an ACPI-aware operating system. In non-APIC systems (which is the default), the SCI IRQ is routed to one of the 8259 interrupts (IRQ 9, 10, or 11). The 8259 interrupt controller must be programmed to level mode for that interrupt. In systems using the APIC, the SCI can be routed to interrupts 9, 10, 11, 20, 21, 22, or 23. The interrupt polarity changes depending on whether it is on an interrupt shareable with a PIRQ or not (see Section 10.1.13). The interrupt remains asserted until all SCI sources are removed. Table 5-26. System Power Plane Plane Controlled By Description Processor SLP_S3# signal The SLP_S3# signal can be used to cut the power to the processor completely. The DPRSLPVR support allows lowering the processor’s voltage during the C4 state. HOT: The new S3HOT state keeps more of the platform logic, including the ICH6 core well, powered to reduce the cost of external power plane logic. SLP_S3# is only used to remove power to the processor and to shut system clocks. This impacts the board design, but there is no specific ICH6 bit or strap needed to indicate which option is selected. MAIN SLP_S3# signal (S3 COLD) or SLP_S4# signal (S3HOT) S3COLD: When SLP_S3# goes active, power can be shut off to any circuit not required to wake the system from the S3 state. Since the S3 state requires that the memory context be preserved, power must be retained to the main memory. The processor, devices on the PCI bus, LPC I/F, and graphics will typically be shut off when the Main power plane is shut, although there may be small subsections powered. HOT: SLP_S4# is used to cut the main power well, rather than using SLP_S3#. This impacts the board design, but there is no specific ICH6 bit or strap needed to indicate which option is selected. MEMORY SLP_S4# signal SLP_S5# signal When the SLP_S4# goes active, power can be shut off to any circuit not required to wake the system from the S4. Since the memory context does not need to be preserved in the S4 state, the power to the memory can also be shut down. When SLP_S5# goes active, power can be shut to any circuit not required to wake the system from the S5 state. Since the memory context does not need to be preserved in the S5 state, the power to the memory can also be shut. DEVICE[n] GPIO Individual subsystems may have their own power plane. For example, GPIO signals may be used to control the power to disk drives, audio amplifiers, or the display screen.

154 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

Table 5-27 shows which events can cause an SMI# and SCI. Note that some events can be programmed to cause either an SMI# or SCI. The usage of the event for SCI (instead of SMI#) is typically associated with an ACPI-based system. Each SMI# or SCI source has a corresponding enable and status bit. Table 5-27. Causes of SMI# and SCI (Sheet 1 of 2) Cause1-5 SCI SMI Additional Enables Where Reported PME# Yes Yes PME_EN=1 PME_STS PME_B0 (internal EHCI controller) Yes Yes PME_B0_EN=1 PME_B0_STS PCI Express* PME Messages Yes Yes PCI_EXP_EN=1 (Not enabled for SMI) PCI_EXP_STS PCI Express Hot Plug Message Yes Yes HOT_PLUG_EN=1 (Not enabled for SMI) HOT_PLUG_STS Power Button Press Yes Yes PWRBTN_EN=1 PWRBTN_STS Power Button Override (Note 6) Yes No None PRBTNOR_STS RTC Alarm Yes Yes RTC_EN=1 RTC_STS Ring Indicate Yes Yes RI_EN=1 RI_STS AC ’97 wakes Yes Yes AC97_EN=1 AC97_STS USB#1 wakes Yes Yes USB1_EN=1 USB1_STS USB#2 wakes Yes Yes USB2_EN=1 USB2_STS USB#3 wakes Yes Yes USB3_EN=1 USB3_STS USB#4 wakes Yes Yes USB4_EN=1 USB4_STS THRM# pin active Yes Yes THRM_EN=1 THRM_STS ACPI Timer overflow (2.34 sec.) Yes Yes TMROF_EN=1 TMROF_STS Any GPI

7 Yes Yes

GPI[x]_Route=10 (SCI) GPI[x]_Route=01 (SMI) GPE0[x]_EN=1 GPI[x]_STS GPE0_STS TCO SCI Logic Yes No TCOSCI_EN=1 TCOSCI_STS TCO SCI message from (G)MCH Yes No none MCHSCI_STS TCO SMI Logic No Yes TCO_EN=1 TCO_STS TCO SMI — Year 2000 Rollover No Yes none NEWCENTURY_STS TCO SMI — TCO TIMEROUT No Yes none TIMEOUT TCO SMI — OS writes to TCO_DAT_IN register No Yes none OS_TCO_SMI TCO SMI — Message from (G)MCH No Yes none MCHSMI_STS TCO SMI — NMI occurred (and NMIs mapped to SMI) No Yes NMI2SMI_EN=1 NMI2SMI_STS TCO SMI — INTRUDER# signal goes active No Yes INTRD_SEL=10 INTRD_DET TCO SMI — Change of the BIOSWP bit from 0 to 1 No Yes BLD=1 BIOSWR_STS TCO SMI — Write attempted to BIOS No Yes BIOSWP=1 BIOSWR_STS

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 155 Functional Description NOTES: 1. SCI_EN must be 1 to enable SCI. SCI_EN must be 0 to enable SMI. 2. SCI can be routed to cause interrupt 9:11 or 20:23 (20:23 only available in APIC mode). 3. GBL_SMI_EN must be 1 to enable SMI. 4. EOS must be written to 1 to re-enable SMI for the next 1. 5. ICH6 must have SMI# fully enabled when ICH6 is also enabled to trap cycles. If SMI# is not enabled in conjunction with the trap enabling, then hardware behavior is undefined. 6. When a power button override first occurs, the system will transition immediately to S5. The SCI will only occur after the next wake to S0 if the residual status bit (PRBTNOR_STS) is not cleared prior to setting SCI_EN. 7. Only GPI[15:0] may generate an SMI# or SCI.

5.14.4.1 PCI Express* SCI

PCI Express ports and the (G)MCH (via DMI) have the ability to cause PME using messages. When a PME message is received, ICH6 will set the PCI_EXP_STS bit. If the PCI_EXP_EN bit is also set, the ICH6 can cause an SCI via the GPE1_STS register.

5.14.4.2 PCI Express* Hot-Plug

PCI Express has a Hot-Plug mechanism and is capable of generating a SCI via the GPE1 register. It is also capable of generating an SMI. However, it is not capable of generating a wake event. BIOS_RLS written to Yes No GBL_EN=1 GBL_STS GBL_RLS written to No Yes BIOS_EN=1 BIOS_STS Write to B2h register No Yes APMC_EN = 1 APM_STS Periodic timer expires No Yes PERIODIC_EN=1 PERIODIC_STS 64 ms timer expires No Yes SWSMI_TMR_EN=1 SWSMI_TMR_STS Enhanced USB Legacy Support Event No Yes LEGACY_USB2_EN = 1 LEGACY_USB2_STS Enhanced USB Intel Specific Event No Yes INTEL_USB2_EN = 1 INTEL_USB2_STS UHCI USB Legacy logic No Yes LEGACY_USB_EN=1 LEGACY_USB_STS Serial IRQ SMI reported No Yes none SERIRQ_SMI_STS Device monitors match address in its range No Yes none DEVMON_STS, DEVACT_STS SMBus Host Controller No Yes SMB_SMI_EN Host Controller Enabled SMBus host status reg. SMBus Slave SMI message No Yes none SMBus_SMI_STS SMBus SMBALERT# signal active No Yes none SMBus_SMI_STS SMBus Host Notify message received No Yes HOST_NOTIFY_INTREN SMBus_SMI_STS HOST_NOTIFY_STS (Mobile Only) BATLOW# assertion Yes Yes BATLOW_EN=1. BATLOW_STS Access microcontroller 62h/66h No Yes MCSMI_EN MCSMI_STS SLP_EN bit written to 1 No Yes SMI_ON_SLP_EN=1 SMI_ON_SLP_EN_STS Table 5-27. Causes of SMI# and SCI (Sheet 2 of 2) Cause1-5 SCI SMI Additional Enables Where Reported

156 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

5.14.5 Dynamic Process or Clock Control

The ICH6 has extensive control for dynamically starting and stopping system clocks. The clock control is used for transitions among the various S0/Cx states, and processor throttling. Each dynamic clock control method is described in this section. The various sleep states may also perform types of non-dynamic clock control. The ICH6 supports the ACPI C0 and C1 states (in desktop) or C0, C1, C2, C3 and C4 (in mobile) states. The Dynamic Processor Clock control is handled using the following signals:

• STPCLK#: Used to halt pro cessor instruction stream.
• (Mobile Only) STP_CPU#: Used to stop processor’s clock
• (Mobile Only) CPUSLP#: Asserted prior to STP_CPU# (in stop grant mode)
• (Mobile Only) DPSLP# Used to fo rce Deeper Sleep for processor.
• (Mobile Only) DPRSLPVR: Used to lo wer voltage of VRM during C4 state.
• (Mobile Only) DPRSTP#: Used to lo wer voltage of VRM during C4 state The C1 state is entered based on the processor performing an auto halt instruction. (Mobile Only) The C2 state is entered based on the processor reading the Level 2 register in the ICH6. It can also be entered from C3 or C4 states if bus masters require snoops and the PUME bit (D31:F0: Offset A9h: bit 3) is set. (Mobile Only) The C3 state is entered based on the processor reading the Level 3 register in the ICH6 and when the C4onC3_EN bit is clear (D31:F0:Offset A0:bit 7). This state can also be entered after a temporary return to C2 from a prior C3 or C4 state. (Mobile Only) The C4 state is entered based on the processor reading the Level 4 register in the ICH6, or by reading the Level 3 register when the C4onC3_EN bit is set. This state can also be entered after a temporary return to C2 from a prior C4 state. A C1 state in desktop or a C1, C2, C3 or C4 state in mobile ends due to a Break event. Based on the break event, the ICH6 returns the system to C0 state. (Mobile Only) Table 5-28 lists the possible break events from C2, C3 or C4. The break events from C1 are indicated in the processor’s datasheet. Table 5-28. Break Events (Mobile Only) (Sheet 1 of 2) Event Breaks from Comment Any unmasked interrupt goes active C2, C3, C4 IRQ[0:15] when using the 8259s, IRQ[0:23] for I/O APIC. Since SCI is an interrupt, any SCI will also be a break event. Any internal event that cause an NMI or SMI# C2, C3, C4 Many possible sources

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 157 Functional Description

5.14.5.1 Transition Rules among S0/Cx and Throttling States

The following priority rules and assumptions apply among the various S0/Cx and throttling states:

• Entry to any S0/Cx state is mutually exclusive with entry to any S1–S5 state. This is because the processor can only perform one register access at a time and Sleep states have higher priority than thermal throttling.
• When the SLP_EN bit is set (system going to a S1 - S5 sleep state), the THTL_EN and FORCE_THTL bits can be internally treated as being disabled (no throttling while going to sleep state).
• (Mobile Only) If the THTL_EN or FORCE_THTL bits are set, and a Level 2, Level 3 or Level 4 read then occurs, the system should immediately go and stay in a C2, C3 or C4 state until a break event occurs. A Level 2, Level 3 or Level 4 read has higher priority than the software initiated throttling.
• (Mobile Only) After an exit from a C2, C3 or C4 state (due to a Break event), and if the THTL_EN or FORCE_THTL bits are still set the system will continue to throttle STPCLK#. Depending on the time of break event, the first transition on STPCLK# active can be delayed by up to one THRM period (1024 PCI clocks = 30.72 µs).
• The Host controller must post Stop-Grant cycles in such a way that the processor gets an indication of the end of the special cycle prior to the ICH6 observing the Stop-Grant cycle. This ensures that the STPCLK# signals stays active for a sufficient period after the processor observes the response phase.
• (Mobile Only) If in the C1 state and the STPCLK# signal goes active, the processor will generate a Stop-Grant cycle, and the system should go to the C2 state. When STPCLK# goes inactive, it should return to the C1 state.

5.14.5.2 Deferred C3/C4 (Mobile Only)

Due to the new DMI protocol, if there is any bus master activity (other than true isoch), then the C0 to C3 transition will pause at the C2 state. ICH6 will keep the processor in a C2 state until:

• ICH6 sees no bus master activity.
• A break event occurs. In this case, the ICH6 will perform the C2 to C0 sequence. Note that bus master traffic is not a break event in this case. Any internal event that cause INIT# to go active C2, C3, C4 Could be indicated by the keyboard controller via the RCIN input signal. Any bus master request (internal, external or DMA, or BMBUSY#) goes active and BM_RLD=1 (D31:F0:Offset PMBASE+04h: bit C3, C4 Need to wake up processor so it can do snoops Note: If the PUME bit (D31:F0: Offset A9h: bit 3) is set, then bus master activity will NOT be treated as a break event. Instead, there will be a return only to the C2 state. Processor Pending Break Event Indication C2, C3, C4 Only available if FERR# enabled for break event indication (See FERR# Mux Enable in GCS, Chipset Configuration Registers:Offset 3410h:bit 6) Table 5-28. Break Events (Mobile Only) (Sheet 2 of 2) Event Breaks from Comment

158 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

To take advantage of the Deferred C3/C4 mode, the BM_STS_ZERO_EN bit must be set. This will cause the BM_STS bit to read as 0 even if some bus master activity is present. If this is not done, then the software may avoid even attempting to go to the C3 or C4 state if it sees the BM_STS bit as 1. If the PUME bit (D31:F0: Offset A9h: bit 3) is 0, then the ICH6 will treat bus master activity as a break event. When reaching the C2 state, if there is any bus master activity, the ICH6 will return the processor to a C0 state.

5.14.5.3 POPUP (Auto C3/C4 to C2) (Mobile Only)

When the PUME bit (D31:F0: Offset A9h: bit 3) is set, the ICH6 enables a mode of operation where standard (non-isoch) bus master activity will not be treated as a full break event from the C3 or C4 states. Instead, these will be treated merely as bus master events and return the platform to a C2 state, and thus allow snoops to be performed. After returning to the C2 state, the bus master cycles will be sent to the (G)MCH, even if the ARB_DIS bit is set.

5.14.5.4 POPDOWN (Auto C2 to C3/C4) (Mobile Only)

After returning to the C2 state from C3/C4, it the PDME bit (D31:F0: Offset A9h: bit 4) is set, the platform can return to a C3 or C4 state (depending on where it was prior to going back up to C2). This behaves similar to the Deferred C3/C4 transition, and will keep the processor in a C2 state until:

• Bus masters are no longer active.
• A break event occurs. Note that bus master traffic is not a break event in this case.

5.14.6 Dynamic PCI Clock Control (Mobile Only)

The PCI clock can be dynamically controlled independent of any other low-power state. This control is accomplished using the CLKRUN# protocol as described in the PCI Mobile Design Guide, and is transparent to software. The Dynamic PCI Clock control is handled using the following signals:

• CLKRUN#: Used by PCI and LPC peripherals to request the system PCI clock to run
• STP_PCI#: Used to stop the system PCI clock Note: The 33 MHz clock to the ICH6 is “free-running” and is not affected by the STP_PCI# signal.

5.14.6.1 Conditions for Ch ecking the PCI Clock

When there is a lack of PCI activity the ICH6 has the capability to stop the PCI clocks to conserve power. “PCI activity” is defined as any activity that would require the PCI clock to be running. Any of the following conditions will indicate that it is not okay to stop the PCI clock:

• Cycles on PCI or LPC
• Cycles of any internal device that would need to go on the PCI bus
• SERIRQ activity

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 159 Functional Description Behavioral Description

• When there is a lack of activity (as defined above) for 29 PCI clocks, the ICH6 de-asserts (drive high) CLKRUN# for 1 clock and then tri-states the signal.

5.14.6.2 Conditions for Main taining the PCI Clock

PCI masters or LPC devices that wish to maintain the PCI clock running will observe the CLKRUN# signal de-asserted, and then must re-assert if (drive it low) within 3 clocks.

• When the ICH6 has tri-stated the CLKRUN# signal after de-asserting it, the ICH6 then checks to see if the signal has been re-asserted (externally).
• After observing the CLKRUN# signal asserted for 1 clock, the ICH6 again starts asserting the signal.
• If an internal device needs the PCI bus, the ICH6 asserts the CLKRUN# signal.

5.14.6.3 Conditions for Stopping the PCI Clock

• If no device re-asserts CLKRUN# once it has been de-asserted for at least 6 clocks, the ICH6 stops the PCI clock by asserting the STP_PCI# signal to the clock synthesizer.

5.14.6.4 Conditions for Re-S tarting the PCI Clock

• A peripheral asserts CLKRUN# to indicate that it needs the PCI clock re-started.
• When the ICH6 observes the CLKRUN# signal asserted for 1 (free running) clock, the ICH6 de-asserts the STP_PCI# signal to the clock synthesizer within 4 (free running) clocks.
• Observing the CLKRUN# signal asserted externally for 1 (free running) clock, the ICH6 again starts driving CLKRUN# asserted. If an internal source requests the clock to be re-started, the ICH6 re-asserts CLKRUN#, and simultaneously de-asserts the STP_PCI# signal.

5.14.6.5 LPC Devices and CLKRUN#

If an LPC device (of any type) needs the 33 MHz PCI clock, such as for LPC DMA or LPC serial interrupt, then it can assert CLKRUN#. Note that LPC devices running DMA or bus master cycles will not need to assert CLKRUN#, since the ICH6 asserts it on their behalf. The LDRQ# inputs are ignored by the ICH6 when the PCI clock is stopped to the LPC devices in order to avoid misinterpreting the request. The ICH6 assumes that only one more rising PCI clock edge occurs at the LPC device after the assertion of STP_PCI#. Upon de-assertion of STP_PCI#, the ICH6 assumes that the LPC device receives its first clock rising edge corresponding to the ICH6’s second PCI clock rising edge after the de-assertion.

160 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

5.14.7 Sleep States

5.14.7.1 Sleep State Overview

The ICH6 directly supports different sleep states (S1–S5), which are entered by setting the SLP_EN bit, or due to a Power Button press. The entry to the Sleep states are based on several assumptions:

• Entry to a Cx state is mutually exclusive with entry to a Sleep state. This is because the processor can only perform one register access at a time. A request to Sleep always has higher priority than throttling.
• Prior to setting the SLP_EN bit, the software turns off processor-controlled throttling. Note that thermal throttling cannot be disabled, but setting the SLP_EN bit disables thermal throttling (since S1–S5 sleep state has higher priority).
• The G3 state cannot be entered via any software mechanism. The G3 state indicates a complete loss of power.

5.14.7.2 Initiating Sleep State

Sleep states (S1–S5) are initiated by:

• Masking interrupts, turning off all bus master enable bits, setting the desired type in the SLP_TYP field, and then setting the SLP_EN bit. The hardware then attempts to gracefully put the system into the corresponding Sleep state.
• Pressing the PWRBTN# Signal for more than 4 seconds to cause a Power Button Override event. In this case the transition to the S5 state is less graceful, since there are no dependencies on observing Stop-Grant cycles from the processor or on clocks other than the RTC clock.

5.14.7.3 Exiting Sleep States

Sleep states (S1–S5) are exited based on Wake events. The Wake events forces the system to a full on state (S0), although some non-critical subsystems might still be shut off and have to be brought back manually. For example, the hard disk may be shut off during a sleep state, and have to be enabled via a GPIO pin before it can be used. Upon exit from the ICH6-controlled Sleep states, the WAK_STS bit is set. The possible causes of Wake Events (and their restrictions) are shown in Table 5-30. Note: (Mobile Only) If the BATLOW# signal is asserted, ICH6 does not attempt to wake from an S1–S5 state, even if the power button is pressed. This prevents the system from waking when the battery power is insufficient to wake the system. Wake events that occur while BATLOW# is asserted are latched by the ICH6, and the system wakes after BATLOW# is de-asserted. Table 5-29. Sleep Types Sleep Type Comment S1 Intel® ICH6 asserts the STPCLK# signal. It also has the option to assert CPUSLP# signal. This lowers the processor’s power consumption. No snooping is possible in this state. S3 ICH6 asserts SLP_S3#. The SLP_S3# signal controls the power to non-critical circuits. Power is only retained to devices needed to wake from this sleeping state, as well as to the memory. S4 ICH6 asserts SLP_S3# and SLP_S4#. The SLP_S4# signal shuts off the power to the memory subsystem. Only devices needed to wake from this state should be powered. S5 Same power state as S4. ICH6 asserts SLP_S3#, SLP_S4# and SLP_S5#.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 161 Functional Description NOTES: 1. If in the S5 state due to a powerbutton override or THRMTRIP#, the possible wake events are due to Power Button, Hard Reset Without Cycling (See Command Type 3 in Table 5-52), and Hard Reset System (See Command Type 4 in Table 5-52). 2. When the WAKE# pin is active and the PCI Express device is enabled to wake the system, the ICH6 will wake the platform. 3. This is a wake event from S5 only if the sleep state was entered by setting the SLP_EN and SLP_TYP bits via software, or if there is a power failure. It is important to understand that the various GPIs have different levels of functionality when used as wake events. The GPIs that reside in the core power well can only generate wake events from sleep states where the core well is powered. Table 5-31 summarizes the use of GPIs as wake events. The latency to exit the various Sleep states varies greatly and is heavily dependent on power supply design, so much so that the exit latencies due to the ICH6 are insignificant. Table 5-30. Causes of Wake Events Cause1,2 States Can Wake From How Enabled RTC Alarm S1 –S53 Set RTC_EN bit in PM1_EN register Power Button S1 –S5 Always enabled as Wake event GPI[0:15] S1 –S53 GPE0_EN register NOTE: GPIs that are in the core well are not capable of waking the system from sleep states where the core well is not powered. Classic USB S1 –S5 Set USB1_EN, USB 2_EN, USB3_EN, and USB4_EN bits in GPE0_EN register LAN S1 –S5 Will use PME#. Wake enable set with LAN logic. RI# S1 –S53 Set RI_EN bit in GPE0_EN register AC ‘97 / Intel High Definition Audio S1–S5 Set AC97_EN bit in GPE0_EN register Primary PME# S1 –S53 PME_B0_EN bit in GPE0_EN register Secondary PME# S1 –S5 Set PME_EN bit in GPE0_EN register. PCI_EXP_WAKE# S1–S5 PCI_EXP_WAKE bit (Note 3) PCI_EXP PME Message S1 Must use the PCI Express* WAKE# pin rather than messages for wake from S3,S4, or S5. SMBALERT# S1 –S5 Always enabled as Wake event SMBus Slave Message S1–S5 Wake/SMI# command always enabled as a Wake event. Note: SMBus Slave Message can wake the system from S1–S5, as well as from S5 due to Power Button Override. SMBus Host Notify message received S1–S5 HOST_NOTIFY_WKEN bit SMBus Slave Command register. Reported in the SMB_WAK_STS bit in the GPEO_STS register. Table 5-31. GPI Wake Events GPI Power Well Wake From Notes GPI[12, 7:0] Core S1 ACPI Compliant GPI[15:13,11:8] Resume S1–S5 ACPI Compliant

162 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

5.14.7.4 PCI Express* WAKE# Si gnal and PME Event Message

PCI Express ports can wake the platform from any sleep state (S1, S3, S4, or S5) using the WAKE# pin. WAKE# is treated as a wake event, but does not cause any bits to go active in the GPE_STS register. PCI Express ports and the (G)MCH (via DMI) have the ability to cause PME using messages. When a PME message is received, ICH6 will set the PCI_EXP_STS bit.

5.14.7.5 Sx-G3-Sx, Ha ndling Power Failures

Depending on when the power failure occurs and how the system is designed, different transitions could occur due to a power failure. The AFTER_G3 bit provides the ability to program whether or not the system should boot once power returns after a power loss event. If the policy is to not boot, the system remains in an S5 state (unless previously in S4). There are only three possible events that will wake the system after a power failure. 1. PWRBTN#: PWRBTN# is always enabled as a wake event. When RSMRST# is low (G3 state), the PWRBTN_STS bit is reset. When the ICH6 exits G3 after power returns (RSMRST# goes high), the PWRBTN# signal is already high (because VCC-standby goes high before RSMRST# goes high) and the PWRBTN_STS bit is 0. 2. RI#: RI# does not have an internal pull-up. Therefore, if this signal is enabled as a wake event, it is important to keep this signal powered during the power loss event. If this signal goes low (active), when power returns the RI_STS bit is set and the system interprets that as a wake event. 3. RTC Alarm: The RTC_EN bit is in the RTC well and is preserved after a power loss. Like PWRBTN_STS the RTC_STS bit is cleared when RSMRST# goes low. The ICH6 monitors both PWROK and RSMRST# to detect for power failures. If PWROK goes low, the PWROK_FLR bit is set. If RSMRST# goes low, PWR_FLR is set. Note: Although PME_EN is in the RTC well, this signal cannot wake the system after a power loss. PME_EN is cleared by RTCRST#, and PME_STS is cleared by RSMRST#. Table 5-32. Transitions Due to Power Failure State at Power Failure AFTERG3_EN bit Transition When Power Returns S0, S1, S3 1 S4 1 S5 1

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 163 Functional Description

5.14.8 Thermal Management

The ICH6 has mechanisms to assist with managing thermal problems in the system.

5.14.8.1 THRM# Signal

The THRM# signal is used as a status input for a thermal sensor. Based on the THRM# signal going active, the ICH6 generates an SMI# or SCI (depending on SCI_EN). If the THRM_POL bit is set low, when the THRM# signal goes low, the THRM_STS bit will be set. This is an indicator that the thermal threshold has been exceeded. If the THRM_EN bit is set, then when THRM_STS goes active, either an SMI# or SCI will be generated (depending on the SCI_EN bit being set). The power management software (BIOS or ACPI) can then take measures to start reducing the temperature. Examples include shutting off unwanted subsystems, or halting the processor. By setting the THRM_POL bit to high, another SMI# or SCI can optionally be generated when the THRM# signal goes back high. This allows the software (BIOS or ACPI) to turn off the cooling methods. Note: THRM# assertion does not cause a TCO event message in S3 or S4. The level of the signal is not reported in the heartbeat message.

5.14.8.2 Processor Initiated Passive Cooling

This mode is initiated by software setting the THTL_EN or THTL_DTY bits. Software sets the THTL_DTY bits to select throttle ratio and THTL_EN bit to enable the throttling. Throttling results in STPCLK# active for a minimum time of 12.5% and a maximum of 87.5%. The period is 1024 PCI clocks. Thus, the STPCLK# signal can be active for as little as 128 PCI clocks or as much as 896 PCI clocks. The actual slowdown (and cooling) of the processor depends on the instruction stream, because the processor is allowed to finish the current instruction. Furthermore, the ICH6 waits for the STOP-GRANT cycle before starting the count of the time the STPCLK# signal is active.

5.14.8.3 THRM# Override Software Bit

The FORCE_THTL bit allows the BIOS to force passive cooling, independent of the ACPI software (that uses the THTL_EN and THTL_DTY bits). If this bit is set, the ICH6 starts throttling using the ratio in the THRM_DTY field. When this bit is cleared, the ICH6 stops throttling, unless the THTL_EN bit is set (indicating that ACPI software is attempting throttling). If both the THTL_EN and FORCE_THTL bits are set, then the ICH should use the duty cycle defined by the THRM_DTY field, not the THTL_DTY field.

5.14.8.4 Active Cooling

Active cooling involves fans. The GPIO signals from the ICH6 can be used to turn on/off a fan.

164 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

5.14.9 Event Input Signals and Their Usage

The ICH6 has various input signals that trigger specific events. This section describes those signals and how they should be used.

5.14.9.1 PWRBTN# (Power Button)

The ICH6 PWRBTN# signal operates as a “Fixed Power Button” as described in the Advanced Configuration and Power Interface, Version 2.0b. PWRBTN# signal has a 16 ms de-bounce on the input. The state transition descriptions are included in Table 5-33. Note that the transitions start as soon as the PWRBTN# is pressed (but after the debounce logic), and does not depend on when the Power Button is released. Note: During the time that the SLP_S4# signal is stretched for the minimum assertion width (if enabled), the Power Button is not a wake event. Refer to Power Button Override Function section below for further detail. Power Button Override Function If PWRBTN# is observed active for at least four consecutive seconds, the state machine should unconditionally transition to the G2/S5 state, regardless of present state (S0–S4), even if PWROK is not active. In this case, the transition to the G2/S5 state should not depend on any particular response from the processor (e.g., a Stop-Grant cycle), nor any similar dependency from any other subsystem. The PWRBTN# status is readable to check if the button is currently being pressed or has been released. The status is taken after the de-bounce, and is readable via the PWRBTN_LVL bit. Note: The 4-second PWRBTN# assertion should only be used if a system lock-up has occurred. The 4-second timer starts counting when the ICH6 is in a S0 state. If the PWRBTN# signal is asserted and held active when the system is in a suspend state (S1–S5), the assertion causes a wake event. Once the system has resumed to the S0 state, the 4-second timer starts. Note: During the time that the SLP_S4# signal is stretched for the minimum assertion width (if enabled by D31:F0:A4h bit 3), the Power Button is not a wake event. As a result, it is conceivable that the user will press and continue to hold the Power Button waiting for the system to awake. Since a 4-second press of the Power Button is already defined as an Unconditional Power down, the power button timer will be forced to inactive while the power-cycle timer is in progress. Once the power-cycle timer has expired, the Power Button awakes the system. Once the minimum SLP_S4# Table 5-33. Transitions Due to Power Button Present State Event Transition/Action Comment S0/Cx PWRBTN# goes low SMI# or SCI generated (depending on SCI_EN) Software typically initiates a Sleep state S1–S5 PWRBTN# goes low Wake Event. Transitions to S0 state Standard wakeup G3 PWRBTN# pressed None No effect since no power Not latched nor detected S0–S4 PWRBTN# held low for at least 4 consecutive seconds Unconditional transition to S5 state No dependence on processor (e.g., Stop-Grant cycles) or any other subsystem

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 165 Functional Description power cycle expires, the Power Button must be pressed for another 4 to 5 seconds to create the Override condition to S5. Sleep Button The Advanced Configuration and Power Interface, Version 2.0b defines an optional Sleep button. It differs from the power button in that it only is a request to go from S0 to S1–S4 (not S5). Also, in an S5 state, the Power Button can wake the system, but the Sleep Button cannot. Although the ICH6 does not include a specific signal designated as a Sleep Button, one of the GPIO signals can be used to create a “Control Method” Sleep Button. See the Advanced Configuration and Power Interface, Version 2.0b for implementation details.

5.14.9.2 RI# (Ring Indicator)

The Ring Indicator can cause a wake event (if enabled) from the S1–S5 states. Table 5-34 shows when the wake event is generated or ignored in different states. If in the G0/S0/Cx states, the ICH6 generates an interrupt based on RI# active, and the interrupt will be set up as a Break event. Note: Filtering/Debounce on RI# will not be done in ICH6. Can be in modem or external.

5.14.9.3 PME# (PCI Power Management Event)

The PME# signal comes from a PCI device to request that the system be restarted. The PME# signal can generate an SMI#, SCI, or optionally a Wake event. The event occurs when the PME# signal goes from high to low. No event is caused when it goes from low to high. There is also an internal PME_B0 bit. This is separate from the external PME# signal and can cause the same effect.

5.14.9.4 SYS_RESET# Signal

When the SYS_RESET# pin is detected as active after the 16 ms debounce logic, the ICH6 attempts to perform a “graceful” reset, by waiting up to 25 ms for the SMBus to go idle. If the SMBus is idle when the pin is detected active, the reset occurs immediately; otherwise, the counter starts. If at any point during the count the SMBus goes idle the reset occurs. If, however, the counter expires and the SMBus is still active, a reset is forced upon the system even though activity is still occurring. Once the reset is asserted, it remains asserted for 5 to 6 ms regardless of whether the SYSRESET# input remains asserted or not. It cannot occur again until SYS_RESET# has been detected inactive after the debounce logic, and the system is back to a full S0 state with PLTRST# inactive. Note that if bit 3 of the CF9h I/O register is set then SYS_RESET# will result in a full power cycle reset. Table 5-34. Transitions Due to RI# Signal Present State Event RI_EN Event S0 RI# Active X Ignored S1–S5 RI# Active 0 Ignored Wake Event

166 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

5.14.9.5 THRMTRIP# Signal

If THRMTRIP# goes active, the processor is indicating an overheat condition, and the ICH6 immediately transitions to an S5 state. However, since the processor has overheated, it does not respond to the ICH6’s STPCLK# pin with a stop grant special cycle. Therefore, the ICH6 does not wait for one. Immediately upon seeing THRMTRIP# low, the ICH6 initiates a transition to the S5 state, drive SLP_S3#, SLP_S4#, SLP_S5# low, and set the CTS bit. The transition looks like a power button override. It is extremely important that when a THRMTRIP# event occurs, the ICH6 power down immediately without following the normal S0 -> S5 path. This path may be taken in parallel, but ICH6 must immediately enter a power down state. It does this by driving SLP_S3#, SLP_S4#, and SLP_S5# immediately after sampling THRMTRIP# active. If the processor is running extremely hot and is heating up, it is possible (although very unlikely) that components around it, such as the ICH6, are no longer executing cycles properly. Therefore, if THRMTRIP# goes active, and the ICH6 is relying on state machine logic to perform the power down, the state machine may not be working, and the system will not power down. The ICH6 follows this flow for THRMTRIP#. 1. At boot (PLTRST# low), THRMTRIP# ignored. 2. After power-up (PLTRST# high), if THRMTRIP# sampled active, SLP_S3#, SLP_S4#, and SLP_S5# assert, and normal sequence of sleep machine starts. 3. Until sleep machine enters the S5 state, SLP_S3#, SLP_S4#, and SLP_S5# stay active, even if THRMTRIP# is now inactive. This is the equivalent of “latching” the thermal trip event. 4. If S5 state reached, go to step #1, otherwise stay here. If the ICH6 never reaches S5, the ICH6 does not reboot until power is cycled. During boot, THRMTRIP# is ignored until SLP_S3#, PWROK, VRMPWRGD/VGATE, and PLTRST# are all ‘1’. During entry into a powered-down state (due to S3, S4, S5 entry, power cycle reset, etc.) THRMTRIP# is ignored until either SLP_S3# = 0, or PWROK = 0, or VRMPWRGD/ VGATE = 0. Note: A thermal trip event will:

• Set the AFTERG3_EN bit
• Clear the PWRBTN_STS bit
• Clear all the GPE0_EN register bits
• Clear the SMB_WAK_STS bit only if SMB_SAK_STS was set due to SMBus slave receiving message and not set due to SMBAlert

5.14.9.6 BMBUSY# (Mobile Only)

The BMBUSY# signal is an input from a graphics component to indicate if it is busy. If prior to going to the C3 state, the BMBUSY# signal is active, then the BM_STS bit will be set. If after going to the C3 state, the BMBUSY# signal goes back active, the ICH6 will treat this as if one of the PCI REQ# signals went active. This is treated as a break event.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 167 Functional Description

5.14.10 ALT Access Mode

Before entering a low power state, several registers from powered down parts may need to be saved. In the majority of cases, this is not an issue, as registers have read and write paths. However, several of the ISA compatible registers are either read only or write only. To get data out of write-only registers, and to restore data into read-only registers, the ICH6 implements an ALT access mode. If the ALT access mode is entered and exited after reading the registers of the ICH6 timer (8254), the timer starts counting faster (13.5 ms). The following steps listed below can cause problems: 1. BIOS enters ALT access mode for read ing the ICH6 timer related registers. 2. BIOS exits ALT access mode. 3. BIOS continues through the execution of other needed steps and passes control to the operating system. After getting control in step #3, if the operating system does not reprogram the system timer again, the timer ticks may be happening faster than expected. For example DOS and its associated software assume that the system timer is running at 54.6 ms and as a result the time-outs in the software may be happening faster than expected. Operating systems (e.g., Microsoft Windows* 98, Windows* 2000, and Windows NT*) reprogram the system timer and therefore do not encounter this problem. For some other loss (e.g., Microsoft MS-DOS*) the BIOS should restore the timer back to 54.6 ms before passing control to the operating system. If the BIOS is entering ALT access mode before entering the suspend state it is not necessary to restore the timer contents after the exit from ALT access mode.

168 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

5.14.10.1 Write Only Registers with Read Paths in

The registers described in Table 5-35 have read paths in ALT access mode. The access number field in the table indicates which register will be returned per access to that port. Table 5-35. Write Only Registers with Read Paths in ALT Access Mode (Sheet 1 of 2) Restore Data Restore Data I/O Addr # of Rds Access Data I/O Addr # of Rds Access Data 00h 2

1 DMA Chan 0 base address low byte

1 Timer Counter 0 status, bits [5:0]

2 DMA Chan 0 base address high byte 2 Timer Counter 0 base count low byte

1 DMA Chan 0 base count low byte 3 Timer Counter 0 base count high

2 DMA Chan 0 base count high byte 4 Timer Counter 1 base count low byte

1 DMA Chan 1 base address low byte 5 Timer Counter 1 base count high

2 DMA Chan 1 base address high byte 6 Timer Counter 2 base count low byte

1 DMA Chan 1 base count low byte 7 Timer Counter 2 base count high

2 DMA Chan 1 base count high byte 41h 1 Tim er Counter 1 status, bits [5:0]

1 DMA Chan 2 base address low byte 42h 1 Timer Counter 2 status, bits [5:0]

2 DMA Chan 2 base address high byte 70h 1 Bit 7 = NMI Enable,

Bits [6:0] = RTC Address 05h 2

1 DMA Chan 2 base count low byte

1 DMA Chan 5 base address low byte

2 DMA Chan 2 base count high byte 2 DMA Chan 5 base address high byte

1 DMA Chan 3 base address low byte

1 DMA Chan 5 base count low byte

2 DMA Chan 3 base address high byte 2 DMA Chan 5 base count high byte

1 DMA Chan 3 base count low byte

1 DMA Chan 6 base address low byte

2 DMA Chan 3 base count high byte 2 DMA Chan 6 base address high byte

1 DMA Chan 0–3 Command 2

1 DMA Chan 6 base count low byte

2 DMA Chan 0–3 Request 2 DMA Chan 6 base count high byte

3 DMA Chan 0 Mode:

Bits(1:0) = 00 CCh 2

1 DMA Chan 7 base address low byte

4 DMA Chan 1 Mode:

Bits(1:0) = 01 2 DMA Chan 7 base address high byte

5 DMA Chan 2 Mode:

Bits(1:0) = 10 CEh 2

1 DMA Chan 7 base count low byte

6 DMA Chan 3 Mode: Bits(1:0) = 11. 2 DMA Chan 7 base count high byte

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 169 Functional Description NOTES: 1. The OCW1 register must be read before entering ALT access mode. 2. Bits 5, 3, 1, and 0 return 0.

5.14.10.2 PIC Reserved Bits

Many bits within the PIC are reserved, and must have certain values written in order for the PIC to operate properly. Therefore, there is no need to return these values in ALT access mode. When reading PIC registers from 20h and A0h, the reserved bits shall return the values listed in Table 5-36. 20h 12

1 PIC ICW2 of Master controller

1 DMA Chan 4–7 Command 2

2 PIC ICW3 of Master controller 2 DMA Chan 4–7 Request

3 PIC ICW4 of Master controller 3 DMA Chan 4 Mode: Bits(1:0) = 00

4 PIC OCW1 of Master controller

1 4 DMA Chan 5 Mode: Bits(1:0) = 01

5 PIC OCW2 of Master controller 5 DMA Chan 6 Mode: Bits(1:0) = 10

6 PIC OCW3 of Master controller 6 DMA Chan 7 Mode: Bits(1:0) = 11.

7 PIC ICW2 of Slave controller

8 PIC ICW3 of Slave controller

9 PIC ICW4 of Slave controller

10 PIC OCW1 of Slave controller

11 PIC OCW2 of Slave controller

12 PIC OCW3 of Slave controller

Table 5-35. Write Only Registers with Read Paths in ALT Access Mode (Sheet 2 of 2) Restore Data Restore Data I/O Addr # of Rds Access Data I/O Addr # of Rds Access Data Table 5-36. PIC Reserved Bits Return Values PIC Reserved Bits Value Returned ICW2(2:0) 000 ICW4(7:5) 000 ICW4(3:2) 00 ICW4(0) 0 OCW2(4:3) 00 OCW3(7) 0 OCW3(5) Reflects bit 6 OCW3(4:3) 01

170 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

5.14.10.3 Read Only Regist ers with Write Paths in

The registers described in Table 5-37 have write paths to them in ALT access mode. Software restores these values after returning from a powered down state. These registers must be handled special by software. When in normal mode, writing to the base address/count register also writes to the current address/count register. Therefore, the base address/count must be written first, then the part is put into ALT access mode and the current address/count register is written.

5.14.11 System Power Supplie s, Planes, and Signals

5.14.11.1 Power Plane Contro l with SLP_S3#, SLP_S4#

and SLP_S5# The usage of SLP_S3# and SLP_S4# depends on whether the platform is configured for S3HOT and S3COLD.

5.14.11.1.1 S3 HOT

The SLP_S3# output signal is used to cut power only to the processor and associated subsystems and to optionally stop system clocks.

5.14.11.1.2 S3 COLD

The SLP_S3# output signal can be used to cut power to the system core supply, since it only goes active for the STR state (typically mapped to ACPI S3). Power must be maintained to the ICH6 resume well, and to any other circuits that need to generate Wake signals from the STR state. Cutting power to the core may be done via the power supply, or by external FETs to the motherboard. The SLP_S4# or SLP_S5# output signal can be used to cut power to the system core supply, as well as power to the system memory, since the context of the system is saved on the disk. Cutting power to the memory may be done via the power supply, or by external FETs to the motherboard. The SLP_S4# output signal is used to remove power to additional subsystems that are powered during SLP_S3#. SLP_S5# output signal can be used to cut power to the system core supply, as well as power to the system memory, since the context of the system is saved on the disk. Cutting power to the memory may be done via the power supply, or by external FETs to the motherboard. Table 5-37. Register Write Accesses in ALT Access Mode I/O Address Register Write Value 08h DMA Status Register for channels 0–3. D0h DMA Status Register for channels 4–7.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 171 Functional Description

5.14.11.2 SLP_S4# and Susp end-To-RAM Sequencing

The system memory suspend voltage regulator is controlled by the Glue logic. The SLP_S4# signal should be used to remove power to system memory rather than the SLP_S5# signal. The SLP_S4# logic in the ICH6 provides a mechanism to fully cycle the power to the DRAM and/or detect if the power is not cycled for a minimum time. Note: To use the minimum DRAM power-down feature that is enabled by the SLP_S4# Assertion Stretch Enable bit (D31:F0:A4h bit 3), the DRAM power must be controlled by the SLP_S4# signal.

5.14.11.3 PWROK Signal

The PWROK input should go active based on the core supply voltages becoming valid. PWROK should go active no sooner than 100 ms after Vcc3_3 and Vcc1_5 have reached their nominal values. Note: 1. SYSRESET# is recommended for implementing the system reset button. This saves external logic that is needed if the PWROK input is used. Additionally, it allows for better handling of the SMBus and processor resets, and avoids improperly reporting power failures. 2. If the PWROK input is used to implement the system reset button, the ICH6 does not provide any mechanism to limit the amount of time that the processor is held in reset. The platform must externally guarantee that maximum reset assertion specs are met. 3. If a design has an active-low reset button electrically AND’d with the PWROK signal from the power supply and the processor’s voltage regulator module the ICH6 PWROK_FLR bit will be set. The ICH6 treats this internally as if the RSMRST# signal had gone active. However, it is not treated as a full power failure. If PWROK goes inactive and then active (but RSMRST# stays high), then the ICH6 reboots (regardless of the state of the AFTERG3 bit). If the RSMRST# signal also goes low before PWROK goes high, then this is a full power failure, and the reboot policy is controlled by the AFTERG3 bit. 4. PWROK and RSMRST# are sampled using the RTC clock. Therefore, low times that are less than one RTC clock period may not be detected by the ICH6. 5. In the case of true PWROK failure, PW ROK goes low first before the VRMPWRGD.

5.14.11.4 CPUPWRGD Signal

This signal is connected to the processor’s VRM via the VRMPWRGD signal and is internally AND’d with the PWROK signal that comes from the system power supply.

5.14.11.5 VRMPWRGD Signal

VRMPWRGD is an input from the regulator indicating that all of the outputs from the regulator are on and within specification. VRMPWRGD may go active before or after the PWROK from the main power supply. ICH6 has no dependency on the order in which these two signals go active or inactive.

5.14.11.6 BATLOW# (Battery Low) (Mobile Only)

The BATLOW# input can inhibit waking from S3, S4, and S5 states if there is not sufficient power. It also causes an SMI# if the system is already in an S0 state.

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5.14.11.7 Controlling Leakage and Power Consumption

To control leakage in the system, various signals tri-state or go low during some low-power states. General principles:

• All signals going to powered down planes (either internally or externally) must be either tri-stated or driven low.
• Signals with pull-up resistors should not be low during low-power states. This is to avoid the power consumed in the pull-up resistor.
• Buses should be halted (and held) in a known state to avoid a floating input (perhaps to some other device). Floating inputs can cause extra power consumption. Based on the above principles, the following measures are taken:
• During S3 (STR), all signals attached to powered down planes are tri-stated or driven low.

5.14.12 Clock Generators

The clock generator is expected to provide the frequencies shown in Table 5-38. Table 5-38. Intel® ICH6 Clock Inputs Clock Domain Frequency Source Usage SATA_CLK Used by SATA controller. Stopped in S3 ~ S5 based on SLP_S3# assertion. DMI_CLK 100 MHz Differential Main Clock Generator Used by DMI and PCI Express*. Stopped in S3 ~ S5 based on SLP_S3# assertion. PCICLK 33 MHz Main Clock Generator Desktop: Free-running PCI Clock to ICH6. Stopped in S3 ~ S5 based on SLP_S3# assertion. Mobile: Free-running (not affected by STP_PCI# PCI Clock to ICH6. This is not the system PCI clock. This clock must keep running in S0 while the system PCI clock may stop based on CLKRUN# protocol. Stopped in S3 ~ S5 based on SLP_S3# assertion. CLK48 48.000 MHz Main Clock Generator Used by USB controllers and Intel High Definition Audio controller. Stopped in S3 ~ S5 based on SLP_S3# assertion. CLK14 14.318 MHz Main Clock Generator Used by ACPI timers. Stopped in S3 ~ S5 based on SLP_S3# assertion. ACZ_BIT_CLK 12.288 MHz AC ’97 Codec AC-link. Control policy is determined by the clock source. NOTE: Becomes clock output when Intel High Definition Audio is enabled. LAN_CLK 0.8 to LAN Connect Interface. Control policy is determined by the clock source.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 173 Functional Description

5.14.12.1 Clock Control Signals from Intel® ICH6 to Clock

Synthesizer (Mobile Only) The clock generator is assumed to have direct connect from the following ICH6 signals:

• STP_CPU# Stops processor cl ocks in C3 and C4 states
• STP_PCI# Stops system PCI clocks (not the ICH6 free-running 33 MHz clock) due to CLKRUN# protocol
• SLP_S3# Expected to drive clock chip PWRDOWN (through inverter), to stop clocks in S3HOT and on the way to S3COLD to S5.

5.14.13 Legacy Power Manageme nt Theory of Operation

Instead of relying on ACPI software, legacy power management uses BIOS and various hardware mechanisms. The scheme relies on the concept of detecting when individual subsystems are idle, detecting when the whole system is idle, and detecting when accesses are attempted to idle subsystems. However, the operating system is assumed to be at least APM enabled. Without APM calls, there is no quick way to know when the system is idle between keystrokes. The ICH6 does not support burst modes.

5.14.13.1 APM Power Management (Desktop Only)

The ICH6 has a timer that, when enabled by the 1MIN_EN bit in the SMI Control and Enable register, generates an SMI# once per minute. The SMI handler can check for system activity by reading the DEV ACT_STS register. If none of the system bits are set, the SMI handler can increment a software counter. When the counter reaches a sufficient number of consecutive minutes with no activity, the SMI handler can then put the system into a lower power state. If there is activity, various bits in the DEV ACT_STS register will be set. Software clears the bits by writing a 1 to the bit position. The DEV ACT_STS register allows for monitoring various internal devices, or Super I/O devices (SP, PP, FDC) on LPC or PCI, keyboard controller accesses, or audio functions on LPC or PCI. Other PCI activity can be monitored by checking the PCI interrupts.

5.14.13.2 Mobile APM Power Ma nagement (Mobile Only)

In mobile systems, there are additional requirements associated with device power management. To handle this, the ICH6 has specific SMI# traps available. The following algorithm is used: 1. The periodic SMI# timer checks if a device is idle for the require time. If so, it puts the device into a low-power state and sets the associated SMI# trap. 2. When software (not the SMI# handler) attempts to access the device, a trap occurs (the cycle does not really go to the device and an SMI# is generated). 3. The SMI# handler turns on th e device and turns off the trap The SMI# handler exits with an I/O restart. This allows the original software to continue.

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5.15 System Management (D31:F0)

The ICH6 provides various functions to make a system easier to manage and to lower the Total Cost of Ownership (TCO) of the system. In addition, ICH6 provides integrated ASF Management support. Features and functions can be augmented via external A/D converters and GPIO, as well as an external microcontroller. The following features and functions are supported by the ICH6:

• Processor present detection — Detects if processor fails to fetc h the first instruction after reset
• Various Error detection (such as ECC Errors) Indicated by host controller — Can generate SMI#, SCI, SERR, NMI, or TCO interrupt
• Intruder Detect input — Can generate TCO interrupt or SMI# when the system cover is removed — INTRUDER# allowed to go active in any power state, including G3
• Detection of bad Firmware Hub programming — Detects if data on first read is FFh (indicates unprogrammed Firmware Hub)
• Ability to hide a PCI device — Allows software to hide a PCI device in term s of configuration space through the use of a device hide register (See Section 7.1.56)
• Integrated ASF Management support Note: V oltage ID from the processor can be read via GPI signals.

5.15.1 Theory of Operation

The System Management functions are designed to allow the system to diagnose failing subsystems. The intent of this logic is that some of the system management functionality be provided without the aid of an external microcontroller.

5.15.1.1 Detecting a System Lockup

When the processor is reset, it is expected to fetch its first instruction. If the processor fails to fetch the first instruction after reset, the TCO timer times out twice and the ICH6 asserts PLTRST#.

5.15.1.2 Handling an Intruder

The ICH6 has an input signal, INTRUDER#, that can be attached to a switch that is activated by the system’s case being open. This input has a two RTC clock debounce. If INTRUDER# goes active (after the debouncer), this will set the INTRD_DET bit in the TCO_STS register. The INTRD_SEL bits in the TCO_CNT register can enable the ICH6 to cause an SMI# or interrupt. The BIOS or interrupt handler can then cause a transition to the S5 state by writing to the SLP_EN bit. The software can also directly read the status of the INTRUDER# signal (high or low) by clearing and then reading the INTRD_DET bit. This allows the signal to be used as a GPI if the intruder function is not required.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 175 Functional Description If the INTRUDER# signal goes inactive some point after the INTRD_DET bit is written as a 1, then the INTRD_DET signal will go to a 0 when INTRUDER# input signal goes inactive. Note that this is slightly different than a classic sticky bit, since most sticky bits would remain active indefinitely when the signal goes active and would immediately go inactive when a 1 is written to the bit. Note: The INTRD_DET bit resides in the ICH6’s RTC well, and is set and cleared synchronously with the RTC clock. Thus, when software attempts to clear INTRD_DET (by writing a 1 to the bit location) there may be as much as two RTC clocks (about 65 µs) delay before the bit is actually cleared. Also, the INTRUDER# signal should be asserted for a minimum of 1 ms to guarantee that the INTRD_DET bit will be set. Note: If the INTRUDER# signal is still active when software attempts to clear the INTRD_DET bit, the bit remains set and the SMI is generated again immediately. The SMI handler can clear the INTRD_SEL bits to avoid further SMIs. However, if the INTRUDER# signal goes inactive and then active again, there will not be further SMIs, since the INTRD_SEL bits would select that no SMI# be generated.

5.15.1.3 Detecting Improper Firmware Hub Programming

The ICH6 can detect the case where the Firmware Hub is not programmed. This results in the first instruction fetched to have a value of FFh. If this occurs, the ICH6 sets the BAD_BIOS bit, which can then be reported via the Heartbeat and Event reporting using an external, Alert on LAN* enabled LAN controller (See Section 5.15.2).

5.15.2 Heartbeat and Even t Reporting via SMBus

The ICH6 integrated LAN controller supports ASF heartbeat and event reporting functionality when used with the 82562EM or 82562EX Platform LAN Connect component. This allows the integrated LAN controller to report messages to a network management console without the aid of the system processor. This is crucial in cases where the processor is malfunctioning or cannot function due to being in a low-power state. All heartbeat and event messages are sent on the SMBus interface. This allows an external LAN controller to act upon these messages if the internal LAN controller is not used. The basic scheme is for the ICH6 integrated LAN controller to send a prepared Ethernet message to a network management console. The prepared message is stored in the non-volatile EEPROM that is connected to the ICH6. Messages are sent by the LAN controller either because a specific event has occurred, or they are sent periodically (also known as a heartbeat). The event and heartbeat messages have the exact same format. The event messages are sent based on events occurring. The heartbeat messages are sent every 30 to 32 seconds. When an event occurs, the ICH6 sends a new message and increments the SEQ[3:0] field. For heartbeat messages, the sequence number does not increment.

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The following rules/steps apply if the system is in a G0 state and the policy is for the ICH6 to reboot the system after a hardware lockup: 1. On detecting the lockup, the SECOND_TO_STS bit is set. The ICH6 may send up to 1 Event message to the LAN controller. The ICH6 then attempts to reboot the processor. 2. If the reboot at step 1 is successful then the BIOS should clear the SECOND_TO_STS bit. This prevents any further Heartbeats from being sent. The BIOS may then perform addition recovery/boot steps. (See note 2, below.) 3. If the reboot attempt in step 1 is not successful, the timer will timeout a third time. At this point the system has locked up and was unsuccessful in rebooting. The ICH6 does not attempt to automatically reboot again. The ICH6 starts sending a message every heartbeat period (30–32 seconds). The heartbeats continue until some external intervention occurs (reset, power failure, etc.). 4. After step 3 (unsuccessful reboot after th ird timeout), if the user does a Power Button Override, the system goes to an S5 state. The ICH6 continues sending the messages every heartbeat period. 5. After step 4 (power button override after unsu ccessful reboot) if the user presses the Power Button again, the system should wake to an S0 state and the processor should start executing the BIOS. 6. If step 5 (power button press) is successful in waking the system, the ICH6 continues sending messages every heartbeat period until the BIOS clears the SECOND_TO_STS bit. (See note 2) 7. If step 5 (power button press) is unsuccessf ul in waking the system, the ICH6 continues sending a message every heartbeat period. The ICH6 does not attempt to automatically reboot again. The ICH6 starts sending a message every heartbeat period (30–32 seconds). The heartbeats continue until some external intervention occurs (reset, power failure, etc.). (See note 3) 8. After step 3 (unsuccessful reboot after third ti meout), if a reset is attempted (using a button that pulses PWROK low or via the message on the SMBus slave I/F), the ICH6 attempts to reset the system. 9. After step 8 (reset attempt) if the reset is successful, the BIOS is run. The ICH6 continues sending a message every heartbeat period until the BIOS clears the SECOND_TO_STS bit. (See note 2) 10. After step 8 (reset attempt), if the reset is unsuccessful, the ICH6 continues sending a message every heartbeat period. The ICH6 does not attempt to reboot the system again without external intervention. (See note 3) The following rules/steps apply if the system is in a G0 state and the policy is for the ICH6 to not reboot the system after a hardware lockup. 1. On detecting the lockup the SECOND_TO_STS bit is set. The ICH6 sends a message with the Watchdog (WD) Event status bit set (and any other bits that must also be set). This message is sent as soon as the lockup is detected, and is sent with the next (incremented) sequence number. 2. After step 1, the ICH6 sends a message every heartbeat period until some external intervention occurs. 3. Rules/steps 4–10 apply if no user interventi on (resets, power button presses, SMBus reset messages) occur after a third timeout of the watchdog timer. If the intervention occurs before the third timeout, then jump to rule/step 11. 4. After step 3 (third timeout), if the user does a Power Button Override, the system goes to an S5 state. The ICH6 continues sending heartbeats at this point.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 177 Functional Description 5. After step 4 (power button override), if the user presses the power button again, the system should wake to an S0 state and the processor should start executing the BIOS. 6. If step 5 (power button press) is successful in waking the system, the ICH6 continues sending heartbeats until the BIOS clears the SECOND_TO_STS bit. (See note 2) 7. If step 5 (power button press) is unsuccessful in waking the system, the ICH6 continues sending heartbeats. The ICH6 does not attempt to reboot the system again until some external intervention occurs (reset, power failure, etc.). (See note 3) 8. After step 3 (third timeout), if a reset is attempted (using a button that pulses PWROK low or via the message on the SMBus slave I/F), the ICH6 attempts to reset the system. 9. If step 8 (reset attempt) is successful, the BIOS is run. The ICH6 continues sending heartbeats until the BIOS clears the SECOND_TO_STS bit. (See note 2) 10. If step 8 (reset attempt), is unsuccessful, the ICH6 continues sending heartbeats. The ICH6 does not attempt to reboot the system again without external intervention. Note: A system that has locked up and can not be restarted with power button press is probably broken (bad power supply, short circuit on some bus, etc.) 11. This and the following rules/steps apply if the user intervention (power button press, reset, SMBus message, etc.) occur prior to the third timeout of the watchdog timer. 12. After step 1 (second timeout), if the user does a Power Button Override, the system goes to an S5 state. The ICH6 continues sending heartbeats at this point. 13. After step 12 (power button override), if the user presses the power button again, the system should wake to an S0 state and the processor should start executing the BIOS. 14. If step 13 (power button press) is successful in waking the system, the ICH6 continues sending heartbeats until the BIOS clears the SECOND_TO_STS bit. (See note 2) 15. If step 13 (power button press) is unsuccessful in waking the system, the ICH6 continues sending heartbeats. The ICH6 does not attempt to reboot the system again until some external intervention occurs (reset, power failure, etc.). (See note 3) 16. After step 1 (second timeout), if a reset is attempted (using a button that pulses PWROK low or via the message on the SMBus slave I/F), the ICH6 attempts to reset the system. 17. If step 16 (reset attempt) is successful, the BIOS is run. The ICH6 continues sending heartbeats until the BIOS clears the SECOND_TO_STS bit. (See note 2) 18. If step 16 (reset attempt), is unsuccessful, the ICH6 continues sending heartbeats. The ICH6 does not attempt to reboot the system again without external intervention. (See note 3) If the system is in a G1 (S1–S4) state, the ICH6 sends a heartbeat message every 30–32 seconds. If an event occurs prior to the system being shutdown, the ICH6 immediately sends an event message with the next incremented sequence number. After the event message, the ICH6 resumes sending heartbeat messages. Note: Notes for previous two numbered lists. 1. Normally, the ICH6 does not se nd heartbeat messages while in the G0 state (except in the case of a lockup). However, if a hardware event (or heartbeat) occurs just as the system is transitioning into a G0 state, the hardware continues to send the message even though the system is in a G0 state (and the status bits may indicate this). These messages are sent via the SMBus. The ICH6 abides by the SMBus rules associated with collision detection. It delays starting a message until the bus is idle, and detects collisions. If a collision is detected the ICH6 waits until the bus is idle, and tries again. 2. WARNING: It is important the BIOS clears the SECOND_TO_STS bit, as the alerts interfere with the LAN device driver from working properly. The alerts reset part of the LAN controller

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and would prevent an operating system’s device driver from sending or receiving some messages. 3. A system that has locked up and can not be restarted with power button press is assumed to have broken hardware (bad power supply, short circuit on some bus, etc.), and is beyond ICH6’s recovery mechanisms. 4. A spurious alert could occu r in the following sequence: — The processor has initiated an alert using the SEND_NOW bit — During the alert, the THRM#, IN TRUDER# or GPI[11] changes state — The system then goes to a non-S0 state. Once the system transitions to the non-S0 state, it may send a single alert with an incremental SEQUENCE number. 5. An inaccurate alert message can be generated in the following scenario — The system successfully boots afte r a second watchdog Timeout occurs. — PWROK goes low (typically due to a reset button press) or a power button override occurs (before the SECOND_TO_STS bit is cleared). — An alert message indicating that the processor is missing or locked up is generated with a new sequence number. Table 5-39 shows the data included in the Alert on LAN messages. Table 5-39. Heartbeat Message Data Field Comment Cover Tamper Status 1 = This bit is set if the intruder detect bit is set (INTRD_DET). Temp Event Status 1 = This bit is set if the Intel ® ICH6 THERM# input signal is asserted. Processor Missing Event Status 1 = This bit is set if the processor failed to fetch its first instruction. TCO Timer Event Status 1 = This bit is set when the TCO timer expires. Software Event Status 1 = This bit is set when software writes a 1 to the SEND_NOW bit. Unprogrammed Firmware Hub Event Status 1 = First BIOS fetch returned a value of FFh, indicating that the Firmware Hub has not yet been programmed (still erased). GPIO Status 1 = This bit is set when GPI[11] signal is high. 0 = This bit is cleared when GPI[11] signal is low. An event message is triggered on an transition of GPI[11]. SEQ[3:0] This is a sequence number. It initially is 0, and increments each time the ICH6 sends a new message. Upon reaching 1111, the sequence number rolls over to 0000. MSB (SEQ3) sent first. System Power State 00 = G0, 01 = G1, 10 = G2, 11 = Pre-Boot. MSB sent first MESSAGE1 Will be the same as the MESSAGE1 Register. MSB sent first. MESSAGE2 Will be the same as the MESSAGE2 Register. MSB sent first. WDSTATUS Will be the same as the WD STATUS Register. MSB sent first.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 179 Functional Description

5.16 IDE Controller (D31:F1)

The ICH6 IDE controller features one sets of interface signals that can be enabled, tri-stated or driven low. The IDE interfaces of the ICH6 can support several types of data transfers:

• Programmed I/O (PIO): Processor is in control of the data transfer.
• 8237 style DMA: DMA protocol that resembles the DMA on the ISA bus, although it does not use the 8237 in the ICH6. This protocol off loads the processor from moving data. This allows higher transfer rate of up to 16 MB/s.
• Ultra ATA/33: DMA protocol that redefines signals on the IDE cable to allow both host and target throttling of data and transfer rates of up to 33 MB/s.
• Ultra ATA/66: DMA protocol that redefines signals on the IDE cable to allow both host and target throttling of data and transfer rates of up to 66 MB/s.
• Ultra ATA/100: DMA protocol that redefines signals on the IDE cable to allow both host and target throttling of data and transfer rates of up to 100 MB/s.

5.16.1 PIO Transfers

The ICH6 IDE controller includes both compatible and fast timing modes. The fast timing modes can be enabled only for the IDE data ports. All other transactions to the IDE registers are run in single transaction mode with compatible timings. Up to two IDE devices may be attached to the IDE connector (drive 0 and drive 1). The IDE_TIMP and IDE_TIMS Registers permit different timing modes to be programmed for drive 0 and drive 1 of the same connector. The Ultra ATA/33/66/100 synchronous DMA timing modes can also be applied to each drive by programming the IDE I/O Configuration register and the Synchronous DMA Control and Timing registers. When a drive is enabled for synchronous DMA mode operation, the DMA transfers are executed with the synchronous DMA timings. The PIO transfers are executed using compatible timings or fast timings if also enabled.

5.16.1.1 PIO IDE Timing Modes

IDE data port transaction latency consists of startup latency, cycle latency, and shutdown latency. Startup latency is incurred when a PCI master cycle targeting the IDE data port is decoded and the DA[2:0] and CSxx# lines are not set up. Startup latency provides the setup time for the DA[2:0] and CSxx# lines prior to assertion of the read and write strobes (DIOR# and DIOW#). Cycle latency consists of the I/O command strobe assertion length and recovery time. Recovery time is provided so that transactions may occur back-to-back on the IDE interface (without incurring startup and shutdown latency) without violating minimum cycle periods for the IDE interface. The command strobe assertion width for the enhanced timing mode is selected by the IDE_TIM Register and may be set to 2, 3, 4, or 5 PCI clocks. The recovery time is selected by the IDE_TIM Register and may be set to 1, 2, 3, or 4 PCI clocks.

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If IORDY is asserted when the initial sample point is reached, no wait-states are added to the command strobe assertion length. If IORDY is negated when the initial sample point is reached, additional wait-states are added. Since the rising edge of IORDY must be synchronized, at least two additional PCI clocks are added. Shutdown latency is incurred after outstanding scheduled IDE data port transactions (either a non-empty write post buffer or an outstanding read prefetch cycles) have completed and before other transactions can proceed. It provides hold time on the DA[2:0] and CSxx# lines with respect to the read and write strobes (DIOR# and DIOW#). Shutdown latency is two PCI clocks in duration. The IDE timings for various transaction types are shown in Table 5-40.

5.16.1.2 IORDY Masking

The IORDY signal can be ignored and assumed asserted at the first IORDY Sample Point (ISP) on a drive by drive basis via the IDETIM Register.

5.16.1.3 PIO 32-Bit ID E Data Port Accesses

A 32-bit PCI transaction run to the IDE data address (01F0h primary) results in two back to back 16-bit transactions to the IDE data port. The 32-bit data port feature is enabled for all timings, not just enhanced timing. For compatible timings, a shutdown and startup latency is incurred between the two, 16-bit halves of the IDE transaction. This guarantees that the chip selects are de-asserted for at least two PCI clocks between the two cycles.

5.16.1.4 PIO IDE Data Port Prefetching and Posting

The ICH6 can be programmed via the IDETIM registers to allow data to be posted to and prefetched from the IDE data ports. Data prefetching is initiated when a data port read occurs. The read prefetch eliminates latency to the IDE data ports and allows them to be performed back to back for the highest possible PIO data transfer rates. The first data port read of a sector is called the demand read. Subsequent data port reads from the sector are called prefetch reads. The demand read and all prefetch reads must be of the same size (16 or 32 bits); software must not mix 32-bit and 16-bit reads. Data posting is performed for writes to the IDE data ports. The transaction is completed on the PCI bus after the data is received by the ICH6. The ICH6 then runs the IDE cycle to transfer the data to the drive. If the ICH6 write buffer is non-empty and an unrelated (non-data or opposite channel) IDE transaction occurs, that transaction will be stalled until all current data in the write buffer is transferred to the drive. Only 16-bit buffer writes are supported. Table 5-40. IDE Transaction Timings (PCI Clocks) IDE Transaction Type Startup Latency IORDY Sample Point (ISP) Recovery Time (RCT) Shutdown Latency Non-Data Port Compatible 4 11 22 2 Data Port Compatible 3 6 14 2 Fast Timing Mode 2 2–5 1–4 2

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 181 Functional Description

5.16.2 Bus Master Function

The ICH6 can act as a PCI Bus master on behalf of an IDE device. One PCI Bus master channel is provided for the IDE connector. By performing the IDE data transfer as a PCI Bus master, the ICH6 off-loads the processor and improves system performance in multitasking environments. Both devices attached to the connector can be programmed for bus master transfers, but only one device can be active at a time.

5.16.2.1 Physical Regi on Descriptor Format

The physical memory region to be transferred is described by a Physical Region Descriptor (PRD). The PRDs are stored sequentially in a Descriptor Table in memory. The data transfer proceeds until all regions described by the PRDs in the table have been transferred. Descriptor Tables must not cross a 64-KB boundary. Each PRD entry in the table is 8 bytes in length. The first 4 bytes specify the byte address of a physical memory region. This memory region must be DWord-aligned and must not cross a 64-KB boundary. The next two bytes specify the size or transfer count of the region in bytes (64-KB limit per region). A value of 0 in these two bytes indicates 64-KB (thus the minimum transfer count is 1). If bit 7 (EOT) of the last byte is a 1, it indicates that this is the final PRD in the Descriptor table. Bus master operation terminates when the last descriptor has been retired. When the Bus Master IDE controller is reading data from the memory regions, bit 1 of the Base Address is masked and byte enables are asserted for all read transfers. When writing data, bit 1 of the Base Address is not masked and if set, will cause the lower Word byte enables to be de-asserted for the first DWord transfer. The write to PCI typically consists of a 32-byte cache line. If valid data ends prior to end of the cache line, the byte enables will be de-asserted for invalid data. The total sum of the byte counts in every PRD of the descriptor table must be equal to or greater than the size of the disk transfer request. If greater than the disk transfer request, the driver must terminate the bus master transaction (by setting bit 0 in the Bus Master IDE Command Register to 0) when the drive issues an interrupt to signal transfer completion. Figure 5-7. Physical Region Descriptor Table Entry EOT Reserved Byte Count [15:1] Memory Region Physical Base Address [31:1] B y t e 3B y t e 2B y t e 1B y t e 0 Memory Region Main Memory o o

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5.16.2.2 Bus Master IDE Timings

The timing modes used for Bus Master IDE transfers are identical to those for PIO transfers. The DMA Timing Enable Only bits in IDE Timing register can be used to program fast timing mode for DMA transactions only. This is useful for IDE devices whose DMA transfer timings are faster than its PIO transfer timings. The IDE device DMA request signal is sampled on the same PCI clock that DIOR# or DIOW# is de-asserted. If inactive, the DMA Acknowledge signal is de-asserted on the next PCI clock and no more transfers take place until DMA request is asserted again.

5.16.2.3 Interrupts

The ICH6 can generate interrupts based upon a signal coming from the PATA device, or due to the completion of a PRD with the ‘I’ bit set. The interrupt is edge triggered and active high. The PATA host controller generates IDEIRQ. When the ICH6 IDE controller is operating independently from the SATA controller (D31:F2), IDEIRQ will generate IRQ14. When operating in conjunction with the SATA controller (combined mode), IDE interrupts will still generate IDEIRQ, but this may in turn generate either IRQ14 or IRQ15, depending upon the value of the MAP.MV (D31:F2:90h:bits 1:0) register. When in combined mode and the SATA controller is emulating the logical secondary channel (MAP.MV = 1h), the PATA channel will emulate the logical primary channel and IDEIRQ will generate IRQ14. Conversely, if the SATA controller in combined mode is emulating the logical primary channel (MAP.MV=2h), IDEIRQ will generate IRQ15. Note: IDE interrupts cannot be communicated through PCI devices or the serial IRQ stream.

5.16.2.4 Bus Master IDE Operation

To initiate a bus master transfer between memory and an IDE device, the following steps are required: 1. Software prepares a PRD table in system me mory. The PRD table must be DWord-aligned and must not cross a 64-KB boundary. 2. Software provides the starti ng address of the PRD Table by loading the PRD Table Pointer Register. The direction of the data transfer is specified by setting the Read/Write Control bit. The interrupt bit and Error bit in the Status register are cleared. 3. Software issues the appropriate DMA transfer command to the disk device. 4. The bus master function is engaged by software writing a 1 to the Start bit in the Command Register. The first entry in the PRD table is fetched and loaded into two registers which are not visible by software, the Current Base and Current Count registers. These registers hold the current value of the address and byte count loaded from the PRD table. The value in these registers is only valid when there is an active command to an IDE device. 5. Once the PRD is loaded internally, the IDE device will receive a DMA acknowledge. 6. The controller transfers data to/from memo ry responding to DMA requests from the IDE device. The IDE device and the host controller may or may not throttle the transfer several times. When the last data transfer for a region has been completed on the IDE interface, the next descriptor is fetched from the table. The descriptor contents are loaded into the Current Base and Current Count registers. 7. At the end of the transfer, th e IDE device signals an interrupt. 8. In response to the interrupt, software resets the Start/Stop bit in the command register. It then reads the controller status followed by the drive status to determine if the transfer completed successfully.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 183 Functional Description The last PRD in a table has the End of List (EOL) bit set. The PCI bus master data transfers terminate when the physical region described by the last PRD in the table has been completely transferred. The active bit in the Status Register is reset and the DDRQ signal is masked. The buffer is flushed (when in the write state) or invalidated (when in the read state) when a terminal count condition exists; that is, the current region descriptor has the EOL bit set and that region has been exhausted. The buffer is also flushed (write state) or invalidated (read state) when the Interrupt bit in the Bus Master IDE Status register is set. Software that reads the status register and finds the Error bit reset, and either the Active bit reset or the Interrupt bit set, can be assured that all data destined for system memory has been transferred and that data is valid in system memory. Table 5-41 describes how to interpret the Interrupt and Active bits in the Status Register after a DMA transfer has started.

5.16.2.5 Error Conditions

IDE devices are sector based mass storage devices. The drivers handle errors on a sector basis; either a sector is transferred successfully or it is not. A sector is 512 bytes. If the IDE device does not complete the transfer due to a hardware or software error, the command will eventually be stopped by the driver setting Command Start bit to 0 when the driver times out the disk transaction. Information in the IDE device registers help isolate the cause of the problem. If the controller encounters an error while doing the bus master transfers it will stop the transfer (i.e., reset the Active bit in the Command register) and set the Error bit in the Bus Master IDE Status register. The controller does not generate an interrupt when this happens. The device driver can use device specific information (PCI Configuration Space Status register and IDE Drive Register) to determine what caused the error. Whenever a requested transfer does not complete properly, information in the IDE device registers (Sector Count) can be used to determine how much of the transfer was completed and to construct a new PRD table to complete the requested operation. In most cases the existing PRD table can be used to complete the operation. Table 5-41. Interrupt/Active Bit Interaction Definition Interrupt Active Description 0 1 DMA transfer is in progress. No interrupt has been generated by the IDE device. The IDE device generated an interrupt. The controller exhausted the Physical Region Descriptors. This is the normal completion case where the size of the physical memory regions was equal to the IDE device transfer size. The IDE device generated an interrupt. The controller has not reached the end of the physical memory regions. This is a valid completion case where the size of the physical memory regions was larger than the IDE device transfer size. This bit combination signals an error condition. If the Error bit in the status register is set, then the controller has some problem transferring data to/from memory. Specifics of the error have to be determined using bus-specific information. If the Error bit is not set, then the PRD's specified a smaller size than the IDE transfer size.

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5.16.3 Ultra ATA/100/66/33 Protocol

The ICH6 supports Ultra ATA/100/66/33 bus mastering protocol, providing support for a variety of transfer speeds with IDE devices. Ultra ATA/33 provides transfers up to 33 MB/s, Ultra ATA/66 provides transfers at up to 44 MB/s or 66 MB/s, and Ultra ATA/100 can achieve read transfer rates up to 100 MB/s and write transfer rates up to 88.9 MB/s. The Ultra ATA/100/66/33 definition also incorporates a Cyclic Redundancy Checking (CRC-16) error checking protocol.

5.16.3.1 Operation

Initial setup programming consists of enabling and performing the proper configuration of the ICH6 and the IDE device for Ultra ATA/100/66/33 operation. For the ICH6, this consists of enabling synchronous DMA mode and setting up appropriate Synchronous DMA timings. When ready to transfer data to or from an IDE device, the Bus Master IDE programming model is followed. Once programmed, the drive and ICH6 control the transfer of data via the Ultra ATA/ 100/66/33 protocol. The actual data transfer consists of three phases, a start-up phase, a data transfer phase, and a burst termination phase. The IDE device begins the start-up phase by asserting DMARQ signal. When ready to begin the transfer, the ICH6 asserts DMACK# signal. When DMACK# signal is asserted, the host controller drives CS0# and CS1# inactive, DA0–DA2 low. For write cycles, the ICH6 de-asserts STOP, waits for the IDE device to assert DMARDY#, and then drives the first data word and STROBE signal. For read cycles, the ICH6 tri-states the DD lines, de-asserts STOP, and asserts DMARDY#. The IDE device then sends the first data word and STROBE. The data transfer phase continues the burst transfers with the data transmitter (ICH6 – writes, IDE device – reads) providing data and toggling STROBE. Data is transferred (latched by receiver) on each rising and falling edge of STROBE. The transmitter can pause the burst by holding STROBE high or low, resuming the burst by again toggling STROBE. The receiver can pause the burst by de-asserting DMARDY# and resumes the transfers by asserting DMARDY#. The ICH6 pauses a burst transaction to prevent an internal line buffer over or under flow condition, resuming once the condition has cleared. It may also pause a transaction if the current PRD byte count has expired, resuming once it has fetched the next PRD. The current burst can be terminated by either the transmitter or receiver. A burst termination consists of a Stop Request, Stop Acknowledge and transfer of CRC data. The ICH6 can stop a burst by asserting STOP, with the IDE device acknowledging by de-asserting DMARQ. The IDE device stops a burst by de-asserting DMARQ and the ICH6 acknowledges by asserting STOP. The transmitter then drives the STROBE signal to a high level. The ICH6 then drives the CRC value onto the DD lines and de-assert DMACK#. The IDE device latches the CRC value on rising edge of DMACK#. The ICH6 terminates a burst transfer if it needs to service the opposite IDE channel, if a Programmed I/O (PIO) cycle is executed to the IDE channel currently running the burst, or upon transferring the last data from the final PRD.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 185 Functional Description

5.16.4 Ultra ATA/33/66/100 Timing

The timings for Ultra ATA/33/66/100 modes are programmed via the Synchronous DMA Timing register and the IDE Configuration register. Different timings can be programmed for each drive in the system. The Base Clock frequency for each drive is selected in the IDE Configuration register. The Cycle Time (CT) and Ready to Pause (RP) time (defined as multiples of the Base Clock) are programmed in the Synchronous DMA Timing Register. The Cycle Time represents the minimum pulse width of the data strobe (STROBE) signal. The Ready to Pause time represents the number of Base Clock periods that the ICH6 waits from de-assertion of DMARDY# to the assertion of STOP when it desires to stop a burst read transaction. Note: The internal Base Clock for Ultra ATA/100 (Mode 5) runs at 133 MHz, and the Cycle Time (CT) must be set for three Base Clocks. The ICH6 thus toggles the write strobe signal every 22.5 ns, transferring two bytes of data on each strobe edge. This means that the ICH6 performs Mode 5 write transfers at a maximum rate of 88.9 MB/s. For read transfers, the read strobe is driven by the ATA/100 device, and the ICH6 supports reads at the maximum rate of 100 MB/s.

5.16.5 ATA Swap Bay

To support PATA swap bay, the ICH6 allows the IDE output signals to be tri-stated and input buffers to be turned off. This should be done prior to the removal of the drive. The output signals can also be driven low. This can be used to remove charge built up on the signals. Configuration bits are included in the IDE I/O Configuration register, offset 54h in the IDE PCI configuration space. In a PATA swap bay operation, an IDE device is removed and a new one inserted while the IDE interface is powered down and the rest of the system is in a fully powered-on state (SO). During a PATA swap bay operation, if the operating system executes cycles to the IDE interface after it has been powered down it will cause the ICH6 to hang the system that is waiting for IORDY to be asserted from the drive. To correct this issue, the following BIOS procedures are required for performing an IDE swap: 1. Program IDE SIG_MODE (Confi guration register at offset 54h) to 10b (drive low mode). 2. Clear IORDY Sample Point Enable (bits 1 or 5 of IDE Timing reg.). This prevents the ICH6 from waiting for IORDY assertion when the operating system accesses the IDE device after the IDE drive powers down, and ensures that 0s are always be returned for read cycles that occur during swap operation. Warning: Software should not attempt to control the outputs (either tri-state or driving low), while an IDE transfer is in progress. Unpredictable results could occur, including a system lockup.

5.16.6 SMI Trapping

Device 31:Function 1: Offset C0h (see Section 11.1.26) contain control for generating SMI# on accesses to the IDE I/O spaces. These bits map to the legacy ranges (1F0–1F7h and 3F6h). Accesses to one of these ranges with the appropriate bit set causes the cycle to not be forwarded to the IDE controller, and for an SMI# to be generated. If an access to the Bus-Master IDE registers occurs while trapping is enabled for the device being accessed, then the register is updated, an SMI# is generated, and the device activity status bits (Device 31:Function 1:Offset C4h) are updated indicating that a trap occurred.

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5.17 SATA Host Controller (D31:F2)

The SATA function in the ICH6 has dual modes of operation to support different operating system conditions. In the case of Native IDE enabled operating systems, the ICH6 has separate PCI functions for serial and parallel ATA (“enhanced mode”). To support legacy operating systems, there is only one PCI function for both the serial and parallel ATA ports if functionality from both SATA and PATA devices is desired (“combined mode”). The MAP register, Section 12.1.29, provides the ability to share PCI functions. When sharing is enabled, all decode of I/O is done through the SATA registers. Device 31, Function 1 (IDE controller) is hidden by software writing to the Function Disable Register (D31, F0, offset F2h, bit 1), and its configuration registers are not used. The ICH6 SATA controller features four (desktop only) / two (mobile only) sets of interface signals (ports) that can be independently enabled or disabled (they cannot be tri-stated or driven low). Each interface is supported by an independent DMA controller. The ICH6 SATA controller interacts with an attached mass storage device through a register interface that is equivalent to that presented by a traditional IDE host adapter. The host software follows existing standards and conventions when accessing the register interface and follows standard command protocol conventions. Note: SATA interface transfer rates are independent of UDMA mode settings. SATA interface transfer rates will operate at the bus’s maximum speed, regardless of the UDMA mode reported by the SATA device or the system BIOS.

5.17.1 Theory of Operation

5.17.1.1 Standard ATA Emulation

The ICH6 contains a set of registers that shadow the contents of the legacy IDE registers. The behavior of the Command and Control Block registers, PIO, and DMA data transfers, resets, and interrupts are all emulated. Note: The ICH6 requires that software wait for BSY=0 and DRDY=1 after drive power-up before writing to the Device Control Register. Further, it is recommended that software perform the following steps for each SATA channel before unmasking the SATA controller’s IRQ: 1. Read the (Task File) Status Re gister of each attached device. 2. Read the existing Bus Mast er Status register value. 3. OR that value with 4 4. Write the resulting value back to the Bus Master Status register. The ICH6 will assert INTR when the master device completes the EDD (Execute Device Diagnostics) command regardless of the command completion status of the slave device. If the master completes EDD first, an INTR is generated and BSY will remain ‘1’ until the slave completes the command. If the slave completes EDD first, BSY will be ‘0’ when teh master completes the EDD command and asserts INTR. Software must wait for BSY to clear before completing an EDD command, as required by the ATA5 through ATA7 (T13) industry specifications.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 187 Functional Description 5.17.1.2 48-Bit LBA Operation The SATA host controller supports 48-bit LBA through the host-to-device register FIS when accesses are performed via writes to the task file. The SATA host controller will ensure that the correct data is put into the correct byte of the host-to-device FIS. There are special considerations when reading from the task file to support 48-bit LBA operation. Software may need to read all 16-bits. Since the registers are only 8-bits wide and act as a FIFO, a bit must be set in the device/control register, which is at offset 3F6h for primary and 376h for secondary (or their native counterparts). If software clears bit 7 of the control register before performing a read, the last item written will be returned from the FIFO. If software sets bit 7 of the control register before performing a read, the first item written will be returned from the FIFO.

5.17.2 SATA Swap Bay Support

Dynamic Hot-Plug (e.g., surprise removal) is not supported by the SATA host controller without special support from AHCI and the proper board hardware. However, the ICH6 does provide for basic SATA swap bay support using the PSC register configuration bits and power management flows. A device can be powered down by software and the port can then be disabled, allowing removal and insertion of a new device. Note: This SATA swap bay operation requires board hardware (implementation specific), BIOS, and operating system support.

5.17.3 Intel ® Matrix Storage Technology Configuration (ICH6R

Only) The Intel Matrix Storage Technology solution offers data striping for higher performance (RAID Level 0), alleviating disk bottlenecks by taking advantage of the independent DMA engines that each SATA port offers in the ICH6R. Intel Matrix Storage Technology also offers mirroring for data security (RAID Level 1). There is no loss of PCI resources (request/grant pair) or add-in card slot. Intel Matrix Storage Technology functionality requires the following items:

• ICH6R
• Intel® Application Accelerator RAID Option ROM must be on the platform
• Intel Application Accelerator RAID Edition drivers, most recent revision.
• Two SATA hard disk drives. Intel Matrix Storage Technology is not available in the following configurations:
• The SATA controller in compatible mode.

5.17.3.1 Intel ® Application Accelerator RAID Option ROM

The Intel Application Accelerator RAID Option ROM is a standard PnP Option ROM that is easily integrated into any System BIOS. When in place, it provides the following three primary functions:

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• Provides a text mode user interface that allows the user to manage the RAID configuration on the system in a pre-operating system environment. Its feature set is kept simple to keep size to a minimum, but allows the user to create & delete RAID volumes and select recovery options when problems occur.
• Provides boot support when using a RAID volume as a boot disk. It does this by providing Int13 services when a RAID volume needs to be accessed by DOS applications (such as NTLDR) and by exporting the RAID volumes to the System BIOS for selection in the boot order.
• At each boot up, provides the user with a status of the RAID volumes and the option to enter the user interface by pressing CTRL-I.

5.17.4 Power Management Operation

Power management of the ICH6 SATA controller and ports will cover operations of the host controller and the SATA wire.

5.17.4.1 Power State Mappings

The D0 PCI power management state for device is supported by the ICH6 SATA controller. SATA devices may also have multiple power states. From parallel ATA, three device states are supported through ACPI. They are:

• D0 – Device is working and instantly available.
• D1 – device enters when it receives a STANDBY IMMEDIATE command. Exit latency from this state is in seconds
• D3 – from the SATA device’s perspective, no different than a D1 state, in that it is entered via the STANDBY IMMEDIATE command. However, an ACPI method is also called which will reset the device and then cut its power. Each of these device states are subsets of the host controller’s D0 state. Finally, SATA defines three PHY layer power states, that have no equivalent mappings to parallel ATA. They are:
• PHY READY – PHY logic and PLL are both on and active
• Partial – PHY logic is powered, but in a reduced state. Exit latency is no longer than 10 ns
• Slumber – PHY logic is powered, but in a reduced state. Exit latency can be up to 10 ms. Since these states have much lower exit latency than the ACPI D1 and D3 states, the SATA controller defines these states as sub-states of the device D0 state.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 189 Functional Description

5.17.4.2 Power State Transitions

5.17.4.2.1 Partial and Slumber State Entry/Exit

The partial and slumber states save interface power when the interface is idle. It would be most analogous to PCI CLKRUN# (in power savings, not in mechanism), where the interface can have power saved while no commands are pending. The SATA controller defines PHY layer power management (as performed via primitives) as a driver operation from the host side, and a device proprietary mechanism on the device side. The SATA controller accepts device transition types, but does not issue any transitions as a host. All received requests from a SATA device will be ACKed. When an operation is performed to the SATA controller such that it needs to use the SATA cable, the controller must check whether the link is in the Partial or Slumber states, and if so, must issue a COM_WAKE to bring the link back online. Similarly, the SATA device must perform the same action.

5.17.4.2.2 Device D1, D3 States

These states are entered after some period of time when software has determined that no commands will be sent to this device for some time. The mechanism for putting a device in these states does not involve any work on the host controller, other then sending commands over the interface to the device. The command most likely to be used in ATA/ATAPI is the “STANDBY IMMEDIATE” command.

5.17.4.2.3 Host Controller D3

After the interface and device have been put into a low power state, the SATA host controller may be put into a low power state. This is performed via the PCI power management registers in configuration space. There are two very important aspects to note when using PCI power management.

• When the power state is D3, only accesses to configuration space are allowed. Any attempt to access the memory or I/O spaces will result in master abort.
• When the power state is D3, no interrupts may be generated, even if they are enabled. If an interrupt status bit is pending when the controller transitions to D0, an interrupt may be generated. Figure 5-8. SATA Power States Intel® ICH6 SATA Controller = D0 Device = D3 Power Resume Latency Device = D0 PHY = Ready Device = D1 PHY = Slumber PHY = Partial PHY = Off (port disabled) PHY = Slumber PHY = Off (port disabled) PHY = Slumber PHY = Off (port disabled)

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When the controller is put into D3, it is assumed that software has properly shut down the device and disabled the ports. Therefore, there is no need to sustain any values on the port wires. The interface will be treated as if no device is present on the cable, and power will be minimized. When returning from a D3 state, an internal reset will not be performed.

5.17.4.2.4 Non-AHCI Mode PME# Generation

When in non-AHCI mode (legacy mode) of operation, the SATA controller does not generate PME#. This includes attach events (since the port must be disabled), or interlock switch events (via the SATAGP pins).

5.17.4.3 SMI Trapping (APM)

Device 31:Function2:Offset C0h (see Section 12.1.40) contain control for generating SMI# on accesses to the IDE I/O spaces. These bits map to the legacy ranges (1F0–1F7h, 3F6h, 170–177h, and 376h). If the SATA controller is in legacy mode and is using these addresses, accesses to one of these ranges with the appropriate bit set causes the cycle to not be forwarded to the SATA controller, and for an SMI# to be generated. If an access to the Bus-Master IDE registers occurs while trapping is enabled for the device being accessed, then the register is updated, an SMI# is generated, and the device activity status bits (Section 12.1.41) are updated indicating that a trap occurred.

5.17.5 SATA LED

The SATALED# output is driven when the BSY bit is set in any SATA port. The SATALED# is an active-low open-collector output. When SATALED# is low, the LED should be active. When SATALED# is high, the LED should be inactive.

5.17.6 AHCI Operation

The ICH6R/ICH6-M provides hardware support for Advanced Host Controller Interface (AHCI), a new programming interface for SATA host controllers developed thru a joint industry effort. AHCI defines transactions between the ICH6R/ICH6-M SATA controller and software and enables advanced performance and usability with SATA. Platforms supporting AHCI may take advantage of performance features such as no master/slave designation for SATA devices—each device is treated as a master—and hardware assisted native command queuing. AHCI also provides usability enhancements (such as Hot-Plug). AHCI requires appropriate software support (e.g., an AHCI driver) and for some features, hardware support in the SATA device or additional platform hardware. The ICH6R/ICH6-M supports all of the mandatory features of the Serial ATA Advanced Host Controller Interface specification, rev 1.0 and many optional features, such as hardware assisted native command queuing, aggressive power management, LED indicator support, and Hot-Plug thru the use of interlock switch support (additional platform hardware and software may be required depending upon the implementation). Note: For reliable device removal notification while in AHCI operation without the use of interlock switches (surprise removal), interface power management should be disabled for the associated port. See section 7.3.1 of the AHCI Specification for more information.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 191 Functional Description

5.18 High Precision Event Timers

This function provides a set of timers that can be used by the operating system. The timers are defined such that in the future, the operating system may be able to assign specific timers to used directly by specific applications. Each timer can be configured to cause a separate interrupt. ICH6 provides three timers. The three timers are implemented as a single counter each with its own comparator and value register. This counter increases monotonically. Each individual timer can generate an interrupt when the value in its value register matches the value in the main counter. The registers associated with these timers are mapped to a memory space (much like the I/O APIC). However, it is not implemented as a standard PCI function. The BIOS reports to the operating system the location of the register space. The hardware can support an assignable decode space; however, the BIOS sets this space prior to handing it over to the operating system (See Section 6.4). It is not expected that the operating system will move the location of these timers once it is set by the BIOS.

5.18.1 Timer Accuracy

1. The timers are accurate over any 1 ms period to within 0.05% of the time specified in the timer resolution fields. 2. Within any 100 microsecond period, the timer reports a time that is up to two ticks too early or too late. Each tick is less than or equal to 100 ns, so this represents an error of less than 0.2%. 3. The timer is monotonic. It does not return the same value on two consecutive reads (unless the counter has rolled over and reached the same value). The main counter is clocked by the 14.31818 MHz clock, synchronized into the 66.666 MHz domain. This results in a non-uniform duty cycle on the synchronized clock, but does have the correct average period. The accuracy of the main counter is as accurate as the 14.3818 MHz clock.

5.18.2 Interrupt Mapping

Mapping Option #1 (Legacy Replacement Option) In this case, the Legacy Replacement Rout bit (LEG_RT_CNF) is set. This forces the mapping found in Table 5-42. Mapping Option #2 (Standard Option) In this case, the Legacy Replacement Rout bit (LEG_RT_CNF) is 0. Each timer has its own routing control. The supported interrupt values are IRQ 20, 21, 22, and 23. Table 5-42. Legacy Replacement Routing Timer 8259 Mapping APIC Mapping Comment 0I R Q 0 I R Q 2 In this case, the 8254 timer will not cause any interrupts 1I R Q 8 I R Q 8 In this case, the RTC will not cause any interrupts. 2 Per IRQ Routing Field. Per IRQ Routing Field

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5.18.3 Periodic vs. Non-Periodic Modes Non-Periodic Mode Timer 0 is configurable to 32 (default) or 64-bit mode, whereas Timers 1 and 2 only support 32-bit mode (See Section 20.1.5). All three timers support non-periodic mode. Periodic Mode HPET Specification for a description of this mode. The following usage model is expected: 1. Software clears the ENABLE_CNF bit to prevent any interrupts 2. Software Clears the main counter by writing a value of 00h to it. 3. Software sets the TIMER0_V AL_SET_CNF bit. 4. Software writes the new value in the TIMER0_COMPARATOR_V AL register 5. Software sets the ENABLE_CNF bit to enable interrupts. The Timer 0 Comparator Value register cannot be programmed reliably by a single 64-bit write in a 32-bit environment except if only the periodic rate is being changed during run-time. If the actual Timer 0 Comparator Value needs to be reinitialized, then the following software solution will always work regardless of the environment: 1. Set TIMER0_V AL_SET_CNF bit 2. Set the lower 32 bits of the Timer0 Comparator Value register 3. Set TIMER0_V AL_SET_CNF bit 4. 4) Set the upper 32 bits of the Timer0 Comparator Value register

5.18.4 Enabling the Timers

The BIOS or operating system PnP code should route the interrupts. This includes the Legacy Rout bit, Interrupt Rout bit (for each timer), interrupt type (to select the edge or level type for each timer) The Device Driver code should do the following for an available timer: 1. Set the Overall Enable bit (Offset 04h, bit 0). 2. Set the timer type field (selects one-shot or periodic). 3. Set the interrupt enable 4. Set the comparator value

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5.18.5 Interrupt Levels

Interrupts directed to the internal 8259s are active high. See Section 5.10 for information regarding the polarity programming of the I/O APIC for detecting internal interrupts. If the interrupts are mapped to the I/O APIC and set for level-triggered mode, they can be shared with PCI interrupts. This may be shared although it’s unlikely for the operating system to attempt to do this. If more than one timer is configured to share the same IRQ (using the TIMERn_INT_ROUT_CNF fields), then the software must configure the timers to level-triggered mode. Edge-triggered interrupts cannot be shared.

5.18.6 Handling Interrupts

If each timer has a unique interrupt and the timer has been configured for edge-triggered mode, then there are no specific steps required. No read is required to process the interrupt. If a timer has been configured to level-triggered mode, then its interrupt must be cleared by the software. This is done by reading the interrupt status register and writing a 1 back to the bit position for the interrupt to be cleared. Independent of the mode, software can read the value in the main counter to see how time has passed between when the interrupt was generated and when it was first serviced. If Timer 0 is set up to generate a periodic interrupt, the software can check to see how much time remains until the next interrupt by checking the timer value register.

5.18.7 Issues Related to 64-Bit Timers with 32-Bit Processors

A 32-bit timer can be read directly using processors that are capable of 32-bit or 64-bit instructions. However, a 32-bit processor may not be able to directly read 64-bit timer. A race condition comes up if a 32-bit processor reads the 64-bit register using two separate 32-bit reads. The danger is that just after reading one half, the other half rolls over and changes the first half. If a 32-bit processor needs to access a 64-bit timer, it must first halt the timer before reading both the upper and lower 32-bits of the timer. If a 32-bit processor does not want to halt the timer, it can use the 64-bit timer as a 32-bit timer by setting the TIMERn_32MODE_CNF bit. This causes the timer to behave as a 32-bit timer. The upper 32-bits are always 0.

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5.19 USB UHCI Host Controlle rs (D29:F0, F1, F2, and F3)

The ICH6 contains four USB 2.0 full/low-speed host controllers that support the standard Universal Host Controller Interface (UHCI), Revision 1.1. Each UHCI Host Controller (UHC) includes a root hub with two separate USB ports each, for a total of eight USB ports.

• Overcurrent detection on all eight USB ports is supported. The overcurrent inputs are not 5 V tolerant, and can be used as GPIs if not needed.
• The ICH6’s UHCI host controllers are arbitrated differently than standard PCI devices to improve arbitration latency.
• The UHCI controllers use the Analog Front End (AFE) embedded cell that allows support for USB full-speed signaling rates, instead of USB I/O buffers.

5.19.1 Data Structures in Main Memory

Section 3.1 - 3.3 of the Universal Host Controller Interface, Revision 1.1 specification details the data structures used to communicate control, status, and data between software and the ICH6.

5.19.2 Data Transfers to/from Main Memory

Section 3.4 of the Universal Host Controller Interface, Revision 1.1 specification describes the details on how HCD and the ICH6 communicate via the Schedule data structures.

5.19.3 Data Encoding and Bit Stuffing

The ICH6 USB employs NRZI data encoding (Non-Return to Zero Inverted) when transmitting packets. Full details on this implementation are given in the Universal Serial Bus Revision 2.0 Specification.

5.19.4 Bus Protocol

5.19.4.1 Bit Ordering

Bits are sent out onto the bus least significant bit (LSb) first, followed by next LSb, through to the most significant bit (MSb) last.

5.19.4.2 SYNC Field

All packets begin with a synchronization (SYNC) field, which is a coded sequence that generates a maximum edge transition density. The SYNC field appears on the bus as IDLE followed by the binary string “KJKJKJKK,” in its NRZI encoding. It is used by the input circuitry to align incoming data with the local clock and is defined to be 8 bits in length. SYNC serves only as a synchronization mechanism and is not shown in the following packet diagrams. The last two bits in the SYNC field are a marker that is used to identify the first bit of the PID. All subsequent bits in the packet must be indexed from this point.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 195 Functional Description

5.19.4.3 Packet Field Formats

All packets have distinct start and end of packet delimiters. Full details are given in the Universal Serial Bus Revision 2.0 Specification in section 8.3.1.

5.19.4.4 Address Fields

Function endpoints are addressed using the function address field and the endpoint field. Full details on this are given in the Universal Serial Bus Revision 2.0 Specification in section 8.3.2.

5.19.4.5 Frame Number Field

The frame number field is an 11-bit field that is incremented by the host on a per frame basis. The frame number field rolls over upon reaching its maximum value of 7FFh, and is sent only for SOF tokens at the start of each frame.

5.19.4.6 Data Field

The data field may range from 0 to 1023 bytes and must be an integral numbers of bytes. Data bits within each byte are shifted out LSB first.

5.19.4.7 Cyclic Redundancy Check (CRC)

CRC is used to protect the all non-PID fields in token and data packets. In this context, these fields are considered to be protected fields. Full details on this are given in the Universal Serial Bus Revision 2.0 Specification in section 8.3.5.

5.19.5 Packet Formats

The USB protocol calls out several packet types: token, data, and handshake packets. Full details on this are given in the Universal Serial Bus Revision 2.0 Specification in section 8.4.

5.19.6 USB Interrupts

There are two general groups of USB interrupt sources, those resulting from execution of transactions in the schedule, and those resulting from an ICH6 operation error. All transaction-based sources can be masked by software through the ICH6’s Interrupt Enable register. Additionally, individual transfer descriptors can be marked to generate an interrupt on completion. When the ICH6 drives an interrupt for USB, it internally drives the PIRQA# pin for USB function #0 and USB function #3, PIRQD# pin for USB function #1, and the PIRQC# pin for USB function #2, until all sources of the interrupt are cleared. In order to accommodate some operating systems, the Interrupt Pin register must contain a different value for each function of this new multi-function device.

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5.19.6.1 Transaction-Based Interrupts

These interrupts are not signaled until after the status for the last complete transaction in the frame has been written back to host memory. This guarantees that software can safely process through (Frame List Current Index -1) when it is servicing an interrupt. CRC Error / Time-Out A CRC/Time-Out error occurs when a packet transmitted from the ICH6 to a USB device or a packet transmitted from a USB device to the ICH6 generates a CRC error. The ICH6 is informed of this event by a time-out from the USB device or by the ICH6’s CRC checker generating an error on reception of the packet. Additionally, a USB bus time-out occurs when USB devices do not respond to a transaction phase within 19-bit times of an EOP. Either of these conditions causes the C_ERR field of the TD to decrement. When the C_ERR field decrements to 0, the following occurs:

• The Active bit in the TD is cleared
• The Stalled bit in the TD is set
• The CRC/Time-out bit in the TD is set.
• At the end of the frame, the USB Error Interrupt bit is set in the HC status register. If the CRC/Time out interrupt is enabled in the Interrupt Enable register, a hardware interrupt will be signaled to the system. Interrupt on Completion Transfer Descriptors contain a bit that can be set to cause an interrupt on their completion. The completion of the transaction associated with that block causes the USB Interrupt bit in the HC Status Register to be set at the end of the frame in which the transfer completed. When a TD is encountered with the IOC bit set to 1, the IOC bit in the HC Status register is set to 1 at the end of the frame if the active bit in the TD is set to 0 (even if it was set to 0 when initially read). If the IOC Enable bit of Interrupt Enable register (bit 2 of I/O offset 04h) is set, a hardware interrupt is signaled to the system. The USB Interrupt bit in the HC status register is set either when the TD completes successfully or because of errors. If the completion is because of errors, the USB Error bit in the HC status register is also set. Short Packet Detect A transfer set is a collection of data which requires more than one USB transaction to completely move the data across the USB. An example might be a large print file which requires numerous TDs in multiple frames to completely transfer the data. Reception of a data packet that is less than the endpoint’s Max Packet size during Control, Bulk or Interrupt transfers signals the completion of the transfer set, even if there are active TDs remaining for this transfer set. Setting the SPD bit in a TD indicates to the HC to set the USB Interrupt bit in the HC status register at the end of the frame in which this event occurs. This feature streamlines the processing of input on these transfer types. If the Short Packet Interrupt Enable bit in the Interrupt Enable register is set, a hardware interrupt is signaled to the system at the end of the frame where the event occurred.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 197 Functional Description Serial Bus Babble When a device transmits on the USB for a time greater than its assigned Max Length, it is said to be babbling. Since isochrony can be destroyed by a babbling device, this error results in the Active bit in the TD being cleared to 0 and the Stalled and Babble bits being set to 1. The C_ERR field is not decremented for a babble. The USB Error Interrupt bit in the HC Status register is set to 1 at the end of the frame. A hardware interrupt is signaled to the system. If an EOF babble was caused by the ICH6 (due to incorrect schedule for instance), the ICH6 forces a bit stuff error followed by an EOP and the start of the next frame. Stalled This event indicates that a device/endpoint returned a STALL handshake during a transaction or that the transaction ended in an error condition. The TDs Stalled bit is set and the Active bit is cleared. Reception of a STALL does not decrement the error counter. A hardware interrupt is signaled to the system. Data Buffer Error This event indicates that an overrun of incoming data or a under-run of outgoing data has occurred for this transaction. This would generally be caused by the ICH6 not being able to access required data buffers in memory within necessary latency requirements. Either of these conditions causes the C_ERR field of the TD to be decremented. When C_ERR decrements to 0, the Active bit in the TD is cleared, the Stalled bit is set, the USB Error Interrupt bit in the HC Status register is set to 1 at the end of the frame and a hardware interrupt is signaled to the system. Bit Stuff Error A bit stuff error results from the detection of a sequence of more that six 1s in a row within the incoming data stream. This causes the C_ERR field of the TD to be decremented. When the C_ERR field decrements to 0, the Active bit in the TD is cleared to 0, the Stalled bit is set to 1, the USB Error Interrupt bit in the HC Status register is set to 1 at the end of the frame and a hardware interrupt is signaled to the system.

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5.19.6.2 Non-Transaction Based Interrupts

If an ICH6 process error or system error occur, the ICH6 halts and immediately issues a hardware interrupt to the system. Resume Received This event indicates that the ICH6 received a RESUME signal from a device on the USB bus during a global suspend. If this interrupt is enabled in the Interrupt Enable register, a hardware interrupt is signaled to the system allowing the USB to be brought out of the suspend state and returned to normal operation. ICH6 Process Error The HC monitors certain critical fields during operation to ensure that it does not process corrupted data structures. These include checking for a valid PID and verifying that the MaxLength field is less than 1280. If it detects a condition that would indicate that it is processing corrupted data structures, it immediately halts processing, sets the HC Process Error bit in the HC Status register and signals a hardware interrupt to the system. This interrupt cannot be disabled through the Interrupt Enable register. Host System Error The ICH6 sets this bit to 1 when a Parity error, Master Abort, or Target Abort occur. When this error occurs, the ICH6 clears the Run/Stop bit in the Command register to prevent further execution of the scheduled TDs. This interrupt cannot be disabled through the Interrupt Enable register.

5.19.7 USB Power Management

The Host controller can be put into a suspended state and its power can be removed. This requires that certain bits of information are retained in the resume power plane of the ICH6 so that a device on a port may wake the system. Such a device may be a fax-modem, which will wake up the machine to receive a fax or take a voice message. The settings of the following bits in I/O space will be maintained when the ICH6 enters the S3, S4, or S5 states. When the ICH6 detects a resume event on any of its ports, it sets the corresponding USB_STS bit in ACPI space. If USB is enabled as a wake/break event, the system wakes up and an SCI generated. Table 5-43. Bits Maintained in Low Power States Register Offset Bit Description Command 00h 3 Enter Global Suspend Mode (EGSM) Status 02h 2 Resume Detect Port Status and Control 10h & 12h

2 Port Enabled/Disabled

6 Resume Detect

8 Low-speed Device Attached

12 Suspend

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 199 Functional Description

5.19.8 USB Legacy Keyboard Operation

When a USB keyboard is plugged into the system, and a standard keyboard is not, the system may not boot, and MS-DOS legacy software will not run, because the keyboard will not be identified. The ICH6 implements a series of trapping operations which will snoop accesses that go to the keyboard controller, and put the expected data from the USB keyboard into the keyboard controller. Note: The scheme described below assumes that the keyboard controller (8042 or equivalent) is on the LPC bus. This legacy operation is performed through SMM space. Figure 5-9 shows the Enable and Status path. The latched SMI source (60R, 60W, 64R, 64W) is available in the Status Register. Because the enable is after the latch, it is possible to check for other events that didn't necessarily cause an SMI. It is the software's responsibility to logically AND the value with the appropriate enable bits. Note also that the SMI is generated before the PCI cycle completes (e.g., before TRDY# goes active) to ensure that the processor doesn't complete the cycle before the SMI is observed. This method is used on MPIIX and has been validated. The logic also needs to block the accesses to the 8042. If there is an external 8042, then this is simply accomplished by not activating the 8042 CS. This is simply done by logically ANDing the four enables (60R, 60W, 64R, 64W) with the 4 types of accesses to determine if 8042CS should go active. An additional term is required for the “pass-through” case. The state table for Figure 5-9 is shown in Table 5-44. Figure 5-9. USB Legacy Keyboard Flow Diagram KBC Accesses PCI Config Read, Write

60 READ

Clear SMI_60_R EN_SMI_ON_60R Comb. Decoder AND Same for 60W, 64R, 64W SMI OR To Individual "Caused By" "Bits" To PIRQD# To "Caused By" Bit AND AND EN_PIRQD# USB_IRQ Clear USB_IRQ EN_SMI_ON_IRQ S D R S D R

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Table 5-44. USB Legacy Keyboard State Transitions Current State Action Data Value Next State Comment IDLE 64h / Write D1h GateState1 Standard D1 command. Cycle passed through to 8042. SMI# doesn't go active. PSTATE (offset C0, bit 6) goes to 1. IDLE 64h / Write Not D1h IDLE Bit 3 in Configuration Register determines if cycle passed through to 8042 and if SMI# generated. IDLE 64h / Read N/A IDLE Bit 2 in Configuration Register determines if cycle passed through to 8042 and if SMI# generated. IDLE 60h / Write Don't Care IDLE Bit 1 in Configuration Register determines if cycle passed through to 8042 and if SMI# generated. IDLE 60h / Read N/A IDLE Bit 0 in Configuration Register determines if cycle passed through to 8042 and if SMI# generated. GateState1 60h / Write XXh GateState2 Cycle passed through to 8042, even if trap enabled in Bit 1 in Configuration Register. No SMI# generated. PSTATE remains 1. If data value is not DFh or DDh then the 8042 may chose to ignore it. GateState1 64h / Write D1h GateState1 Cycle passed through to 8042, even if trap enabled via Bit 3 in Configuration Register. No SMI# generated. PSTATE remains 1. Stay in GateState1 because this is part of the double-trigger sequence. GateState1 64h / Write Not D1h ILDE Bit 3 in Configuration space determines if cycle passed through to 8042 and if SMI# generated. PSTATE goes to 0. If Bit 7 in Configuration Register is set, then SMI# should be generated. GateState1 60h / Read N/A IDLE This is an invalid sequence. Bit 0 in Configuration Register determines if cycle passed through to 8042 and if SMI# generated. PSTATE goes to 0. If Bit 7 in Configuration Register is set, then SMI# should be generated. GateState1 64h / Read N/A GateState1 Just stay in same state. Generate an SMI# if enabled in Bit 2 of Configuration Register. PSTATE remains 1. GateState2 64 / Write FFh IDLE Standard end of sequence. Cycle passed through to 8042. PSTATE goes to 0. Bit 7 in Configuration Space determines if SMI# should be generated. GateState2 64h / Write Not FFh IDLE Improper end of sequence. Bit 3 in Configuration Register determines if cycle passed through to 8042 and if SMI# generated. PSTATE goes to 0. If Bit 7 in Configuration Register is set, then SMI# should be generated. GateState2 64h / Read N/A GateState2 Just stay in same state. Generate an SMI# if enabled in Bit 2 of Configuration Register. PSTATE remains 1. GateState2 60h / Write XXh IDLE Improper end of sequence. Bit 1 in Configuration Register determines if cycle passed through to 8042 and if SMI# generated. PSTATE goes to 0. If Bit 7 in Configuration Register is set, then SMI# should be generated. GateState2 60h / Read N/A IDLE Improper end of sequence. Bit 0 in Configuration Register determines if cycle passed through to 8042 and if SMI# generated. PSTATE goes to 0. If Bit 7 in Configuration Register is set, then SMI# should be generated.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 201 Functional Description

5.20 USB EHCI Host Controller (D29:F7)

The ICH6 contains an Enhanced Host Controller Interface (EHCI) compliant host controller which supports up to eight USB 2.0 high-speed compliant root ports. USB 2.0 allows data transfers up to 480 Mb/s using the same pins as the eight USB full-speed/low-speed ports. The ICH6 contains port-routing logic that determines whether a USB port is controlled by one of the UHCI controllers or by the EHCI controller. USB 2.0 based Debug Port is also implemented in the ICH6. A summary of the key architectural differences between the USB UHCI host controllers and the EHCI host controller are shown in Table 5-45.

5.20.1 EHC Initialization

The following descriptions step through the expected ICH6 Enhanced Host Controller (EHC) initialization sequence in chronological order, beginning with a complete power cycle in which the suspend well and core well have been off.

5.20.1.1 BIOS Initialization

BIOS performs a number of platform customization steps after the core well has powered up. Contact your Intel Field Representative for additional ICH6 BIOS information.

5.20.1.2 Driver Initialization

See Chapter 4 of the Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0. Table 5-45. UHCI vs. EHCI Parameter USB UHCI USB EHCI Accessible by I/O space Memory Space Memory Data Structure Single linked list Se parated in to Periodic and Asynchronous lists Differential Signaling Voltage 3.3 V 400 mV Ports per Controller 2 8

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5.20.1.3 EHC Resets

In addition to the standard ICH6 hardware resets, portions of the EHC are reset by the HCRESET bit and the transition from the D3HOT device power management state to the D0 state. The effects of each of these resets are shown in the following table: If the detailed register descriptions give exceptions to these rules, those exceptions override these rules. This summary is provided to help explain the reasons for the reset policies.

5.20.2 Data Structures in Main Memory

See Section 3 and Appendix B of the Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0 for details. 5.20.3 USB 2.0 Enhanced Host Controller DMA The ICH6 USB 2.0 EHC implements three sources of USB packets. They are, in order of priority on USB during each microframe: 1. The USB 2.0 Debug Port (see Section USB 2.0 Based Debug Port), 2. The Periodic DMA engine, and 3. The Asynchronous DMA engine. The ICH6 always performs any currently-pending debug port transaction at the beginning of a microframe, followed by any pending periodic traffic for the current microframe. If there is time left in the microframe, then the EHC performs any pending asynchronous traffic until the end of the microframe (EOF1). Note that the debug port traffic is only presented on one port (Port #0), while the other ports are idle during this time.

5.20.4 Data Encoding and Bit Stuffing

See Chapter 8 of the Universal Serial Bus Specification, Revision 2.0.

5.20.5 Packet Formats

See Chapter 8 of the Universal Serial Bus Specification, Revision 2.0. Reset Does Reset Does not Reset Comments HCRESET bit set. Memory space registers except Structural Parameters (which is written by BIOS). Configuration registers. The HCRESET must only affect registers that the EHCI driver controls. PCI Configuration space and BIOS-programmed parameters can not be reset. Software writes the Device Power State from D3 HOT (11b) to D0 (00b). Core well registers (except BIOS- programmed registers). Suspend well registers; BIOS- programmed core well registers. The D3-to-D0 transition must not cause wake information (suspend well) to be lost. It also must not clear BIOS-programmed registers because BIOS may not be invoked following the D3-to-D0 transition.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 203 Functional Description The ICH6 EHCI allows entrance to USB test modes, as defined in the USB 2.0 specification, including Test J, Test Packet, etc. However note that the ICH6 Test Packet test mode interpacket gap timing may not meet the USB2.0 specification. 5.20.6 USB 2.0 Interrupt s and Error Conditions Section 4 of the Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0 goes into detail on the EHC interrupts and the error conditions that cause them. All error conditions that the EHC detects can be reported through the EHCI Interrupt status bits. Only ICH6-specific interrupt and error-reporting behavior is documented in this section. The EHCI Interrupts Section must be read first, followed by this section of the datasheet to fully comprehend the EHC interrupt and error-reporting functionality.

• Based on the EHC’s Buffer sizes and buffer management policies, the Data Buffer Error can never occur on the ICH6.
• Master Abort and Target Abort responses from hub interface on EHC-initiated read packets will be treated as Fatal Host Errors. The EHC halts when these conditions are encountered.
• The ICH6 may assert the interrupts which are based on the interrupt threshold as soon as the status for the last complete transaction in the interrupt interval has been posted in the internal write buffers. The requirement in the Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0 (that the status is written to memory) is met internally, even though the write may not be seen on DMI before the interrupt is asserted.
• Since the ICH6 supports the 1024-element Frame List size, the Frame List Rollover interrupt occurs every 1024 milliseconds.
• The ICH6 delivers interrupts using PIRQH#.
• The ICH6 does not modify the CERR count on an Interrupt IN when the “Do Complete-Split” execution criteria are not met.
• For complete-split transactions in the Periodic list, the “Missed Microframe” bit does not get set on a control-structure-fetch that fails the late-start test. If subsequent accesses to that control structure do not fail the late-start test, then the “Missed Microframe” bit will get set and written back. 5.20.6.1 Aborts on USB 2.0- Initiated Memory Reads If a read initiated by the EHC is aborted, the EHC treats it as a fatal host error. The following actions are taken when this occurs:
• The Host System Error status bit is set
• The DMA engines are halted after completing up to one more transaction on the USB interface
• If enabled (by the Host System Error Enable), then an interrupt is generated
• If the status is Master Abort, then the Received Master Abort bit in configuration space is set
• If the status is Target Abort, then the Received Target Abort bit in configuration space is set
• If enabled (by the SERR Enable bit in the function’s configuration space), then the Signaled System Error bit in configuration bit is set.

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5.20.7 USB 2.0 Power Management

5.20.7.1 Pause Feature

This feature allows platforms (especially mobile systems) to dynamically enter low-power states during brief periods when the system is idle (i.e., between keystrokes). This is useful for enabling power management features like Intel SpeedStep technology in the ICH6. The policies for entering these states typically are based on the recent history of system bus activity to incrementally enter deeper power management states. Normally, when the EHC is enabled, it regularly accesses main memory while traversing the DMA schedules looking for work to do; this activity is viewed by the power management software as a non-idle system, thus preventing the power managed states to be entered. Suspending all of the enabled ports can prevent the memory accesses from occurring, but there is an inherent latency overhead with entering and exiting the suspended state on the USB ports that makes this unacceptable for the purpose of dynamic power management. As a result, the EHCI software drivers are allowed to pause the EHC’s DMA engines when it knows that the traffic patterns of the attached devices can afford the delay. The pause only prevents the EHC from generating memory accesses; the SOF packets continue to be generated on the USB ports (unlike the suspended state).

5.20.7.2 Suspend Feature

The Enhanced Host Controller Interface (EHCI) For Universal Serial Bus Specification, Section 4.3 describes the details of Port Suspend and Resume.

5.20.7.3 ACPI Device States

The USB 2.0 function only supports the D0 and D3 PCI Power Management states. Notes regarding the ICH6 implementation of the Device States: 1. The EHC hardware does not inherently consume any more power when it is in the D0 state than it does in the D3 state. However, software is required to suspend or disable all ports prior to entering the D3 state such that the maximum power consumption is reduced. 2. In the D0 state, all implem ented EHC features are enabled. 3. In the D3 state, accesses to the EHC memory-map ped I/O range will master abort. Note that, since the Debug Port uses the same memory range, the Debug Port is only operational when the EHC is in the D0 state. 4. In the D3 state, the EHC interrupt must never assert for any reason. The internal PME# signal is used to signal wake events, etc. 5. When the Device Power State field is written to D0 from D3, an internal reset is generated. See section EHC Resets for general rules on the effects of this reset. 6. Attempts to write any other value into the Device Power State field other than 00b (D0 state) and 11b (D3 state) will complete normally without changing the current value in this field.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 205 Functional Description

5.20.7.4 ACPI System States

The EHC behavior as it relates to other power management states in the system is summarized in the following list: — The System is always in the S0 state when th e EHC is in the D0 state. However, when the EHC is in the D3 state, the system may be in any power management state (including S0). — When in D0, the Pause feature (See Section 5.20.7.1) enables dynamic processor low- power states to be entered. — The PLL in the EHC is di sabled when entering the S3HOT state (48 MHz clock stops), or the S3COLD/S4/S5 states (core power turns off). — All core well logic is reset in the S3/S4/S5 states.

5.20.7.5 Mobile Considerations

The ICH6 USB 2.0 implementation does not behave differently in the mobile configurations versus the desktop configurations. However, some features may be especially useful for the mobile configurations.

• If a system (e.g., mobile) does not implement all eight USB 2.0 ports, the ICH6 provides mechanisms for changing the structural parameters of the EHC and hiding unused UHCI controllers. See ICH6 BIOS Specification on how BIOS should configure the ICH6.
• Mobile systems may want to minimize the conditions that will wake the system. The ICH6 implements the “Wake Enable” bits in the Port Status and Control registers, as specified in the EHCI spec, for this purpose.
• Mobile systems may want to cut suspend well power to some or all USB ports when in a low-power state. The ICH6 implements the optional Port Wake Capability Register in the EHC Configuration Space for this platform-specific information to be communicated to software.

5.20.8 Interaction with UHCI Host Controllers

The Enhanced Host controller shares the eight USB ports with four UHCI Host controllers in the ICH6. The UHC at D29:F0 shares ports 0 and 1; the UHC at D29:F1 shares ports 2 and 3; the UHC at D29:F2 shares ports 4 and 5; and the UHC at D29:F3 shares ports 6 and 7 with the EHC. There is very little interaction between the Enhanced and the UHCI controllers other than the multiplexing control which is provided as part of the EHC. Figure 5-10 shows the USB Port Connections at a conceptual level.

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5.20.8.1 Port-Routing Logic

Integrated into the EHC functionality is port-routing logic, that performs the multiplexing between the UHCI and EHCI host controllers. The ICH6 conceptually implements this logic as described in Section 4.2 of the Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0. If a device is connected that is not capable of USB 2.0’s high-speed signaling protocol or if the EHCI software drivers are not present as indicated by the Configured Flag, then the UHCI controller owns the port. Owning the port means that the differential output is driven by the owner and the input stream is only visible to the owner. The host controller that is not the owner of the port internally sees a disconnected port. Note that the port-routing logic is the only block of logic within the ICH6 that observes the physical (real) connect/disconnect information. The port status logic inside each of the host controllers observes the electrical connect/disconnect information that is generated by the port-routing logic. Only the differential signal pairs are multiplexed/demultiplexed between the UHCI and EHCI host controllers. The other USB functional signals are handled as follows:

• The Overcurrent inputs (OC[7:0]#) are directly routed to both controllers. An overcurrent event is recorded in both controllers’ status registers. The Port-Routing logic is implemented in the Suspend power well so that re-enumeration and re-mapping of the USB ports is not required following entering and exiting a system sleep state in which the core power is turned off. The ICH6 also allows the USB Debug Port traffic to be routed in and out of Port #0. When in this mode, the Enhanced Host controller is the owner of Port #0. Figure 5-10. Intel® ICH6-USB Port Connections UHCI #3 (D29:F3) UCHI #0 (D29:F0) UHCI #1 (D29:F1) UHCI #2 (D29:F2) Enhanced Host Controller LogicDebug Port Port 7 Port 3 Port 4 Port 5 Port 6 Port 2 Port 1 Port 0

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5.20.8.2 Device Connects

The Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0 describes the details of handling Device Connects in Section 4.2. There are four general scenarios that are summarized below. 1. Configure Flag = 0 and a full-speed /low-speed-only Device is connected — In this case, the UHC is the owner of the po rt both before and after the connect occurs. The EHC (except for the port-routing logic) never sees the connect occur. The UHCI driver handles the connection and initialization process. 2. Configure Flag = 0 and a high-s peed-capable Device is connected — In this case, the UHC is the owner of the po rt both before and after the connect occurs. The EHC (except for the port-routing logic) never sees the connect occur. The UHCI driver handles the connection and initialization process. Since the UHC does not perform the high-speed chirp handshake, the device operates in compatible mode. 3. Configure Flag = 1 and a full-speed /low-speed-only Device is connected — In this case, the EHC is the ow ner of the port before the connect occurs. The EHCI driver handles the connection and performs the port reset. After the reset process completes, the EHC hardware has cleared (not set) the Port Enable bit in the EHC’s PORTSC register. The EHCI driver then writes a 1 to the Port Owner bit in the same register, causing the UHC to see a connect event and the EHC to see an “electrical” disconnect event. The UHCI driver and hardware handle the connection and initialization process from that point on. The EHCI driver and hardware handle the perceived disconnect. 4. Configure Flag = 1 and a high-s peed-capable Device is connected — In this case, the EHC is the owner of the port before, and remains the owner after, the connect occurs. The EHCI driver handles the connection and performs the port reset. After the reset process completes, the EHC hardware has set the Port Enable bit in the EHC’s PORTSC register. The port is functional at this point. The UHC continues to see an unconnected port.

5.20.8.3 Device Disconnects

The Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0 describes the details of handling Device Connects in Section 4.2. There are three general scenarios that are summarized below. 1. Configure Flag = 0 and the device is disconnected — In this case, the UHC is the owner of the po rt both before and after the disconnect occurs. The EHC (except for the port-routing logic) never sees a device attached. The UHCI driver handles disconnection process. 2. Configure Flag = 1 and a full-speed/low -speed-capable Device is disconnected — In this case, the UHC is the owner of th e port before the disconnect occurs. The disconnect is reported by the UHC and serviced by the associated UHCI driver. The port-routing logic in the EHC cluster forces the Port Owner bit to 0, indicating that the EHC owns the unconnected port. 3. Configure Flag = 1 and a high-spe ed-capable Device is disconnected — In this case, the EHC is the owner of the port before, and remains the owner after, the disconnect occurs. The EHCI hardware and driver handle the disconnection process. The UHC never sees a device attached.

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5.20.8.4 Effect of Reset s on Port-Routing Logic

As mentioned above, the Port Routing logic is implemented in the suspend power well so that remuneration and re-mapping of the USB ports is not required following entering and exiting a system sleep state in which the core power is turned off. 5.20.9 USB 2.0 Legacy Keyboard Operation The ICH6 must support the possibility of a keyboard downstream from either a full-speed/low- speed or a high-speed port. The description of the legacy keyboard support is unchanged from USB 1.1 (See Section 5.19.8). The EHC provides the basic ability to generate SMIs on an interrupt event, along with more sophisticated control of the generation of SMIs. 5.20.10 USB 2.0 Based Debug Port The ICH6 supports the elimination of the legacy COM ports by providing the ability for new debugger software to interact with devices on a USB 2.0 port. High-level restrictions and features are:

• Operational before USB 2.0 drivers are loaded.
• Functions even when the port is disabled.
• Works even though non-configured port is default-routed to the UHCI. Note that the Debug Port can not be used to debug an issue that requires a full-speed/low-speed device on Port #0 using the UHCI drivers.
• Allows normal system USB 2.0 traffic in a system that may only have one USB port.
• Debug Port device (DPD) must be high-speed capable and connect directly to Port #0 on ICH6 systems (e.g., the DPD cannot be connected to Port #0 thru a hub).
• Debug Port FIFO always makes forward progress (a bad status on USB is simply presented back to software).
• The Debug Port FIFO is only given one USB access per microframe. Reset Event Effect on Configure Flag Effect on Port Owner Bits Suspend Well Reset cleared (0) set (1) Core Well Reset no effect no effect D3-to-D0 Reset no effect no effect HCRESET cleared (0) set (1)

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 209 Functional Description The Debug port facilitates operating system and device driver debug. It allows the software to communicate with an external console using a USB 2.0 connection. Because the interface to this link does not go through the normal USB 2.0 stack, it allows communication with the external console during cases where the operating system is not loaded, the USB 2.0 software is broken, or where the USB 2.0 software is being debugged. Specific features of this implementation of a debug port are:

• Only works with an external USB 2.0 debug device (console)
• Implemented for a specific port on the host controller
• Operational anytime the port is not suspended AND the host controller is in D0 power state.
• Capability is interrupted when port is driving USB RESET

5.20.10.1 Theory of Operation

There are two operational modes for the USB debug port: 1. Mode 1 is when the USB port is in a disabled state from the viewpoint of a standard host controller driver. In Mode 1, the Debug Port controller is required to generate a “keepalive” packets less than 2 ms apart to keep the attached debug device from suspending. The keepalive packet should be a standalone 32-bit SYNC field. 2. Mode 2 is when the host controller is running (i.e., host controller’s Run/Stop# bit is 1). In Mode 2, the normal transmission of SOF packets will keep the debug device from suspending. Behavioral Rules 1. In both modes 1 and 2, the Debug Port controller must check for software requested debug transactions at least every 125 microseconds. 2. If the debug port is enabled by the debug driver, and the standard host controller driver resets the USB port, USB debug transactions are held off for the duration of the reset and until after the first SOF is sent. 3. If the standard host controller driver suspe nds the USB port, then USB debug transactions are held off for the duration of the suspend/resume sequence and until after the first SOF is sent. 4. The ENABLED_CNT bit in the debug register space is independent of the similar port control bit in the associated Port Status and Control register.

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Table 5-46 shows the debug port behavior related to the state of bits in the debug registers as well as bits in the associated Port Status and Control register.

5.20.10.1.1 OUT Transactions

An Out transaction sends data to the debug device. It can occur only when the following are true:

• The debug port is enabled
• The debug software sets the GO_CNT bit
• The WRITE_READ#_CNT bit is set The sequence of the transaction is: 1. Software sets the appropriate values in the following bits: — USB_ADDRESS_CNF — USB_ENDPOINT_CNF — DATA_BUFFER[63:0] — TOKEN_PID_CNT[7:0] — SEND_PID_CNT[15:8] — DATA_LEN_CNT — WRITE_READ#_CNT (note: this will always be 1 for OUT transactions) — GO_CNT (note: this will always be 1 to initiate the transaction) Table 5-46. Debug Port Behavior OWNER_CNT ENABLED_CT Port Enable Run / Stop Suspend Debug Port Behavior 0X X X X Debug port is not being used. Normal operation. 10 X X X Debug port is not being used. Normal operation. 11 0 0 X Debug port in Mode 1. SYNC keepalives sent plus debug traffic 11 0 1 X Debug port in Mode 2. SOF (and only SOF) is sent as keepalive. Debug traffic is also sent. Note that no other normal traffic is sent out this port, because the port is not enabled. 11 1 0 0 Illegal. Host controller driver should never put controller into this state (enabled, not running and not suspended). 11 1 0 1 Port is suspended. No debug traffic sent. 11 1 1 0 Debug port in Mode 2. Debug traffic is interspersed with normal traffic. 11 1 1 1 Port is suspended. No debug traffic sent.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 211 Functional Description 2. The debug port controller sends a token packet consisting of: —S Y N C — TOKEN_PID_CNT field — USB_ADDRESS_CNT field — USB_ENDPOINT_CNT field — 5-bit CRC field 3. After sending the token packet, the debug port controller sends a data packet consisting of: —S Y N C — SEND_PID_CNT field — The number of data bytes indicated in DATA_LEN_CNT from the DATA_BUFFER — 16-bit CRC NOTE: A DATA_LEN_CNT value of 0 is valid in which case no data bytes would be included in the packet. 4. After sending the data packet, the controller waits for a handshake response from the debug device.

• If a handshake is received, the debug port controller: — a. Places the received PID in the RECEIVED_PID_STS field — b. Resets the ERROR_GOOD#_STS bit — c. Sets the DONE_STS bit
• If no handshake PID is received, the debug port controller: — a. Sets the EXCEPTION_STS field to 001b — b. Sets the ERROR_GOOD#_STS bit — c. Sets the DONE_STS bit

5.20.10.1.2 IN Transactions

An IN transaction receives data from the debug device. It can occur only when the following are true:

• The debug port is enabled
• The debug software sets the GO_CNT bit
• The WRITE_READ#_CNT bit is reset The sequence of the transaction is: 1. Software sets the appropriate values in the following bits: — USB_ADDRESS_CNF — USB_ENDPOINT_CNF — TOKEN_PID_CNT[7:0] — DATA_LEN_CNT — WRITE_READ#_CNT (note: this will always be 0 for IN transactions) — GO_CNT (note: this will always be 1 to initiate the transaction)

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1. The debug port controller sends a token packet consisting of: — SYNC — TOKEN_PID_CNT field — USB_ADDRESS_CNT field — USB_ENDPOINT_CNT field — 5-bit CRC field. 3. After sending the token packet, the debug port controller waits for a response from the debug device. If a response is received: — The received PID is placed into the RECEIVED_PID_STS field — Any subsequent bytes are placed into the DATA_BUFFER — The DATA_LEN_CNT field is updated to show the number of bytes that were received after the PID. 4. If valid packet was received from the device that was one byte in length (indicating it was a handshake packet), then the debug port controller: — Resets the ERROR_GOOD#_STS bit — Sets the DONE_STS bit 5. If valid packet was received fr om the device that was more than one byte in length (indicating it was a data packet), then the debug port controller: — Transmits an ACK handshake packet — Resets the ERROR_GOOD#_STS bit — Sets the DONE_STS bit 6. If no valid packet is received, then the debug port controller: — Sets the EXCEPTION_STS field to 001b — Sets the ERROR_GOOD#_STS bit — Sets the DONE_STS bit.

5.20.10.1.3 Debug Software

There are two mutually exclusive conditions that debug software must address as part of its startup processing:

• The EHCI has been initialized by system software
• The EHCI has not been initialized by system software Debug software can determine the current ‘initialized’ state of the EHCI by examining the Configure Flag in the EHCI USB 2.0 Command Register. If this flag is set, then system software has initialized the EHCI. Otherwise the EHCI should not be considered initialized. Debug software will initialize the debug port registers depending on the state the EHCI. However, before this can be accomplished, debug software must determine which root USB port is designated as the debug port.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 213 Functional Description Determining the Debug Port Debug software can easily determine which USB root port has been designated as the debug port by examining bits 20:23 of the EHCI Host Controller Structural Parameters register. This 4-bit field represents the numeric value assigned to the debug port (i.e., 0000=port 0). Debug Software Startup with Non-Initialized EHCI Debug software can attempt to use the debug port if after setting the OWNER_CNT bit, the Current Connect Status bit in the appropriate (See Determining the Debug Port) PORTSC register is set. If the Current Connect Status bit is not set, then debug software may choose to terminate or it may choose to wait until a device is connected. If a device is connected to the port, then debug software must reset/enable the port. Debug software does this by setting and then clearing the Port Reset bit the PORTSC register. To guarantee a successful reset, debug software should wait at least 50 ms before clearing the Port Reset bit. Due to possible delays, this bit may not change to 0 immediately; reset is complete when this bit reads as 0. Software must not continue until this bit reads 0. If a high-speed device is attached, the EHCI will automatically set the Port Enabled/Disabled bit in the PORTSC register and the debug software can proceed. Debug software should set the ENABLED_CNT bit in the Debug Port Control/Status register, and then reset (clear) the Port Enabled/Disabled bit in the PORTSC register (so that the system host controller driver does not see an enabled port when it is first loaded). Debug Software Startup with Initialized EHCI Debug software can attempt to use the debug port if the Current Connect Status bit in the appropriate (See Determining the Debug Port) PORTSC register is set. If the Current Connect Status bit is not set, then debug software may choose to terminate or it may choose to wait until a device is connected. If a device is connected, then debug software must set the OWNER_CNT bit and then the ENABLED_CNT bit in the Debug Port Control/Status register. Determining Debug Peripheral Presence After enabling the debug port functionality, debug software can determine if a debug peripheral is attached by attempting to send data to the debug peripheral. If all attempts result in an error (Exception bits in the Debug Port Control/Status register indicates a Transaction Error), then the attached device is not a debug peripheral. If the debug port peripheral is not present, then debug software may choose to terminate or it may choose to wait until a debug peripheral is connected.

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5.21 SMBus Controller (D31:F3)

The ICH6 provides a System Management Bus (SMBus) 2.0 compliant host controller as well as a SMBus slave interface. The host controller provides a mechanism for the processor to initiate communications with SMBus peripherals (slaves). The ICH6 is also capable of operating in a mode in which it can communicate with I2C compatible devices. The ICH6 can perform SMBus messages with either packet error checking (PEC) enabled or disabled. The actual PEC calculation and checking is performed in hardware by the ICH6. The Slave Interface allows an external master to read from or write to the ICH6. Write cycles can be used to cause certain events or pass messages, and the read cycles can be used to determine the state of various status bits. The ICH6’s internal host controller cannot access the ICH6’s internal Slave Interface. The ICH6 SMBus logic exists in Device 31:Function 3 configuration space, and consists of a transmit data path, and host controller. The transmit data path provides the data flow logic needed to implement the seven different SMBus command protocols and is controlled by the host controller. The ICH6 SMBus controller logic is clocked by RTC clock. The SMBus Address Resolution Protocol (ARP) is supported by using the existing host controller commands through software, except for the new Host Notify command (which is actually a received message). The programming model of the host controller is combined into two portions: a PCI configuration portion, and a system I/O mapped portion. All static configuration, such as the I/O base address, is done via the PCI configuration space. Real-time programming of the Host interface is done in system I/O space. The ICH6 SMBus host controller checks for parity errors as a target. If an error is detected, the detected parity error bit in the PCI Status Register (Device 31:Function 3:Offset 06h:bit 15) is set. If bit 6 and bit 8 of the PCI Command Register (Device 31:Function 3:Offset 04h) are set, an SERR# is generated and the signaled SERR# bit in the PCI Status Register (bit 14) is set. Unless otherwise specified, all of the SMBus logic and its registers are reset by either RSMRST# or a similar reset via CF9h.

5.21.1 Host Controller

The SMBus host controller is used to send commands to other SMBus slave devices. Software sets up the host controller with an address, command, and, for writes, data and optional PEC; and then tells the controller to start. When the controller has finished transmitting data on writes, or receiving data on reads, it generates an SMI# or interrupt, if enabled. The host controller supports eight command protocols of the SMBus interface (see System Management Bus (SMBus) Specification, Version 2.0): Quick Command, Send Byte, Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block Read/Write, Block Write–Block Read Process Call, and Host Notify. The SMBus host controller requires that the various data and command fields be setup for the type of command to be sent. When software sets the START bit, the SMBus Host controller performs the requested transaction, and interrupts the processor (or generates an SMI#) when the transaction is completed. Once a START command has been issued, the values of the “active registers” (Host Control, Host Command, Transmit Slave Address, Data 0, Data 1) should not be changed or read

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 215 Functional Description until the interrupt status bit (INTR) has been set (indicating the completion of the command). Any register values needed for computation purposes should be saved prior to issuing of a new command, as the SMBus host controller updates all registers while completing the new command. Using the SMB host controller to send commands to the ICH6’s SMB slave port is supported. The ICH6 is fully compliant with the System Management Bus (SMBus) Specification, Version 2.0. Slave functionality, including the Host Notify protocol, is available on the SMBus pins. The SMLink and SMBus signals should not be tied together externally.

5.21.1.1 Command Protocols

In all of the following commands, a Host Status Register is used to determine the progress of the command. While the command is in operation, the HOST_BUSY bit is set. If the command completes successfully, the INTR bit will be set in the Host Status Register. If the device does not respond with an acknowledge, and the transaction times out, the DEV_ERR bit is set. If software sets the KILL bit in the Host Control Register while the command is running, the transaction will stop and the FAILED bit will be set. Quick Command When programmed for a Quick Command, the Transmit Slave Address Register is sent. The PEC byte is never appended to the Quick Protocol. Software should force the PEC_EN bit to 0 when performing the Quick Command. Software must force the I2C_EN bit to 0 when running this command. See section 5.5.1 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol. Send Byte / Receive Byte For the Send Byte command, the Transmit Slave Address and Device Command Registers are sent For the Receive Byte command, the Transmit Slave Address Register is sent. The data received is stored in the DATA0 register. Software must force the I2C_EN bit to 0 when running this command. The Receive Byte is similar to a Send Byte, the only difference is the direction of data transfer. See format of the protocol. Write Byte/Word The first byte of a Write Byte/Word access is the command code. The next 1 or 2 bytes are the data to be written. When programmed for a Write Byte/Word command, the Transmit Slave Address, Device Command, and Data0 Registers are sent. In addition, the Data1 Register is sent on a Write Word command. Software must force the I2C_EN bit to 0 when running this command. See section 5.5.4 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol. Read Byte/Word Reading data is slightly more complicated than writing data. First the ICH6 must write a command to the slave device. Then it must follow that command with a repeated start condition to denote a read from that device's address. The slave then returns 1 or 2 bytes of data. Software must force the I2C_EN bit to 0 when running this command.

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When programmed for the read byte/word command, the Transmit Slave Address and Device Command Registers are sent. Data is received into the DATA0 on the read byte, and the DAT0 and DATA1 registers on the read word. See section 5.5.5 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol. Process Call The process call is so named because a command sends data and waits for the slave to return a value dependent on that data. The protocol is simply a Write Word followed by a Read Word, but without a second command or stop condition. When programmed for the Process Call command, the ICH6 transmits the Transmit Slave Address, Host Command, DATA0 and DATA1 registers. Data received from the device is stored in the DATA0 and DATA1 registers. The Process Call command with I2C_EN set and the PEC_EN bit set produces undefined results. Software must force either I2C_EN or PEC_EN to 0 when running this command. See section 5.5.6 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol. Note: For process call command, the value written into bit 0 of the Transmit Slave Address Register (SMB I/O register, offset 04h) needs to be 0. Note: If the I2C_EN bit is set, the protocol sequence changes slightly: the Command Code (bits 18:11 in the bit sequence) are not sent - as a result, the slave will not acknowledge (bit 19 in the sequence). Block Read/Write The ICH6 contains a 32-byte buffer for read and write data that can be enabled by setting bit 1 of the Auxiliary Control register at offset 0Dh in I/O space, as opposed to a single byte of buffering. This 32-byte buffer is filled with write data before transmission, and filled with read data on reception. In the ICH6, the interrupt is generated only after a transmission or reception of 32 bytes, or when the entire byte count has been transmitted/received. The byte count field is transmitted but ignored by the ICH6 as software will end the transfer after all bytes it cares about have been sent or received. For a Block Write, software must either force the I2C_EN bit or both the PEC_EN and AAC bits to 0 when running this command. The block write begins with a slave address and a write condition. After the command code the ICH6 issues a byte count describing how many more bytes will follow in the message. If a slave had 20 bytes to send, the first byte would be the number 20 (14h), followed by 20 bytes of data. The byte count may not be 0. A Block Read or Write is allowed to transfer a maximum of 32 data bytes. When programmed for a block write command, the Transmit Slave Address, Device Command, and Data0 (count) registers are sent. Data is then sent from the Block Data Byte register; the total data sent being the value stored in the Data0 Register. On block read commands, the first byte received is stored in the Data0 register, and the remaining bytes are stored in the Block Data Byte register. See section 5.5.7 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol. Note: For Block Write, if the I2C_EN bit is set, the format of the command changes slightly. The ICH6 will still send the number of bytes (on writes) or receive the number of bytes (on reads) indicated in the DATA0 register. However, it will not send the contents of the DATA0 register as part of the

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 217 Functional Description message. Also, the Block Write protocol sequence changes slightly: the Byte Count (bits 27:20 in the bit sequence) are not sent - as a result, the slave will not acknowledge (bit 28 in the sequence). I2C Read This command allows the ICH6 to perform block reads to certain I2C devices, such as serial E2PROMs. The SMBus Block Read supports the 7-bit addressing mode only. However, this does not allow access to devices using the I2C “Combined Format” that has data bytes after the address. Typically these data bytes correspond to an offset (address) within the serial memory chips. Note: This command is supported independent of the setting of the I2C_EN bit. The I2C Read command with the PEC_EN bit set produces undefined results. Software must force both the PEC_EN and AAC bit to 0 when running this command. For I2C Read command, the value written into bit 0 of the Transmit Slave Address Register (SMB I/O register, offset 04h) needs to be 0. The format that is used for the command is shown in Table 5-47. The ICH6 will continue reading data from the peripheral until the NAK is received. Table 5-47. I2C Block Read Bit Description 1S t a r t 8:2 Slave Address — 7 bits 9W r i t e

10 Acknowledge from slave

18:11 Send DATA1 register

19 Acknowledge from slave

20 Repeated Start

27:21 Slave Address — 7 bits

28 Read

29 Acknowledge from slave

37:30 Data byte 1 from slave — 8 bits

38 Acknowledge

46:39 Data byte 2 from slave — 8 bits

47 Acknowledge

– Data bytes from slave / Acknowledge – Data byte N from slave — 8 bits – NOT Acknowledge –S t o p

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Block Write–Block Read Process Call The block write-block read process call is a two-part message. The call begins with a slave address and a write condition. After the command code the host issues a write byte count (M) that describes how many more bytes will be written in the first part of the message. If a master has 6 bytes to send, the byte count field will have the value 6 (0000 0110b), followed by the 6 bytes of data. The write byte count (M) cannot be 0. The second part of the message is a block of read data beginning with a repeated start condition followed by the slave address and a Read bit. The next byte is the read byte count (N), which may differ from the write byte count (M). The read byte count (N) cannot be 0. The combined data payload must not exceed 32 bytes. The byte length restrictions of this process call are summarized as follows:

• M ≥ 1 byte
• N ≥ 1 byte
• M + N ≤ 32 bytes The read byte count does not include the PEC byte. The PEC is computed on the total message beginning with the first slave address and using the normal PEC computational rules. It is highly recommended that a PEC byte be used with the Block Write-Block Read Process Call. Software must do a read to the command register (offset 2h) to reset the 32 byte buffer pointer prior to reading the block data register. Note that there is no STOP condition before the repeated START condition, and that a NACK signifies the end of the read transfer. Note: E32B bit in the Auxiliary Control register must be set when using this protocol. See section 5.5.8 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol.

5.21.2 Bus Arbitration

Several masters may attempt to get on the bus at the same time by driving the SMBDATA line low to signal a start condition. The ICH6 continuously monitors the SMBDATA line. When the ICH6 is attempting to drive the bus to a 1 by letting go of the SMBDATA line, and it samples SMBDATA low, then some other master is driving the bus and the ICH6 will stop transferring data. If the ICH6 sees that it has lost arbitration, the condition is called a collision. The ICH6 will set the BUS_ERR bit in the Host Status Register, and if enabled, generate an interrupt or SMI#. The processor is responsible for restarting the transaction. When the ICH6 is a SMBus master, it drives the clock. When the ICH6 is sending address or command as an SMBus master, or data bytes as a master on writes, it drives data relative to the clock it is also driving. It will not start toggling the clock until the start or stop condition meets proper setup and hold time. The ICH6 will also guarantee minimum time between SMBus transactions as a master. Note: The ICH6 supports the same arbitration protocol for both the SMBus and the System Management (SMLINK) interfaces.

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5.21.3 Bus Timing

5.21.3.1 Clock Stretching

Some devices may not be able to handle their clock toggling at the rate that the ICH6 as an SMBus master would like. They have the capability of stretching the low time of the clock. When the ICH6 attempts to release the clock (allowing the clock to go high), the clock will remain low for an extended period of time. The ICH6 monitors the SMBus clock line after it releases the bus to determine whether to enable the counter for the high time of the clock. While the bus is still low, the high time counter must not be enabled. Similarly, the low period of the clock can be stretched by an SMBus master if it is not ready to send or receive data.

5.21.3.2 Bus Time Out (Intel ® ICH6 as SMBus Master)

If there is an error in the transaction, such that an SMBus device does not signal an acknowledge, or holds the clock lower than the allowed time-out time, the transaction will time out. The ICH6 will discard the cycle and set the DEV_ERR bit. The time out minimum is 25 ms (800 RTC clocks). The time-out counter inside the ICH6 will start after the last bit of data is transferred by the ICH6 and it is waiting for a response. The 25 ms timeout counter will not count under the following conditions: 1. BYTE_DONE_STATUS bit (SMBus I/O Offset 00h, bit 7) is set 2. The SECOND_TO_STS bit (TCO I/O Offset 06h, bit 1) is not set (this indicates that the system has not locked up)

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5.21.4 Interrupts / SMI#

The ICH6 SMBus controller uses PIRQB# as its interrupt pin. However, the system can alternatively be set up to generate SMI# instead of an interrupt, by setting the SMBus_SMI_EN bit (Device 31:Function 0:Offset 40h:bit 1). Table 5-49 and Table 5-50 specify how the various enable bits in the SMBus function control the generation of the interrupt, Host and Slave SMI, and Wake internal signals. The rows in the tables are additive, which means that if more than one row is true for a particular scenario then the Results for all of the activated rows will occur. Table 5-48. Enable for SMBALERT# Event INTREN (Host Control I/O Register, Offset 02h, Bit 0) SMB_SMI_EN (Host Configuration Register, D31:F3:Offset 40h, Bit 1) SMBALERT_DIS (Slave Command I/O Register, Offset 11h, Bit 2) Result SMBALERT# asserted low (always reported in Host Status Register, Bit 5) X X X Wake generated X1 0 Slave SMI# generated (SMBus_SMI_STS) 1 0 0 Interrupt generated Table 5-49. Enables for SMBus Slave Write and SMBus Host Events Event INTREN (Host Control I/O Register, Offset 02h, Bit 0) SMB_SMI_EN (Host Configuration Register, D31:F3:Offset 40h, Bit1) Event Slave Write to Wake/ SMI# Command XX Wake generated when asleep. Slave SMI# generated when awake (SMBus_SMI_STS). Slave Write to SMLINK_SLAVE_SMI Command XX Slave SMI# generated when in the S0 state (SMBus_SMI_STS) Any combination of Host Status Register [4:1] asserted

0 X None

1 1 Host SMI# generated Table 5-50. Enables for the Host Notify Command HOST_NOTIFY_INTREN (Slave Control I/O Register, Offset 11h, bit 0) SMB_SMI_EN (Host Configuration Register, D31:F3:Off40h, Bit 1) HOST_NOTIFY_WKEN (Slave Control I/O Register, Offset 11h, bit 1) Result

0 X 0 None

11X Slave SMI# generated (SMBus_SMI_STS)

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5.21.5 SMBALERT#

SMBALERT# is multiplexed with GPI[11]. When enable and the signal is asserted, The ICH6 can generate an interrupt, an SMI#, or a wake event from S1–S5. Note: Any event on SMBALERT# (regardless whether it is programmed as a GPI or not), causes the event message to be sent in heartbeat mode.

5.21.6 SMBus CRC Generation and Checking

If the AAC bit is set in the Auxiliary Control register, the ICH6 automatically calculates and drives CRC at the end of the transmitted packet for write cycles, and will check the CRC for read cycles. It will not transmit the contents of the PEC register for CRC. The PEC bit must not be set in the Host Control register if this bit is set, or unspecified behavior will result. If the read cycle results in a CRC error, the DEV_ERR bit and the CRCE bit in the Auxiliary Status register at offset 0Ch will be set.

5.21.7 SMBus Slave Interface

The ICH6’s SMBus slave interface is accessed via the SMBus. The SMBus slave logic will not generate or handle receiving the PEC byte and will only act as a Legacy Alerting Protocol device. The slave interface allows the ICH6 to decode cycles, and allows an external microcontroller to perform specific actions. Key features and capabilities include:

• Supports decode of three types of messages: Byte Write, Byte Read, and Host Notify.
• Receive Slave Address register: This is the address that the ICH6 decodes. A default value is provided so that the slave interface can be used without the processor having to program this register.
• Receive Slave Data register in the SMBus I/O space that includes the data written by the external microcontroller.
• Registers that the external microcontroller can read to get the state of the ICH6.
• Status bits to indicate that the SMBus slave logic caused an interrupt or SMI# due to the reception of a message that matched the slave address. — Bit 0 of the Slave Status Regist er for the Host Notify command — Bit 16 of the SMI Status Register ( Section 10.8.3.13) for all others If a master leaves the clock and data bits of the SMBus interface at 1 for 50 µs or more in the middle of a cycle, the ICH6 slave logic's behavior is undefined. This is interpreted as an unexpected idle and should be avoided when performing management activities to the slave logic. Note: When an external microcontroller accesses the SMBus slave interface over the SMBus a translation in the address is needed to accommodate the least significant bit used for read/write control. For example, if the ICH6 slave address (RCV_SLV A) is left at 44h (default), the external micro controller would use an address of 88h/89h (write/read).

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5.21.7.1 Format of Slave Write Cycle

The external master performs Byte Write commands to the ICH6 SMBus slave interface. The “Command” field (bits 11:18) indicate which register is being accessed. The Data field (bits 20:27) indicate the value that should be written to that register. Table 5-51 has the values associated with the registers. NOTE: The external microcontroller is responsible to make sure that it does not update the contents of the data byte registers until they have been read by the system processor. The ICH6 overwrites the old value with any new value received. A race condition is possible where the new value is being written to the register just at the time it is being read. ICH6 will not attempt to cover this race condition (i.e., unpredictable results in this case). Table 5-51. Slave Write Registers Register Function 0 Command Register. See Table 5-52 below for legal values written to this register. 1–3 Reserved

4 Data Message Byte 0

5 Data Message Byte 1

6–7 Reserved

8 Reserved

9–FFh Reserved Table 5-52. Command Types (Sheet 1 of 2) Command Type Description 0R e s e r v e d WAKE/SMI#. This command wakes the system if it is not already awake. If system is already awake, an SMI# is generated. NOTE: The SMB_WAK_STS bit will be set by this command, even if the system is already awake. The SMI handler should then clear this bit. 2 Unconditional Powerdown. This command sets the PWRBTNOR_STS bit, and has the same effect as the Powerbutton Override occurring. HARD RESET WITHOUT CYCLING: This command causes a hard reset of the system (does not include cycling of the power supply). This is equivalent to a write to the CF9h register with bits 2:1 set to 1, but bit 3 set to 0. 4 HARD RESET SYSTEM. This command causes a hard reset of the system (including cycling of the power supply). This is equivalent to a write to the CF9h register with bits 3:1 set to 1. Disable the TCO Messages. This command will disable the Intel® ICH6 from sending Heartbeat and Event messages (as described in Section 5.15.2). Once this command has been executed, Heartbeat and Event message reporting can only be re-enabled by assertion and de- assertion of the RSMRST# signal. 6 WD RELOAD: Reload watchdog timer. 7R e s e r v e d

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 223 Functional Description

5.21.7.2 Format of Read Command

The external master performs Byte Read commands to the ICH6 SMBus Slave I/F. The “Command” field (bits 18:11) indicate which register is being accessed. The Data field (bits 30:37) contain the value that should be read from that register. Table 5-53 shows the Read Cycle Format. Table 5-54 shows the register mapping for the data byte. SMLINK_SLV_SMI. When ICH6 detects this command type while in the S0 state, it sets the SMLINK_SLV_SMI_STS bit (see Section 10.9.5). This command should only be used if the system is in an S0 state. If the message is received during S1–S5 states, the ICH6 acknowledges it, but the SMLINK_SLV_SMI_STS bit does not get set. NOTE: It is possible that the system transitions out of the S0 state at the same time that the SMLINK_SLV_SMI command is received. In this case, the SMLINK_SLV_SMI_STS bit may get set but not serviced before the system goes to sleep. Once the system returns to S0, the SMI associated with this bit would then be generated. Software must be able to handle this scenario. 9–FFh Reserved Table 5-52. Command Types (Sheet 2 of 2) Command Type Description Table 5-53. Read Cycle Format Bit Description Driven by Comment

1 Start External Microcontroller

8:2 Slave Address - 7 bits External Microcontroller Must match value in Receive Slave Address register

9 Write External Microcontroller Always 0

10 ACK Intel ® ICH6

18:11 Command code - 8 bits External Microcontroller Indicates which register is being accessed See Table 5-54

19 ACK ICH6

20 Repeated Start External Microcontroller

27:21 Slave Address - 7 bits External Microcontroller Must match value in Receive Slave Address register

28 Read External Microcontroller Always 1

29 ACK ICH6

37:30 Datay Byte ICH6 Value depends on register being accessed. See Table 5-54

38 NOT ACK External Microcontroller

39 Stop External Microcontroller

224 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

Table 5-54. Data Values for Slave Read Registers Register Bits Description 07 : 0 R e s e r v e d 12 : 0 System Power State 000 = S0 001 = S1 010 = Reserved 011 = S3 100 = S4 101 = S5 110 = Reserved 111 = Reserved 17 : 3 R e s e r v e d 2 3:0 Frequency Strap Register 27 : 4 R e s e r v e d 3 5:0 Watchdog Timer current value 37 : 6 R e s e r v e d 40 1 = The Intruder Detect (INTRD_DET) bit is set. This indicates that the system cover has probably been opened. 41 1 = BTI Temperature Event occurred. This bit will be set if the Intel ® ICH6’s THRM# input signal is active. Need to take after polarity control. 42 Boot-status. This bit will be 1 when the processor does not fetch the first instruction.

43 This bit will be set after the TCO timer times out a second time (Both

TIMEOUT and SECOND_TO_STS bits set). 46 : 4 R e s e r v e d The bit will reflect the state of the GPI11/SMBALERT# signal, and will depend on the GP_INV11 bit. It does not matter if the pin is configured as GPI11 or SMBALERT#.

• If the GP_INV11 bit is 1, the value of register 4 bit 7 will equal the level of the GPI11/SMBALERT# pin (high = 1, low = 0).
• If the GP_INV11 bit is 0, the value of register 4 bit 7 will equal the inverse of the level of the GPI11/SMBALERT# pin (high = 1, low = 0). 50 Unprogrammed flash BIOS bit. This bit will be 1 to indicate that the first BIOS fetch returned FFh, that indicates that the flash BIOS is probably blank.

51 R e s e r v e d

52 Processor Power Failure Status. 1 if the CPUPWR_FLR bit in the GEN_PMCON_2 register is set. 57 : 3 R e s e r v e d 6 7:0 Contents of the Message 1 register. 7 7:0 Contents of the Message 2 register. 8 7:0 Contents of the WDSTATUS register. 9-FFh 7:0 Reserved

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 225 Functional Description

5.21.7.2.1 Behavioral Notes

According to SMBus protocol, Read and Write messages always begin with a Start bit – Address– Write bit sequence. When the ICH6 detects that the address matches the value in the Receive Slave Address register, it will assume that the protocol is always followed and ignore the Write bit (bit 9) and signal an Acknowledge during bit 10. In other words, if a Start –Address–Read occurs (which is illegal for SMBus Read or Write protocol), and the address matches the ICH6’s Slave Address, the ICH6 will still grab the cycle. Also according to SMBus protocol, a Read cycle contains a Repeated Start–Address–Read sequence beginning at bit 20. Once again, if the Address matches the ICH6’s Receive Slave Address, it will assume that the protocol is followed, ignore bit 28, and proceed with the Slave Read cycle. Note: An external microcontroller must not attempt to access the ICH6’s SMBus Slave logic until at least 1 second after both RTCRST# and RSMRST# are de-asserted (high).

5.21.7.3 Format of Host Notify Command

The ICH6 tracks and responds to the standard Host Notify command as specified in the System Management Bus (SMBus) Specification, Version 2.0. The host address for this command is fixed to 0001000b. If the ICH6 already has data for a previously-received host notify command that has not been serviced yet by the host software (as indicated by the HOST_NOTIFY_STS bit), then it will NACK following the host address byte of the protocol. This allows the host to communicate non-acceptance to the master and retain the host notify address and data values for the previous cycle until host software completely services the interrupt. Note: Host software must always clear the HOST_NOTIFY_STS bit after completing any necessary reads of the address and data registers. Table 5-55 shows the Host Notify format. Table 5-55. Host Notify Format Bit Description Driven By Comment

1 Start External Master

8:2 SMB Host Address — 7 bits External Master Always 0001_000

9 Write External Master Always 0

10 ACK (or NACK) Intel ® ICH6 ICH6 NACKs if HOST_NOTIFY_STS is 1

17:11 Device Address – 7 bits External Master Indicates the address of the master; loaded into the Notify Device Address Register

18 Unused — Always 0 External Master 7-bit-only address; this bit is inserted to complete

27:20 Data Byte Low — 8 bits External Master Loaded into the Notify Data Low Byte Register

28 ACK ICH6

36:29 Data Byte High — 8 bits External Master Loaded into the Notify Data High Byte Register

37 ACK ICH6

38 Stop External Master

226 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

5.22 AC ’97 Controller (Audio D30:F2, Modem D30:F3)

Note: All references to AC ’97 in this document refer to the AC ’97 Specification, Version 2.3. For further information on the operation of the AC-link protocol, see the AC ’97 Specification, Version 2.3. The ICH6 AC ’97 controller features include:

• Independent PCI functions for audio and modem.
• Independent bus master logic for dual Microphone input, dual PCM Audio input (2-channel stereo per input), PCM audio output (2-, 4- or 6-channel audio), Modem input, Modem output and S/PDIF output.
• 20-bit sample resolution
• Multiple sample rates up to 48 kHz
• Support for 16 codec-implemented GPIOs
• Single modem line
• Configure up to three codecs with three ACZ_SDIN pins Table 5-56 shows a detailed list of features supported by the ICH6 AC ’97 digital controller. Table 5-56. Features Supported by Intel® ICH6 (Sheet 1 of 2) Feature Description System Interface
• Isochronous low latency bus master memory interface
• Scatter/gather support for word-aligned buffers in memory (all mono or stereo 20-bit and 16-bit data types are supported, no 8-bit data types are supported)
• Data buffer size in system memory from 3 to 65535 samples per input
• Data buffer size in system memory from 0 to 65535 samples per output
• Independent PCI audio and modem functions with configuration and I/O spaces
• AC ’97 codec registers are shadowed in system memory via driver
• AC ’97 codec register accesses are serialized via semaphore bit in PCI I/O space (new accesses are not allowed while a prior access is still in progress) Power Management • Power management via PCI Power Management PCI Audio Function
• Read/write access to audio codec regist ers 00h–3Ah and vendor registers 5Ah–7Eh
• 20-bit stereo PCM output, up to 48 kHz (L,R, Center, Sub-woofer, L-rear and R-rear channels on slots 3,4,6,7,8,9,10,11)
• 16-bit stereo PCM input, up to 48 kHz (L,R channels on slots 3,4)
• 16-bit mono mic in w/ or w/o mono mix, up to 48 kHz (L,R channel, slots 3,4) (mono mix supports mono hardware AEC reference for speakerphone)
• 16-bit mono PCM input, up to 48 kHz from dedicated mic ADC (slot 6) (supports speech recognition or stereo hardware AEC ref for speakerphone)
• During cold reset ACZ_RST# is held low until after POST and software de-assertion of ACZ_RST# (supports passive PC_BEEP to speaker connection during POST)

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 227 Functional Description Note: Throughout this document, references to D31:F5 indicate that the audio function exists in PCI Device 31, Function 5. References to D31:F6 indicate that the modem function exists in PCI Device 31, Function 6. Note: Throughout this document references to tertiary, third, or triple codecs refer to the third codec in the system connected to the ACZ_SDIN2 pin. The AC ’97 v2.3 Specification refers to non-primary codecs as multiple secondary codecs. To avoid confusion and excess verbiage, this datasheet refers to it as the third or tertiary codec. PCI Modem function

• Read/write access to modem codec registers 3Ch–58h and vendor registers 5Ah–7Eh
• 16-bit mono modem line 1 output and input, up to 48 kHz (slot 5)
• Low latency GPIO[15:0] via hardwired update between slot 12 and PCI I/O register
• Programmable PCI interrupt on modem GPIO input changes via slot 12 GPIO_INT
• SCI event generation on ACZ_SDIN[2:0] wake-up signal AC-link
• AC ’97 2.3 AC-link interface
• Variable sample rate output support via AC ’97 SLOTREQ protocol (slots
• Variable sample rate input support via monito ring of slot valid tag bits (slots 3,4,5,6)
• 3.3 V digital operation meets AC ’97 2.3 DC switching levels
• AC-link I/O driver capability meets AC ’97 2.3 triple codec specifications
• Codec register status reads must be returned with data in the next AC-link frame, per AC ’97 v2.3 Specification. Multiple Codec
• Triple codec addressing: All AC ’97 Audio codec register accesses are addressable to codec ID 00 (primary), codec ID 01 (secondary), or codec ID 10 (tertiary).
• Modem codec addressing: All AC ‘97 Modem codec register accesses are addressable to codec ID 00 (primary) or codec ID 01 (secondary).
• Triple codec receive capabi lity via ACZ_SDIN[2:0] pins (ACZ_SDIN[2:0] frames are internally validated, synchronized, and OR’d depending on the Steer Enable bit status in the SDM register)
• ACZ_SDIN mapping to DMA engine mapping ca pability allows for simultaneous input from two different audio codecs. NOTES: 1. Audio Codec IDs are remappable and not limited to 00,01,10. 2. Modem Codec IDs are remappable and limited to 00, 01. 3. When using multiple codecs, the Modem Codec must be ID 01.Figure 5-11. Intel® ICH6-Based Audio Codec ’97 Specification, Version 2.3 Table 5-56. Features Supported by Intel® ICH6 (Sheet 2 of 2) Feature Description Audio In (Record) Audio Out (6 Channel Playback) PC Mic.2 S/PDIF* Output Mic.1 Modem

228 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

5.22.1 PCI Power Management

This Power Management section applies for all AC ’97 controller functions. After a power management event is detected, the AC ’97 controller wakes the host system. The following sections describe these events and the AC ’97 controller power states. Device Power States The AC ’97 controller supports D0 and D3 PCI Power Management states. The following are notes regarding the AC ’97 controller implementation of the Device States: 1. The AC ’97 controller hardware does not inherently consume any more power when it is in the D0 state than it does in D3 state. However, software can halt the DMA engine prior to entering these low power states such that the maximum power consumption is reduced. 2. In the D0 state, all implemented AC ’97 controller features are enabled. 3. In D3 state, accesses to the AC ’97 controller memory-mapped or I/O range results in master abort. 4. In D3 state, the AC ’97 controller interrupt will never assert for any reason. The internal PME# signal is used to signal wake events, etc. 5. When the Device Power Stat e field is written from D3HOT to D0, an internal reset is generated. See Section 17.1 for general rules on the effects of this reset. 6. AC97 STS bit is set only when the audio or modem resume events were detected and their respective PME enable bits were set. 7. GPIO Status change interrupt no longer has a direct path to the AC97 STS bit. This causes a wake up event only if the modem controller was in D3 8. Resume events on ACZ_SDIN[2:0] cause resume in terrupt status bits to be set only if their respective controllers are not in D3. 9. Edge detect logic prevents the interrupts from being asserted in case the AC97 controller is switched from D3 to D0 after a wake event. 10. Once the interrupt status bits are set, they will cause PIRQB# if their respective enable bits were set. One of the audio or the modem drivers will handle the interrupt.

5.22.2 AC-Link Overview

The ICH6 is an AC ’97 2.3 controller that communicates with companion codecs via a digital serial link called the AC-link. All digital audio/modem streams and command/status information is communicated over the AC-link. The AC-link is a bi-directional, serial PCM digital stream. It handles multiple input and output data streams, as well as control register accesses, employing a time division multiplexed (TDM) scheme. The AC-link architecture provides for data transfer through individual frames transmitted in a serial fashion. Each frame is divided into 12 outgoing and 12 incoming data streams, or slots. The architecture of the ICH6 AC-link allows a maximum of three codecs to be connected. Figure 5-12 shows a three codec topology of the AC-link for the ICH6. The AC-link consists of a five signal interface between the ICH6 and codec(s). Note: The ICH6’s AC ‘97 controller shares the signal interface with the Intel High Definition Audio controller. However, only one controller may be enabled at a time.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 229 Functional Description ICH6 core well outputs may be used as strapping options for the ICH6, sampled during system reset. These signals may have weak pullups/pulldowns; however, this will not interfere with link operation. ICH6 inputs integrate weak pulldowns to prevent floating traces when a secondary and/ or tertiary codec is not attached. When the Shut Off bit in the control register is set, all buffers will be turned off and the pins will be held in a steady state, based on these pullups/pulldowns. ACZ_BIT_CLK is fixed at 12.288 MHz and is sourced by the primary codec. It provides the necessary clocking to support the twelve 20-bit time slots. AC-link serial data is transitioned on each rising edge of ACZ_BIT_CLK. The receiver of AC-link data samples each serial bit on the falling edge of ACZ_BIT_CLK. If ACZ_BIT_CLK makes no transitions for four consecutive PCI clocks, the ICH6 assumes the primary codec is not present or not working. It sets bit 28 of the Global Status Register (I/O offset 30h). All accesses to codec registers with this bit set will return data of FFh to prevent system hangs. Figure 5-12. AC ’97 2.3 Controller-Codec Connection Intel® ICH6 Primary Codec AC / MC / AMC AC97 ICH6 codec conn ACZ_SDIN2 ACZ_SDIN1 ACZ_RST# ACZ_SDOUT ACZ_SYNC ACZ_BIT_CLK Secondary Codec AC / MC / AMC Tertiary Codec AC / MC / AMC ACZ_SDIN0

230 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

Synchronization of all AC-link data transactions is signaled by the AC ’97 controller via the ACZ_SYNC signal, as shown in Figure 5-13. The primary codec drives the serial bit clock onto the AC-link, which the AC ’97 controller then qualifies with the ACZ_SYNC signal to construct data frames. ACZ_SYNC, fixed at 48 kHz, is derived by dividing down ACZ_BIT_CLK. ACZ_SYNC remains high for a total duration of 16 ACZ_BIT_CLK at the beginning of each frame. The portion of the frame where ACZ_SYNC is high is defined as the tag phase. The remainder of the frame where ACZ_SYNC is low is defined as the data phase. Each data bit is sampled on the falling edge of ACZ_BIT_CLK. The ICH6 has three ACZ_SDIN pins allowing a single, dual, or triple codec configuration. When multiple codecs are connected, the primary, secondary, and tertiary codecs can be connected to any ACZ_SDIN line. The ICH6 does not distinguish between codecs on its ACZ_SDIN[2:0] pins, however the registers do distinguish between ACZ_SDIN[0], ACZ_SDIN[1], and ACZ_SDIN[2] for wake events, etc. If using a Modem Codec it is recommended to connect it to ACZ_SDIN1. See your Platform Design Guide for a matrix of valid codec configurations. The ICH6 does not support optional test modes as outlined in the AC ’97 Specification, Version 2.3.

5.22.2.1 Register Access

In the ICH6 implementation of the AC-link, up to three codecs can be connected to the SDOUT pin. The following mechanism is used to address the primary, secondary, and tertiary codecs individually. The primary device uses bit 19 of slot 1 as the direction bit to specify read or write. Bits [18:12] of slot 1 are used for the register index. For I/O writes to the primary codec, the valid bits [14:13] for slots 1 and 2 must be set in slot 0, as shown in Table 5-57. Slot 1 is used to transmit the register address, and slot 2 is used to transmit data. For I/O reads to the primary codec, only slot 1 should be valid since only an address is transmitted. For I/O reads only slot 1 valid bit is set, while for I/O writes both slots 1 and 2 valid bits are set. The secondary and tertiary codec registers are accessed using slots 1 and 2 as described above, however the slot valid bits for slots 1 and 2 are marked invalid in slot 0 and the codec ID bits [1:0] (bit 0 and bit 1 of slot 0) is set to a non-zero value. This allows the secondary or tertiary codec to monitor the slot valid bits of slots 1 and 2, and bits [1:0] of slot 0 to determine if the access is directed to the secondary or tertiary codec. If the register access is targeted to the secondary or tertiary codec, slot 1 and 2 will contain the address and data for the register access. Since slots 1 and 2 are marked invalid, the primary codec will ignore these accesses. Figure 5-13. AC-Link Protocol SYNC BIT_CLK SDIN slot(1) Time Slot "Valid" Bits 20.8uS (48 KHz) Slot 1 Slot 2 01 9 0 1 9 0 19 0 Slot 3 Slot 12 81.4 nS

12.288 MHz

("1" = time slot contains valid PCM 19Codec Ready End of previous Audio Frame Tag Phase Data Phase

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 231 Functional Description When accessing the codec registers, only one I/O cycle can be pending across the AC-link at any time. The ICH6 implements write posting on I/O writes across the AC-link (i.e., writes across the link are indicated as complete before they are actually sent across the link). In order to prevent a second I/O write from occurring before the first one is complete, software must monitor the CAS bit in the Codec Access Semaphore register which indicates that a codec access is pending. Once the CAS bit is cleared, then another codec access (read or write) can go through. The exception to this being reads to offset 54h/D4h/154h (slot 12) which are returned immediately with the most recently received slot 12 data. Writes to offset 54h, D4h, and 154h (primary, secondary and tertiary codecs), get transmitted across the AC-link in slots 1 and 2 as a normal register access. Slot 12 is also updated immediately to reflect the data being written. The controller does not issue back to back reads. It must get a response to the first read before issuing a second. In addition, codec reads and writes are only executed once across the link, and are not repeated.

5.22.3 AC-Link Low Power Mode

The AC-link signals can be placed in a low-power mode. When the AC ’97 Powerdown register (26h), is programmed to the appropriate value, both ACZ_BIT_CLK and ACZ_SDIN will be brought to, and held at a logic low voltage level. Table 5-57. Output Tag Slot 0 Bit Primary Access Example Secondary Access Example Description 15 1 1 Frame Valid 14 1 0 Slot 1 Valid, Command Addr ess bit (Primary codec only) 13 1 0 Slot 2 Valid, Command Da ta bit (Primary codec only) 12:3 X X Slot 3–12 Valid 2 0 0 Reserved 1:0 00 01 Codec ID (00 reserved for primary; 01 indicate secondary; 10 indicate tertiary) Figure 5-14. AC-Link Powerdown Timing ACZ_SDOUT TAG ACZ_SYNC ACZ_BIT_CLK Write to 0x20 Data PR4 slot 12 prev. frame TAG slot 12 prev. frame ACZ_SDIN[2:0] Note: ACZ_BIT_CLK not to scale

232 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

ACZ_BIT_CLK and ACZ_SDIN transition low immediately after a write to the Powerdown Register (26h) with PR4 enabled. When the AC ’97 controller driver is at the point where it is ready to program the AC-link into its low-power mode, slots 1 and 2 are assumed to be the only valid stream in the audio output frame. The AC ’97 controller also drives ACZ_SYNC, and ACZ_SDOUT low after programming AC ’97 to this low power, halted mode Once the codec has been instructed to halt, ACZ_BIT_CLK, a special wake up protocol must be used to bring the AC-link to the active mode since normal output and input frames can not be communicated in the absence of ACZ_BIT_CLK. Once in a low-power mode, the ICH6 provides three methods for waking up the AC-link; external wake event, cold reset and warm reset. Note: Before entering any low-power mode where the link interface to the codec is expected to be powered down while the rest of the system is awake, the software must set the “Shut Off” bit in the control register.

5.22.3.1 External Wake Event

Codecs can signal the controller to wake the AC-link, and wake the system using ACZ_SDIN. The minimum ACZ_SDIN wake up pulse width is 1 us. The rising edge of ACZ_SDIN[0], ACZ_SDIN[1] or ACZ_SDIN[2] causes the ICH6 to sequence through an AC-link warm reset and set the AC97_STS bit in the GPE0_STS register to wake the system. The primary codec must wait to sample ACZ_SYNC high and low before restarting ACZ_BIT_CLK as diagrammed in Figure 5-15. The codec that signaled the wake event must keep its ACZ_SDIN high until it has sampled ACZ_SYNC having gone high, and then low. The AC-link protocol provides for a cold reset and a warm reset. The type of reset used depends on the system’s current power down state. Unless a cold or register reset (a write to the Reset register in the codec) is performed, wherein the AC ’97 codec registers are initialized to their default values, registers are required to keep state during all power down modes. Once powered down, activation of the AC-link via re-assertion of the ACZ_SYNC signal must not occur for a minimum of four audio frame times following the frame in which the power down was triggered. When AC-link powers up, it indicates readiness via the codec ready bit. Figure 5-15. SDIN Wake Signaling ACZ_ SDOUT TAG ACZ_SYNC ACZ_BIT_CLK Write to 0x20 Data PR4 slot 12 prev. frame TAG slot 12 prev. frame ACZ_ SDIN[2:0] TAG Slot 1 Slot 2 Power Down Frame Wake Event Sleep State New Audio Frame TAG Slot 1 Slot 2

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 233 Functional Description

5.22.4 AC ’97 Cold Reset

A cold reset is achieved by asserting ACZ_RST# for 1 µs. By driving ACZ_RST# low, ACZ_BIT_CLK, and ACZ_SDOUT will be activated and all codec registers will be initialized to their default power on reset values. ACZ_RST# is an asynchronous AC ’97 input to the codec.

5.22.5 AC ’97 Warm Reset

A warm reset re-activates the AC-link without altering the current codec register values. A warm reset is signaled by driving ACZ_SYNC high for a minimum of 1 µs in the absence of ACZ_BIT_CLK. Within normal frames, ACZ_SYNC is a synchronous AC ’97 input to the codec. However, in the absence of ACZ_BIT_CLK, ACZ_SYNC is treated as an asynchronous input to the codec used in the generation of a warm reset. The codec must not respond with the activation of ACZ_BIT_CLK until ACZ_SYNC has been sampled low again by the codec. This prevents the false detection of a new frame. Note: On receipt of wake up signaling from the codec, the digital controller issues an interrupt if enabled. Software then has to issue a warm or cold reset to the codec by setting the appropriate bit in the Global Control Register.

5.22.6 Hardware Assist to Dete rmine ACZ_SDIN Used Per Codec

Software first performs a read to one of the audio codecs. The read request goes out on ACZ_SDOUT. Since the ICH6 allows one read to be performed at a time on the link, eventually the read data will come back in on one of the ACZ_SDIN[2:0] lines. The codec does this by indicating that status data is valid in its TAG, then echoes the read address in slot 1 followed by the read data in slot 2. The new function of the ICH6 hardware is to notice which ACZ_SDIN line contains the read return data, and to set new bits in the new register indicating which ACZ_SDIN line the register read data returned on. If it returned on ACZ_SDIN[0], bits [1:0] contain the value 00. If it returned on ACZ_SDIN[1], the bits contain the value 01, etc. ICH6 hardware can set these bits every time register read data is returned from a function 5 read. No special command is necessary to cause the bits to be set. The new driver/BIOS software reads the bits from this register when it cares to, and can ignore it otherwise. When software is attempting to establish the codec-to-ACZ_SDIN mapping, it will single feed the read request and not pipeline to ensure it gets the right mapping, we cannot ensure the serialization of the access.

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5.23 Intel ® High Definition Audio (D27:F0)

5.23.1 Link Protocol Overview

The Intel High Definition Audio Link is the digital serial interface that connects HD audio codecs to the ICH6 HD audio controller. The HD audio link protocol is synchronous with the controller based on a fixed 24.000 MHz clock (ACZ_BIT_CLK), and is purely isochronous (no flow control), with a 48 KHz framing period. Separate input and output serial digital signals support multiple inbound and outbound streams, as well as fixed command and response channels. Since the HD Audio link is purely an isochronous transport mechanism, all link data transmission occurs within periodic time frames. A frame is defined as a 20.833 ms window of time marked by the falling edge of the Frame Sync marker, identifying the start of each frame. The HD Audio controller is responsible for generating the Frame Sync marker, which is a high-going pulse on the ACZ_SYNC signal, exactly 4 ACZ_BIT_CLK cycles in width.

5.23.1.1 Frame Composition

Basic inbound and outbound frames are made up of three major components: Command/Response field, Stream Packets, and Null fields.

5.23.1.1.1 Command/Response field

This field is used for link and codec management. One of these fields appears exactly once per frame, most significant bit first, and is always the first field in the frame. It is composed of a 40-bit Command Field on each outbound frame and a 36-bit Response Field on each inbound frame.

5.23.1.1.2 Stream Packet

A stream packet is the logical “envelop” in which data is transferred on the link. Since all data is associated with a given stream, each stream packet is delineated with an associated stream tag, which provides the stream ID or stream number of the packet data. The stream packet is made up with zero or more sample blocks each of which has the same length (or sample size) and same time reference (or sample point). A sample block contains one or more samples, the number of which is specified by a control register. As an example, a monaural stream has one sample per sample block; a stereo stream has two samples per sample block; a 5.1multi-channel stream has 6 samples per sample block, and so forth. Figure 5-16. Intel® High Definition Audio Link Protocol Example Command Stream Stream 1 Data Stream 5 Data Tframe_sync= 20.833µs (48kHz) Response Stream Stream ‘b’ DataTag Frame SYNC Tag Next FramePrevious Frame ACZ_BIT_CLK (24.00 MHz) ACZ_SYNC ACZ_SDOUT ACZ_SDIN ACZ_RST#

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 235 Functional Description

5.23.1.1.3 Null field

The remainder of bits contained in each inbound or outbound frame that are not used for Command / Response fields or for Stream Packets, are a null field. A null field is transmitted as logical zeros.

5.23.2 Link Reset

A link reset is signaled on the HD Audio link by assertion of the ACZ_RST# signal. Link reset results in all HD Audio codec and controller interface logic, including registers, being initialized to their default state. Note however, that codecs may contain critical logic associated with power management functions, such as power state information or Caller ID in a modem codec, that may or may not be reset depending on the state of the codec at the time that ACZ_RST# was asserted. The link reset sequence occurs in response to three classes of events:

• Reset occurring on the HD Audio controller’s host bus, including system power-up sequencing.
• Software initiating link reset.
• Certain software-initiated power management sequences. Regardless of the reason for entering the link reset state, the link may be existed only under software control.

5.23.3 Link Power Management

The HD Audio link is designed to support all relevant power management features. In most cases, all power management state changes are driven by software, either through controller control registers, or Command verbs to Codecs. The exception to this is when a codec is put into a low power mode awaiting an external wake up event, such as a ring indication on a modem. When the HD Audio link is commanded to enter a low power state, it enters the link reset state.

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Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 237 Register and Memory Mapping

6 Register and Memory Mapping

The ICH6 contains registers that are located in the processor’s I/O space and memory space and sets of PCI configuration registers that are located in PCI configuration space. This chapter describes the ICH6 I/O and memory maps at the register-set level. Register access is also described. Register-level address maps and Individual register bit descriptions are provided in the following chapters. The following notations and definitions are used in the register/instruction description chapters. RO Read Only. In some cases, If a register is read only, writes to this register location have no effect. However, in other cases, two separate registers are located at the same location where a read accesses one of the registers and a write accesses the other register. See the I/O and memory map tables for details. WO Write Only. In some cases, If a register is write only, reads to this register location have no effect. However, in other cases, two separate registers are located at the same location where a read accesses one of the registers and a write accesses the other register. See the I/O and memory map tables for details. R/W Read/Write. A register with this attribute can be read and written. R/WC Read/Write Clear. A register bit with this attribute can be read and written. However, a write of 1 clears (sets to 0) the corresponding bit and a write of 0 has no effect. R/WO Read/Write-Once. A register bit with this attribute can be written only once after power up. After the first write, the bit becomes read only. R/WLO Read/Write, Lock-Once. A register bit with this attribute can be written to the non-locked value multiple times, but to the locked value only once. After the locked value has been written, the bit becomes read only. Default When ICH6 is reset, it sets its registers to predetermined default states. The default state represents the minimum functionality feature set required to successfully bring up the system. Hence, it does not represent the optimal system configuration. It is the responsibility of the system initialization software to determine configuration, operating parameters, and optional system features that are applicable, and to program the ICH6 registers accordingly. Bold Register bits that are highlighted in bold text indicate that the bit is implemented in the ICH6. Register bits that are not implemented or are hardwired will remain in plain text.

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6.1 PCI Devices and Functions

The ICH6 incorporates a variety of PCI functions as shown in Table 6-1. These functions are divided into six logical devices (B0:D30, B0:D31, B0:D29, B0:D28, B0:D27 and B1:D8). D30 contains the DMI interface-to-PCI bridge and the AC ’97 Audio and Modem controller. D31 contains the PCI-to-LPC bridge, IDE controller, SATA controller, and the SMBus controller. D29 contains the four USB UHCI controllers and one USB EHCI controller. D27 contains the Intel High Definition Audio controller. B1:D8 is the integrated LAN controller. Note: From a software perspective, the integrated LAN controller resides on the ICH6’s external PCI bus. This is typically Bus 1, but may be assigned a different number depending on system configuration. If for some reason, the particular system platform does not want to support any one of the Device Functions, with the exception of D30:F0, they can individually be disabled. The integrated LAN controller will be disabled if no Platform LAN Connect component is detected (See Chapter 5.3). When a function is disabled, it does not appear at all to the software. A disabled function will not respond to any register reads or writes, insuring that these devices appear hidden to software. b NOTES: 1. The LPC controller contains registers that control LPC, Power Management, System Management, GPIO, processor Interface, RTC, Interrupts, Timers, DMA. Table 6-1. PCI Devices and Functions Bus:Device:Function Function Description Bus 0:Device 30:Function 0 PCI-to-PCI Bridge Bus 0:Device 30:Function 2 AC ’97 Audio Controller Bus 0:Device 30:Function 3 AC ’97 Modem Controller Bus 0:Device 31:Function 0 LPC Controller Bus 0:Device 31:Function 1 IDE Controller Bus 0:Device 31:Function 2 SATA Controller Bus 0:Device 31:Function 3 SMBus Controller Bus 0:Device 29:Function 0 USB UHCI Controller 1 Bus 0:Device 29:Function 1 USB UHCI Controller 2 Bus 0:Device 29:Function 2 USB UHCI Controller 3 Bus 0:Device 29:Function 3 USB UHCI Controller 4 Bus 0:Device 29:Function 7 USB 2.0 EHCI Controller Bus 0:Device 28:Function 0 PCI Express* Port 1 Bus 0:Device 28:Function 1 PCI Express Port 2 Bus 0:Device 28:Function 2 PCI Express Port 3 Bus 0:Device 28:Function 3 PCI Express Port 4 Bus 0:Device 27:Function 0 Intel High Definition Audio Controller Bus n:Device 8:Function 0 LAN Controller

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 239 Register and Memory Mapping

6.2 PCI Configuration Map

Each PCI function on the ICH6 has a set of PCI configuration registers. The register address map tables for these register sets are included at the beginning of the chapter for the particular function. Configuration Space registers are accessed through configuration cycles on the PCI bus by the Host bridge using configuration mechanism #1 detailed in the PCI Local Bus Specification, Revision 2.3. Some of the PCI registers contain reserved bits. Software must deal correctly with fields that are reserved. On reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. On writes, software must ensure that the values of reserved bit positions are preserved. That is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back. Note the software does not need to perform read, merge, write operation for the configuration address register. In addition to reserved bits within a register, the configuration space contains reserved locations. Software should not write to reserved PCI configuration locations in the device-specific region (above address offset 3Fh).

6.3 I/O Map

The I/O map is divided into Fixed and Variable address ranges. Fixed ranges cannot be moved, but in some cases can be disabled. Variable ranges can be moved and can also be disabled.

6.3.1 Fixed I/O Address Ranges

Table 6-2 shows the Fixed I/O decode ranges from the processor perspective. Note that for each I/ O range, there may be separate behavior for reads and writes. DMI (Direct Media Interface) cycles that go to target ranges that are marked as “Reserved” will not be decoded by the ICH6, and will be passed to PCI unless the Substractive Decode Policy bit is set (D31:F0:Offset 42h, bit 0). If a PCI master targets one of the fixed I/O target ranges, it will be positively decoded by the ICH6 in medium speed. Address ranges that are not listed or marked “Reserved” are not decoded by the ICH6 (unless assigned to one of the variable ranges).

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Register and Memory Mapping Table 6-2. Fixed I/O Ranges Decoded by Intel® ICH6 (Sheet 1 of 2) I/O Address Read Target Write Target Internal Unit 00h–08h DMA Controller DMA Controller DMA 09h–0Eh RESERVED DMA Controller DMA 0Fh DMA Controller DMA Controller DMA 10h–18h DMA Controller DMA Controller DMA 19h–1Eh RESERVED DMA Controller DMA 1Fh DMA Controller DMA Controller DMA 20h–21h Interrupt Controller Interrupt Controller Interrupt 24h–25h Interrupt Controller Interrupt Controller Interrupt 28h–29h Interrupt Controller Interrupt Controller Interrupt 2Ch–2Dh Interrupt Controller Interrupt Controller Interrupt 2E–2F LPC SIO LPC SIO Forwarded to LPC 30h–31h Interrupt Controller Interrupt Controller Interrupt 34h–35h Interrupt Controller Interrupt Controller Interrupt 38h–39h Interrupt Controller Interrupt Controller Interrupt 3Ch–3Dh Interrupt Controller Interrupt Controller Interrupt 40h–42h Timer/Counter Timer/Counter PIT (8254) 43h RESERVED Timer/Counter PIT 4E–4F LPC SIO LPC SIO Forwarded to LPC 50h–52h Timer/Counter Timer/Counter PIT 53h RESERVED Timer/Counter PIT 60h Microcontroller Microcontroller Forwarded to LPC 61h NMI Controller NMI Controller Processor I/F 62h Microcontroller Microcontroller Forwarded to LPC 64h Microcontroller Microcontroller Forwarded to LPC 66h Microcontroller Microcontroller Forwarded to LPC 70h RESERVED NMI and RTC Controller RTC 71h RTC Controller RTC Controller RTC 72h RTC Controller NMI and RTC Controller RTC 73h RTC Controller RTC Controller RTC 74h RTC Controller NMI and RTC Controller RTC 75h RTC Controller RTC Controller RTC 76h RTC Controller NMI and RTC Controller RTC 77h RTC Controller RTC Controller RTC 80h DMA Controller, or LPC, or PCI DMA Controller and LPC or PCI DMA 81h–83h DMA Controller DMA Controller DMA 84h–86h DMA Controller DMA Controller and LPC or PCI DMA 87h DMA Controller DMA Controller DMA

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 241 Register and Memory Mapping NOTES: 1. A read to this address will subtractively go to PCI, where it will master abort. 2. Only if IDE I/O space is enabled (D31:F1:40 bit 15) and the IDE controller is in legacy mode. Otherwise, the target is PCI. 88h DMA Controller DMA Controller and LPC or PCI DMA 89h–8Bh DMA Controller DMA Controller DMA 8Ch–8Eh DMA Controller DMA Controller and LPC or PCI DMA 08Fh DMA Controller DMA Controller DMA 90h–91h DMA Controller DMA Controller DMA 92h Reset Generator Reset Generator Processor I/F 93h–9Fh DMA Controller DMA Controller DMA A0h–A1h Interrupt Controller Interrupt Controller Interrupt A4h–A5h Interrupt Controller Interrupt Controller Interrupt A8h–A9h Interrupt Controller Interrupt Controller Interrupt ACh–ADh Interrupt Controller Interrupt Controller Interrupt B0h–B1h Interrupt Controller Interrupt Controller Interrupt B2h–B3h Power Management Power Management Power Management B4h–B5h Interrupt Controller Interrupt Controller Interrupt B8h–B9h Interrupt Controller Interrupt Controller Interrupt BCh–BDh Interrupt Controller Interrupt Controller Interrupt C0h–D1h DMA Controller DMA Controller DMA D2h–DDh RESERVED DMA Controller DMA DEh–DFh DMA Controller DMA Controller DMA F0h PCI and Master Abort

1 FERR#/IGNNE# / Interrupt

170h–177h IDE Controller, SATA Controller, or PCI IDE Controller, SATA Controller, or PCI Forwarded to IDE or SATA 1F0h–1F7h IDE Controller, SATA Controller, or PCI 2 IDE Controller, SATA Controller, or PCI Forwarded to IDE or SATA 376h IDE Controller, SATA Controller, or PCI IDE Controller, SATA Controller, or PCI Forwarded to IDE or SATA 3F6h IDE Controller, SATA Controller, or PCI IDE Controller, SATA Controller, or PCI Forwarded IDE or SATA 4D0h–4D1h Interrupt Controller Interrupt Controller Interrupt CF9h Reset Generator Reset Generator Processor I/F Table 6-2. Fixed I/O Ranges Decoded by Intel® ICH6 (Sheet 2 of 2) I/O Address Read Target Write Target Internal Unit

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6.3.2 Variable I/O Decode Ranges

Table 6-3 shows the Variable I/O Decode Ranges. They are set using Base Address Registers (BARs) or other configuration bits in the various PCI configuration spaces. The PNP software (PCI or ACPI) can use their configuration mechanisms to set and adjust these values. Warning: The Variable I/O Ranges should not be set to conflict with the Fixed I/O Ranges. Unpredictable results if the configuration software allows conflicts to occur. The ICH6 does not perform any checks for conflicts. NOTE: 1. Decode range size determined by D31:F0:ADh:bits 5:4 Table 6-3. Variable I/O Decode Ranges Range Name Mappable Size (Bytes) Target ACPI Anywhere in 64 KB I/O Space 64 Power Management IDE Bus Master Anywhere in 64 KB I/O Space 16 IDE Unit Native IDE Command Anywhere in 64 KB I/O Space 8 IDE Unit Native IDE Control Anywhere in 64 KB I/O Space 4 IDE Unit USB UHCI Controller #1 Anywhere in 64 KB I/O Space 32 USB Unit 1 USB UHCI Controller #2 Anywhere in 64 KB I/O Space 32 USB Unit 2 USB UHCI Controller #3 Anywhere in 64 KB I/O Space 32 USB Unit 3 USB UHCI Controller #4 Anywhere in 64 KB I/O Space 32 USB Unit 4 SMBus Anywhere in 64 KB I/O Space 32 SMB Unit AC ’97 Audio Mixer Anywhere in 64 KB I/O Space 256 AC ’97 Unit AC ’97 Audio Bus Master Anywhere in 64 KB I/O Space 64 AC ’97 Unit AC ’97 Modem Mixer Anywhere in 64 KB I/O Space 256 AC ’97 Unit AC ’97 Modem Bus Master Anywhere in 64 KB I/O Space 128 AC ’97 Unit TCO 96 Bytes above ACPI Base 32 TCO Unit GPIO Anywhere in 64 KB I/O Space 64 GPIO Unit Parallel Port 3 Ranges in 64 KB I/O Space 8 LPC Peripheral Serial Port 1 8 Ranges in 64 KB I/O Space 8 LPC Peripheral Serial Port 2 8 Ranges in 64 KB I/O Space 8 LPC Peripheral Floppy Disk Controller 2 Ranges in 64 KB I/O Space 8 LPC Peripheral LAN Anywhere in 64 KB I/O Space 64 LAN Unit LPC Generic 1 Anywhere in 64 KB I/O Space 128 LPC Peripheral LPC Generic 2 Anywhere in 64 KB I/O Space 16, 32, or

641 LPC Peripheral

I/O Trapping Ranges Anywhere in 64 KB I/O Space 1 to 256 Trap on Backbone

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 243 Register and Memory Mapping

6.4 Memory Map

Table 6-4 shows (from the processor perspective) the memory ranges that the ICH6 decodes. Cycles that arrive from DMI that are not directed to any of the internal memory targets that decode directly from DMI will be driven out on PCI unless the Substractive Decode Policy bit is set (D31:F0:Offset 42h, bit 0). The ICH6 may then claim the cycle for the internal LAN controller. PCI cycles generated by external PCI masters will be positively decoded unless they fall in the PCI-to-PCI bridge memory forwarding ranges (those addresses are reserved for PCI peer-to-peer traffic). If the cycle is not in the internal LAN controller’s range, it will be forwarded up to DMI. Software must not attempt locks to the ICH6’s memory-mapped I/O ranges for EHCI and HPET. If attempted, the lock is not honored which means potential deadlock conditions may occur. Table 6-4. Memory Decode Ranges from Processor Perspective (Sheet 1 of 2) Memory Range Target Dependency/Comments 0000 0000h–000D FFFFh 0010 0000h–TOM (Top of Memory) Main Memory TOM registers in Host controller 000E 0000h–000E FFFFh Firmware Hub Bit 6 in Firmware Hub Decode Enable register is set 000F 0000h–000F FFFFh Firmware Hub Bit 7 in Firmware Hub Decode Enable register is set FEC0 0000h–FEC0 0100h I/O APIC inside ICH6 FFC0 0000h–FFC7 FFFFh FF80 0000h–FF87 FFFFh Firmware Hub (or PCI)

3 Bit 8 in Firmware Hub Decode Enable register is set

FFC8 0000h–FFCF FFFFh FF88 0000h–FF8F FFFFh Firmware Hub (or PCI)3 Bit 9 in Firmware Hub Decode Enable register is set FFD0 0000h–FFD7 FFFFh FF90 0000h–FF97 FFFFh Firmware Hub (or PCI)3 Bit 10 in Firmware Hub Decode Enable register is set FFD8 0000h–FFDF FFFFh FF98 0000h–FF9F FFFFh Firmware Hub (or PCI)3 Bit 11 in Firmware Hub Decode Enable register is set FFE0 000h–FFE7 FFFFh FFA0 0000h–FFA7 FFFFh Firmware Hub (or PCI)3 Bit 12 in Firmware Hub Decode Enable register is set FFE8 0000h–FFEF FFFFh FFA8 0000h–FFAF FFFFh Firmware Hub (or PCI)3 Bit 13 in Firmware Hub Decode Enable register is set FFF0 0000h–FFF7 FFFFh FFB0 0000h–FFB7 FFFFh Firmware Hub (or PCI)3 Bit 14 in Firmware Hub Decode Enable register is set FFF8 0000h–FFFF FFFFh FFB8 0000h–FFBF FFFFh Firmware Hub (or PCI)3 Always enabled. The top two, 64 KB blocks of this range can be swapped, as described in Section 7.4.1. FF70 0000h–FF7F FFFFh FF30 0000h–FF3F FFFFh Firmware Hub (or PCI)

3 Bit 3 in Firmware Hub Decode Enable register is set

FF60 0000h–FF6F FFFFh FF20 0000h–FF2F FFFFh Firmware Hub (or PCI)3 Bit 2 in Firmware Hub Decode Enable register is set FF50 0000h–FF5F FFFFh FF10 0000h–FF1F FFFFh Firmware Hub (or PCI)3 Bit 1 in Firmware Hub Decode Enable register is set FF40 0000h–FF4F FFFFh FF00 0000h–FF0F FFFFh Firmware Hub (or PCI)3 Bit 0 in Firmware Hub Decode Enable register is set

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Register and Memory Mapping NOTES: 1. Only LAN cycles can be seen on PCI. 2. Software must not attempt locks to memory mapped I/O ranges for USB EHCI or High Precision Event Timers. If attempted, the lock is not honored, which means potential deadlock conditions may occur. 3. PCI is the target when the Boot BIOS Destination selection bit is low (Chipset Configuration Registers:Offset 3401:bit 3). When PCI selected, the Firmware Hub Decode Enable bits have no effect.

6.4.1 Boot-Block Update Scheme

The ICH6 supports a “top-block swap” mode that has the ICH6 swap the top block in the Firmware Hub (the boot block) with another location. This allows for safe update of the Boot Block (even if a power failure occurs). When the “TOP_SWAP” Enable bit is set, the ICH6 will invert A16 for cycles targeting Firmware Hub space. When this bit is 0, the ICH6 will not invert A16. This bit is automatically set to 0 by RTCRST#, but not by PLTRST#. The scheme is based on the concept that the top block is reserved as the “boot” block, and the block immediately below the top block is reserved for doing boot-block updates. The algorithm is: 1. Software copies the top block to the block immediately below the top 2. Software checks that the copied block is correct. This could be done by performing a checksum calculation. 3. Software sets the TOP_SWAP bit. This will invert A16 for cycles going to the Firmware Hub. processor access to FFFF_0000h through FFFF_FFFFh will be directed to FFFE_0000h through FFFE_FFFFh in the Firmware Hub, and processor accesses to FFFE_0000h through FFFE_FFFF will be directed to FFFF_0000h through FFFF_FFFFh. 4. Software erases the top block 5. Software writes the new top block 6. Software checks the new top block 7. Software clears the TOP_SWAP bit 8. Software sets the Top_Swap Lock-Down bit

4 KB anywhere in 4-GB

Enable via BAR in Device 29:Function 0 (Integrated LAN Controller)

1 KB anywhere in 4-GB

2 Enable via standard PCI mechanism (Device 29,

Function 7)

512 B anywhere in 4-GB

AC ’97 Host Controller (Mixer) Enable via standard PCI mechanism (Device 30, Function 2)

256 B anywhere in 4-GB

AC ’97 Host Controller (Bus Master) Enable via standard PCI mechanism (Device 30, Function 3)

512 B anywhere in 64-bit

Enable via standard PCI mechanism (Device 30, Function 1) FED0 X000h–FED0 X3FFh High Precision Event Timers 2 BIOS determines the “fixed” location which is one of four, 1-KB ranges where X (in the first column) is 0h, 1h, 2h, or 3h. All other PCI None Table 6-4. Memory Decode Ranges from Processor Perspective (Sheet 2 of 2) Memory Range Target Dependency/Comments

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 245 Register and Memory Mapping If a power failure occurs at any point after step 3, the system will be able to boot from the copy of the boot block that is stored in the block below the top. This is because the TOP_SWAP bit is backed in the RTC well. Note: The top-block swap mode may be forced by an external strapping option (See Section 2.22.1). When top-block swap mode is forced in this manner, the TOP_SWAP bit cannot be cleared by software. A re-boot with the strap removed will be required to exit a forced top-block swap mode. Note: Top-block swap mode only affects accesses to the Firmware Hub space, not feature space. Note: The top-block swap mode has no effect on accesses below FFFE_0000h.

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Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 247 Chipset Configuration Registers

7 Chipset Configuration Registers

This section describes all registers and base functionality that is related to chipset configuration and not a specific interface (such as LPC, PCI, or PCI Express*). It contains the root complex register block, which describes the behavior of the upstream internal link. This block is mapped into memory space, using register RCBA of the PCI-to-LPC bridge. Accesses in this space must be limited to 32-(DW) bit quantities. Burst accesses are not allowed.

7.1 Chipset Configuration Registers (Memory Space)

Note: Address locations that are not shown should be treated as Reserved (see Section 6.2 for details). Table 7-1. Chipset Configuration Register Memory Map (Memory Space) (Sheet 1 of 3) Offset Mnemonic Register Name Default Type 0000–0003h VCH Virtual Channel Capability Header 10010002h RO 0004–0007h VCAP1 Virtual Channel Capability #1 00000801h RO 0008–000Bh VCAP2 Virtual Channel Capability #2 00000001h RO 000C–000Dh PVC Port VC Control 0000h R/W, RO 000E–000Fh PVS Port VC Status 0000h RO 0010–0013h V0CAP VC 0 Resource Capability 00000001h RO 0014–0017h V0CTL VC 0 Resource Control 800000FFh R/W, RO 001A–001Bh V0STS VC 0 Resource Status 0000h RO 0100–0103h RCTCL Root Complex Topology Capability List 1A010005h RO 0104–0107h ESD Element Self Description 00000602h R/WO, RO 0110–0113h ULD Upstream Link Descriptor 00000001h R/WO, RO 0118–011Fh ULBA Upstream Link Base Address 0000000000000000h R/WO 0120–0123h RP1D Root Port 1 Descriptor 01xx0002h R/WO, RO 0128–012Fh RP1BA Root Port 1 Base Address 00000000000E0000h RO 0130–0133h RP2D Root Port 2 Descriptor 02xx0002h R/WO, RO 0138–013Fh RP2BA Root Port 2 Base Address 00000000000E1000h RO 0140–0143h RP3D Root Port 3 Descriptor 03xx0002h R/WO, RO 0148–014Fh RP3BA Root Port 3 Base Address 00000000000E2000h RO 0150–0153h RP4D Root Port 4 Descriptor 04xx0002h R/WO, RO 0158–015Fh RP4BA Root Port 4 Base Address 00000000000E3000h RO 0160–0163h HDD Intel High Definition Audio Descriptor 05xx0002h R/WO, RO 0168–016Fh HDBA Intel High Definition Audio Base Address 00000000000D8000h RO 01A0–01A3h ILCL Internal Link Capability List 00010006h RO

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Chipset Configuration Registers 01A4–01A7h LCAP Link Capabilities 00012441h RO, R/WO 01A8–01A9h LCTL Link Control 0000h R/W 01AA–01ABh LSTS Link Status 0041h RO 0200–0203h CSIR5 Chipset Initialization Register 5 01100220h R/W 020C–020Fh CSIR6 Chipset Initialization Register 6 00201004h R/W 0220–0223h BCR Backbone Configuration Register 00008000h R/W 0224–0227h RPC Root Port Configuration 0000000xh R/W, RO 1D40–1D43h CSIR7 Chipset Initialization Register 7 00000000 R/W 1E00–1E03h TRSR Trap Status Register 00h R/WC, RO 1E10–1E17h TRCR Trapped Cycle Register 0000000000000000h RO 1E18–1E1Fh TWDR Trapped Write Data Register 0000000000000000h RO 1E80–1E87h IOTR0 I/O Trap Register 0 0000000000000000h R/W, RO 1E88–1E8Fh IOTR1 I/O Trap Register 1 0000000000000000h R/W, RO 1E90–1E97h IOTR2 I/O Trap Register 2 0000000000000000h R/W, RO 1E98–1E9Fh IOTR3 I/O Trap Register 3 0000000000000000h R/W, RO 2010-2013h DMC DMI Misc. Control (Mobile Only) N/A R/W 2020–2023h CSCR1 Chipset Configuration Register 1 00C4B0DBh R/W 2027h CSCR2 Chipset Configuration Register 2 0Ah R/W 2078-207Bh PLLMC PLL Misc. Control (Mobile Only) N/A R/W 3000–3001h TCTL TCO Control 00h R/W 3100–3103h D31IP Device 31 Interrupt Pin 00042210h R/W, RO 3104–3107h D30IP Device 30 Interrupt Pin 00002100h R/W, RO 3108–310Bh D29IP Device 29 Interrupt Pin 10004321h R/W 310C–310Fh D28IP Device 28 Interrupt Pin 00004321h R/W 3110–3113h D27IP Device 27 Interrupt Pin 00000001h R/W 3140–3141h D31IR Device 31 Interrupt Route 3210h R/W 3142–3143h D30IR Device 30 Interrupt Route 3210h R/W 3144–3145h D29IR Device 29 Interrupt Route 3210h R/W 3146–3147h D28IR Device 28 Interrupt Route 3210h R/W 3148–3149h D27IR Device 27 Interrupt Route 3210h R/W 31FF–31FFh OIC Other Interrupt Control 00h R/W 3400–3403h RC RTC Configuration 00000000h R/W, R/WLO 3404–3407h HPTC High Precision Timer Configuration 00000000h R/W 3410–3413h GCS General Control and Status 0000000xh R/W, R/WLO 3414–3414h BUC Backed Up Control 0000001xb (Mobile) 0000000xb (Desktop) R/W 3418–341Bh FD Function Disable See bit description R/W, RO Table 7-1. Chipset Configuration Register Memory Map (Memory Space) (Sheet 2 of 3) Offset Mnemonic Register Name Default Type

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 249 Chipset Configuration Registers

7.1.1 VCH—Virtual Channel Capability Header Register

Offset Address: 0000–0003h Attribute: RO Default Value: 10010002h Size: 32-bit

7.1.2 VCAP1—Virtual Channel Capability #1 Register

Offset Address: 0004–0007h Attribute: RO Default Value: 00000801h Size: 32-bit 341C–341Fh CG Clock Gating 00000000h R/W, RO 3E08–3E09h CSIR1 Chipset Initialization Register 1 0000h R/W 3E0Eh CSIR3 Chipset Initialization Register 4 00h R/W 3E48–3E49h CSIR2 Chipset Initialization Register 2 0000h R/W 3E4Eh CSIR4 Chipset Initialization Register 4 00h R/W Table 7-1. Chipset Configuration Register Memory Map (Memory Space) (Sheet 3 of 3) Offset Mnemonic Register Name Default Type Bit Description 31:20 Next Capability Offset (NCO) — RO. This field indicates the next item in the list. 19:16 Capability Version (CV) — RO . This field indicates support as a version 1 capability structure. 15:0 Capability ID (CID) — RO. This field indicates this is the Virtual Channel capability item. Bit Description 31:12 Reserved 11:10 Port Arbitration Table Entry Size (PATS) — RO. This field indicates the size of the port arbitration table is 4 bits (to allow up to 8 ports). 9:8 Reference Clock (RC) — RO. Fixed at 100 ns.

7 Reserved

6:4 Low Priority Extended VC Count (LPEVC) — RO. This field indicates that there are no additional VCs of low priority with extended capabilities. 3:0 Reserved

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7.1.3 VCAP2—Virtual Channel Capability #2 Register

Offset Address: 0008–000Bh Attribute: RO Default Value: 00000001h Size: 32-bit

7.1.4 PVC—Port Virtual Ch annel Control Register

Offset Address: 000C–000Dh Attribute: R/W, RO Default Value: 0000h Size: 16-bit

7.1.5 PVS—Port Virtual Channel Status Register

Offset Address: 000E–000Fh Attribute: RO Default Value: 0000h Size: 16-bit Bit Description 31:24 VC Arbitration Table Offset (ATO) — RO. This bi t indicates that no table is present for VC arbitration since it is fixed. 23:0 Reserved Bit Description 15:04 Reserved 3:1 VC Arbitration Select (AS) — RO. This bit indi cates which VC should be programmed in the VC arbitration table. The root complex takes no action on the setting of this field since there is no arbitration table. Load VC Arbitration Table (LAT) — RO. This bit indicates that the table programmed should be loaded into the VC arbitration table. This bit is defined as read/write with always returning 0 on reads. Bit Description 15:01 Reserved VC Arbitration Table Status (VAS) — RO. This bit indicates the coherency status of the VC Arbitration table when it is being updated. This field is always 0 in the root complex since there is no VC arbitration table.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 251 Chipset Configuration Registers

7.1.6 V0CAP—Virtual Channel 0 Resource Capability Register

Offset Address: 0010–0013h Attribute: RO Default Value: 00000001h Size: 32-bit

7.1.7 V0CTL—Virtual Channel 0 Resource Control Register

Offset Address: 0014–0017h Attribute: R/W, RO Default Value: 800000FFh Size: 32-bit Bit Description 31:24 Port Arbitration Table Offset (AT) — RO. This VC implements no port arbitration table since the arbitration is fixed.

23 Reserved

22:16 Maximum Time Slots (MTS) — RO. This VC implem ents fixed arbitration, and therefore this field is not used. 15 Reject Snoop Transactions (RTS) — RO. This VC must be able to take snoopable transactions. 14 Advanced Packet Switching (APS) — RO. This VC is capable of all transactions, not just advanced packet switching transactions. 13:8 Reserved 7:0 Port Arbitration Capability (PAC) — RO. This field indicates that this VC uses fixed port arbitration. Bit Description 31 Virtual Channel Enable (EN) — RO. Always set to 1. VC0 is always enabled and cannot be disabled. 30:27 Reserved 26:24 Virtual Channel Identifier (ID) — RO. This field indicates the ID to use for this virtual channel. 23:20 Reserved 19:17 Port Arbitration Select (PAS) — R/W. Indicates which port tabl e is being programmed. The root complex takes no action on this setting since the arbitration is fixed and there is no arbitration table. 16 Load Port Arbitration Table (LAT) — RO. The root complex does not implement an arbitration table for this virtual channel. 15:8 Reserved 7:1 Transaction Class / Virtual Channel Map (TVM) — R/W. This field indicates which transaction classes are mapped to this virtual channel. When a bit is set, this transaction class is mapped to the virtual channel.

0 Reserved

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7.1.8 V0STS—Virtual Channel 0 Resource Status Register

Offset Address: 001A–001Bh Attribute: RO Default Value: 0000h Size: 16-bit

7.1.9 RCTCL—Root Complex Topolo gy Capabilities List Register

Offset Address: 0100–0103h Attribute: RO Default Value: 1A010005h Size: 32-bit

7.1.10 ESD—Element Self Description Register

Offset Address: 0104–0 107h Attribute: R/WO, RO Default Value: 00000602h Size: 32-bit Bit Description 15:02 Reserved VC Negotiation Pending (NP) — RO. 1 = Virtual channel is still being negotiated with ingress ports. 0 Port Arbitration Tables Status (ATS) — RO. There is no port arbitration table for this VC, so this bit is reserved at 0. Bit Description 31:20 Next Capability (NEXT) — RO. This fi eld indicates the next item in the list. 19:16 Capability Version (CV) — RO . This field indicates the version of the capability structure. 15:0 Capability ID (CID) — RO. This fi eld indicates this is a PCI Express* link capability section of an RCRB. Bit Description 31:24 Port Number (PN) — RO. A value of 0 to indicate the egress port for the Intel ® ICH6. 23:16 Component ID (CID) — R/WO. This field indicates the co mponent ID assigned to this element by software. This is written once by platform BIOS and is locked until a platform reset. 15:8 Number of Link Entries (NLE) — RO. This fiel d indicates that one link entry (corresponding to DMI), 4 root port entries (for the downstream ports), and the Intel High Definition Audio device are described by this RCRB. 7:4 Reserved 3:0 Element Type (ET) — RO. This field indicates t hat the element type is a root complex internal link.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 253 Chipset Configuration Registers

7.1.11 ULD—Upstream Link Descriptor Register

Offset Address: 0110–0113h Attribute: R/WO, RO Default Value: 00000001h Size: 32-bit

7.1.12 ULBA—Upstream Link Base Address Register

Offset Address: 0118–011Fh Attribute: R/WO Default Value: 0000000000000000h Size: 64-bit

7.1.13 RP1D—Root Port 1 Descriptor Register

Offset Address: 0120–0123h Attribute: R/WO, RO Default Value: 01xx0002h Size: 32-bit Bit Description 31:24 Target Port Number (PN) — R/WO. This field is programmed by platform BIOS to match the port number of the (G)MCH RCRB that is attached to this RCRB. 23:16 Target Component ID (TCID) — R/WO. This field is programmed by platform BIOS to match the component ID of the (G)MCH RCRB that is attached to this RCRB. 15:2 Reserved 1 Link Type (LT) — RO. This bit indicates that t he link points to the (G)MCH RCRB. 0 Link Valid (LV) — RO. This bit indicates th at the link entry is valid. Bit Description 63:32 Base Address Upper (BAU) — R/WO. This field is programmed by platform BIOS to match the upper 32-bits of base address of the (G)MCH RCRB that is attached to this RCRB. 31:0 Base Address Lower (BAL) — R/WO. This field is programmed by platform BIOS to match the lower 32-bits of base address of the (G)MCH RCRB that is attached to this RCRB. Bit Description 31:24 Target Port Number (PN) — RO. This field indicates the target port number is 1h (root port #1). 23:16 Target Component ID (TCID) — R/WO. This field returns the value of the ESD.CID (offset 0104h, bits 23:16) field programmed by platform BIOS, since the root port is in the same component as the RCRB. 15:2 Reserved 1 Link Type (LT) — RO. This bit indicates that the link points to a root port. 0 Link Valid (LV) — RO. When FD.PE1D (offset 3418h, bit 16) is set, this link is not valid (returns 0). When FD.PE1D is cleared, this link is valid (returns 1).

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7.1.14 RP1BA—Root Port 1 Base Address Register

Offset Address: 0128–012Fh Attribute: RO Default Value: 00000000000E0000h Size: 64-bit

7.1.15 RP2D—Root Port 2 Descriptor Register

Offset Address: 0130–0 133h Attribute: R/WO, RO Default Value: 02xx0002h Size: 32-bit

7.1.16 RP2BA—Root Port 2 Base Address Register

Offset Address: 0138–013Fh Attribute: RO Default Value: 00000000000E1000h Size: 64-bit Bit Description 63:32 Reserved 31:28 Reserved 27:20 Bus Number (BN) — RO. This field indicates the root port is on bus #0. 19:15 Device Number (DN) — RO. This field indicates the root port is on device #28. 14:12 Function Number (FN) — RO. This field indicates the root port is on function #0. 11:0 Reserved Bit Description 31:24 Target Port Number (PN) — RO. This field indicates the target port number is 2h (root port #2). 23:16 Target Component ID (TCID) — R/WO. This field returns the value of the ESD.CID (offset 0104h, bits 23:16) field programmed by platform BIOS, since the root port is in the same component as the RCRB. 15:2 Reserved 1 Link Type (LT) — RO. This bit indicate s that the link points to a root port. Link Valid (LV) — RO. When RPC.PC (offset 0224h, bits 1: 0) is ‘01’, ‘10’, or ‘11’, or FD.PE2D (offset 3418h, bit 17) is set, the link for this root port is not valid (return 0). When RPC.PC is ‘00’ and FD.PE2D is cleared, the link for this root port is valid (return 1). Bit Description 63:32 Reserved 31:28 Reserved 27:20 Bus Number (BN) — RO. This field indicates the root port is on bus #0. 19:15 Device Number (DN) — RO. This field indicates the root port is on device #28. 14:12 Function Number (FN) — RO. This field indicates the root port is on function #1. 11:0 Reserved

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 255 Chipset Configuration Registers

7.1.17 RP3D—Root Port 3 Descriptor Register

Offset Address: 0140–0143h Attribute: R/WO, RO Default Value: 03xx0002h Size: 32-bit

7.1.18 RP3BA—Root Port 3 Base Address Register

Offset Address: 0148–014Fh Attribute: RO Default Value: 00000000000E2000h Size: 64-bit

7.1.19 RP4D—Root Port 4 Descriptor Register

Offset Address: 0150–0153h Attribute: R/WO, RO Default Value: 04xx0002h Size: 32-bit Bit Description 31:24 Target Port Number (PN) — RO. This field indicates the target port number is 3h (root port #3). 23:16 Target Component ID (TCID) — R/WO. This field returns the value of the ESD.CID (offset 0104h, bits 23:16) field programmed by platform BIOS, since the root port is in the same component as the RCRB. 15:2 Reserved 1 Link Type (LT) — RO. This bit indicates that the link points to a root port. Link Valid (LV) — RO. When RPC.PC (offset 0224h, bits 1: 0) is ‘11’, or FD.PE3D (offset 3418h, bit 18) is set, the link for this root port is not valid (return 0). When RPC.PC is ‘00’, ‘01’, or “10’, and FD.PE3D is cleared, the link for this root port is valid (return 1). Bit Description 63:32 Reserved 31:28 Reserved 27:20 Bus Number (BN) — RO. This field indicates the root port is on bus #0. 19:15 Device Number (DN) — RO. This fiel d indicates the root port is on device #28. 14:12 Function Number (FN) — RO. This field indicates the root port is on function #2. 11:0 Reserved Bit Description 31:24 Target Port Number (PN) — RO. This field indicates the target port number is 4h (root port #4). 23:16 Target Component ID (TCID) — R/WO. This field returns the value of the ESD.CID (offset 0104h, bits 23:16) field programmed by platform BIOS, since the root port is in the same component as the RCRB. 15:2 Reserved 1 Link Type (LT) — RO. This bit indicates that the link points to a root port. Link Valid (LV) — RO. When RPC.PC (offset 0224h, bits 1:0) is ‘10’ or ‘11’, or FD.PE4D (offset 3418h, bit 19) is set, the link for this root port is not valid (return 0). When RPC.PC is ‘00’ or ‘01’ and FD.PE4D is cleared, the link for this root port is valid (return 1).

256 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

Chipset Configuration Registers

7.1.20 RP4BA—Root Port 4 Base Address Register

Offset Address: 0158–015Fh Attribute: RO Default Value: 00000000000E3000h Size: 64-bit

7.1.21 HDD—Intel ® High Definition Audio Descriptor Register

Offset Address: 0160–0 163h Attribute: R/WO, RO Default Value: 05xx0002h Size: 32-bit

7.1.22 HDBA—Intel ® High Definition Audio Base Address Register

Offset Address: 0168–016Fh Attribute: RO Default Value: 00000000000D8000h Size: 64-bit Bit Description 63:32 Reserved 31:28 Reserved 27:20 Bus Number (BN) — RO. This field indicates the root port is on bus #0. 19:15 Device Number (DN) — RO. This field indicates the root port is on device #28. 14:12 Function Number (FN) — RO. This field indicates the root port is on function #3. 11:0 Reserved Bit Description 31:24 Target Port Number (PN) — RO. This field indicates the target port number is 5h (Intel High Definition Audio). 23:16 Target Component ID (TCID) — R/WO. This field returns the value of the ESD.CID (offset 0104h, bits 23:16) field programmed by platform BIOS, since the root port is in the same component as the RCRB. 15:2 Reserved 1 Link Type (LT) — RO. This bit indicate s that the link points to a root port. Link Valid (LV) — RO. When FD.ZD (offset 3418h, bit 4) is set, the link to Intel High Definition Audio is not valid (return 0). When FD.ZD is cleared, the link to Intel High Definition Audio is valid (return 1). Bit Description 63:32 Reserved 31:28 Reserved 27:20 Bus Number (BN) — RO. This field indicates the root port is on bus #0. 19:15 Device Number (DN) — RO. This field indicates the root port is on device #27. 14:12 Function Number (FN) — RO. This field indicates the root port is on function #0. 11:0 Reserved

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 257 Chipset Configuration Registers

7.1.23 ILCL—Internal Link Capabilities List Register

Offset Address: 01A0–01A3h Attribute: RO Default Value: 00010006h Size: 32-bit

7.1.24 LCAP—Link Capabilities Register

Offset Address: 01A4–01A7h Attribute: RO, R/WO Default Value: 00012441h Size: 32-bit

7.1.25 LCTL—Link Control Register

Offset Address: 01A8–01A9h Attribute: R/W Default Value: 0000h Size: 16-bit Bit Description 31:20 Next Capability Offset (NEXT) — RO. This fiel d indicates this is the last item in the list. 19:16 Capability Version (CV) — RO. This field i ndicates the version of the capability structure. 15:0 Capability ID (CID) — RO. This field indicates this is capability for DMI. Bit Description 31:18 Reserved 17:15 L1 Exit Latency (EL1) — L1 not supported on DMI. 14:12 L0s Exit Latency (EL0) — R/WO. This field indicate s that exit latency is 128 ns to less than 256 ns. 11:10 Active State Link PM Support (APMS) — R/WO. This field indicates that L0s is supported on DMI. 9:4 Maximum Link Width (MLW) — This field indicates the maximum link width is 4 ports. 3:0 Maximum Link Speed (MLS) — This field indicates the link speed is 2.5 Gb/s. Bit Description 15:8 Reserved 7 Extended Synch (ES) — R/W. When set, forces extended transmission of FTS ordered sets when exiting L0s prior to entering L0. 6:2 Reserved 1:0 Active State Link PM Control (APMC) — R/W. This field indicate s whether DMI should enter L0s. 00 = Disabled 01 = L0s entry enabled 10 = Reserved 11 = Reserved

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Chipset Configuration Registers

7.1.26 LSTS—Link Status Register

Offset Address: 01AA–01ABh Attribute: RO Default Value: 0041h Size: 16-bit

7.1.27 CSIR5—Chipset Init ialization Register 5

Offset Address: 0200–0203h Attribute: R/W Default Value: 01100220h Size: 32-bit

7.1.28 CSIR6—Chipset Init ialization Register 6

Offset Address: 020C–020Fh Attribute: R/W Default Value: 00201004h Size: 32-bit Bit Description 15:10 Reserved 9:4 Negotiated Link Width (NLW) — RO. Negotiated link width is x4 (000100b). ICH6-M may also indicate x2 (000010b), depending on (G)MCH configuration. 3:0 Link Speed (LS) — RO. Link is 2.5 Gb/s. Bit Description 31:14 Reserved 13:8 Chipset Initialization Register Bits[13:8] — R/W. BIOS programs this field to 100000b. 7:6 Reserved 5:0 Chipset Initialization Register Bits[5:0] — R/W. BIOS programs this field to 001000b. Bit Description 31:22 Reserved 21:16 Chipset Initialization Register Bits[21:16] — R/W. BIOS programs this field to 000100b. 15:14 Reserved 13:8 Chipset Initialization Register Bits[13:8] — R/W. BIOS programs this field to 000010b. 7:6 Reserved 5:0 Chipset Initialization Register Bits[5:0] — R/W. BIOS programs this field to 000001b.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 259 Chipset Configuration Registers

7.1.29 BCR—Backbone Co nfiguration Register

Offset Address: 0220–0223h Attribute: R/W Default Value: 000008000h Size: 32-bit

7.1.30 RPC—Root Port Configuration Register

Offset Address: 0224–0227h Attribute: R/W, RO Default Value: 0000000xh Size: 32-bit Bit Description 31:8 Reserved 7:5 Backbone Configuration Register Bits[8:5] — R/W. BIOS sets this field to 111b.

4 Reserved

3:0 Backbone Configuration Register Bits[3:0] — R/W. BIOS sets this field to 0101b. Bit Description 31:8 Reserved High Priority Port Enable (HPE) — R/W. 0 = The high priority path is not enabled. 1 = The port selected by the HPP field in this r egister is enabled for high priority. It will be arbitrated above all other VC0 (including integrated VC0) devices.

6 Reserved

5:4 High Priority Port (HPP) — R/W. This field controls which port is enabled for high priority when the HPE bit in this register is set. 11 = Port 4 10 = Port 3 01 = Port 2 00 = Port 1 3:2 Reserved 1:0 Port Configuration (PC) — RO. This field controls how the PCI bridges are organized in various modes of operation. For the following mappings, if a port is not shown, it is considered a x1 port with no connection. These bits represent the strap values of ACZ_SDOUT (bit 1) and ACZ_SYNC (bit 0) when TP[3] is not pulled low at the rising edge of PWROK. 11 = 1 x4, Port 1 (x4) (Enterprise applications only) 10 = Reserved 01 = Reserved 00 = 4 x1s, Port 1 (x1), Port 2 (x1), Port 3 (x1), Port 4 (x1) These bits live in the resume well and are only reset by RSMRST#.

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7.1.31 CSIR7—Chipset Init ialization Register 7

Offset Address: 1D40–1D43h Attribute: R/W Default Value: 00000000h Size: 32-bit

7.1.32 TRSR—Trap Status Register

Offset Address: 1E00–1E03h Attribute: R/WC, RO Default Value: 00000000h Size: 32-bit

7.1.33 TRCR—Trapped Cycle Register

Offset Address: 1E10–1E17h Attribute: RO Default Value: 0000000000000000h Size: 64-bit This register saves information about the I/O Cycle that was trapped and generated the SMI# for software to read. Bit Description 31:1 Reserved 0 Chipset Initialization Register 7 Bit[0] — R/W. BIOS sets this bit to 1. Bit Description 31:4 Reserved 3:0 Cycle Trap SMI# Status (CTSS) — R/WC. These bits are set by hardware when the corresponding Cycle Trap register is enabled and a matching cycle is received (and trapped). These bits are OR’ed together to create a single status bit in the Power Management register space. Note that the SMI# and trapping must be enabled in order to set these bits. These bits are set before the completion is generated for the trapped cycle, thereby guaranteeing that the processor can enter the SMI# handler when the instruction completes. Each status bit is cleared by writing a 1 to the corresponding bit location in this register. Bit Description 63:25 Reserved Read/Write# (RWI) — RO. 0 = Trapped cycle was a write cycle. 1 = Trapped cycle was a read cycle. 23:20 Reserved 19:16 Active-high Byte Enables (AHBE) — RO. This is the DWord-al igned byte enables associated with the trapped cycle. A 1 in any bit location indicates that the corresponding byte is enabled in the cycle. 15:2 Trapped I/O Address (TIOA) — RO. This is the DWord-aligned address of the trapped cycle. 1:0 Reserved

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 261 Chipset Configuration Registers

7.1.34 TWDR—Trapped Write Data Register

Offset Address: 1E18–1E1Fh Attribute: RO Default Value: 0000000000000000h Size: 64-bit This register saves the data from I/O write cycles that are trapped for software to read.

7.1.35 IOTRn—I/O Trap Register(0:3)

Offset Address: 1E80–1E87h Re gister 0 Attribute: R/W, RO 1E88–1E8Fh Register 1 1E90–1E97h Register 2 1E98–1E9Fh Register 3 Default Value: 0000000000000000h Size: 64-bit These registers are used to specify the set of I/O cycles to be trapped and to enable this functionality. Bit Description 63:32 Reserved 31:0 Trapped I/O Data (TIOD) — RO. DWord of I/O write data. Th is field is undefined after trapping a read cycle. Bit Description 63:50 Reserved Read/Write Mask (RWM) — R/W. 0 = The cycle must match the type specified in bit 48. 1 = Trapping logic will operate on both read and write cycles. Read/Write# (RWIO) — R/W. 0 = Write 1 = Read NOTE: The value in this field does not matter if bit 49 is set. 47:40 Reserved 39:36 Byte Enable Mask (BEM) — R/W. A 1 in any bit position indicates that any value in the corresponding byte enable bit in a received cycle will be treated as a match. The corresponding bit in the Byte Enables field, below, is ignored. 35:32 Byte Enables (TBE) — R/W. Active-high DWord-aligned byte enables. 31:24 Reserved 23:18 Address[7:2] Mask (ADMA) — R/W. A 1 in any bit position indicates that any value in the corresponding address bit in a received cycle will be treated as a match. The corresponding bit in the Address field, below, is ignored. The mask is only provided for the lower 6 bits of the DWord address, allowing for traps on address ranges up to 256 bytes in size. 17:16 Reserved 15:2 I/O Address[15:2] (IOAD) — R/W. DWord-aligned address

1 Reserved

Trap and SMI# Enable (TRSE) — R/W. 0 = Trapping and SMI# logic disabled. 1 = The trapping logic specified in this register is enabled.

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Chipset Configuration Registers

7.1.36 DMC—DMI Miscellaneous Co ntrol Register (Mobile Only)

Offset Address: 2010–2013h Attribute: R/W Default Value: N/A Size: 32-bit

7.1.37 CSCR1—Chipset Configuration Register 1

Offset Address: 2020–2023h Attribute: R/W Default Value: 00C4B0DBh Size: 32-bits

7.1.38 CSCR2—Chipset Configuration Register 2

Offset Address: 2027h Attribute: R/W Default Value: 0Ah Size: 8-bits Bit Description 31:2 Reserved DMI Misc. Control Field 1 — R/W. BIOS shall always program this field as per the BIOS Specification. 0 = Disable DMI Power Savings. 1 = Enable DMI Power Savings. 0R e s e r v e d Bit Description 31:28 Chipset Configuration Register 1 Bits[31:28] — R/W. Refer to the ICH6 BIOS Specification for the programming of this field. 27:9 Reserved 8:6 Chipset Configuration Register 1 Bits[8:6] — R/W. BIOS programs this field to 001b. 5:0 Reserved Bit Description 7:0 Chipset Configuration Register 2 Bits[7:0] — R/W. BIOS programs this field to 0Dh.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 263 Chipset Configuration Registers

7.1.39 PLLMC—PLL Miscellaneous Co ntrol Register (Mobile Only)

Offset Address: 2078–207Bh Attribute: R/W Default Value: N/A Size: 32-bit

7.1.40 TCTL—TCO Conf iguration Register

Offset Address: 3000–3000h Attribute: R/W Default Value: 00h Size: 8-bit Bit Description 31:25 Reserved PLL Misc. Control Field 2 — R/W. BIOS shall always program this field as per the BIOS Specification. 0 = Disable Clock Gating. 1 = Enable Clock Gating.. PLL Misc. Control Field 1 — R/W. BIOS shall always program this field as per the BIOS Specification. 0 = Disable Clock Gating. 1 = Enable Clock Gating.. 21:0 Reserved Bit Description TCO IRQ Enable (IE) — R/W. 0 = TCO IRQ is disabled. 1 = TCO IRQ is enabled, as selected by the TCO_IRQ_SEL field. 6:3 Reserved 2:0 TCO IRQ Select (IS) — R/W. This field specifies on whic h IRQ the TCO will internally appear. If not using the APIC, the TCO interrupt must be routed to IRQ9:11, and that interrupt is not sharable with the SERIRQ stream, but is shareable with other PCI interrupts. If using the APIC, the TCO interrupt can also be mapped to IRQ20:23, and can be shared with other interrupt. 000 = IRQ 9 001 = IRQ 10 010 = IRQ 11 011 = Reserved 100 = IRQ 20 (only if APIC enabled) 101 = IRQ 21 (only if APIC enabled) 110 = IRQ 22 (only if APIC enabled) 111 = IRQ 23 (only if APIC enabled) When setting the these bits, the IE bit should be cleared to prevent glitching. When the interrupt is mapped to APIC interrupts 9, 10 or 11, the APIC should be programmed for active-high reception. When the interrupt is mapped to APIC interrupts 20 through 23, the APIC should be programmed for active-low reception.

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Chipset Configuration Registers

7.1.41 D31IP—Device 31 Interrupt Pin Register

Offset Address: 3100–3 103h Attribute: R/W, RO Default Value: 00042210h Size: 32-bit Bit Description 31:16 Reserved 15:12 SM Bus Pin (SMIP) — R/W. This field indicates which pi n the SMBus controller drives as its interrupt. 0h = No interrupt 1h = INTA# 2h = INTB# (Default) 3h = INTC# 4h = INTD# 5h–7h = Reserved 11:8 SATA Pin (SIP) — R/W. This field indicates which pin t he SATA controller drives as its interrupt. 0h = No interrupt 1h = INTA# 2h = INTB# (Default) 3h = INTC# 4h = INTD# 5h–7h = Reserved 7:4 PATA Pin (SMIP) — R/W. This field indicates which pin t he PATA controller drives as its interrupt. 0h = No interrupt 1h = INTA# (Default) 2h = INTB# 3h = INTC# 4h = INTD# 5h–7h = Reserved 3:0 PCI Bridge Pin (PIP) — RO. Currently, the PCI br idge does not generate an interrupt, so this field is read-only and 0.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 265 Chipset Configuration Registers

7.1.42 D30IP—Device 30 Interrupt Pin Register

Offset Address: 3104–3107h Attribute: R/W, RO Default Value: 00002100h Size: 32-bit Bit Description 31:16 Reserved 15:12 AC ‘97 Modem Pin (AMIP) — R/W. This field indicates which pin the AC ‘97 Modem controller drives as its interrupt. 0h = No interrupt 1h = INTA# 2h = INTB# (Default) 3h = INTC# 4h = INTD# 5h–7h = Reserved 11:8 AC ‘97 Audio Pin (AAIP) — R/W. This field indi cates which pin the AC ‘97 audio controller drives as its interrupt. 0h = No interrupt 1h = INTA# (Default) 2h = INTB# 3h = INTC# 4h = INTD# 5h–7h = Reserved 7:4 Reserved 3:0 LPC Bridge Pin (LIP) — RO. Currently, the LPC bridge does not generate an interrupt, so this field is read-only and 0.

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7.1.43 D29IP—Device 29 Interrupt Pin Register

Offset Address: 3108–310Bh Attribute: R/W Default Value: 10004321h Size: 32-bit Bit Description 31:28 EHCI Pin (EIP) — R/W. This field indicate s which pin the EHCI controller drives as its interrupt. 0h = No interrupt 1h = INTA# (Default) 2h = INTB# 3h = INTC# 4h = INTD# 5h–7h = Reserved 27:16 Reserved 15:12 UHCI #3 Pin (U3P) — R/W. This field indica tes which pin the UHCI controller #3 (ports 6 and 7) drives as its interrupt. 0h = No interrupt 1h = INTA# 2h = INTB# 3h = INTC# 4h = INTD# (Default) 5h–7h = Reserved 11:8 UHCI #2 Pin (U2P) — R/W. This field indica tes which pin the UHCI controller #2 (ports 4 and 5) drives as its interrupt. 0h = No interrupt 1h = INTA# 2h = INTB# 3h = INTC# (Default) 4h = INTD# 5h–7h = Reserved 7:4 UHCI #1 Pin (U1P) — R/W. This field indica tes which pin the UHCI controller #1 (ports 2 and 3) drives as its interrupt. 0h = No interrupt 1h = INTA# 2h = INTB# (Default) 3h = INTC# 4h = INTD# 5h–7h = Reserved 3:0 UHCI #0 Pin (U0P) — R/W. This field indica tes which pin the UHCI controller #0 (ports 0 and 1) drives as its interrupt. 0h = No interrupt 1h = INTA# (Default) 2h = INTB# 3h = INTC# 4h = INTD# 5h–7h = Reserved

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 267 Chipset Configuration Registers

7.1.44 D28IP—Device 28 Interrupt Pin Register

Offset Address: 310C–310Fh Attribute: R/W Default Value: 00004321h Size: 32-bit

7.1.45 D27IP—Device 27 Interrupt Pin Register

Offset Address: 3110–3113h Attribute: R/W Default Value: 00000001h Size: 32-bit Bit Description 31:16 Reserved 15:12 PCI Express #4 Pin (P4IP) — R/W. This field indicates which pin the PCI Express* port #4 drives as its interrupt. 0h = No interrupt 1h = INTA# 2h = INTB# 3h = INTC# 4h = INTD# (Default) 5h–7h = Reserved 11:8 PCI Express #3 Pin (P3IP) — R/W. This field indicates whic h pin the PCI Express port #3 drives as its interrupt. 0h = No interrupt 1h = INTA# 2h = INTB# 3h = INTC# (Default) 4h = INTD# 5h–7h = Reserved 7:4 PCI Express #2 Pin (P2IP) — R/W. This field indicates whic h pin the PCI Express port #2 drives as its interrupt. 0h = No interrupt 1h = INTA# 2h = INTB# (Default) 3h = INTC# 4h = INTD# 5h–7h = Reserved 3:0 PCI Express #1 Pin (P1IP) — R/W. This field indicates whic h pin the PCI Express port #1 drives as its interrupt. 0h = No interrupt 1h = INTA# (Default) 2h = INTB# 3h = INTC# 4h = INTD# 5h–7h = Reserved Bit Description 31:4 Reserved 3:0 Intel High Definition Audio Pin (ZIP) — R/W. This field indicates which pin the Intel High Definition Audio controller drives as its interrupt. 0h = No interrupt 1h = INTA# (Default) 2h = INTB# 3h = INTC# 4h = INTD# 5h–7h = Reserved

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Chipset Configuration Registers

7.1.46 D31IR—Device 31 Interrupt Route Register

Offset Address: 3140–3141h Attribute: R/W Default Value: 3210h Size: 16-bit Bit Description

15 Reserved

14:12 Interrupt D Pin Route (IDR) — R/W. This field indicates which physical pin on the Intel ® ICH6 is connected to the INTD# pin reported for device 31 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# (Default) 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH#

11 Reserved

10:8 Interrupt C Pin Route (ICR) — R/W. This field indicates which physical pin on the ICH is connected to the INTC# pin reported for device 31 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# (Default) 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 7R e s e r v e d 6:4 Interrupt B Pin Route (IBR) — R/W. This field indicates which physical pin on the ICH is connected to the INTB# pin reported for device 31 functions. 0h = PIRQA# 1h = PIRQB# (Default) 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 3R e s e r v e d 2:0 Interrupt A Pin Route (IAR) — R/W. This field indicates which physical pin on the ICH is connected to the INTA# pin reported for device 31 functions. 0h = PIRQA# (Default) 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH#

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 269 Chipset Configuration Registers

7.1.47 D30IR—Device 30 Interrupt Route Register

Offset Address: 3142–3143h Attribute: R/W Default Value: 3210h Size: 16-bit Bit Description 14:12 Interrupt D Pin Route (IDR) — R/W. This field indicates which physical pin on the Intel® ICH6 is connected to the INTD# pin reported for device 30 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# (Default) 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 10:8 Interrupt C Pin Route (ICR) — R/W. This field indicates wh ich physical pin on the ICH is connected to the INTC# pin reported for device 30 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# (Default) 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 6:4 Interrupt B Pin Route (IBR) — R/W. This field indicates wh ich physical pin on the ICH is connected to the INTB# pin reported for device 30 functions. 0h = PIRQA# 1h = PIRQB# (Default) 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH#

3 Reserved

2:0 Interrupt A Pin Route (IAR) — R/W. This field indicates wh ich physical pin on the ICH is connected to the INTA# pin reported for device 30 functions. 0h = PIRQA# (Default) 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH#

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7.1.48 D29IR—Device 29 Interrupt Route Register

Offset Address: 3144–3145h Attribute: R/W Default Value: 3210h Size: 16-bit Bit Description 14:12 Interrupt D Pin Route (IDR) — R/W. This field indicates which physical pin on the Intel® ICH6 is connected to the INTD# pin reported for device 29 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# (Default) 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 10:8 Interrupt C Pin Route (ICR) — R/W. This field indicates wh ich physical pin on the ICH6 is connected to the INTC# pin reported for device 29 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# (Default) 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 7R e s e r v e d 6:4 Interrupt B Pin Route (IBR) — R/W. This field indicates which physical pin on the ICH is connected to the INTB# pin reported for device 29 functions. 0h = PIRQA# 1h = PIRQB# (Default) 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 3R e s e r v e d 2:0 Interrupt A Pin Route (IAR) — R/W. This field indicates wh ich physical pin on the ICH6 is connected to the INTA# pin reported for device 29 functions. 0h = PIRQA# (Default) 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH#

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 271 Chipset Configuration Registers

7.1.49 D28IR—Device 28 Interrupt Route Register

Offset Address: 3146–3147h Attribute: R/W Default Value: 3210h Size: 16-bit Bit Description 14:12 Interrupt D Pin Route (IDR) — R/W. This field indicates which physical pin on the Intel® ICH6 is connected to the INTD# pin reported for device 28 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# (Default) 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 10:8 Interrupt C Pin Route (ICR) — R/W. This field indicates which physical pin on the ICH is connected to the INTC# pin reported for device 28 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# (Default) 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 6:4 Interrupt B Pin Route (IBR) — R/W. This field indicates which physical pin on the ICH is connected to the INTB# pin reported for device 28 functions. 0h = PIRQA# 1h = PIRQB# (Default) 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 2:0 Interrupt A Pin Route (IAR) — R/W. This field indicates which physical pin on the ICH is connected to the INTA# pin reported for device 28 functions. 0h = PIRQA# (Default) 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH#

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7.1.50 D27IR—Device 27 Interrupt Route Register

Offset Address: 3148–3149h Attribute: R/W Default Value: 3210h Size: 16-bit Bit Description 14:12 Interrupt D Pin Route (IDR) — R/W. This field indicates which physical pin on the Intel® ICH6 is connected to the INTD# pin reported for device 27 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# (Default) 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 10:8 Interrupt C Pin Route (ICR) — R/W. This field indicates which physical pin on the ICH is connected to the INTC# pin reported for device 27 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# (Default) 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 7R e s e r v e d 6:4 Interrupt B Pin Route (IBR) — R/W. This field indicates which physical pin on the ICH is connected to the INTB# pin reported for device 27 functions. 0h = PIRQA# 1h = PIRQB# (Default) 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 3R e s e r v e d 2:0 Interrupt A Pin Route (IAR) — R/W. This field indicates which physical pin on the ICH is connected to the INTA# pin reported for device 27 functions. 0h = PIRQA# (Default) 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH#

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 273 Chipset Configuration Registers

7.1.51 OIC—Other Interrupt Control Register

Offset Address: 31FF–31FFh Attribute: R/W Default Value: 00h Size: 8-bit

7.1.52 RC—RTC Configuration Register

Offset Address: 3400–3403h Attribute: R/W, R/WLO Default Value: 00000000h Size: 32-bit Bit Description 7:2 Reserved Coprocessor Error Enable (CEN) — R/W. 0 = FERR# will not generate IRQ13 nor IGNNE#. 1 = If FERR# is low, the Intel ® ICH6 generates IRQ13 internally and holds it until an I/O port F0h write. It will also drive IGNNE# active. APIC Enable (AEN) — R/W. 0 = The internal IOxAPIC is disabled. 1 = Enables the internal IOxAPIC and its address decode. Bit Description 31:5 Reserved Upper 128 Byte Lock (UL) — R/WLO. 0 = Bytes not locked. 1 = Bytes 38h–3Fh in the upper 128-byte bank of RTC RAM are locked and cannot be accessed. Writes will be dropped and reads will not return any guaranteed data. Bit reset on system reset. Lower 128 Byte Lock (LL) — R/WLO. 0 = Bytes not locked. 1 = Bytes 38h–3Fh in the lower 128-byte bank of RTC RAM are locked and cannot be accessed. Writes will be dropped and reads will not return any guaranteed data. Bit reset on system reset. Upper 128 Byte Enable (UE) — R/W. 0 = Bytes locked. 1 = The upper 128-byte bank of RTC RAM can be accessed. 1:0 Reserved

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7.1.53 HPTC—High Precision Timer Configuration Register

Offset Address: 3404–3407h Attribute: R/W Default Value: 00000000h Size: 32-bit

7.1.54 GCS—General Control and Status Register

Offset Address: 3410–3413h Attribute: R/W, R/WLO Default Value: 0000000yh y=(00x0x000b) Size: 32-bit Bit Description 31:8 Reserved Address Enable (AE) — R/W. 0 = Address disabled. 1 = The Intel ® ICH6 will decode the High Precision Timer memory address range selected by bits 1:0 below. 6:2 Reserved 1:0 Address Select (AS) — R/W. This 2-bit field selects 1 of 4 possible memory address ranges for the High Precision Timer functionality. The encodings are: 00 = FED0_0000h–FED0_03FFh 01 = FED0_1000h–FED0_13FFh 10 = FED0_2000h–FED0_23FFh 11 = FED0_3000h–FED0_33FFh Bit Description 31:10 Reserved Server Error Reporting Mode (SERM) — R/W. 0 = The Intel ® ICH6 is the final target of all errors. The (G)MCH sends a messages to the ICH for the purpose of generating NMI. 1 = The (G)MCH is the final target of all errors from PCI Express* and DMI. In this mode, if the ICH6 detects a fatal, non-fatal, or correctable error on DMI or its downstream ports, it sends a message to the (G)MCH. If the ICH6 receives an ERR_* message from the downstream port, it sends that message to the (G)MCH. 8R e s e r v e d (Mobile) Mobile IDE Configuration Lock Down (MICLD) — R/WLO. 0 = Disabled. 1 = BUC.PRS (offset 3414h, bit 1) is locked and cannot be written until a system reset occurs. This prevents rogue software from changing the default state of the PATA pins during boot after BIOS configures them. This bit is write once, and is cleared by system reset and when returning from the S3/S4/S5 states. (Desktop) Reserved FERR# MUX Enable (FME) — R/W. This bit enables FERR# to be a processor break event indication. 0 = Disabled. 1 = The ICH6 examines FERR# during a C2 , C3, or C4 state as a break event. See Chapter 5.14.5 for a functional description.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 275 Chipset Configuration Registers No Reboot (NR) — R/W. This bit is set when the “No Reboot” strap (SPKR pin on ICH6) is sampled high on PWROK. This bit may be set or cleared by software if the strap is sampled low but may not override the strap when it indicates “No Reboot”. 0 = System will reboot upon the second timeout of the TCO timer. 1 = The TCO timer will count down and generate the SMI# on the first timeout, but will not reboot on the second timeout. Alternate Access Mode Enable (AME) — R/W. 0 = Disabled. 1 = Alternate access read only registers can be written, and write only registers can be read. Before entering a low power state, several registers from powered down parts may need to be saved. In the majority of cases, this is not an issue, as registers have read and write paths. However, several of the ISA compatible registers are either read only or write only. To get data out of write-only registers, and to restore data into read-only registers, the ICH implements an alternate access mode. For a list of these registers see Section 5.14.10. Boot BIOS Destination (BBD) — R/W. The default value of this bit is determined by a strap allowing systems with corrupted or unprogrammed flash to boot from a PCI device. The value of the strap can be overwritten by software. When this bit is 0, the PCI-to-PCI bridge memory space enable bit does not need to be set (nor any other bits) in order for these cycles to go to PCI. Note that BIOS enable ranges and the other BIOS protection and update bits associated with the FWH interface have no effect when this bit is 0 = The top 16 MB of memory below 4 GB (F F00_0000h to FFFF_FFFFh) is accepted by the primary side of the PCI P2P bridge and forwarded to the PCI bus. 1 = The top 16 MB of memory below 4 GB (FF00_0000h to FFFF_FFFFh) is not decoded to PCI and the LPC bridge claims these cycles based on the FWH Decode Enable bits. NOTE: This functionality intended for debug/testing only. Reserved Page Route (RPR) — R/W. Determines where to send the reserved page registers. These addresses are sent to PCI or LPC for the purpose of generating POST codes. The I/O addresses modified by this field are: 80h, 84h, 85h, 86h, 88h, 8Ch, 8Dh, and 8Eh. 0 = Writes will be forwarded to LPC, shadowed within the ICH, and reads will be returned from the internal shadow 1 = Writes will be forwarded to PCI, shadowed within the ICH, and reads will be returned from the internal shadow. Note, if some writes are done to LPC/PCI to these I/O ranges, and then this bit is flipped, such that writes will now go to the other interface, the reads will not return what was last written. Shadowing is performed on each interface. The aliases for these registers, at 90h, 94h, 95h, 96h, 98h, 9Ch, 9Dh, and 9Eh, are always decoded to LPC. Top Swap Lock-Down (TSLD) — R/WLO. 0 = Disabled. 1 = Prevents BUC.TS (offset 3414, bit 0) from bei ng changed. This bit can only be written from 0 to 1 once. Bit Description

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7.1.55 BUC—Backed Up Control Register

Offset Address: 3414–3414h Attribute: R/W Default Value: 0000001xb (Mobile) Size: 8-bit 0000000xb (Desktop) All bits in this register are in the RTC well and only cleared by RTCRST# Bit Description 7:3 Reserved CPU BIST Enable (CBE) — R/W. This bit is in the resume well and is reset by RSMRST#, but not PLTRST# nor CF9h writes. 0 = Disabled. 1 = The INIT# signals will be driven active when CPURST# is active. INIT# and INIT3_3V# will go inactive with the same timings as the other processor I/F signals (hold time after CPURST# inactive). (Mobile) PATA Reset State (PRS) — R/W. 0 = The reset state of the PATA pins will be driven. 1 = The reset state of the PATA pins will be tri-state. (Desktop) Reserved Top Swap (TS) — R/W. 0 = Intel ® ICH6 will not invert A16. 1 = ICH6 will invert A16 for cycles going to the BIOS space (but not the feature space) in the FWH. If ICH is strapped for Top-Swap (GNT[6]# is low at rising edge of PWROK), then this bit cannot be cleared by software. The strap jumper should be removed and the system rebooted.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 277 Chipset Configuration Registers

7.1.56 FD—Function Disable Register

Offset Address: 3418–341Bh Attribute: R/W, RO Default Value: See bit description Size: 32-bit The UHCI functions must be disabled from highest function number to lowest. For example, if only three UHCIs are wanted, software must disable UHCI #4 (UD4 bit set). When disabling UHCIs, the EHCI Structural Parameters Registers must be updated with coherent information in “Number of Companion Controllers” and “N_Ports” fields. When disabling a function, only the configuration space is disabled. Software must ensure that all functionality within a controller that is not desired (such as memory spaces, I/O spaces, and DMA engines) is disabled prior to disabling the function. When a function is disabled, software must not attempt to re-enable it. A disabled function can only be re-enabled by a platform reset. Bit Description 31:20 Reserved PCI Express 4 Disable (PE4D) — R/W. Default is 0. When disabled, the link for this port is put into the “link down” state. 0 = PCI Express* port #4 is enabled. 1 = PCI Express port #4 is disabled. PCI Express 3 Disable (PE3D) — R/W. Default is 0. When disabled, the link for this port is put into the link down state. 0 = PCI Express port #3 is enabled. 1 = PCI Express port #3 is disabled. PCI Express 2 Disable (PE2D) — R/W. Default is 0. When disabled, the link for this port is put into the link down state. 0 = PCI Express port #2 is enabled. 1 = PCI Express port #2 is disabled. PCI Express 1 Disable (PE1D) — R/W. Default is 0. When disabled, the link for this port is put into the link down state. 0 = PCI Express port #1 is enabled. 1 = PCI Express port #1 is disabled. EHCI Disable (EHCID) — R/W. Default is 0. 0 = The EHCI is enabled. 1 = The EHCI is disabled. LPC Bridge Disable (LBD) — R/W. Default is 0. 0 = The LPC bridge is enabled. 1 = The LPC bridge is disabled. Unlike the other di sables in this register, the following additional spaces will no longer be decoded by the LPC bridge:

• Memory cycles below 16 MB (1000000h)
• I/O cycles below 64 kB (10000h)
• The Internal I/OxAPIC at FEC0_0000 to FECF_FFFF Memory cycles in the LPC BIOS range below 4 GB will still be decoded when this bit is set, but the aliases at the top of 1 MB (the E and F segment) no longer will be decoded. 13:12 Reserved UHCI #4 Disable (U4D) — R/W. Default is 0. 0 = The 4th UHCI (ports 6 and 7) is enabled. 1 = The 4th UHCI (ports 6 and 7) is disabled. UHCI #3 Disable (U3D) — R/W. Default is 0. 0 = The 3rd UHCI (ports 4 and 5) is enabled. 1 = The 3rd UHCI (ports 4 and 5) is disabled.

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7.1.57 CG—Clock Gating

Offset Address: 341C–341Fh Attribute: R/W, RO Default Value: 00000000h Size: 32-bit UHCI #2 Disable (U2D) — R/W. Default is 0. 0 = The 2nd UHCI (ports 2 and 3) is enabled. 1 = The 2nd UHCI (ports 2 and 3) is disabled. UHCI #1 Disable (U1D) — R/W. Default is 0. 0 = The 1st UHCI (ports 0 and 1) is enabled. 1 = The 1st UHCI (ports 0 and 1) is disabled. Hide Internal LAN (HIL) — R/W. Default is 0. 0 = The LAN controller is enabled. 1 = The LAN controller is disabled and will not decode configuration cycles off of PCI. AC ‘97 Modem Disable (AMD) — R/W. Default is 0. 0 = The AC ‘97 modem function is enabled. 1 = The AC ‘97 modem function is disabled. AC ‘97 Audio Disable (AAD) — R/W. Default is 0. 0 = The AC ‘97 audio function is enabled. 1 = The AC ‘97 audio function is disabled. Intel High Definition Audio Disable (ZD) — R/W. Default is 0. 0 = The Intel High Definition Audio controller is enabled. 1 = The Intel High Definition Audio controller is disabled and its PCI configuration space is not accessible. SM Bus Disable (SD) — R/W. Default is 0. 0 = The SM Bus controller is enabled. 1 = The SM Bus controller is disabled. In ICH5 and previous, this also disabled the I/O space. In ICH6, it only disables the configuration space. Serial ATA Disable (SAD) — R/W. Default is 0. 0 = The SATA controller is enabled. 1 = The SATA controller is disabled. Parallel ATA Disable (PAD) — R/W. Default is 0. 0 = The PATA controller is enabled. 1 = The PATA controller is disabled and its PCI configuration space is not accessible. 0R e s e r v e d Bit Description Bit Description 31:1 Reserved PCI Express root port Static Clock Gate Enable (PESCG) — R/W. 0 = Static Clock Gating is Disabled for the PCI Express* root port. 1 = Static Clock Gating is Enabled for the PCI Express root port when the corresponding port is disabled in the Function Disable register (Chipset Configuration Registers:Offset 3418h) In addition to the PCI Express function disable register, the PCI Express root port physical layer static clock gating is also qualified by the Root Port Configuration RPC.PC (Chipset Configuration Registers:Offset 0224h:bits 1:0) as the physical layer may be required by an enabled port in a x4 configuration.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 279 Chipset Configuration Registers

7.1.58 CSIR1—Chipset Initialization Register 1

Offset Address: 3E08–3E09h Attribute: R/W Default Value: 0000h Size: 16-bits

7.1.59 CSIR2—Chipset Initialization Register 2

Offset Address: 3E48–3E49h Attribute: R/W Default Value: 0000h Size: 16-bits

7.1.60 CSIR3—Chipset Initialization Register 3

Offset Address: 3E0Eh Attribute: R/W Default Value: 00h Size: 8-bits

7.1.61 CSIR4—Chipset Initialization Register 4

Offset Address: 3E4Eh Attribute: R/W Default Value: 00h Size: 8-bits § Bit Description 15:8 Reserved 7 Chipset Initialization Register 1 Bit[7] — R/W. BIOS sets this bit to 1. 6:0 Reserved Bit Description 15:8 Reserved 7 Chipset Initialization Register 2 Bit[7] — R/W. BIOS sets this bit to 1. 6:0 Reserved Bit Description 7 Chipset Initialization Register 3 Bit[7] — R/W. BIOS sets this bit to 1. 6:0 Reserved Bit Description 7 Chipset Initialization Register 4 Bit[7] — R/W. BIOS sets this bit to 1. 6:0 Reserved

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Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 281 LAN Controller Registers (B1:D8:F0)

8 LAN Controller Registers

(B1:D8:F0) The ICH6 integrated LAN controller appears to reside at PCI Device 8, Function 0 on the secondary side of the ICH6’s virtual PCI-to-PCI bridge. This is typically Bus 1, but may be assigned a different number depending upon system configuration. The LAN controller acts as both a master and a slave on the PCI bus. As a master, the LAN controller interacts with the system main memory to access data for transmission or deposit received data. As a slave, some of the LAN controller’s control structures are accessed by the host processor to read or write information to the on-chip registers. The processor also provides the LAN controller with the necessary commands and pointers that allow it to process receive and transmit data.

8.1 PCI Configuration Registers

(LAN Controller—B1:D8:F0) Note: Address locations that are not shown should be treated as Reserved (See Section 6.2 for details). Table 8-1. LAN Controller PCI Register Address Map (LAN Controller—B1:D8:F0) (Sheet 1 of Offset Mnemonic Register Name Default Type 00–01h VID Vendor Identification 8086h RO 02–03h DID Device Identification 1065h RO 04–05h PCICMD PCI Command 0000h RO, R/W 06–07h PCISTS PCI Status 0290h RO, R/WC 08h RID Revision Identification See register description. RO 0Ah SCC Sub Class Code 00h RO 0Bh BCC Base Class Code 02 RO 0Ch CLS Cache Line Size 00h R/W 0Dh PMLT Primary Master Latency Timer 00h R/W 0Eh HEADTYP Header Type 00h RO 10–13h CSR_MEM_BASE CSR Memory–Mapped Base Address 00000008h R/W, RO 14–17h CSR_IO_BASE CSR I/O–Mapped Base Address 00000001h R/W, RO 2C–2Dh SVID Subsystem Vendor Identification 0000h RO 2E–2Fh SID Subsystem Identification 0000h RO 34h CAP_PTR Capabilities Pointer DCh RO 3Ch INT_LN Interrupt Line 00h R/W 3Dh INT_PN Interrupt Pin 01h RO 3Eh MIN_GNT Minimum Grant 08h RO 3Fh MAX_LAT Maximum Latency 38h RO DCh CAP_ID Capability ID 01h RO DDh NXT_PTR Next Item Pointer 00h RO

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8.1.1 VID—Vendor Identification Register

(LAN Controller—B1:D8:F0) Offset Address: 00 –01h Attribute: RO Default Value: 8086h Size: 16 bits

8.1.2 DID—Device Identification Register

(LAN Controller—B1:D8:F0) Offset Address: 02 –03h Attribute: RO Default Value: 1065h Size: 16 bits DE–DFh PM_CAP Power Management Capabilities FE21h (Desktop) 7E21h (Mobile) RO E0–E1h PMCSR Power Management Control/Status 0000h R/W, RO, R/WC E3 PCIDATA PCI Power Management Data 00h RO Table 8-1. LAN Controller PCI Register Address Map (LAN Controller—B1:D8:F0) (Sheet 2 of Offset Mnemonic Register Name Default Type Bit Description 15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel. Bit Description 15:0 Device ID — RO. This is a 16-bit value assi gned to the ICH6 integrated LAN controller. 1. If the EEPROM is not present (or not properly pr ogrammed), reads to the Device ID return the default value of 1065h. 2. If the EEPROM is present (and properly programmed) and if the value of word 23h is not 0000h or FFFFh, the Device ID is loaded from the EEPROM, word 23h after the hardware reset. (See Section 8.1.14 - SID, Subsystem ID of LAN controller for detail)

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 283 LAN Controller Registers (B1:D8:F0)

8.1.3 PCICMD—PCI Command Register

(LAN Controller—B1:D8:F0) Offset Address: 04 –05h Attribute: RO, R/W Default Value: 0000h Size: 16 bits Bit Description 15:11 Reserved Interrupt Disable — R/W. 0 = Enable. 1 = Disables LAN controller to assert its INTA signal. 9 Fast Back to Back Enable (FBE) — RO. Hardwired to 0. The integrated LAN controller will not run fast back-to-back PCI cycles. SERR# Enable (SERR_EN) — R/W. 0 = Disable. 1 = Enable. Allow SERR# to be asserted. 7 Wait Cycle Control (WCC) — RO. Hardwired to 0. Not implemented. Parity Error Response (PER) — R/W. 0 = The LAN controller will ignore PCI parity errors. 1 = The integrated LAN controller will take norma l action when a PCI parity error is detected and will enable generation of parity on DMI. 5 VGA Palette Snoop (VPS) — RO. Hardwired to 0. Not Implemented. Memory Write and Invalidate Enable (MWIE) — R/W. 0 = Disable. The LAN controller will not us e the Memory Write and Invalidate command. 1 = Enable. 3 Special Cycle Enable (SCE) — RO. Hardwired to 0. The LAN controller ignores special cycles. Bus Master Enable (BME) — R/W. 0 = Disable. 1 = Enable. The ICH6’s integrated LAN controller may function as a PCI bus master. Memory Space Enable (MSE) — R/W. 0 = Disable. 1 = Enable. The ICH6’s integrated LAN controller will respond to the memory space accesses. I/O Space Enable (IOSE) — R/W. 0 = Disable. 1 = Enable. The ICH6’s integrated LAN controller will respond to the I/O space accesses.

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LAN Controller Registers (B1:D8:F0)

8.1.4 PCISTS—PCI Status Register

(LAN Controller—B1:D8:F0) Offset Address: 06 –07h Attribute: RO, R/WC Default Value: 0290h Size: 16 bits Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no effect. Bit Description Detected Parity Error (DPE) — R/WC. 0 = Parity error Not detected. 1 = The Intel ® ICH6’s integrated LAN controller has detected a parity error on the PCI bus (will be set even if Parity Error Response is disabled in the PCI Command register). Signaled System Error (SSE) — R/WC. 0 = Integrated LAN controller has not asserted SERR# 1 = The ICH6’s integrated LAN controller has asserted SERR#. SERR# can be routed to cause NMI, SMI#, or interrupt. Master Abort Status (RMA) — R/WC. 0 = Master Abort not generated 1 = The ICH6’s integrated LAN controller (as a PCI master) has generated a master abort. Received Target Abort (RTA) — R/WC. 0 = Target abort not received. 1 = The ICH6’s integrated LAN controller (as a PCI master) has received a target abort. 11 Signaled Target Abort (STA) — RO. Hardwired to 0. The device will never signal Target Abort. 10:9 DEVSEL# Timing Status (DEV_STS) — RO. 01h = Medium timing. Data Parity Error Detected (DPED) — R/WC. 0 = Parity error not detected (conditions below are not met). 1 = All of the following three conditions have been met: 1.The LAN controller is acting as bus master 2.The LAN controller has asserted PERR# (for reads) or detected PERR# asserted (for writes) 3.The Parity Error Response bit in the LAN controller’s PCI Command Register is set.

7 Fast Back to Back

Capable (FB2BC) — RO. Hardwired to 1. The device can accept fast back-to- back transactions. 6 User Definable Features (UDF) — RO. Hardwired to 0. Not implemented. 5 66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0. The device does not support 66 MHz PCI. Capabilities List (CAP_LIST) — RO. 0 = The EEPROM indicates that the integrated LAN controller does not support PCI Power Management. 1 = The EEPROM indicates that the integrated LAN controller supports PCI Power Management. 3 Interrupt Status (INTS) — RO. This bit indicates that an inte rrupt is pending. It is independent from the state of the Interrupt Enable bit in the command register. 2:0 Reserved

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 285 LAN Controller Registers (B1:D8:F0)

8.1.5 RID—Revision Identification Register

(LAN Controller—B1:D8:F0) Offset Address: 08h Attribute: RO Default Value: See bit description Size: 8 bits

8.1.6 SCC—Sub Class Code Register

(LAN Controller—B1:D8:F0) Offset Address: 0Ah Attribute: RO Default Value: 00h Size: 8 bits

8.1.7 BCC—Base-Class Code Register

(LAN Controller—B1:D8:F0) Offset Address: 0Bh Attribute: RO Default Value: 02h Size: 8 bits Bit Description 7:0 Revision ID (RID) — RO. This field is an 8-bit value that indicates the revision number for the integrated LAN controller. The three least significant bits in this register may be overridden by the ID and REV ID fields in the EEPROM. Refer to the Intel® I/O Controller Hub 6 (ICH6) Family Specification Update for the value of the Revision ID Register. Bit Description 7:0 Sub Class Code (SCC) — RO. This 8-bit value specifies the sub-class of the device as an Ethernet controller. Bit Description 7:0 Base Class Code (BCC) — RO. This 8-bit value specifies the base class of the device as a network controller.

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8.1.8 CLS—Cache Line Size Register

(LAN Controller—B1:D8:F0) Offset Address: 0Ch Attribute: R/W Default Value: 00h Size: 8 bits

8.1.9 PMLT—Primary Master Latency Timer Register

(LAN Controller—B1:D8:F0) Offset Address: 0Dh Attribute: R/W Default Value: 00h Size: 8 bits

8.1.10 HEADTYP—Header Type Register

(LAN Controller—B1:D8:F0) Offset Address: 0Eh Attribute: RO Default Value: 00h Size: 8 bits Bit Description 7:5 Reserved 4:3 Cache Line Size (CLS) — R/W. 00 = Memory Write and Invalidate (MWI) command will not be used by the integrated LAN controller. 01 = MWI command will be used with Cache Line Size set to 8 DWords (only set if a value of 08h is written to this register). 10 = MWI command will be used with Cache Line Size set to 16 DWords (only set if a value of 10h is written to this register). 11 = Invalid. MWI command will not be used. 2:0 Reserved Bit Description 7:3 Master Latency Timer Count (MLTC) — R/W. This field defines t he number of PCI clock cycles that the integrated LAN controller may own the bus while acting as bus master. 2:0 Reserved Bit Description 7 Multi-Function Device (MFD) — RO. Hardwired to 0 to indicate a single function device. 6:0 Header Type (HTYPE) — RO. This 7-bit field identifies the header layout of the configuration space as an Ethernet controller.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 287 LAN Controller Registers (B1:D8:F0)

8.1.11 CSR_MEM_BASE — CS R Memory-Mapped Base

Address Register (LAN Controller—B1:D8:F0) Offset Address: 10 –13h Attribute: R/W, RO Default Value: 00000008h Size: 32 bits Note: The ICH6’s integrated LAN controller requires one BAR for memory mapping. Software determines which BAR (memory or I/O) is used to access the LAN controller’s CSR registers.

8.1.12 CSR_IO_BASE — CSR I/O-M apped Base Address Register

(LAN Controller—B1:D8:F0) Offset Address: 14 –17h Attribute: R/W, RO Default Value: 00000001h Size: 32 bits Note: The ICH6’s integrated LAN controller requires one BAR for memory mapping. Software determines which BAR (memory or I/O) is used to access the LAN controller’s CSR registers.

8.1.13 SVID — Subsystem Vendor Identification

(LAN Controller—B1:D8:F0) Offset Address: 2C –2D Attribute: RO Default Value: 0000h Size: 16 bits Bit Description 31:12 Base Address (MEM_ADDR) — R/W. This field contains the upper 20 bits of the base address provides 4 KB of memory-Mapped space for the LAN controller’s Control/Status registers. 11:4 Reserved 3 Prefetchable (MEM_PF) — RO. Hardwired to 0 to indicate that this is not a pre-fetchable memory- Mapped address range. 2:1 Type (MEM_TYPE) — RO. Hardwired to 00b to indicate the memory-Mapped address range may be located anywhere in 32-bit address space. 0 Memory-Space Indicator (MEM_SPACE) — RO. Hardwi red to 0 to indicate that this base address maps to memory space. Bit Description 31:16 Reserved 15:6 Base Address (IO_ADDR)— R/W. This field provides 64 bytes of I/O-Mapped address space for the LAN controller’s Control/Status registers. 5:1 Reserved 0 I/O Space Indicator (IO_SPACE) — RO. Hardwired to 1 to indicate that this base address maps to I/O space. Bit Description 15:0 Subsystem Vendor ID (SVID) — RO. See Section 8.1.14 for details.

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8.1.14 SID — Subsystem Identification

(LAN Controller—B1:D8:F0) Offset Address: 2E –2Fh Attribute: RO Default Value: 0000h Size: 16 bits Note: The ICH6’s integrated LAN controller provides support for configurable Subsystem ID and Subsystem Vendor ID fields. After reset, the LAN controller automatically reads addresses Ah through Ch, and 23h of the EEPROM. The LAN controller checks bits 15:13 in the EEPROM word Ah, and functions according to Table 8-2. NOTES: 1. The Revision ID is subject to change according to the silicon stepping. 2. The Device ID is loaded from Word 23h only if the value of Word 23h is not 0000h or FFFFh

8.1.15 CAP_PTR — Ca pabilities Pointer

(LAN Controller—B1:D8:F0) Offset Address: 34h Attribute: RO Default Value: DCh Size: 8 bits

8.1.16 INT_LN — Interrupt Line Register

(LAN Controller—B1:D8:F0) Offset Address: 3Ch Attribute: R/W Default Value: 00h Size: 8 bits Bit Description 15:0 Subsystem ID (SID) — RO. Table 8-2. Configuration of Subsystem ID and Subsystem Vendor ID via EEPROM Bits 15:14 Bit 13 Device ID Vendor ID Revision ID Subsystem ID Subsystem Vendor ID 11b, 10b, 00b X 1051h 8086h 00h 0000h 0000h 01b 0b Word 23h 8086h 00h Word Bh Word Ch 01b 1b Word 23h Word Ch 80h + Word Ah, bits 10:8 Word Bh Word Ch Bit Description 7:0 Capabilities Pointer (CAP_PTR) — RO. Hardwired to DCh to indicate the offset within configuration space for the location of the Power Management registers. Bit Description 7:0 Interrupt Line (INT_LN) — R/W. This field identifies the sy stem interrupt line to which the LAN controller’s PCI interrupt request pin (as defined in the Interrupt Pin Register) is routed.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 289 LAN Controller Registers (B1:D8:F0)

8.1.17 INT_PN — Interrupt Pin Register

(LAN Controller—B1:D8:F0) Offset Address: 3Dh Attribute: RO Default Value: 01h Size: 8 bits

8.1.18 MIN_GNT — Minimum Grant Register

(LAN Controller—B1:D8:F0) Offset Address: 3Eh Attribute: RO Default Value: 08h Size: 8 bits

8.1.19 MAX_LAT — Maxi mum Latency Register

(LAN Controller—B1:D8:F0) Offset Address: 3Fh Attribute: RO Default Value: 38h Size: 8 bits

8.1.20 CAP_ID — Capability Identification Register

(LAN Controller—B1:D8:F0) Offset Address: DCh Attribute: RO Default Value: 01h Size: 8 bits Bit Description 7:0 Interrupt Pin (INT_PN) — RO. Hardwired to 01h to indicate that the LAN controller’s interrupt request is connected to PIRQA#. However, in the ICH6 implementation, when the LAN controller interrupt is generated PIRQE# will go active, not PIRQA#. Note that if the PIRQE# signal is used as a GPI, the external visibility will be lost (though PIRQE# will still go active internally). Bit Description 7:0 Minimum Grant (MIN_GNT) — RO. This field indicates the amount of time (in increments of 0.25 µs) that the LAN controller needs to retain ownership of the PCI bus when it initiates a transaction. Bit Description 7:0 Maximum Latency (MAX_LAT) — RO. This field defines how often (in increments of 0.25 µs) the LAN controller needs to access the PCI bus. Bit Description 7:0 Capability ID (CAP_ID) — RO. Hardwired to 01h to indicate that the Intel® ICH6’s integrated LAN controller supports PCI power management.

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8.1.21 NXT_PTR — Next Item Pointer

(LAN Controller—B1:D8:F0) Offset Address: DDh Attribute: RO Default Value: 00h Size: 8 bits

8.1.22 PM_CAP — Power Ma nagement Capabilities

(LAN Controller—B1:D8:F0) Offset Address: DE –DFh Attribute: RO Default Value: FE21h (In Desktop) Size: 16 bits 7E21h (In Mobile) Bit Description 7:0 Next Item Pointer (NXT_PTR) — RO. Hardwired to 00b to indicate that power management is the last item in the capabilities list. Bit Description 15:11 PME Support (PME_SUP) — RO. Hardwired to 11111b. This 5-bit field indicates the power states in which the LAN controller may assert PME#. The LAN controller supports wake-up in all power states. 10 D2 Support (D2_SUP) — RO. Hardwired to 1 to indicate that the LAN controller supports the D2 power state. 9 D1 Support (D1_SUP) — RO. Hardwired to 1 to indicate that the LAN controller supports the D1 power state. 8:6 Auxiliary Current (AUX_CUR) — RO. Hardwired to 000b to indicate that the LAN controller implements the Data registers. The auxiliary power consumption is the same as the current consumption reported in the D3 state in the Data register. Device Specific Initialization (DSI) — RO. Hardwired to 1 to indicate that special initialization of this function is required (beyond the standard PCI configuration header) before the generic class device driver is able to use it. DSI is required for the LAN controller after D3-to-D0 reset. 4R e s e r v e d 3 PME Clock (PME_CLK) — RO. Hardwired to 0 to indicate that the LAN controller does not require a clock to generate a power management event. 2:0 Version (VER) — RO. Hardwired to 010b to indicate that the LAN controller complies with of the PCI Power Management Specification, Revision 1.1.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 291 LAN Controller Registers (B1:D8:F0)

8.1.23 PMCSR — Power Management Control/

Status Register (LAN Controller—B1:D8:F0) Offset Address: E0 –E1h Attribute: RO, R/W, R/WC Default Value: 0000h Size: 16 bits Bit Description PME Status (PME_STAT) — R/WC. 0 = Software clears this bit by writing a 1 to it. This also de-asserts the PME# signal and clears the PME status bit in the Power Management Driver Register. When the PME# signal is enabled, the PME# signal reflects the state of the PME status bit. 1 = Set upon occurrence of a wake-up event, independent of the state of the PME enable bit. 14:13 Data Scale (DSCALE) — RO. This field indicates the data register scaling factor. It equals 10b for registers 0 through 8 and 00b for registers nine through fifteen, as selected by the “Data Select” field. 12:9 Data Select (DSEL) — R/W. This field is used to select which data is reported through the Data register and Data Scale field. PME Enable (PME_EN) — R/W. This bit enables the ICH6’s integrated LAN controller to assert PME#. 0 = The device will not assert PME#. 1 = Enable PME# assertion when PME Status is set. 7:5 Reserved 4 Dynamic Data (DYN_DAT) — RO. Hardwired to 0 to indicate that the device does not support the ability to monitor the power consumption dynamically. 3:2 Reserved 1:0 Power State (PWR_ST) — R/W. This 2-bit field is used to determine the current power state of the integrated LAN controller, and to put it into a new power state. The definition of the field values is as follows: 00 = D0 01 = D1 10 = D2 11 = D3

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8.1.24 PCIDATA — PCI Power Management Data Register

(LAN Controller—B1:D8:F0) Offset Address: E3h Attribute: RO Default Value: 00h Size: 8 bits The data register is an 8-bit read only register that provides a mechanism for the ICH6’s integrated LAN controller to report state dependent maximum power consumption and heat dissipation. The value reported in this register depends on the value written to the Data Select field in the PMCSR register. The power measurements defined in this register have a dynamic range of 0 W to 2.55 W with 0.01 W resolution, scaled according to the Data Scale field in the PMCSR. The structure of the Data Register is given in Table 8-3. Bit Description 7:0 Power Management Data (PWR_MGT) — RO. State dependent power consumption and heat dissipation data. Table 8-3. Data Register Structure Data Select Data Scale Data Reported 0 2 D0 Power Consumption 1 2 D1 Power Consumption 2 2 D2 Power Consumption 3 2 D3 Power Consumption 4 2 D0 Power Dissipated 5 2 D1 Power Dissipated 6 2 D2 Power Dissipated 7 2 D3 Power Dissipated 8 2 Common Function Power Dissipated 9–15 0 Reserved

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 293 LAN Controller Registers (B1:D8:F0)

8.2 LAN Control / Status Registers (CSR)

(LAN Controller— B1:D8:F0) Table 8-4. Intel® ICH6 Integrated LAN Controller CSR Space Register Address Map Offset Mnemonic Register Name Default Type 00h–01h SCB_STA System Control Block Status Word 0000h R/WC, RO 02h–03h SCB_CMD System Control Block Command Word 0000h R/W, WO 04h–07h SCB_GENPNT System Control Block General Pointer 0000 0000h R/W 08h–0Bh PORT PORT Interface 0000 0000h R/W (special) 0Ch–0Dh — Reserved — — 0Eh EEPROM_CNTL EEPROM Control 00 R/W, RO, WO 0Fh — Reserved — — 10h–13h MDI_CNTL Management Data Interface Control 0000 0000h R/W (special) 14h–17h REC_DMA_BC Receive DMA Byte Count 0000 0000h RO 18h EREC_INTR Early Receive Interrupt 00h R/W 19–1Ah FLOW_CNTL Flow Control 0000h RO, R/W (special) 1Bh PMDR Power Management Driver 00h R/WC 1Ch GENCNTL General Control 00h R/W 1Dh GENSTA General Status 00h RO 1Eh — Reserved — — 1Fh SMB_PCI SMB via PCI 27h R/W, RO 20h–3Ch — Reserved — —

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8.2.1 SCB_STA—System Control Block Status Word Register

(LAN Controller—B1:D8:F0) Offset Address: 00 –01h Attribute: R/WC, RO Default Value: 0000h Size: 16 bits The ICH6’s integrated LAN controller places the status of its Command Unit (CU) and Receive Unit (RC) and interrupt indications in this register for the processor to read. Bit Description Command Unit (CU) Executed (CX) — R/WC. 0 = Software acknowledges the interrupt and clear s this bit by writing a 1 to the bit position. 1 = Interrupt signaled because the CU has comple ted executing a command with its interrupt bit set. Frame Received (FR) — R/WC. 0 = Software acknowledges the interrupt and clear s this bit by writing a 1 to the bit position. 1 = Interrupt signaled because the Receive Unit (RU) has finished receiving a frame. CU Not Active (CNA) — R/WC. 0 = Software acknowledges the interrupt and clear s this bit by writing a 1 to the bit position. 1 = The Command Unit left the Active state or entered the Idle state. There are 2 distinct states of the CU. When configured to generate CNA interrupt, the interrupt will be activated when the CU leaves the Active state and enters either the Idle or the Suspended state. When configured to generate CI interrupt, an interrupt will be generated only when the CU enters the Idle state. Receive Not Ready (RNR) — R/WC. 0 = Software acknowledges the interrupt and clear s this bit by writing a 1 to the bit position. 1 = Interrupt signaled because the Receive Unit left the Ready state. This may be caused by an RU Abort command, a no resources situation, or set suspend bit due to a filled Receive Frame Descriptor. Management Data Interrupt (MDI) — R/WC. 0 = Software acknowledges the interrupt and clear s this bit by writing a 1 to the bit position. 1 = Set when a Management Data Interface read or write cycle has completed. The management data interrupt is enabled through the interrupt enable bit (bit 29 in the Management Data Interface Control register in the CSR). Software Interrupt (SWI) — R/WC. 0 = Software acknowledges the interrupt and clear s this bit by writing a 1 to the bit position. 1 = Set when software generates an interrupt. Early Receive (ER) — R/WC. 0 = Software acknowledges the interrupt and clear s this bit by writing a 1 to the bit position. 1 = Indicates the occurrence of an Early Receive Interrupt. Flow Control Pause (FCP) — R/WC. 0 = Software acknowledges the interrupt and clear s this bit by writing a 1 to the bit position. 1 = Indicates Flow Control Pause interrupt. 7:6 Command Unit Status (CUS) — RO. 00 = Idle 01 = Suspended 10 = LPQ (Low Priority Queue) active 11 = HPQ (High Priority Queue) active

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 295 LAN Controller Registers (B1:D8:F0) 5:2 Receive Unit Status (RUS) — RO. 1:0 Reserved Bit Description Value Status Value Status 0000b Idle 1000b Reserved 0001b Suspended 1001b Suspended with no more RBDs 0010b No Resources 1010b No resources due to no more RBDs 0011b Reserved 1011b Reserved 0100b Ready 1100b Ready with no RBDs present 0101b Reserved 1101b Reserved 0110b Reserved 1110b Reserved 0111b Reserved 1111b Reserved

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8.2.2 SCB_CMD—System Control Block Command Word

Register (LAN Controller—B1:D8:F0) Offset Address: 02 –03h Attribute: R/W, WO Default Value: 0000h Size: 16 bits The processor places commands for the Command and Receive units in this register. Interrupts are also acknowledged in this register. Bit Description CX Mask (CX_MSK) — R/W. 0 = Interrupt not masked. 1 = Disable the generation of a CX interrupt. FR Mask (FR_MSK) — R/W. 0 = Interrupt not masked. 1 = Disable the generation of an FR interrupt. CNA Mask (CNA_MSK) — R/W. 0 = Interrupt not masked. 1 = Disable the generation of a CNA interrupt. RNR Mask (RNR_MSK) — R/W. 0 = Interrupt not masked. 1 = Disable the generation of an RNR interrupt. ER Mask (ER_MSK) — R/W. 0 = Interrupt not masked. 1 = Disable the generation of an ER interrupt. FCP Mask (FCP_MSK) — R/W. 0 = Interrupt not masked. 1 = Disable the generation of an FCP interrupt. Software Generated Interrupt (SI) — WO. 0 = No Effect. 1 = Setting this bit causes the LAN controller to generate an interrupt. Interrupt Mask (IM) — R/W. This bit enables or disables the LAN controller’s assertion of the INTA# signal. This bit has higher precedence that the Specific Interrupt Mask bits and the SI bit. 0 = Enable the assertion of INTA#. 1 = Disable the assertion of INTA#.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 297 LAN Controller Registers (B1:D8:F0) 7:4 Command Unit Command (CUC) — R/W. Valid values are listed below. All other values are Reserved. 0000 = NOP: Does not affect the current state of the unit. 0001 = CU Start: Start execution of the first command on the CBL. A pointer to the first CB of the CBL should be placed in the SCB General Pointer before issuing this command. The CU Start command should only be issued when the CU is in the Idle or Suspended states (never when the CU is in the active state), and all of the previously issued Command Blocks have been processed and completed by the CU. Sometimes it is only possible to determine that all Command Blocks are completed by checking that the Complete bit is set in all previously issued Command Blocks. 0010 = CU Resume: Resume operation of the Command unit by executing the next command. This command will be ignored if the CU is idle. 0011 = CU HPQ Start: Start execution of the first command on the high priority CBL. A pointer to the first CB of the HPQ CBL should be placed in the SCB General POinter before issuing this command. 0100 = Load Dump Counters Address: Indicates to the device where to write dump data when using the Dump Statistical Counters or Dump and Reset Statistical Counters commands. This command must be executed at least once before any usage of the Dump Statistical Counters or Dump and Reset Statistical Counters commands. The address of the dump area must be placed in the General Pointer register. 0101 = Dump Statistical Counters: Tells the device to dump its statistical counters to the area designated by the Load Dump Counters Address command. 0110 = Load CU Base: The device’s internal CU Base Register is loaded with the value in the CSB General Pointer. 0111 = Dump and Reset Statistical Counters: Indicates to the device to dump its statistical counters to the area designated by the Load Dump Counters Address command, and then to clear these counters. 1010 = CU Static Resume: Resume operation of the Command unit by executing the next command. This command will be ignored if the CU is idle. This command should be used only when the CU is in the Suspended state and has no pending CU Resume commands. 1011 = CU HPQ Resume: Resume execution of the first command on the HPQ CBL. this command will be ignored if the HPQ was never started. 2:0 Receive Unit Command (RUC) — R/W. Valid values are: 000 = NOP: Does not affect the current state of the unit. 001 = RU Start: Enables the receive unit. The pointer to the RFA must be placed in the SCB General POinter before using this command. The device pre-fetches the first RFD and the first RBD (if in flexible mode) in preparation to receive incoming frames that pass its address filtering. 010 = RU Resume: Resume frame reception (only when in suspended state). 011 = RCV DMA Redirect: Resume the RCV DMA when configured to “Direct DMA Mode.” The buffers are indicated by an RBD chain which is pointed to by an offset stored in the General Pointer Register (this offset will be added to the RU Base). 100 = RU Abort: Abort RU receive operation immediately. 101 = Load Header Data Size (HDS): This value defines the size of the Header portion of the RFDs or Receive buffers. The HDS value is defined by the lower 14 bits of the SCB General Pointer, so bits 31:15 should always be set to 0’s when using this command. Once a Load HDS command is issued, the device expects only to find Header RFDs, or be used in “RCV Direct DMA mode” until it is reset. Note that the value of HDS should be an even, non-zero number. 110 = Load RU Base: The device’s internal RU Base Register is loaded with the value in the SCB General Pointer. 111 = RBD Resume: Resume frame reception into the RFA. This command should only be used when the RU is already in the “No Resources due to no RBDs” state or the “Suspended with no more RBDs” state. Bit Description

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8.2.3 SCB_GENPNT—System Cont rol Block General Pointer

Register (LAN Controller—B1:D8:F0) Offset Address: 04 –07h Attribute: R/W Default Value: 0000 0000h Size: 32 bits

8.2.4 PORT—PORT Interface Register

(LAN Controller—B1:D8:F0) Offset Address: 08 –0Bh Attribute: R/W (special) Default Value: 0000 0000h Size: 32 bits The PORT interface allows the processor to reset the ICH6’s internal LAN controller, or perform an internal self test. The PORT DWord may be written as a 32-bit entity, two 16-bit entities, or four 8-bit entities. The LAN controller will only accept the command after the high byte (offset 0Bh) is written; therefore, the high byte must be written last. Bit Description 15:0 SCB General Pointer — R/W. The SCB General Pointer register is programmed by software to point to various data structures in main memory depending on the current SCB Command word. Bit Description 31:4 Pointer Field (PORT_PTR) — R/W (special). A 16-byte aligned addre ss must be written to this field when issuing a Self-Test command to the PORT interface.The results of the Self Test will be written to the address specified by this field. 3:0 PORT Function Selection (PORT_FUNC) — R/W (special). Valid values are listed below. All other values are reserved. 0000 = PORT Software Reset: Completely resets the LAN controller (all CSR and PCI registers). This command should not be used when the device is active. If a PORT Software Reset is desired, software should do a Selective Reset (described below), wait for the PORT register to be cleared (completion of the Selective Reset), and then issue the PORT Software Reset command. Software should wait approximately 10 µs after issuing this command before attempting to access the LAN controller’s registers again. 0001 = Self Test: The Self-Test begins by issuing an internal Selective Reset followed by a general internal self-test of the LAN controller. The results of the self-test are written to memory at the address specified in the Pointer field of this register. The format of the self-test result is shown in Table 8-5. After completing the self-test and writing the results to memory, the LAN controller will execute a full internal reset and will re-initialize to the default configuration. Self-Test does not generate an interrupt of similar indicator to the host processor upon completion. 0010 = Selective Reset: Sets the CU and RU to the Idle state, but otherwise maintains the current configuration parameters (RU and CU Base, HDSSize, Error Counters, Configure information and Individual/Multicast Addresses are preserved). Software should wait approximately 10 µs after issuing this command before attempting to access the LAN controller’s registers again.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 299 LAN Controller Registers (B1:D8:F0)

8.2.5 EEPROM_CNTL—EEPROM Control Register

(LAN Controller—B1:D8:F0) Offset Address: 0Eh Attribute: RO, R/W, WO Default Value: 00h Size: 8 bits The EEPROM Control Register is a 16-bit field that enables a read from and a write to the external EEPROM. Table 8-5. Self-Test Results Format Bit Description 31:13 Reserved General Self-Test Result (SELF_TST) — R/W (special). 0 = Pass 1 = Fail 11:6 Reserved Diagnose Result (DIAG_RSLT) — R/W (special). This bit provi des the result of an internal diagnostic test of the Serial Subsystem. 0 = Pass 1 = Fail Register Result (REG_RSLT) — R/W (special). This bit provides the result of a test of the internal Parallel Subsystem registers. 0 = Pass 1 = Fail ROM Content Result (ROM_RSLT) — R/W (special). This bit provides the result of a test of the internal microcode ROM. 0 = Pass 1 = Fail 1:0 Reserved Bit Description 7:4 Reserved EEPROM Serial Data Out (EEDO) — RO. Note that this bit represents “Data Out” from the perspective of the EEPROM device. This bit contains the value read from the EEPROM when performing read operations. EEPROM Serial Data In (EEDI) — WO. Note that this bit represent s “Data In” from the perspective of the EEPROM device. The value of this bit is written to the EEPROM when performing write operations. EEPROM Chip Select (EECS) — R/W. 0 = Drives the ICH6’s EE_CS signal low to disable the EEPROM. this bit must be set to 0 for a minimum of 1 µs between consecutive instruction cycles. 1 = Drives the ICH6’s EE_CS signal high, to enable the EEPROM. EEPROM Serial Clock (EESK) — R/W. Toggling this bi t clocks data into or out of the EEPROM. Software must ensure that this bit is toggled at a rate that meets the EEPROM component’s minimum clock frequency specification. 0 = Drives the ICH6’s EE_SHCLK signal low. 1 = Drives the ICH6’s EE_SHCLK signal high.

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8.2.6 MDI_CNTL—Management Da ta Interface (MDI) Control

Register (LAN Controller—B1:D8:F0) Offset Address: 10 –13h Attribute: R/W (special) Default Value: 0000 0000h Size: 32 bits The Management Data Interface (MDI) Control register is a 32-bit field and is used to read and write bits from the LAN Connect component. This register may be written as a 32-bit entity, two 16-bit entities, or four 8-bit entities. The LAN controller will only accept the command after the high byte (offset 13h) is written; therefore, the high byte must be written last.

8.2.7 REC_DMA_BC—Receive DMA Byte Count Register

(LAN Controller—B1:D8:F0) Offset Address: 14 –17h Attribute: RO Default Value: 0000 0000h Size: 32 bits Bit Description 31:30 These bits are reserved and should be set to 00b. Interrupt Enable — R/W (special). 0 = Disable. 1 = Enables the LAN controller to assert an interrupt to indicate the end of an MDI cycle. Ready — R/W (special). 0 = Expected to be reset by software at the same time the command is written. 1 = Set by the LAN controller at the end of an MDI transaction. 27:26 Opcode — R/W (special). These bits define the opcode: 00 = Reserved 01 = MDI write 10 = MDI read 11 = Reserved 25:21 LAN Connect Address — R/W (special). This field of bits contains the LAN Connect address. 20:16 LAN Connect Register Address — R/W (special). This field contains the LAN Connect Register Address. 15:0 Data — R/W (special). In a write command, software places the data bits in this field, and the LAN controller transfers the data to the external LAN Connect component. During a read command, the LAN controller reads these bits serially from the LAN Connect, and software reads the data from this location. Bit Description 31:0 Receive DMA Byte Count — RO. This field keeps track of how many bytes of receive data have been passed into host memory via DMA.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 301 LAN Controller Registers (B1:D8:F0)

8.2.8 EREC_INTR—Early Receive Interrupt Register

(LAN Controller—B1:D8:F0) Offset Address: 18h Attribute: R/W Default Value: 00h Size: 8 bits The Early Receive Interrupt register allows the internal LAN controller to generate an early interrupt depending on the length of the frame. The LAN controller will generate an interrupt at the end of the frame regardless of whether or not Early Receive Interrupts are enabled. Note: It is recommended that software not use this register unless receive interrupt latency is a critical performance issue in that particular software environment. Using this feature may reduce receive interrupt latency, but will also result in the generation of more interrupts, which can degrade system efficiency and performance in some environments. Bit Description 7:0 Early Receive Count — R/W. When some non-zero value x is programmed into this register, the LAN controller will set the ER bit in the SCB Status Word Register and assert INTA# when the byte count indicates that there are x QWords remaining to be received in the current frame (based on the Type/Length field of the received frame). No Early Receive interrupt will be generated if a value of 00h (the default value) is programmed into this register.

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8.2.9 FLOW_CNTL—Flow Control Register

(LAN Controller—B1:D8:F0) Offset Address: 19 –1Ah Attribute: RO, R/W (special) Default Value: 0000h Size: 16 bits Bit Description 15:13 Reserved FC Paused Low — RO. 0 = Cleared when the FC timer reaches 0, or a Pause frame is received. 1 = Set when the LAN controller receives a Pause Low command with a value greater than 0. FC Paused — RO. 0 = Cleared when the FC timer reaches 0. 1 = Set when the LAN controller receives a Pause command regardless of its cause (FIFO reaching Flow Control Threshold, fetching a Receive Frame Descriptor with its Flow Control Pause bit set, or software writing a 1 to the Xoff bit). FC Full — RO. 0 = Cleared when the FC timer reaches 0. 1 = Set when the LAN controller sends a P ause command with a value greater than 0. Xoff — R/W (special). This bit should only be used if the LAN controller is configured to operate with IEEE frame-based flow control. 0 = This bit can only be cleared by writing a 1 to the Xon bit (bit 8 in this register). 1 = Writing a 1 to this bit forces the Xoff request to 1 and causes the LAN controller to behave as if the FIFO extender is full. This bit will also be set to 1 when an Xoff request due to an “RFD Xoff” bit. Xon — WO. This bit should only be used if the LAN controller is configured to operate with IEEE frame-based flow control. 0 = This bit always returns 0 on reads. 1 = Writing a 1 to this bit resets the Xoff request to the LAN controller, clearing bit 9 in this register. 7:3 Reserved 2:0 Flow Control Threshold — R/W. The LAN controller can gene rate a Flow Control Pause frame when its Receive FIFO is almost full. The value programmed into this field determines the number of bytes still available in the Receive FIFO when the Pause frame is generated. Bits 2:0 Free Bytes in RX FIFO Comment 000b 0.50 KB Fast system (recommended default) 001b 1.00 KB 010b 1.25 KB 011b 1.50 KB 100b 1.75 KB 101b 2.00 KB 110b 2.25 KB 111b 2.50 KB Slow system

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 303 LAN Controller Registers (B1:D8:F0)

8.2.10 PMDR—Power Manage ment Driver Register

(LAN Controller—B1:D8:F0) Offset Address: 1Bh Attribute: R/WC Default Value: 00h Size: 8 bits The ICH6’s internal LAN controller provides an indication in the PMDR that a wake-up event has occurred. Bit Description Link Status Change Indication — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = The link status change bit is set following a change in link status. Magic Packet — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set when a Magic Pa cket is received regardless of the Magic Packet wake-up disable bit in the configuration command and the PME Enable bit in the Power Management Control/ Status Register. Interesting Packet — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set when an “interesting” packet is received. Interesting packets are defined by the LAN controller packet filters. 4:3 Reserved 2 ASF Enabled — RO. This bit is set to 1 when the LAN controller is in ASF mode. TCO Request — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set to 1b when the LAN c ontroller is busy with TCO activity. PME Status — R/WC. This bit is a reflection of the PME Status bit in the Power Management Control/Status Register (PMCSR). 0 = Software clears this bit by wri ting a 1 to it.This also clears the PME Status bit in the PMCSR and de-asserts the PME signal. 1 = Set upon a wake-up event, independent of the PME Enable bit.

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8.2.11 GENCNTL—General Control Register

(LAN Controller—B1:D8:F0) Offset Address: 1Ch Attribute: R/W Default Value: 00h Size: 8 bits

8.2.12 GENSTA—General Status Register

(LAN Controller—B1:D8:F0) Offset Address: 1Dh Attribute: RO Default Value: 00h Size: 8 bits Bit Description 7:4 Reserved. These bits should be set to 0000b. LAN Connect Software Reset — R/W. 0 = Cleared by software to begin normal LAN Connect operating mode. Software must not attempt to access the LAN Connect interface for at least 1ms after clearing this bit. 1 = Software can set this bit to force a reset condition on the LAN Connect interface. 2 Reserved. This bit should be set to 0. Deep Power-Down on Link Down Enable — R/W. 0 = Disable 1 = Enable. The ICH6’s internal LAN controller may enter a deep power-down state (sub-3 mA) in the D2 and D3 power states while the link is down. In this state, the LAN controller does not keep link integrity. This state is not supported for point-to-point connection of two end stations. 0R e s e r v e d Bit Description 7:3 Reserved Duplex Mode — RO. This bit indicates the wire duplex mode. 0 = Half duplex 1 = Full duplex Speed — RO. This bit indicates the wire speed. 0 = 10 Mb/s 1 = 100 Mb/s Link Status Indication — RO. This bit indicates the status of the link. 0 = Invalid 1 = Valid

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 305 LAN Controller Registers (B1:D8:F0)

8.2.13 SMB_PCI—SMB via PCI Register

(LAN Controller—B1:D8:F0) Offset Address: 1Fh Attribute: R/W, RO Default Value: 27h Size: 8 bits Software asserts SREQ when it wants to isolate the PCI-accessible SMBus to the ASF registers/ commands. It waits for SGNT to be asserted. At this point SCLI, SDAO, SCLO, and SDAI can be toggled/read to force ASF controller SMBus transactions without affecting the external SMBus. After all operations are completed, the bus is returned to idle (SCLO=1b,SDAO=1b, SCLI=1b, SDAI=1b), SREQ is released (written 0b). Then SGNT goes low to indicate released control of the bus. The logic in the ASF controller only asserts or de-asserts SGNT at times when it determines that it is safe to switch (all SMBuses that are switched in/out are idle). When in isolation mode (SGNT=1), software can access the ICH6 SMBus slaves that allow configuration without affecting the external SMBus. This includes configuration register accesses and ASF command accesses. However, this capability is not available to the external TCO controller. When SGNT=0, the bit-banging and reads are reflected on the main SMBus and the PCISML_SDA0, PCISML_SCL0 read only bits. Bit Description 7:6 Reserved 5 PCISML_SCLO — RO. SMBus Clock from the ASF controller. 4 PCISML_SGNT — RO. SMBus Isolation Grant from the ASF controller. 3 PCISML_SREQ — R/W. SMBus Isolation Request to the ASF controller. 2 PCISML_SDAO — RO. SMBus Data from the ASF controller. 1 PCISML_SDAI — R/W. SMBus Data to the ASF controller. 0 PCISML_SCLI — R/W. SMBus Clock to the ASF controller.

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8.2.14 Statistical Counters

(LAN Controller—B1:D8:F0) The ICH6’s integrated LAN controller provides information for network management statistics by providing on-chip statistical counters that count a variety of events associated with both transmit and receive. The counters are updated by the LAN controller when it completes the processing of a frame (that is, when it has completed transmitting a frame on the link or when it has completed receiving a frame). The Statistical Counters are reported to the software on demand by issuing the Dump Statistical Counters command or Dump and Reset Statistical Counters command in the SCB Command Unit Command (CUC) field. Table 8-6. Statistical Counters (Sheet 1 of 2) ID Counter Description

0 Transmit Good Frames

This counter contains the number of frames that were transmitted properly on the link. It is updated only after the actual transmission on the link is completed, not when the frame was read from memory as is done for the Transmit Command Block status. Transmit Maximum Collisions (MAXCOL) Errors This counter contains the number of frames that were not transmitted because they encountered the configured maximum number of collisions. Transmit Late Collisions (LATECOL) Errors This counter contains the number of frames that were not transmitted since they encountered a collision later than the configured slot time.

12 Transmit Underrun

A transmit underrun occurs because the system bus cannot keep up with the transmission. This counter contains the number of frames that were either not transmitted or retransmitted due to a transmit DMA underrun. If the LAN controller is configured to retransmit on underrun, this counter may be updated multiple times for a single frame.

16 Transmit Lost Carrier

Sense (CRS) This counter contains the number of frames that were transmitted by the LAN controller despite the fact that it detected the de-assertion of CRS during the transmission.

20 Transmit Deferred This counter contains the number of frames that were deferred before

transmission due to activity on the link.

24 Transmit Single

This counter contains the number of transmitted frames that encountered one collision.

28 Transmit Multiple

This counter contains the number of transmitted frames that encountered more than one collision.

32 Transmit Total

This counter contains the total number of collisions that were encountered while attempting to transmit. This count includes late collisions and frames that encountered MAXCOL.

36 Receive Good Frames

This counter contains the number of frames that were received properly from the link. It is updated only after the actual reception from the link is completed and all the data bytes are stored in memory.

40 Receive CRC Errors

This counter contains the number of aligned frames discarded because of a CRC error. This counter is updated, if needed, regardless of the Receive Unit state. The Receive CRC Errors counter is mutually exclusive of the Receive Alignment Errors and Receive Short Frame Errors counters.

44 Receive Alignment

This counter contains the number of frames that are both misaligned (for example, CRS de-asserts on a non-octal boundary) and contain a CRC error. The counter is updated, if needed, regardless of the Receive Unit state. The Receive Alignment Errors counter is mutually exclusive of the Receive CRC Errors and Receive Short Frame Errors counters.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 307 LAN Controller Registers (B1:D8:F0) The Statistical Counters are initially set to 0 by the ICH6’s integrated LAN controller after reset. They cannot be preset to anything other than 0. The LAN controller increments the counters by internally reading them, incrementing them and writing them back. This process is invisible to the processor and PCI bus. In addition, the counters adhere to the following rules:

• The counters are wrap-around counters. After reaching FFFFFFFFh the counters wrap around to 0.
• The LAN controller updates the required counters for each frame. It is possible for more than one counter to be updated as multiple errors can occur in a single frame.
• The counters are 32 bits wide and their behavior is fully compatible with the IEEE 802.1 standard. The LAN controller supports all mandatory and recommend statistics functions through the status of the receive header and directly through these Statistical Counters. The processor can access the counters by issuing a Dump Statistical Counters SCB command. This provides a “snapshot”, in main memory, of the internal LAN controller statistical counters. The LAN controller supports 21 counters. The dump could consist of the either 16, 19, or all 21 counters, depending on the status of the Extended Statistics Counters and TCO Statistics configuration bits in the Configuration command.

48 Receive Resource

This counter contains the number of good frames discarded due to unavailability of resources. Frames intended for a host whose Receive Unit is in the No Resources state fall into this category. If the LAN controller is configured to Save Bad Frames and the status of the received frame indicates that it is a bad frame, the Receive Resource Errors counter is not updated.

52 Receive Overrun

This counter contains the number of frames known to be lost because the local system bus was not available. If the traffic problem persists for more than one frame, the frames that follow the first are also lost; however, because there is no lost frame indicator, they are not counted.

56 Receive Collision

Detect (CDT) This counter contains the number of frames that encountered collisions during frame reception.

60 Receive Short Frame

This counter contains the number of received frames that are shorter than the minimum frame length. The Receive Short Frame Errors counter is mutually exclusive to the Receive Alignment Errors and Receive CRC Errors counters. A short frame will always increment only the Receive Short Frame Errors counter.

64 Flow Control Transmit

This counter contains the number of Flow Control frames transmitted by the LAN controller. This count includes both the Xoff frames transmitted and Xon (PAUSE(0)) frames transmitted.

68 Flow Control Receive

This counter contains the number of Flow Control frames received by the LAN controller. This count includes both the Xoff frames received and Xon (PAUSE(0)) frames received.

72 Flow Control Receive

This counter contains the number of MAC Control frames received by the LAN controller that are not Flow Control Pause frames. These frames are valid MAC control frames that have the predefined MAC control Type value and a valid address but has an unsupported opcode.

76 Receive TCO Frames This counter contains the number of TCO packets received by the LAN

controller. 78 Transmit TCO Frames This counter contains the number of TCO packets transmitted. Table 8-6. Statistical Counters (Sheet 2 of 2) ID Counter Description

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8.3 ASF Configuration Registers

(LAN Controller—B1:D8:F0) Table 8-7. ASF PCI Configuration Register Address Map (LAN Controller—B1:D8:F0) Offset Mnemonic Register Name Default Type E0h ASF_RID ASF Revision Identification ECh RO E1h SMB_CNTL SMBus Control 40h R/W E2h ASF_CNTL ASF Control 00h R/W, RO E3h ASF_CNTL_EN ASF Control Enable 00h R/W E4h ENABLE Enable 00h R/W E5h APM APM 08h R/W E6–E7h — Reserved — — E8h WTIM_CONF Watchdog Timer Configuration 00h R/W E9h HEART_TIM Heartbeat Timer 02h R/W EAh RETRAN_INT Retransmission Interval 02h R/W EBh RETRAN_PCL Retransmission Packet Count Limit 03h R/W ECh ASF_WTIM1 ASF Watchdog Timer 1 01h R/W EDh ASF_WTIM2 ASF Watchdog Timer 2 00h R/W F0h PET_SEQ1 PET Sequence 1 00h R/W F1h PET_SEQ2 PET Sequence 2 00h R/W F2h STA Status 40h R/W F3h FOR_ACT Forced Actions 02h R/W F4h RMCP_SNUM RMCP Sequence Number 00h R/W F5h SP_MODE Special Modes x0h R/WC, RO F6h INPOLL_TCONF Inter-Poll Timer Configuration 10h R/W F7h PHIST_CLR Poll History Clear 00h R/WC F8h PMSK1 Polling Mask 1 XXh R/W F9h PMSK2 Polling Mask 2 XXh R/W FAh PMSK3 Polling Mask 3 XXh R/W FBh PMSK4 Polling Mask 4 XXh R/W FCh PMSK5 Polling Mask 5 XXh R/W FDh PMSK6 Polling Mask 6 XXh R/W FEh PMSK7 Polling Mask 7 XXh R/W FFh PMSK8 Polling Mask 8 XXh R/W

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 309 LAN Controller Registers (B1:D8:F0)

8.3.1 ASF_RID—ASF Revision Identification Register

(LAN Controller—B1:D8:F0) Offset Address: E0h Attribute: RO Default Value: ECh Size: 8 bits

8.3.2 SMB_CNTL—SMBus Control Register

(LAN Controller—B1:D8:F0) Offset Address: E1h Attribute: R/W Default Value: 40h Size: 8 bits This register is used to control configurations of the SMBus ports. Bit Description 7:3 ASF ID — RO. Hardwired to 11101 to identify the ASF controller. 2:0 ASF Silicon Revision — RO. This field provides the silicon revision. Bit Description SMBus Remote Control ASF Enable (SMB_RCASF) — R/W. 0 = Legacy descriptors and operations are used. 1 = ASF descriptors and operations are used. SMBus ARP Enable (SMB_ARPEN) — R/W. 0 = Disable. 1 = ASF enables the SMBus ARP protocol. 5:4 Reserved SMBus Drive Low (SMB_DRVLO) — R/W. 0 = ASF will not drive the main SM Bus signals low while PWR_GOOD = 0. 1 = ASF will drive the main SMBus signals low while PWR_GOOD = 0. 2:0 Reserved

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8.3.3 ASF_CNTL—ASF Control Register

(LAN Controller—B1:D8:F0) Offset Address: E2h Attribute: R/W, RO Default Value: 00h Size: 8 bits This register contains enables for special modes and SOS events. CTL_PWRLS should be set if ASF should be expecting a power loss due to software action. Otherwise, an EEPROM reload will happen when the power is lost. Bit Description SMBus Hang SOS Enable (CTL_SMBHG) — R/W. 0 = Disable 1 = Enables SMBus Hang SOS to be sent. Watchdog SOS Enable (CTL_WDG) — R/W. 0 = Disable. 1 = Enables Watchdog SOS to be sent. Link Loss SOS Enable (CTL_LINK) — R/W. 0 = Disable. 1 = Enables Link Loss SOS to be sent. OS Hung Status (CTL_OSHUNG) — RO. 1 = This bit will be set to 1 when ASF has detected a Watchdog Expiration. NOTE: This condition is only clearable by a PCI RST# assertion (system reset). Power-Up SOS Enable (CTL_PWRUP) — R/W. 0 = Disable. 1 = Enables Power-Up SOS to be sent. 2R e s e r v e d Receive ARP Enable (CTL_RXARP) — R/W. The LAN controller interface provides a mode where all packets can be requested. 0 = Disable. 1 = Enable. ASF requests all packets when doing a Receive Enable. This is necessary in LAN controller to get ARP packets. NOTE: Changes to this bit will not take effect until the next Receive Enable command to the LAN. Power Loss OK (CTL_PWRLS) — R/W. 0 = Power Loss will reload EEPROM 1 = Power Loss will not reload EEPROM

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 311 LAN Controller Registers (B1:D8:F0)

8.3.4 ASF_CNTL_EN—ASF Co ntrol Enable Register

(ASF Controller—B1:D8:F0) Offset Address: E3h Attribute: R/W Default Value: 00h Size: 8 bits This register is used to enable global processing as well as polling. GLOBAL ENABLE controls all of the SMBus processing and packet creation. Bit Description Global Enable (CENA_ALL) — R/W. 0 = Disable 1 = All control and polling enabled Receive Enable (CENA_RX) — R/W. 0 = Disable 1 = TCO Receives enabled. Transmit Enable (CENA_TX) — R/W. 0 = Disable 1 = SOS and RMCP Transmits enabled ASF Polling Enable (CENA_APOL) — R/W. 0 = Disable 1 = Enable ASF Sensor Polling. Legacy Polling Enable (CENA_LPOL) — R/W. 0 = Disable 1 = Enable Legacy Sensor Polling. 2:0 Number of Legacy Poll Devices (CENA_NLPOL) — R/W. This 3-bit value indicates how many of the eight possible polling descriptors are active. 000 = First polling descriptor is active. 001 = First two polling descriptors are active. ... 111 = Enables all eight descriptors.

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8.3.5 ENABLE—Enable Register

(ASF Controller—B1:D8:F0) Offset Address: E4h Attribute: R/W Default Value: 00h Size: 8 bits This register provides the mechanism to enable internal SOS operations and to enable the remote control functions. Bit Description Enable OSHung ARPs (ENA_OSHARP) — R/W. 0 = Disable 1 = ASF will request all packets when in a OSHung state. This allows ASF to receive ARP frames and respond as appropriate. State-based Security Destination Port Select (ENA_SB0298) — R/W. 0 = State-based security will be honored on packets received on port 026Fh. 1 = Packets received on port 0298h will be honored. PET VLAN Enable (ENA_VLAN) — R/W. 0 = Disable 1 = Indicates a VLAN header for PET NOTE: If this bit is set, the PET packet in EEPROM must have the VLAN tag within the packet. 4R e s e r v e d System Power Cycle Enable (ENA_CYCLE) — R/W. 0 = Disable 1 = Enables RMCP Power Cycle action. System Power-Down Enable (ENA_DWN) — R/W. 0 = Disable 1 = Enables RMCP Power-Down action. System Power-Up Enable (ENA_UP) — R/W. 0 = Disable 1 = Enables RMCP Power-Up action. System Reset Enable (ENA_RST) — R/W. 0 = Disable 1 = Enables RMCP Reset action

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 313 LAN Controller Registers (B1:D8:F0)

8.3.6 APM—APM Register

(ASF Controller—B1:D8:F0) Offset Address: E5h Attribute: R/W Default Value: 08h Size: 8 bits This register contains the configuration bit to disable state-based security.

8.3.7 WTIM_CONF—Watchdog Time r Configuration Register

(ASF Controller—B1:D8:F0) Offset Address: E8h Attribute: R/W Default Value: 00h Size: 8 bits This register contains a single bit that enables the Watchdog timer. This bit is not intended to be accessed by software, but should be configured appropriately in the EEPROM location for this register default. The bit provides real-time control for enabling/disabling the Watchdog timer. When set the timer will count down. When cleared the counter will stop. Timer Start ASF SMBus messages will set this bit. Timer Stop ASF SMBus transactions will clear this bit. Bit Description 7:4 Reserved Disable State-based Security (APM_DISSB) — R/W. 0 = State-based security on OSHung is enabled. 1 = State-based security is disabled and actions are not gated by OSHung. 2:0 Reserved Bit Description 7:1 Reserved Timer Enable (WDG_ENA) — R/W. 0 = Disable 1 = Enable Counter

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8.3.8 HEART_TIM—Heartbeat Timer Register

(ASF Controller—B1:D8:F0) Offset Address: E9h Attribute: R/W Default Value: 02h Size: 8 bits The HeartBeat Timer register implements the heartbeat timer. This defines the period of the heartbeats packets. It contains a down counting value when enabled and the time-out value when the counter is disabled. The timer can be configured and enabled in a single write. Note: The heartbeat timer controls the heartbeat status packet frequency. The timer is free-running and the configured time is only valid from one heartbeat to the next. When enabled by software, the next heartbeat may occur in any amount of time less than the configured time.

8.3.9 RETRAN_INT—Retransmission Interval Register

(ASF Controller—B1:D8:F0) Offset Address: EAh Attribute: R/W Default Value: 02h Size: 8 bits This register implements the retransmission timer. This is the time between packet transmissions for multiple packets due to a SOS. Bit Description 7:1 Heartbeat Timer Value (HBT_VAL) — R/W. Heartbeat timer load value in 10.7-second resolution. This field can only be written while the timer is disabled. (10.7 sec – 23 min range). Read as load value when HBT_ENA=0. Read as decrementing value when HBT_ENA=1. Timer resolution is 10.7 seconds. A value of 00h is invalid. Timer Enable (HBT_ENA) — R/W. 0 = Disable 1 = Enable / Reset Counter Bit Description 7:1 Retransmit Timer Value (RTM_VAL) — R/W. Retransmit timer load value 2.7 second resolution. This field is always writable (2.7 sec – 5.7 min range). Timer is accurate to +0 seconds, – 0.336 seconds. Reads always show the load value (decrement value never shown). A value of 00h is invalid. 0R e s e r v e d

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 315 LAN Controller Registers (B1:D8:F0)

8.3.10 RETRAN_PCL—Retransmi ssion Packet Count Limit

Register (ASF Controller—B1:D8:F0) Offset Address: EBh Attribute: R/W Default Value: 03h Size: 8 bits This register defines the number of packets that are to be sent due to an SOS.

8.3.11 ASF_WTIM1—ASF Watchdog Timer 1 Register

(ASF Controller—B1:D8:F0) Offset Address: ECh Attribute: R/W Default Value: 01h Size: 8 bits This register is used to load the low byte of the timer. When read, it reports the decrementing value. This register is not intended to be written by software, but should be configured appropriately in the EEPROM location for this register default. Timer Start ASF SMBus transactions will load values into this register. Once the timer has expired (0000h), the timer will be disabled (EDG_ENA=0b) and the value in this register will remain at 00h until otherwise changed.

8.3.12 ASF_WTIM2—ASF Watchdog Timer 2 Register

(ASF Controller—B1:D8:F0) Offset Address: EDh Attribute: R/W Default Value: 00h Size: 8 bits This register is used to load the high byte of the timer. When read, it reports the decrementing value. This register is not intended to be written by software, but should be configured appropriately in the EEPROM location for this register default. Timer Start ASF SMBus transactions will load values into this register. Once the timer has expired (0000h), the timer will be disabled (EDG_ENA=0b) and the value in this register will remain at 00h until otherwise changed. Bit Description 7:0 Retransmission Packet Count Limit (RPC_VAL) — R/W. This field provides the number of packets to be sent for all SOS packets that require retransmissions. Bit Description 7:0 ASF Watchdog Timer 1 (AWD1_VAL) — R/W. This field provides the low byte of the ASF 1-second resolution timer. The timer is accurate to +0 seconds, –0.336 seconds. Bit Description 7:0 ASF Watchdog Timer 2 (AWD2_VAL) — R/W. This field provides the high byte of the ASF 1-second resolution timer. The timer is accurate to +0 seconds, –0.336 seconds.

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8.3.13 PET_SEQ1—PET Sequence 1 Register

(ASF Controller—B1:D8:F0) Offset Address: F0h Attribute: R/W Default Value: 00h Size: 8 bits This register (low byte) holds the current value of the PET sequence number. This field is read/ write-able through this register, and is also automatically incremented by the hardware when new PET packets are generated. By policy, software should not write to this register unless transmission is disabled.

8.3.14 PET_SEQ2—PET Sequence 2 Register

(ASF Controller—B1:D8:F0) Offset Address: F1h Attribute: R/W Default Value: 00h Size: 8 bits This register (high byte) holds the current value of the PET sequence number. This field is read/ write-able through this register, and is also automatically incremented by the hardware when new PET packets are generated. By policy, software should not write to this register unless transmission is disabled. Bit Description 7:0 PET Sequence Byte 1 (PSEQ1_VAL) — R/W. This field provides the low byte. Bit Description 7:0 PET Sequence Byte 2 (PSEQ2_VAL) — R/W. This field provides the high byte.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 317 LAN Controller Registers (B1:D8:F0)

8.3.15 STA—Status Register

(ASF Controller—B1:D8:F0) Offset Address: F2h Attribute: R/W Default Value: 40h Size: 8 bits This register gives status indication about several aspects of ASF. Bit Description 7 EEPROM Loading (STA_LOAD) — R/W. EEPROM defaults are in the process of being loaded when this bit is a 1. EEPROM Invalid Checksum Indication (STA_ICRC) — R/W. This bit should be read only after the EEC_LOAD bit is a 0. 0 = Valid 1 = Invalid checksum detected for ASF portion of the EEPROM. 5:4 Reserved Power Cycle Status (STA_CYCLE) — R/W. 0 = Software clears th is bit by writing a 1. 1 = This bit is set when a Power Cycle operation has been issued. Power Down Status (STA_DOWN) — R/W. 0 = Software clears th is bit by writing a 1 1 = This bit is set when a Power Down operation has been issued. Power Up Status (STA_UP) — R/W. 0 = Software clears th is bit by writing a 1 1 = This bit is set when a Powe r Up operation has been issued. System Reset Status (STA_RST) — R/W. 0 = Software clears th is bit by writing a 1 1 = This bit is set when a System Reset operation has been issued.

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8.3.16 FOR_ACT—Forced Actions Register

(ASF Controller—B1:D8:F0) Offset Address: F3h Attribute: R/W Default Value: 02h Size: 8 bits This register contains many different forcible actions including APM functions, flushing internal pending SOS operations, software SOS operations, software reset, and EEPROM reload. Writes to this register must only set one bit per-write. Setting multiple bits in a single write can have indeterminate results. Note: For bits in this register, writing a 1 invokes the operation. The bits self-clear immediately.

8.3.17 RMCP_SNUM—RMCP Sequence Number Register

(ASF Controller—B1:D8:F0) Offset Address: F4h Attribute: R/W Default Value: 00h Size: 8 bits This register is a means for software to read the current sequence number that hardware is using in RMCP packets. Software can also change the value. Software should only write to this register while the GLOBAL ENABLE is off. Bit Description Software Reset (FRC_RST) — R/W. This bit is used to reset the ASF controller. It performs the equivalent of a hardware reset and re-read the EEPROM. This bit self-clears immediately. Software should wait for the EEC_LOAD bit to clear. Force EEPROM Reload (FRC_EELD) — R/W. Force Reload of EEPROM without affect current monitoring state of the ASF controller. This bit self-clears immediately. NOTE: Software registers in EEPROM are not loaded by this action. Software should disable the ASF controller before issuing this command and wait for STA_LOAD to clear before enabling again. Flush SOS (FRC_FLUSH) — R/W. This bit is used to flush any pending SOSes or history internal to the ASF controller. This is necessary because the Status register only shows events that have happened as opposed to SOS events sent. Also, the history bits in the ASF controller are not software visible. Self-clears immediately. 4R e s e r v e d 3 Force APM Power Cycle (FRC_ACYC) — R/W. This mode forces the ASF controller to initiate a power cycle to the system. The bit self-clears immediately. 2 Force APM Hard Power Down (FRC_AHDN) — R/W. This mode forces the ASF controller to initiate a hard power down of the system immediately. The bit self-clears immediately. Clear ASF Polling History (FRC_CLRAPOL) — R/W. Writing a 1b to this bit position will clear the Poll History associated with all ASF Polling. Writing a 0b has no effect. This bit self-clears immediately. 0 Force APM Reset (FRC_ARST) — R/W. This mode forces the ASF controller to initiate a hard reset of the system immediately. The bit self-clears immediately. Bit Description 7:0 RMCP Sequence Number (RSEQ_VAL) — R/W. This is the current sequence number of the RMCP packet being sent or the sequence number of the next RMCP packet to be sent. This value can be set by software. At reset, it defaults to 00h. If the sequence number is not FFh, the ASF controller will automatically increment this number by one (or rollover to 00h if incrementing from FEh) after a successful RMCP packet transmission.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 319 LAN Controller Registers (B1:D8:F0)

8.3.18 SP_MODE—Special Modes Register

(ASF Controller—B1:D8:F0) Offset Address: F5h Attribute: R/WC, RO Default Value: x0h Size: 8 bits The register contains miscellaneous functions.

8.3.19 INPOLL_TCONF—Inter-Poll Timer Configuration Register

(ASF Controller—B1:D8:F0) Offset Address: F6h Attribute: R/W Default Value: 10h Size: 8 bits This register is used to load and hold the value (in increments of 5 ms) for the polling timer. This value determines how often the ASF polling timer expires which determines the minimum idle time between sensor polls. Bit Description SMBus Activity Bit (SPE_ACT) — RO. 1 = ASF controller is active with a SMBus transacti on. This is an indicator to software that the ASF controller is still processing commands on the SMBus. Watchdog Status (SPE_WDG) — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set when a watchdog expiration occurs. Link Loss Status (SPE_LNK) — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set when a link loss occurs (link is down for more than 5 seconds). 4:0 Reserved Bit Description 7:0 Inter-Poll Timer Configuration (IPTC_VAL) — R/W. This field identifie s the time, in 5.24 ms units that the ASF controller will wait between the end of the one ASF Poll Alert Message to start on the next. The value 00h is illegal and unsupported.

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8.3.20 PHIST_CLR—Poll Hi story Clear Register

(ASF Controller—B1:D8:F0) Offset Address: F7h Attribute: R/WC Default Value: 00h Size: 8 bits This register is used to clear the history of the Legacy Poll operations. ASF maintains history of the last poll data for each Legacy Poll operation to compare against the current poll to detect changes. By setting the appropriate bit, the history for that Legacy Poll is cleared to 0s.

8.3.21 PMSK1—Polling Mask 1 Register

(ASF Controller—B1:D8:F0) Offset Address: F8h Attribute: R/W Default Value: XXh Size: 8 bits This register provides software an interface for the Polling #1 Data Mask. Bit Description 7 Clear Polling Descriptor 8 History (PHC_POLL8) — R/WC. Writing a 1b to this bit position will clear the Poll History associated with Polling Descriptor #8. Writing a 0b has no effect. 6 Clear Polling Descriptor 7 History (PHC_POLL7) — R/WC. Writing a 1b to this bit position will clear the Poll History associated with Polling Descriptor #7. Writing a 0b has no effect. 5 Clear Polling Descriptor 6 History (PHC_POLL6) — R/WC. Writing a 1b to this bit position will clear the Poll History associated with Polling Descriptor #6. Writing a 0b has no effect. 4 Clear Polling Descriptor 5 History (PHC_POLL5) — R/WC. Writing a 1b to this bit position will clear the Poll History associated with Polling Descriptor #5. Writing a 0b has no effect. 3 Clear Polling Descriptor 4 History (PHC_POLL4) — R/WC. Writing a 1b to this bit position will clear the Poll History associated with Polling Descriptor #4. Writing a 0b has no effect. 2 Clear Polling Descriptor 3 History (PHC_POLL3) — R/WC. Writing a 1b to this bit position will clear the Poll History associated with Polling Descriptor #3. Writing a 0b has no effect. 1 Clear Polling Descriptor 2 History (PHC_POLL2) — R/WC. Writing a 1b to this bit position will clear the Poll History associated with Polling Descriptor #2. Writing a 0b has no effect. 0 Clear Polling Descriptor 1 History (PHC_POLL1) — R/WC. Writing a 1b to this bit position will clear the Poll History associated with Polling Descriptor #1. Writing a 0b has no effect. Bit Description 7:0 Polling Mask for Polling Descriptor #1 (POL1_MSK) — R/W. This field is used to read and write the data mask for Polling Descriptor #1. Software should only access this register when the ASF controller is GLOBAL DISABLED.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 321 LAN Controller Registers (B1:D8:F0)

8.3.22 PMSK2—Polling Mask 2 Register

(ASF Controller—B1:D8:F0) Offset Address: F9h Attribute: R/W Default Value: XXh Size: 8 bits This register provides software an interface for the Polling #2 Data Mask.

8.3.23 PMSK3—Polling Mask 3 Register

(ASF Controller—B1:D8:F0) Offset Address: FAh Attribute: R/W Default Value: XXh Size: 8 bits This register provides software an interface for the Polling #3 Data Mask.

8.3.24 PMSK4—Polling Mask 4 Register

(ASF Controller—B1:D8:F0) Offset Address: FBh Attribute: R/W Default Value: XXh Size: 8 bits This register provides software an interface for the Polling #4 Data Mask. Bit Description 7:0 Polling Mask for Polling Descriptor #2 (POL2_MSK) — R/W. This field is used to read and write the data mask for Polling Descriptor #2. Software should only access this register when the ASF controller is GLOBAL DISABLED. Bit Description 7:0 Polling Mask for Polling Descriptor #3 (POL3_MSK) — R/W. This register is used to read and write the data mask for Polling Descriptor #3. Software should only access this register when the ASF controller is GLOBAL DISABLED. Bit Description 7:0 Polling Mask for Polling Descriptor #4 (POL4_MSK) — R/W. This register is used to read and write the data mask for Polling Descriptor #4. Software should only access this register when the ASF controller is GLOBAL DISABLED.

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8.3.25 PMSK5—Polling Mask 5 Register

(ASF Controller—B1:D8:F0) Offset Address: FCh Attribute: R/W Default Value: XXh Size: 8 bits This register provides software an interface for the Polling #5 Data Mask.

8.3.26 PMSK6—Polling Mask 6 Register

(ASF Controller—B1:D8:F0) Offset Address: FDh Attribute: R/W Default Value: XXh Size: 8 bits This register provides software an interface for the Polling #6 Data Mask.

8.3.27 PMSK7—Polling Mask 7 Register

(ASF Controller—B1:D8:F0) Offset Address: FEh Attribute: R/W Default Value: XXh Size: 8 bits This register provides software an interface for the Polling #7 Data Mask. Bit Description 7:0 Polling Mask for Polling Descriptor #5 (POL5_MSK) — R/W. This register is used to read and write the data mask for Polling Descriptor #5. Software should only access this register when the ASF controller is GLOBAL DISABLED. Bit Description 7:0 Polling Mask for Polling Descriptor #6 (POL6_MSK) — R/W. This register is used to read and write the data mask for Polling Descriptor #6. Software should only access this register when the ASF controller is GLOBAL DISABLED. Bit Description 7:0 Polling Mask for Polling Descriptor #7 (POL7_MSK) — R/W. This register is used to read and write the data mask for Polling Descriptor #7. Software should only access this register when the ASF controller is GLOBAL DISABLED.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 323 LAN Controller Registers (B1:D8:F0)

8.3.28 PMSK8—Polling Mask 8 Register

(ASF Controller—B1:D8:F0) Offset Address: FFh Attribute: R/W Default Value: XXh Size: 8 bits This register provides software an interface for the Polling #8 Data Mask. Bit Description 7:0 Polling Mask for Polling Descriptor #8 (POL8_MSK) — R/W. This register is used to read and write the data mask for Polling Descriptor #8. Software should only access this register when the ASF controller is GLOBAL DISABLED.

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Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 325 PCI-to-PCI Bridge Registers (D30:F0)

9 PCI-to-PCI Bridge Registers

(D30:F0) The ICH6 PCI bridge resides in PCI Device 30, Function 0 on bus #0. This implements the buffering and control logic between PCI and the backbone. The arbitration for the PCI bus is handled by this PCI device.

9.1 PCI Configuration Registers (D30:F0)

Note: Address locations that are not shown should be treated as Reserved (see Section 6.2 for details). Table 9-1. PCI Bridge Register Address Map (PCI-PCI—D30:F0) (Sheet 1 of 2) Offset Mnemonic Register Name Default Type 00–01h VID Vendor Identification 8086h RO 02–03h DID Device Identification 244Eh (Desktop) 2448h (ICH6-M) RO 04–05h PCICMD PCI Command 0000h R/W, RO 06–07h PSTS PCI Status 0010h R/WC, RO 08h RID Revision Identification See register description. RO 09-0Bh CC Class Code 060401h RO 0Dh PMLT Primary Master Latency Timer 00h RO 0Eh HEADTYP Header Type 81h RO 18-1Ah BNUM Bus Number 000000h R/W, RO 1Bh SMLT Secondary Master Latency Timer 00h R/W, RO 1C-1Dh IOBASE_LIMIT I/O Base and Limit 0000h R/W, RO 1E–1Fh SECSTS Secondary Status 0280h R/WC, RO 20–23h MEMBASE_LIMIT Memory Base and Limit 00000000h R/W, RO 24–27h PREF_MEM_BASE _LIMIT Prefetchable Memory Base and Limit 00010001h R/W, RO 28–2Bh PMBU32 Prefetchable Memory Upper 32 Bits 00000000h R/W 2C–2Fh PMLU32 Prefetchable Memory Limit Upper 32 Bits 00000000h R/W 34h CAPP Capability List Pointer 50h RO 3C-3Dh INTR Interrupt Information 0000h R/W, RO 3E–3Fh BCTRL Bridge Control 0000h R/WC, RO 40–41h SPDH Secondary PCI Device Hiding 00h R/W, RO

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9.1.1 VID— Vendor Identificati on Register (PCI-PCI—D30:F0)

Offset Address: 00–01h Attribute: RO Default Value: 8086h Size: 16 bits

9.1.2 DID— Device Identification Register (PCI-PCI—D30:F0)

Offset Address: 02–03h Attribute: RO Default Value: 2448h (Mobile) Size: 16 bits 244Eh (Desktop) 42h PDPR PCI Decode Policy Register 00h R/W 44-47h DTC Delayed Transaction Control 00000000h R/W, RO 48-4B BTS Bridge Proprietary Status 00000000h R/WC, RO 4C-4F BPC Bridge Policy Configuration 00000000h R/W RO 50–51h SVCAP Subsystem Vendor Capability Pointer 000Dh RO 54-57 SVID Subsystem Vendor IDs 00000000 R/WO Table 9-1. PCI Bridge Register Address Map (PCI-PCI—D30:F0) (Sheet 2 of 2) Offset Mnemonic Register Name Default Type Bit Description 15:0 Vendor ID — RO. This is a 16-bit va lue assigned to Intel. Intel VID = 8086h. Bit Description 15:0 Device ID — RO.This is a 16-bit value assigned to the PCI bridge. Mobile = 2448h (ICH6-M) Desktop = 244Eh (ICH6, ICH6R)

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 327 PCI-to-PCI Bridge Registers (D30:F0)

9.1.3 PCICMD—PCI Command (PCI-PCI—D30:F0)

Offset Address: 04 –05h Attribute: R/W, RO Default Value: 0000h Size: 16 bits Bit Description 15:11 Reserved 10 Interrupt Disable (ID) — RO. Hardwired to 0. The PCI bridge has no interrupts to disable 9 Fast Back to Back Enable (FBE) — RO. Hardwired to 0, per the PCI Express* Base Specification, Revision 1.0a. SERR# Enable (SERR_EN) — R/W. 0 = Disable. 1 = Enable the ICH6 to generate an NMI (or SMI# if NMI routed to SMI#) when the D30:F0 SSE bit (offset 06h, bit 14) is set. 7 Wait Cycle Control (WCC) — RO. Hardwired to 0, per the PCI Express* Base Specification, Revision 1.0a. Parity Error Response (PER) — R/W. 0 = The ICH6 ignores parity errors on the PCI bridge. 1 = The ICH6 will set the SSE bit (D30:F0, offset 06h, bit 14) when parity errors are detected on the PCI bridge. 5 VGA Palette Snoop (VPS) — RO. Hardwired to 0, per the PCI Express* Base Specification, Revision 1.0a. 4 Memory Write and Invalidate Enable (MWE) — RO. Hardwired to 0, per the PCI Express* Base Specification, Revision 1.0a 3 Special Cycle Enable (SCE) — RO. Hardwired to 0, per the PCI Express* Base Specification, Revision 1.0a and the PCI- to-PCI Bridge Specification. Bus Master Enable (BME) — R/W. 0 = Disable 1 = Enable. Allows the PCI-to-PCI bridge to accept cycles from PCI. Memory Space Enable (MSE) — R/W. Controls the response as a target for memory cycles targeting PCI. 0 = Disable 1 = Enable I/O Space Enable (IOSE) — R/W. Controls the response as a target for I/O cycles targeting PCI. 0 = Disable 1 = Enable

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9.1.4 PSTS—PCI Status Re gister (PCI-PCI—D30:F0)

Offset Address: 06 –07h Attribute: R/WC, RO Default Value: 0010h Size: 16 bits Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no effect. Bit Description Detected Parity Error (DPE) — R/WC. 0 = Parity error Not detected. 1 = Indicates that the ICH6 detected a parity error on the internal backbone. This bit gets set even if the Parity Error Response bit (D30:F0:04 bit 6) is not set. Signaled System Error (SSE) — R/WC. Several internal and external sources of the bridge can cause SERR#. The first class of errors is parity errors related to the backbone. The PCI bridge captures generic data parity errors (errors it finds on the backbone) as well as errors returned on backbone cycles where the bridge was the master. If either of these two conditions is met, and the primary side of the bridge is enabled for parity error response, SERR# will be captured as shown below. As with the backbone, the PCI bus captures the same sets of errors. The PCI bridge captures generic data parity errors (errors it finds on PCI) as well as errors returned on PCI cycles where the bridge was the master. If either of these two conditions is met, and the secondary side of the bridge is enabled for parity error response, SERR# will be captured as shown below. The final class of errors is system bus errors. There are three status bits associated with system bus errors, each with a corresponding enable. The diagram capturing this is shown below. After checking for the three above classes of errors, an SERR# is generated, and PSTS.SSE logs the generation of SERR#, if CMD.SEE (D30:F0:04, bit 8) is set, as shown below.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 329 PCI-to-PCI Bridge Registers (D30:F0)

9.1.5 RID—Revision Identificati on Register (PCI-PCI—D30:F0)

Offset Address: 08h Attribute: RO Default Value: See bit description Size: 8 bits

9.1.6 CC—Class Code Register (PCI-PCI—D30:F0)

Offset Address: 09-0Bh Attribute: RO Default Value: 060401h Size: 32 bits Received Master Abort (RMA) — R/WC. 0 = No master abort received. 1 = Set when the bridge receives a master abort status from the backbone. Received Target Abort (RTA) — R/WC. 0 = No target abort received. 1 = Set when the bridge receives a target abort status from the backbone. Signaled Target Abort (STA) — R/WC. 0 = No signaled target abort 1 = Set when the bridge generates a completion pa cket with target abort status on the backbone. 10:9 Reserved. Data Parity Error Detected (DPD) — R/WC. 0 = Data parity error Not detected. 1 = Set when the bridge receives a completion pa cket from the backbone from a previous request, and detects a parity error, and CMD.PERE is set (D30:F0:04 bit 6). 7:5 Reserved. 4 Capabilities List (CLIST) — RO. Hardwired to 1. Capability list exist on the PCI bridge. 3 Interrupt Status (IS) — RO. Hardwired to 0. The PCI bridge does not generate interrupts. 2:0 Reserved I/O Space Enable (IOSE) — R/W. Controls the response as a target for I/O cycles targeting PCI. 0 = Disable 0 = Enable Bit Description Bit Description 7:0 Revision ID — RO. Refer to the Intel® I/O Controller Hub 6 (ICH6) Family Specification Update for the value of the Revision ID Register Bit Description 23:16 Base Class Code (BCC) — RO. Hardwired to 06h. Indicates this is a bridge device. 15:8 Sub Class Code (SCC) — RO. Hardwired to 04h. Indicates this device is a PCI-to-PCI bridge. 7:0 Programming Interface (PI) — RO. Hardwired to 01h. Indicates the bridge is subtractive decode

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9.1.7 PMLT—Primary Master Latency Timer Register

(PCI-PCI—D30:F0) Offset Address: 0Dh Attribute: RO Default Value: 00h Size: 8 bits

9.1.8 HEADTYP—Header Type Register (PCI-PCI—D30:F0)

Offset Address: 0Eh Attribute: RO Default Value: 81h Size: 8 bits

9.1.9 BNUM—Bus Number Re gister (PCI-PCI—D30:F0)

Offset Address: 18-1Ah Attribute: R/W, RO Default Value: 000000h Size: 24 bits Bit Description 7:3 Master Latency Timer Count (MLTC) — RO. Reserved per the PCI Express* Base Specification, Revision 1.0a. 2:0 Reserved Bit Description Multi-Function Device (MFD) — RO. The value reported here depends upon the state of the AC ‘97 function hide (FD) register (Chipset Configuration Registers:Offset 3418h), per the following table: 6:0 Header Type (HTYPE) — RO. This 7-bit field identifie s the header layout of the configuration space, which is a PCI-to-PCI bridge in this case. FD.AAD FD.AMD MFD 00 1 01 1 10 1 11 0 Bit Description 23:16 Subordinate Bus Number (SBBN) — R/W. Indicates the highest PCI bus number below the bridge. 15:8 Secondary Bus Number (SCBN) — R/W. Indicates the bus number of PCI. 7:0 Primary Bus Number (PBN) — RO. Hardwired to 00h for legacy software compatibility.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 331 PCI-to-PCI Bridge Registers (D30:F0)

9.1.10 SMLT—Secondary Maste r Latency Timer Register

(PCI-PCI—D30:F0) Offset Address: 1Bh Attribute: R/W, RO Default Value: 00h Size: 8 bits This timer controls the amount of time the ICH6 PCI-to-PCI bridge will burst data on its secondary interface. The counter starts counting down from the assertion of FRAME#. If the grant is removed, then the expiration of this counter will result in the de-assertion of FRAME#. If the grant has not been removed, then the ICH6 PCI-to-PCI bridge may continue ownership of the bus.

9.1.11 IOBASE_LIMIT—I/O Base and Limit Register

(PCI-PCI—D30:F0) Offset Address: 1C-1Dh Attribute: R/W, RO Default Value: 0000h Size: 16 bits Bit Description 7:3 Master Latency Timer Count (MLTC) — R/W. This 5-bit field indicates the number of PCI clocks, in 8-clock increments, that the ICH6 remains as master of the bus. 2:0 Reserved Bit Description 15:12 I/O Limit Address Limit bits[15:12] — R/W. I/O These base address bits corresponding to address lines 15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to FFFh. 11:8 II/O Limit Address Capability (IOLC) — RO. This field indicates that the bridge does not support 32- bit I/O addressing. 7:4 I/O Base Address (IOBA) — R/W. These I/O Base address bits corresponding to address lines 15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to 000h. 3:0 I/O Base Address Capability (IOBC) — RO. This fi eld indicates that the bridge does not support 32- bit I/O addressing.

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9.1.12 SECSTS—Secondary Statu s Register (PCI-PCI—D30:F0)

Offset Address: 1E –1Fh Attribute: R/WC, RO Default Value: 0280h Size: 16 bits Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no effect. Bit Description Detected Parity Error (DPE) — R/WC. 0 = Parity error not detected. 1 = Intel ® ICH6 PCI bridge detected an address or data parity error on the PCI bus Received System Error (RSE) — R/WC. 0 = SERR# assertion not received 1 = SERR# assertion is received on PCI. Received Master Abort (RMA) — R/WC. 0 = No master abort. 1 = This bit is set whenever the bridge is acting as an initiator on the PCI bus and the cycle is master-aborted. For (G)MCH/ICH6 interface packets that have completion required, this must also cause a target abort to be returned and sets PSTS.STA. (D30:F0:06 bit 11) Received Target Abort (RTA) — R/WC. 0 = No target abort. 1 = This bit is set whenever the br idge is acting as an initiator on PCI and a cycle is target-aborted on PCI. For (G)MCH/ICH6 interface packets that have completion required, this event must also cause a target abort to be returned, and sets PSTS.STA. (D30:F0:06 bit 11). Signaled Target Abort (STA) — R/WC. 0 = No target abort. 1 = This bit is set when the bridge is acting as a target on the PCI Bus and signals a target abort. 10:9 DEVSEL# Timing (DEVT) — RO. 01h = Medium decode timing. Data Parity Error Detected (DPD) — R/WC. 0 = Conditions described below not met. 1 = The ICH6 sets this bit when all of the following three conditions are met:

• The bridge is the initiator on PCI.
• PERR# is detected asserted or a parity error is detected internally
• BCTRL.PERE (D30:F0:3E bit 0) is set. 7 Fast Back to Back Capable (FBC) — RO. Hardwired to 1 to indicate that the PCI to PCI target logic is capable of receiving fast back-to-back cycles. 6R e s e r v e d 5 66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0. This bridge is 33 MHz capable only. 4:0 Reserved

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 333 PCI-to-PCI Bridge Registers (D30:F0)

9.1.13 MEMBASE_LIMIT—Memory Base and Limit Register

(PCI-PCI—D30:F0) Offset Address: 20–23h Attribute: R/W, RO Default Value: 00000000h Size: 32 bits This register defines the base and limit, aligned to a 1-MB boundary, of the non-prefetchable memory area of the bridge. Accesses that are within the ranges specified in this register will be sent to PCI if CMD.MSE is set. Accesses from PCI that are outside the ranges specified will be accepted by the bridge if CMD.BME is set.

9.1.14 PREF_MEM_BASE_LIMIT— Prefetchable Memory Base

and Limit Register (PCI-PCI—D30:F0) Offset Address: 24–27h Attribute: R/W, RO Default Value: 00010001h Size: 32-bit Defines the base and limit, aligned to a 1-MB boundary, of the prefetchable memory area of the bridge. Accesses that are within the ranges specified in this register will be sent to PCI if CMD.MSE is set. Accesses from PCI that are outside the ranges specified will be accepted by the bridge if CMD.BME is set. Bit Description 31-20 Memory Limit (ML) — R/W. These bits are compared wi th bits 31:20 of the incoming address to determine the upper 1-MB aligned value (exclusive) of the range. The incoming address must be less than this value. 19-16 Reserved 15:4 Memory Base (MB) — R/W. These bits are compared with bits 31:20 of the incoming address to determine the lower 1-MB aligned value (inclusive) of the range. The incoming address must be greater than or equal to this value. 3:0 Reserved Bit Description 31-20 Prefetchable Memory Limit (PML) — R/W. These bits are compared with bits 31:20 of the incoming address to determine the upper 1-MB aligned value (exclusive) of the range. The incoming address must be less than this value. 19-16 64-bit Indicator (I64L) — RO. This field indicates support for 64-bit addressing. 15:4 Prefetchable Memory Base (PMB) — R/W. These bits are compared with bits 31:20 of the incoming address to determine the lower 1-MB aligned value (inclusive) of the range. The incoming address must be greater than or equal to this value. 3:0 64-bit Indicator (I64B) — RO. This field indicates support for 64-bit addressing.

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9.1.15 PMBU32—Prefetchable Me mory Base Upper 32 Bits

Register (PCI-PCI—D30:F0) Offset Address: 28–2Bh Attribute: R/W Default Value: 00000000h Size: 32 bits

9.1.16 PMLU32—Prefetchable Me mory Limit Upper 32 Bits

Register (PCI-PCI—D30:F0) Offset Address: 2C–2Fh Attribute: R/W Default Value: 00000000h Size: 32 bits

9.1.17 CAPP—Capability List Poin ter Register (PCI-PCI—D30:F0)

Offset Address: 34h Attribute: RO Default Value: 50h Size: 8 bits

9.1.18 INTR—Interrupt Informat ion Register (PCI-PCI—D30:F0)

Offset Address: 3C –3Dh Attribute: R/W, RO Default Value: 0000h Size: 16 bits Bit Description 31:0 Prefetchable Memory Base Upper Portion (PMBU) — R/W. This field pr ovides the upper 32-bits of the prefetchable address base. Bit Description 31:0 Prefetchable Memory Limit Upper Portion (PMLU) — R/W. This field provides the upper 32-bits of the prefetchable address limit. Bit Description 7:0 Capabilities Pointer (PTR) — RO. This field indicates that the pointer for the first entry in the capabilities list is at 50h in configuration space. Bit Description 15:8 Interrupt Pin (IPIN) — RO. The PCI bridge does not assert an interrupt. 7:0 Interrupt Line (ILINE) — R/W. Software written value to indi cate which interrupt line (vector) the interrupt is connected to. No hardware action is taken on this register. Since the bridge does not generate an interrupt, BIOS should program this value to FFh as per the PCI bridge specification.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 335 PCI-to-PCI Bridge Registers (D30:F0)

9.1.19 BCTRL—Bridge Control Register (PCI-PCI—D30:F0)

Offset Address: 3E –3Fh Attribute: R/WC, RO Default Value: 0000h Size: 16 bits Bit Description 15:12 Reserved Discard Timer SERR# Enable (DTE) — R/W. This bit controls the generation of SERR# on the primary interface in response to the DTS bit being set: 0 = Do not generate SERR# on a secondary timer discard 1 = Generate SERR# in response to a secondary timer discard 10 Discard Timer Status (DTS) — R/WC. This bit is set to 1 wh en the secondary discard timer (see the SDT bit below) expires for a delayed transaction in the hard state. Secondary Discard Timer (SDT) — R/W. This bit sets the maxi mum number of PCI clock cycles that the Intel® ICH6 waits for an initiator on PCI to repeat a delayed transaction request. The counter starts once the delayed transaction data is has been returned by the system and is in a buffer in the ICH6 PCI bridge. If the master has not repeated the transaction at least once before the counter expires, the ICH6 PCI bridge discards the transaction from its queue. 0 = The PCI master timeout value is between 2 15 and 216 PCI clocks 1 = The PCI master timeout value is between 2 10 and 211 PCI clocks 8 Primary Discard Timer (PDT) — R/W. This bit is R/W for software compatibility only. 7 Fast Back to Back Enable (FBE) — RO. Hardwired to 0. The PCI logic will not generate fast back-to- back cycles on the PCI bus. Secondary Bus Reset (SBR) — R/W. This bit controls PCIRST# assertion on PCI. 0 = Bridge de-asserts PCIRST# 1 = Bridge asserts PCIRST#. When PCIRST# is asse rted, the delayed transaction buffers, posting buffers, and the PCI bus are initialized back to reset conditions. The rest of the part and the configuration registers are not affected. Note: When PCIRST# is asserted by setting this bit, the PCI bus will be in reset. PCI transactions will not be able to complete while this bit is set. When cleared, the bus will exit the reset state and transactions can be completed. Master Abort Mode (MAM) — R/W. This bit controls the IC H6 PCI bridge’s behavior when a master abort occurs: Master Abort on (G)MCH/ICH6 Interconnect (DMI): 0 = Bridge asserts TRDY# on PCI. It drives all 1s for reads, and discards data on writes. 1 = Bridge returns a target abort on PCI. Master Abort PCI (non-locked cycles): 0 = Normal completion status will be returned on the (G)MCH/ICH6 interconnect. 1 = Target abort completion status will be returned on the (G)MCH/ICH6 interconnect. NOTE: All locked reads will return a completer abort completion status on the (G)MCH/ICH6 interconnect. VGA 16-Bit Decode (V16D) — R/W. Enables the ICH6 PCI bri dge to provide 16-bits decoding of VGA I/O address precluding the decode of VGA alias addresses every 1 KB. This bit requires the VGAE bit in this register be set.

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9.1.20 SPDH—Secondary PCI Device Hiding Register

(PCI-PCI—D30:F0) Offset Address: 40–41h Attribute: R/W, RO Default Value: 00h Size: 16 bits This register allows software to hide the PCI devices, either plugged into slots or on the motherboard. VGA Enable (VGAE) — R/W. When set to a 1, the ICH6 PCI bridge forwards the following transactions to PCI regardless of the value of the I/O base and limit registers. The transactions are qualified by CMD.MSE (D30:F0:04 bit 1) and CMD.IOSE (D30:F0:04 bit 0) being set.

• Memory addresses: 000A0000h-000BFFFFh
• I/O addresses: 3B0h-3BBh and 3C0h-3DFh. For the I/O addresses, bits [63:16] of the address must be 0, and bits [15:10] of the address are ignored (i.e., aliased). The same holds true from secondary accesses to the primary interface in reverse. That is, when the bit is 0, memory and I/O addresses on the secondary interface between the above ranges will be claimed. ISA Enable (IE) — R/W. This bit only applies to I/O address es that are enabled by the I/O Base and I/O Limit registers and are in the first 64 KB of PCI I/O space. If this bit is set, the ICH6 PCI bridge will block any forwarding from primary to secondary of I/O transactions addressing the last 768 bytes in each 1-KB block (offsets 100h to 3FFh). SERR# Enable (SEE) — R/W. This bit controls the forwarding of secondary interface SERR# assertions on the primary interface. When set, the PCI bridge will forward SERR# pin.
• SERR# is asserted on the secondary interface.
• This bit is set.
• CMD.SEE (D30:F0:04 bit 8) is set. Parity Error Response Enable (PERE) — R/W. 0 = Disable 1 = The ICH6 PCI bridge is enabled for parity error reporting based on parity errors on the PCI bus. Bit Description Bit Description 15:8 Reserved 7 Hide Device 7 (HD7) — R/W, RO. Same as bit 0 of this register, except for device 7 (AD[23]) 6 Hide Device 6 (HD6) — R/W, RO. Same as bit 0 of this register, except for device 6 (AD[22]) 5 Hide Device 5 (HD5) — R/W, RO. Same as bit 0 of this register, except for device 5 (AD[21]) 4 Hide Device 4 (HD4) — R/W, RO. Same as bit 0 of this register, except for device 4 (AD[20]) 3 Hide Device 3 (HD3) — R/W, RO. Same as bit 0 of this register, except for device 3 (AD[19]) 2 Hide Device 2 (HD2) — R/W, RO. Same as bit 0 of this register, except for device 2 (AD[18]) 1 Hide Device 1 (HD1) — R/W, RO. Same as bit 0 of this register, except for device 1 (AD[17]) Hide Device 0 (HD0) — R/W, RO. 0 = The PCI configuration cycles for this slot are not affected. 1 = Intel ® ICH6 hides device 0 on the PCI bus. This is done by masking the IDSEL (keeping it low) for configuration cycles to that device. Since the device will not see its IDSEL go active, it will not respond to PCI configuration cycles and the processor will think the device is not present. AD[16] is used as IDSEL for device 0.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 337 PCI-to-PCI Bridge Registers (D30:F0)

9.1.21 PDPR—PCI Deco de Policy Register

(PCI-PCI—D30:F0) Offset Address: 42h Attribute: R/W Default Value: 00h Size: 8 bits Bit Description 7:1 Reserved Subtractive Decode Policy (SDP) — R/W. 0 = The PCI bridge always forwards memory and I/O cycles that are not claimed by any other device on the backbone (primary interface) to the PCI bus (secondary interface). 1 = The PCI bridge will not claim and forward memo ry or I/O cycles at all unless the corresponding Space Enable bit is set in the Command register. NOTE: The Boot BIOS Destination Selection strap can force the BIOS accesses to PCI.

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9.1.22 DTC—Delayed Transaction Control Register

(PCI-PCI—D30:F0) Offset Address: 44 –47h Attribute: R/W, RO Default Value: 00000000h Size: 32 bits Bit Description Discard Delayed Transactions (DDT) — R/W. 0 = Logged delayed transactions are kept. 1 = The ICH6 PCI bridge will discard any delay ed transactions it has logged. This includes transactions in the pending queue, and any transactions in the active queue, whether in the hard or soft DT state. The prefetchers will be disabled and return to an idle state. NOTE: If a transaction is running on PCI at the time this bit is set, that transaction will continue until either the PCI master disconnects (by de-asserting FRAME#) or the PCI bridge disconnects (by asserting STOP#). This bit is cleared by the PCI bridge when the delayed transaction queues are empty and have returned to an idle state. Software sets this bit and polls for its completion Block Delayed Transactions (BDT) — R/W. 0 = Delayed transactions accepted 1 = The ICH6 PCI bridge will not accept incomi ng transactions which will result in delayed transactions. It will blindly retry these cycles by asserting STOP#. All postable cycles (memory writes) will still be accepted. 29: 8 Reserved 7: 6 Maximum Delayed Transactions (MDT) — R/W. Controls the maximum number of delayed transactions that the ICH6 PCI bridge will run. Encodings are: 00 =) 2 Active, 5 pending 01 =) 2 active, no pending 10 =) 1 active, no pending 11 =) Reserved

5 Reserved

Auto Flush After Disconnect Enable (AFADE) — R/W. 0 = The PCI bridge will retain any fetched data until required to discard by producer/consumer rules. 1 = The PCI bridge will flush any prefetched data after either the PCI master (by de-asserting FRAME#) or the PCI bridge (by asserting STOP#) disconnects the PCI transfer. Never Prefetch (NP) — R/W. 0 = Prefetch enabled 1 = The ICH6 will only fetch a single DW and wi ll not enable prefetching, regardless of the command being an Memory read (MR), Memory read line (MRL), or Memory read multiple (MRM). Memory Read Multiple Prefetch Disable (MRMPD) — R/W. 0 = MRM commands will fetch multiple cache li nes as defined by the prefetch algorithm. 1 = Memory read multiple (MRM) commands will fe tch only up to a single, 64-byte aligned cache line. Memory Read Line Prefetch Disable (MRLPD) — R/W. 0 = MRL commands will fetch multiple cache li nes as defined by the prefetch algorithm. 1 = Memory read line (MRL) commands will fetch only up to a single, 64-byte aligned cache line. Memory Read Prefetch Disable (MRPD) — R/W. 0 = MR commands will fetch up to a 64-byte aligned cache line. 1 = Memory read (MR) commands will fetch only a single DW.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 339 PCI-to-PCI Bridge Registers (D30:F0)

9.1.23 BPS—Bridge Propri etary Status Register

(PCI-PCI—D30:F0) Offset Address: 48 –4Bh Attribute: R/WC, RO Default Value: 00000000h Size: 32 bits Bit Description 31:17 Reserved PERR# Assertion Detected (PAD) — R/WC. This bit is set by hardware whenever the PERR# pin is asserted on the rising edge of PCI clock. This includes cases in which the chipset is the agent driving PERR#. It remains asserted until cleared by software writing a 1 to this location. When enabled by the PERR#-to-SERR# Enable bit (in the Bridge Policy Configuration register), a 1 in this bit can generate an internal SERR# and be a source for the NMI logic. This bit can be used by software to determine the source of a system problem. 15:7 Reserved 6:4 Number of Pending Transactions (NPT) — RO. This read-only indicator tells debug software how many transactions are in the pending queue. Possible values are: 000 = No pending transaction 001 = 1 pending transaction 010 = 2 pending transactions 011 = 3 pending transactions 100 = 4 pending transactions 101 = 5 pending transactions 110 - 111 = Reserved NOTE: This field is not valid if DTC.MDT (offset 44h:bits 7:6) is any value other than ‘00’. 3:2 Reserved 1:0 Number of Active Transactions (NAT) — RO. This read-onl y indicator tells debug software how many transactions are in the active queue. Possible values are: 00 = No active transactions 01 = 1 active transaction 10 = 2 active transactions 11 = Reserved

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9.1.24 BPC—Bridge Policy Configuration Register

(PCI-PCI—D30:F0) Offset Address: 4C –4Fh Attribute: R/W, RO Default Value: 00000000h Size: 32 bits

9.1.25 SVCAP—Subsystem Ve ndor Capability Register

(PCI-PCI—D30:F0) Offset Address: 50 –51h Attribute: RO Default Value: 000Dh Size: 16 bits Bit Description 31:7 Reserved PERR#-to-SERR# Enable (PSE) — R/W. When this bit is set, a 1 in the PERR# Assertion status bit (in the Bridge Proprietary Status register) will result in an internal SERR# assertion on the primary side of the bridge (if also enabled by the SERR# Enable bit in the primary Command register). SERR# is a source of NMI. Secondary Discard Timer Testmode (SDTT) — R/W. 0 = The secondary discard timer expiration will be defined in BCTRL.SDT (D30:F0:3E, bit 9) 1 = The secondary discard timer will expire after 128 PCI clocks. 4:3 Reserved 2R e s e r v e d Received Target Abort SERR# Enable (RTAE) — R/W. When set, the PCI bridge will report SERR# when PSTS.RTA (D30:F0:06 bit 12) or SSTS.RTA (D30:F0:1E bit 12) are set, and CMD.SEE (D30:F0:04 bit 8) is set. Bit Description 15:8 Next Capability (NEXT) — RO. Value of 00h indicates this is the last item in the list. 7:0 Capability Identifier (CID) — RO. Value of 0Dh indicates this is a PCI bridge subsystem vendor capability.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 341 PCI-to-PCI Bridge Registers (D30:F0)

9.1.26 SVID—Subsystem Vendor IDs Register (PCI-PCI—D30:F0)

Offset Address: 54 –57h Attribute: R/WO Default Value: 00000000h Size: 32 bits Bit Description 31:16 Subsystem Identifier (SID) — R/WO. This field indicates the s ubsystem as identified by the vendor. This field is write once and is locked down until a bridge reset occurs (not the PCI bus reset). 15:0 Subsystem Vendor Identifier (SVID) — R/WO. This field indicates the manufacturer of the subsystem. This field is write once and is locked down until a bridge reset occurs (not the PCI bus reset).

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Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 343 LPC Interface Bridge Registers (D31:F0)

10 LPC Interface Bridge Registers

(D31:F0) The LPC bridge function of the ICH6 resides in PCI Device 31:Function 0. This function contains many other functional units, such as DMA and Interrupt controllers, Timers, Power Management, System Management, GPIO, RTC, and LPC Configuration Registers. Registers and functions associated with other functional units (EHCI, UHCI, IDE, etc.) are described in their respective sections.

10.1 PCI Configuration Registers (LPC I/F—D31:F0)

Note: Address locations that are not shown should be treated as Reserved. Table 10-1. LPC Interface PCI Register Address Map (LPC I/F—D31:F0) (Sheet 1 of 2) Offset Mnemonic Register Name Default Type 00–01h VID Vendor Identification 8086h RO 02–03h DID Device Identification 2641h ICH6-M 2640h ICH6/ICH6R RO 04–05h PCICMD PCI Command 0007h R/W, RO 06–07h PCISTS PCI Status 0200h R/WC, RO 08h RID Revision Identification See register description. RO 09h PI Programming Interface 00h RO 0Ah SCC Sub Class Code 01h RO 0Bh BCC Base Class Code 06h RO 0Dh PLT Primary Latency Timer 00h RO 0Eh HEADTYP Header Type 80h RO 2C–2Fh SS Sub System Identifiers 00000000h R/WO 40–43h PMBASE ACPI Base Address 00000001h R/W, RO 44h ACPI_CNTL ACPI Control 00h R/W 48–4Bh GPIOBASE GPIO Base Address 00000001h R/W, RO 4C GC GPIO Control 00h R/W 60–63h PIRQ[ n]_ROUT PIRQ[A–D] Routing Control 80h R/W 64h SIRQ_CNTL Serial IRQ Control 10h R/W, RO 68–6Bh PIRQ[ n]_ROUT PIRQ[E–H] Routing Control 80h R/W 80h LPC_I/O_DEC I/O Decode Ranges 0000h R/W 82–83h LPC_EN LPC I/F Enables 0000h R/W

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10.1.1 VID—Vendor Identification Register (LPC I/F—D31:F0)

Offset Address: 00 –01h Attribute: RO Default Value: 8086h Size: 16-bit Lockable: No Power Well: Core10.1.2 DID—Device Identificatio n Register (LPC I/F—D31:F0) Offset Address: 02 –03h Attribute: RO Default Value: ICH6/ICH6R: 2640h Size: 16-bit ICH6-M: 2641h Lockable: No Power Well: Core 84–85h GEN1_DEC LPC I/F Generic Decode Range 1 0000h R/W 88–89h GEN2_DEC LPC I/F Generic Decode Range 2 0000h R/W A0–CFh Power Management (See Section 10.8.1) D0–D3h FWH_SEL1 Firmware Hub Select 1 00112233h R/W, RO D4–D5h FWH_SEL2 Firmware Hub Select 2 4567h R/W D8–D9h FWH_DEC_EN1 Firmware Hub Decode Enable 1 FFCFh R/W, RO DCh BIOS_CNTL BIOS Control 00h R/WLO, R/W F0-F3h RCBA Root Complex Base Address 00000000h R/W Table 10-1. LPC Interface PCI Register Address Map (LPC I/F—D31:F0) (Sheet 2 of 2) Offset Mnemonic Register Name Default Type Bit Description 15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h Bit Description 15:0 Device ID — RO. This is a 16-bit value assigned to the ICH6 LPC bridge.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 345 LPC Interface Bridge Registers (D31:F0)

10.1.3 PCICMD—PCI COMMAND Register (LPC I/F—D31:F0)

Offset Address: 04 –05h Attribute: R/W, RO Default Value: 0007h Size: 16-bit Lockable: No Power Well: Core Bit Description 15:10 Reserved 9 Fast Back to Back Enable (FBE) — RO. Hardwired to 0. SERR# Enable (SERR_EN) — R/W. The LPC bridge generates SERR# if this bit is set. 7 Wait Cycle Control (WCC) — RO. Hardwired to 0. Parity Error Response Enable (PERE) — R/W. 0 = No action is taken when detecting a parity error. 1 = Enables the ICH6 LPC bridge to respond to parity errors detected on backbone interface. 5 VGA Palette Snoop (VPS) — RO. Hardwired to 0. 4 Memory Write and Invalidate Enable (MWIE) — RO. Hardwired to 0. 3 Special Cycle Enable (SCE) — RO. Hardwired to 0. 2 Bus Master Enable (BME) — RO. Bus Masters cannot be disabled. 1 Memory Space Enable (MSE) — RO. Memo ry space cannot be disabled on LPC. 0 I/O Space Enable (IOSE) — RO. I/O space cannot be disabled on LPC.

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10.1.4 PCISTS—PCI Status Register (LPC I/F—D31:F0)

Offset Address: 06 –07h Attribute: RO, R/WC Default Value: 0200h Size: 16-bit Lockable: No Power Well: Core Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no effect. Bit Description Detected Parity Error (DPE) — R/WC. Set when the LPC bridge detects a parity error on the internal backbone. Set even if the PCICMD.PERE bit (D31:F0:04, bit 6) is 0 0 = Parity Error Not detected. 1 = Parity Error detected. 14 Signaled System Error (SSE)— R/WC. Set when the LPC bridge signals a system error to the internal SERR# logic. Master Abort Status (RMA) — R/WC. 0 = Unsupported request status not received. 1 = The bridge received a completion with unsupported request status from the backbone. Received Target Abort (RTA) — R/WC. 0 = Completion abort not received. 1 = Completion with completion abo rt received from the backbone. Signaled Target Abort (STA) — R/WC. 0 = Target abort Not generated on the backbone. 1 = LPC bridge generated a completion packet with target abort status on the backbone. 10:9 DEVSEL# Timing Status (DEV_STS) — RO. 01 = Medium Timing. Data Parity Error Detected (DPED) — R/WC. 0 = All conditions listed below Not met. 1 = Set when all three of the following conditions are met:

• LPC bridge receives a completion packet fr om the backbone from a previous request,
• Parity error has been detected (D31:F0:06, bit 15)
• PCICMD.PERE bit (D31:F0:04, bit 6) is set. 7 Fast Back to Back Capable (FBC): Reserved – bit has no meaning on the internal backbone. 6 Reserved. 5 66 MHz Capable (66MHZ_CAP) — Reserved – bit has no meaning on internal backbone. 4 Capabilities List (CLIST) — RO. No ca pability list exist on the LPC bridge. 3 Interrupt Status (IS) — RO. The LPC bridge does not generate interrupts. 2:0 Reserved.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 347 LPC Interface Bridge Registers (D31:F0)

10.1.5 RID—Revision Identific ation Register (LPC I/F—D31:F0)

Offset Address: 08h Attribute: RO Default Value: See bit description Size: 8 bits

10.1.6 PI—Programming Interfac e Register (LPC I/F—D31:F0)

Offset Address: 09h Attribute: RO Default Value: 00h Size: 8 bits

10.1.7 SCC—Sub Class Code Register (LPC I/F—D31:F0)

Offset Address: 0Ah Attribute: RO Default Value: 01h Size: 8 bits

10.1.8 BCC—Base Class Code Register (LPC I/F—D31:F0)

Offset Address: 0Bh Attribute: RO Default Value: 06h Size: 8 bits Bit Description 7:0 Revision ID (RID) — RO. Refer to the Intel® I/O Controller Hub 6 (ICH6) Family Specification Update for the value of the Revision ID Register Bit Description 7:0 Programming Interface — RO. Bit Description 7:0 Sub Class Code — RO. 8-bit value that indicates t he category of bridge for the LPC bridge. 01h = PCI-to-ISA bridge. Bit Description 7:0 Base Class Code — RO. This field is an 8-bit value that indicates the type of device for the LPC bridge. 06h = Bridge device.

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10.1.9 PLT—Primary Latency Time r Register (LPC I/F—D31:F0)

Offset Address: 0Dh Attribute: RO Default Value: 00h Size: 8 bits

10.1.10 HEADTYP—Header Type Register (LPC I/F—D31:F0)

Offset Address: 0Eh Attribute: RO Default Value: 80h Size: 8 bits

10.1.11 SS—Sub System Identifi ers Register (LPC I/F—D31:F0)

Offset Address: 2C –2Fh Attribute: R/WO Default Value: 00000000h Size: 32 bits This register is initialized to logic 0 by the assertion of PLTRST#. This register can be written only once after PLTRST# de-assertion. Bit Description 7:3 Master Latency Count (MLC) — Reserved. 2:0 Reserved. Bit Description 7 Multi-Function Device — RO. This bit is 1 to indi cate a multi-function device. 6:0 Header Type — RO. This 7-bit field identifies the header layout of the configuration space. Bit Description 31:16 Subsystem ID (SSID) — R/WO. This field is written by BI OS. No hardware action taken on this value. 15:0 Subsystem Vendor ID (SSVID) — R/WO. This field is written by BIOS. No hardware action taken on this value.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 349 LPC Interface Bridge Registers (D31:F0)

10.1.12 PMBASE—ACPI Base Addre ss Register (LPC I/F—D31:F0)

Offset Address: 40 –43h Attribute: R/W, RO Default Value: 00000001h Size: 32 bit Lockable: No Usage: ACPI, Legacy Power Well: Core Sets base address for ACPI I/O registers, GPIO registers and TCO I/O registers. These registers can be mapped anywhere in the 64-K I/O space on 128-byte boundaries.

10.1.13 ACPI_CNTL—ACPI Control Register (LPC I/F — D31:F0)

Offset Address: 44h Attribute: R/W Default Value: 00h Size: 8 bit Lockable: No Usage: ACPI, Legacy Power Well: Core Bit Description 31:16 Reserved 15:7 Base Address — R/W. This field provides 128 bytes of I/O space for ACPI, GPIO, and TCO logic. This is placed on a 128-byte boundary. 6:1 Reserved 0 Resource Type Indicator (RTE) — RO. Ha rdwired to 1 to indicate I/O space. Bit Description ACPI Enable (ACPI_EN) — R/W. 0 = Disable. 1 = Decode of the I/O range pointed to by the ACPI base register is enabled, and the ACPI power management function is enabled. Note that the APM power management ranges (B2/B3h) are always enabled and are not affected by this bit. 6:3 Reserved 2:0 SCI IRQ Select (SCI_IRQ_SEL) — R/W. This field specifies on wh ich IRQ the SCI will internally appear. If not using the APIC, the SCI must be routed to IRQ9–11, and that interrupt is not sharable with the SERIRQ stream, but is shareable with other PCI interrupts. If using the APIC, the SCI can also be mapped to IRQ20–23, and can be shared with other interrupts. NOTE: When the TCO interrupt is mapped to APIC interrupts 9, 10 or 11, the signal is in fact active high. When the TCO interrupt is mapped to IRQ 20, 21, 22, or 23, the signal is active low and can be shared with PCI interrupts that may be mapped to those same signals (IRQs). Bits SCI Map 000b IRQ9 001b IRQ10 010b IRQ11 011b Reserved 100b IRQ20 (Only available if APIC enabled) 101b IRQ21 (Only available if APIC enabled) 110b IRQ22 (Only available if APIC enabled) 111b IRQ23 (Only available if APIC enabled)

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10.1.14 GPIOBASE—GPIO Base Address Register (LPC I/F —

D31:F0) Offset Address: 48–4Bh Attribute: R/W, RO Default Value: 00000001h Size: 32 bit

10.1.15 GC—GPIO Control Regi ster (LPC I/F — D31:F0)

Offset Address: 4Ch Attribute: R/W Default Value: 00h Size: 8 bit Bit Description 31:16 Reserved. Always 0. 15:6 Base Address (BA) — R/W. This field provides the 64 bytes of I/O space for GPIO. 5:1 Reserved. Always 0. 0 RO. Hardwired to 1 to indicate I/O space. Bit Description 7:5 Reserved. GPIO Enable (EN) — R/W. This bit enables/disables dec ode of the I/O range pointed to by the GPIO Base Address register (D31:F0:48h) and enables the GPIO function. 0 = Disable. 1 = Enable. 3:0 Reserved.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 351 LPC Interface Bridge Registers (D31:F0)

10.1.16 PIRQ[n]_ROUT—PIRQ[A,B,C ,D] Routing Control Register

(LPC I/F—D31:F0) Offset Address: PIRQA – 60h, PIRQB – 61h, Attribute: R/W PIRQC – 62h, PIRQD – 63h Default Value: 80h Size: 8 bit Lockable: No Power Well: Core Bit Description Interrupt Routing Enable (IRQEN) — R/W. 0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts specified in bits[3:0]. 1 = The PIRQ is not routed to the 8259. NOTE: BIOS must program this bit to 0 during POST for any of the PIRQs that are being used. The value of this bit may subsequently be changed by the OS when setting up for I/O APIC interrupt delivery mode. 6:4 Reserved 3:0 IRQ Routing — R/W. (ISA compatible.) Value IRQ Value IRQ 0000b Reserved 1000b Reserved 0001b Reserved 1001b IRQ9 0010b Reserved 1010b IRQ10 0011b IRQ3 1011b IRQ11 0100b IRQ4 1100b IRQ12 0101b IRQ5 1101b Reserved 0110b IRQ6 1110b IRQ14 0111b IRQ7 1111b IRQ15

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10.1.17 SIRQ_CNTL—Serial IRQ Control Register

(LPC I/F—D31:F0) Offset Address: 64h Attribute: R/W, RO Default Value: 10h Size: 8 bit Lockable: No Power Well: Core Bit Description Serial IRQ Enable (SIRQEN) — R/W. 0 = The buffer is input only and internally SERIRQ will be a 1. 1 = Serial IRQs will be rec ognized. The SERIRQ pin will be configured as SERIRQ. Serial IRQ Mode Select (SIRQMD) — R/W. 0 = The serial IRQ machine will be in quiet mode. 1 = The serial IRQ machine will be in continuous mode. NOTE: For systems using Quiet Mode, this bit should be set to 1 (Continuous Mode) for at least one frame after coming out of reset before switching back to Quiet Mode. Failure to do so will result in the ICH6 not recognizing SERIRQ interrupts. 5:2 Serial IRQ Frame Size (SIRQSZ) — RO. This field is fixed to indi cate the size of the SERIRQ frame as 21 frames. 1:0 Start Frame Pulse Width (SFPW) — R/W. This is the number of PCI clocks that the SERIRQ pin will be driven low by the serial IRQ machine to signal a start frame. In continuous mode, the ICH6 will drive the start frame for the number of clocks specified. In quiet mode, the ICH6 will drive the start frame for the number of clocks specified minus one, as the first clock was driven by the peripheral. 00 = 4 clocks 01 = 6 clocks 10 = 8 clocks 11 = Reserved

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 353 LPC Interface Bridge Registers (D31:F0)

10.1.18 PIRQ[n]_ROUT—PIRQ[E,F,G ,H] Routing Control Register

(LPC I/F—D31:F0) Offset Address: PIRQE – 68h, PIRQF – 69h, Attribute: R/W PIRQG – 6Ah, PIRQH – 6Bh Default Value: 80h Size: 8 bit Lockable: No Power Well: Core Bit Description Interrupt Routing Enable (IRQEN) — R/W. 0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts specified in bits[3:0]. 1 = The PIRQ is not routed to the 8259. NOTE: BIOS must program this bit to 0 during POST for any of the PIRQs that are being used. The value of this bit may subsequently be changed by the OS when setting up for I/O APIC interrupt delivery mode. 6:4 Reserved 3:0 IRQ Routing — R/W. (ISA compatible.) Value IRQ Value IRQ 0000b Reserved 1000b Reserved 0001b Reserved 1001b IRQ9 0010b Reserved 1010b IRQ10 0011b IRQ3 1011b IRQ11 0100b IRQ4 1100b IRQ12 0101b IRQ5 1101b Reserved 0110b IRQ6 1110b IRQ14 0111b IRQ7 1111b IRQ15

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LPC Interface Bridge Registers (D31:F0)

10.1.19 LPC_I/O_DEC—I/O Decode Ranges Register

(LPC I/F—D31:F0) Offset Address: 80h Attribute: R/W Default Value: 0000h Size: 16 bit Bit Description 15:13 Reserved FDD Decode Range — R/W. This bit determines which range to decode for the FDD Port 0 = 3F0h – 3F5h, 3F7h (Primary) 1 = 370h – 375h, 377h (Secondary) 11:10 Reserved 9:8 LPT Decode Range — R/W. This field determines which range to decode for the LPT Port. 00 = 378h – 37Fh and 778h – 77Fh 01 = 278h – 27Fh (port 279h is read only) and 678h – 67Fh 10 = 3BCh –3BEh and 7BCh – 7BEh 11 = Reserved 6:4 COMB Decode Range — R/W. This field determines whic h range to decode for the COMB Port. 000 = 3F8h – 3FFh (COM1) 001 = 2F8h – 2FFh (COM2) 010 = 220h – 227h 011 = 228h – 22Fh 100 = 238h – 23Fh 101 = 2E8h – 2EFh (COM4) 110 = 338h – 33Fh 111 = 3E8h – 3EFh (COM3) 2:0 COMA Decode Range — R/W. This field determines whic h range to decode for the COMA Port. 000 = 3F8h – 3FFh (COM1) 001 = 2F8h – 2FFh (COM2) 010 = 220h – 227h 011 = 228h – 22Fh 100 = 238h – 23Fh 101 = 2E8h – 2EFh (COM4) 110 = 338h – 33Fh 111 = 3E8h – 3EFh (COM3)

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 355 LPC Interface Bridge Registers (D31:F0)

10.1.20 LPC_EN—LPC I/F Enable s Register (LPC I/F—D31:F0)

Offset Address: 82h – 83h Attribute: R/W Default Value: 0000h Size: 16 bit Power Well: Core Bit Description 15:14 Reserved CNF2_LPC_EN — R/W. Microcontroller Enable # 2. 0 = Disable. 1 = Enables the decoding of the I/O locations 4Eh and 4Fh to the LPC interface. This range is used for a microcontroller. CNF1_LPC_EN — R/W. Super I/O Enable. 0 = Disable. 1 = Enables the decoding of the I/O locations 2Eh and 2Fh to the LPC interface. This range is used for Super I/O devices. MC_LPC_EN — R/W. Microcontroller Enable # 1. 0 = Disable. 1 = Enables the decoding of the I/O locations 62h and 66h to the LPC interface. This range is used for a microcontroller. KBC_LPC_EN — R/W. Keyboard Enable. 0 = Disable. 1 = Enables the decoding of the I/O locations 60h and 64h to the LPC interface. This range is used for a microcontroller. GAMEH_LPC_EN — R/W. High Gameport Enable 0 = Disable. 1 = Enables the decoding of the I/O locations 2 08h to 20Fh to the LPC interface. This range is used for a gameport. GAMEL_LPC_EN — R/W. Low Gameport Enable 0 = Disable. 1 = Enables the decoding of the I/O locations 2 00h to 207h to the LPC interface. This range is used for a gameport. 7:4 Reserved FDD_LPC_EN — R/W. Floppy Drive Enable 0 = Disable. 1 = Enables the decoding of the FDD range to the LPC interface. This range is selected in the LPC_FDD/LPT Decode Range Register (D31:F0:80h, bit 12). LPT_LPC_EN — R/W. Parallel Port Enable 0 = Disable. 1 = Enables the decoding of the LPTrange to the LPC interface. This range is selected in the LPC_FDD/LPT Decode Range Register (D31:F0:80h, bit 9:8). COMB_LPC_EN — R/W. Com Port B Enable 0 = Disable. 1 = Enables the decoding of the COMB range to t he LPC interface. This range is selected in the LPC_COM Decode Range Register (D31:F0:80h, bits 6:4). COMA_LPC_EN — R/W. Com Port A Enable 0 = Disable. 1 = Enables the decoding of the COMA range to t he LPC interface. This range is selected in the LPC_COM Decode Range Register (D31:F0:80h, bits 3:2).

356 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

LPC Interface Bridge Registers (D31:F0)

10.1.21 GEN1_DEC—LPC I/F Generic Decode Range 1 Register

(LPC I/F—D31:F0) Offset Address: 84h – 85h Attribute: R/W Default Value: 0000h Size: 16 bit Power Well: Core

10.1.22 GEN2_DEC—LPC I/F Generic Decode Range 2 Register

(LPC I/F—D31:F0) Offset Address: 88h – 89h Attribute: R/W Default Value: 0000h Size: 16 bit Power Well: Core Bit Description 15:7 Generic I/O Decode Range 1 Base Address (GEN1_BASE) — R/W. This address is aligned on a 128-byte boundary, and must have address lines 31:16 as 0. NOTE: This generic decode is for I/O addresses only, not memory addresses. The size of this range is 128 bytes. 6:1 Reserved Generic Decode Range 1 Enable (GEN1_EN) — R/W. 0 = Disable. 1 = Enable the GEN1 I/O range to be forwarded to the LPC I/F Bit Description 15:4 Generic I/O Decode Range 2 Base Address (GEN2_BASE) — R/W. This address is aligned on a 16-byte, 32-byte, or 64-byte boundary, and must have address lines 31:16 as 0. NOTES: 1. This generic decode is for I/O addresses only, not memory addresses. The size of this range is 16, 32, or 64 bytes. 2. Size of decode range is determined by D31:F0:ADh:bits 5:4. 3:1 Reserved. Read as 0. Generic I/O Decode Range 2 Enable (GEN2_EN) — R/W. 0 = Disable. 1 = Accesses to the GEN2 I/O range will be forwarded to the LPC I/F

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 357 LPC Interface Bridge Registers (D31:F0)

10.1.23 FWH_SEL1—Firmware Hub Select 1 Register

(LPC I/F—D31:F0) Offset Address: D0h –D3h Attribute: R/W, RO Default Value: 00112233h Size: 32 bits Bit Description 31:28 FWH_F8_IDSEL — RO. IDSEL for two 512-KB Firmware Hub memory ranges and one 128-KB memory range. This field is fixed at 0000. The IDSEL programmed in this field addresses the following memory ranges: FFF8 0000h – FFFF FFFFh FFB8 0000h – FFBF FFFFh 000E 0000h – 000F FFFFh 27:24 FWH_F0_IDSEL — R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFF0 0000h – FFF7 FFFFh FFB0 0000h – FFB7 FFFFh 23:20 FWH_E8_IDSEL — R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFE8 0000h – FFEF FFFFh FFA8 0000h – FFAF FFFFh 19:16 FWH_E0_IDSEL — R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFE0 0000h – FFE7 FFFFh FFA0 0000h – FFA7 FFFFh 15:12 FWH_D8_IDSEL — R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFD8 0000h – FFDF FFFFh FF98 0000h – FF9F FFFFh 11:8 FWH_D0_IDSEL — R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFD0 0000h – FFD7 FFFFh FF90 0000h – FF97 FFFFh 7:4 FWH_C8_IDSEL — R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFC8 0000h – FFCF FFFFh FF88 0000h – FF8F FFFFh 3:0 FWH_C0_IDSEL — R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFC0 0000h – FFC7 FFFFh FF80 0000h – FF87 FFFFh

358 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

LPC Interface Bridge Registers (D31:F0)

10.1.24 FWH_SEL2—Firmware Hub Select 2 Register

(LPC I/F—D31:F0) Offset Address: D4h –D5h Attribute: R/W Default Value: 4567h Size: 16 bits Bit Description 15:12 FWH_70_IDSEL — R/W. IDSEL for two, 1-M Firmware Hub memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FF70 0000h – FF7F FFFFh FF30 0000h – FF3F FFFFh 11:8 FWH_60_IDSEL — R/W. IDSEL for two, 1-M Firmware Hub memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FF60 0000h – FF6F FFFFh FF20 0000h – FF2F FFFFh 7:4 FWH_50_IDSEL — R/W. IDSEL for two, 1-M Firmware Hub memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FF50 0000h – FF5F FFFFh FF10 0000h – FF1F FFFFh 3:0 FWH_40_IDSEL — R/W. IDSEL for two, 1-M Firmware Hub memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FF40 0000h – FF4F FFFFh FF00 0000h – FF0F FFFFh

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 359 LPC Interface Bridge Registers (D31:F0)

10.1.25 FWH_DEC_EN1—Firmware Hu b Decode Enable Register

(LPC I/F—D31:F0) Offset Address: D8h –D9h Attribute: R/W, RO Default Value: FFCFh Size: 16 bits Bit Description FWH_F8_EN — RO. This bit enables decoding two 512-KB Firmware Hub memory ranges, and one 128-KB memory range. 0 = Disable 1 = Enable the following ranges for the Firmware Hub FFF80000h – FFFFFFFFh FFB80000h – FFBFFFFFh FWH_F0_EN — R/W. This bit enables decoding tw o 512-KB Firmware Hub memory ranges. 0 = Disable. 1 = Enable the following ranges for the Firmware Hub: FFF00000h – FFF7FFFFh FFB00000h – FFB7FFFFh FWH_E8_EN — R/W. This bit enables decoding tw o 512-KB Firmware Hub memory ranges. 0 = Disable. 1 = Enable the following ranges for the Firmware Hub: FFE80000h – FFEFFFFh FFA80000h – FFAFFFFFh FWH_E0_EN — R/W. This bit enables decoding tw o 512-KB Firmware Hub memory ranges. 0 = Disable. 1 = Enable the following ranges for the Firmware Hub: FFE00000h – FFE7FFFFh FFA00000h – FFA7FFFFh FWH_D8_EN — R/W. This bit enables decoding tw o 512-KB Firmware Hub memory ranges. 0 = Disable. 1 = Enable the following ranges for the Firmware Hub FFD80000h – FFDFFFFFh FF980000h – FF9FFFFFh FWH_D0_EN — R/W. This bit enables decoding tw o 512-KB Firmware Hub memory ranges. 0 = Disable. 1 = Enable the following ranges for the Firmware Hub FFD00000h – FFD7FFFFh FF900000h – FF97FFFFh FWH_C8_EN — R/W. This bit enables decoding tw o 512-KB Firmware Hub memory ranges. 0 = Disable. 1 = Enable the following ranges for the Firmware Hub FFC80000h – FFCFFFFFh FF880000h – FF8FFFFFh FWH_C0_EN — R/W. This bit enables decoding tw o 512-KB Firmware Hub memory ranges. 0 = Disable. 1 = Enable the following ranges for the Firmware Hub FFC00000h – FFC7FFFFh FF800000h – FF87FFFFh FWH_Legacy_F_EN — R/W. This enables the decoding of the legacy 128-K range at F0000h – FFFFFh. 0 = Disable. 1 = Enable the following legacy ranges for the Firmware Hub F0000h – FFFFFh

360 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

LPC Interface Bridge Registers (D31:F0)

10.1.26 BIOS_CNTL—BIO S Control Register

(LPC I/F—D31:F0) Offset Address: DCh Attribute: R/WLO, R/W Default Value: 00h Size: 8 bit Lockable: No Power Well: Core FWH_Legacy_E_EN — R/W. This bit enables the decoding of the legacy 128-K range at E0000h – EFFFFh. 0 = Disable. 1 = Enable the following legacy ranges for the Firmware Hub E0000h – EFFFFh 5:4 Reserved FWH_70_EN — R/W. This bit enables decoding tw o 1-M Firmware Hub memory ranges. 0 = Disable. 1 = Enable the following ranges for the Firmware Hub FF70 0000h – FF7F FFFFh FF30 0000h – FF3F FFFFh FWH_60_EN — R/W. This bit enables decoding tw o 1-M Firmware Hub memory ranges. 0 = Disable. 1 = Enable the following ranges for the Firmware Hub FF60 0000h – FF6F FFFFh FF20 0000h – FF2F FFFFh FWH_50_EN — R/W. This bit enables decoding two 1-M Firmware Hub memory ranges. 0 = Disable. 1 = Enable the following ranges for the Firmware Hub FF50 0000h – FF5F FFFFh FF10 0000h – FF1F FFFFh FWH_40_EN — R/W. This bit enables decoding tw o 1-M Firmware Hub memory ranges. 0 = Disable. 1 = Enable the following ranges for the Firmware Hub FF40 0000h – FF4F FFFFh FF00 0000h – FF0F FFFFh Bit Description Bit Description 7:2 Reserved BIOS Lock Enable (BLE) — R/WLO. 0 = Setting the BIOSWE will not cause SMIs. 1 = Enables setting the BIOSWE bit to cause SMIs . Once set, this bit can only be cleared by a PLTRST# BIOS Write Enable (BIOSWE) — R/W. 0 = Only read cycles result in Firmware Hub I/F cycles. 1 = Access to the BIOS space is enabled for bot h read and write cycles. When this bit is written from a 0 to a 1 and BIOS Lock Enable (BLE) is also set, an SMI# is generated. This ensures that only SMI code can update BIOS.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 361 LPC Interface Bridge Registers (D31:F0)

10.1.27 RCBA—Root Comple x Base Address Register

(LPC I/F—D31:F0) Offset Address: F0h Attribute: R/W Default Value: 00000000h Size: 32 bit

10.2 DMA I/O Registers (LPC I/F—D31:F0)

31:14 Base Address (BA) — R/W. This field provides the base address for the root complex register block decode range. This address is aligned on a 16-KB boundary. 13:1 Reserved 0 Enable (EN) — R/W. When set, this bit enables the range s pecified in BA to be claimed as the Root Complex Register Block. Table 10-2. DMA Registers (Sheet 1 of 2) Port Alias Register Name Default Type 00h 10h Channel 0 DMA Base & Current Address Undefined R/W 01h 11h Channel 0 DMA Base & Current Count Undefined R/W 02h 12h Channel 1 DMA Base & Current Address Undefined R/W 03h 13h Channel 1 DMA Base & Current Count Undefined R/W 04h 14h Channel 2 DMA Base & Current Address Undefined R/W 05h 15h Channel 2 DMA Base & Current Count Undefined R/W 06h 16h Channel 3 DMA Base & Current Address Undefined R/W 07h 17h Channel 3 DMA Base & Current Count Undefined R/W 08h 18h Channel 0–3 DMA Command Undefined WO Channel 0–3 DMA Status Undefined RO 0Ah 1Ah Channel 0–3 DMA Write Single Mask 000001XXb WO 0Bh 1Bh Channel 0–3 DMA Channel Mode 000000XXb WO 0Ch 1Ch Channel 0–3 DMA Clear Byte Pointer Undefined WO 0Dh 1Dh Channel 0–3 DMA Master Clear Undefined WO 0Eh 1Eh Channel 0–3 DMA Clear Mask Undefined WO 0Fh 1Fh Channel 0–3 DMA Write All Mask 0Fh R/W 80h 90h Reserved Page Undefined R/W 81h 91h Channel 2 DMA Memory Low Page Undefined R/W 82h — Channel 3 DMA Memory Low Page Undefined R/W 83h 93h Channel 1 DMA Memory Low Page Undefined R/W 84h–86h 94h–96h Reserved Pages Undefined R/W 87h 97h Channel 0 DMA Memory Low Page Undefined R/W 88h 98h Reserved Page Undefined R/W

362 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

LPC Interface Bridge Registers (D31:F0) 89h 99h Channel 6 DMA Memory Low Page Undefined R/W 8Ah 9Ah Channel 7 DMA Memory Low Page Undefined R/W 8Bh 9Bh Channel 5 DMA Memory Low Page Undefined R/W 8Ch–8Eh 9Ch–9Eh Reserved Page Undefined R/W 8Fh 9Fh Refresh Low Page Undefined R/W C0h C1h Channel 4 DMA Base & Current Address Undefined R/W C2h C3h Channel 4 DMA Base & Current Count Undefined R/W C4h C5h Channel 5 DMA Base & Current Address Undefined R/W C6h C7h Channel 5 DMA Base & Current Count Undefined R/W C8h C9h Channel 6 DMA Base & Current Address Undefined R/W CAh CBh Channel 6 DMA Base & Current Count Undefined R/W CCh CDh Channel 7 DMA Base & Current Address Undefined R/W CEh CFh Channel 7 DMA Base & Current Count Undefined R/W D0h D1h Channel 4–7 DMA Command Undefined WO Channel 4–7 DMA Status Undefined RO D4h D5h Channel 4–7 DMA Write Single Mask 000001XXb WO D6h D7h Channel 4–7 DMA Channel Mode 000000XXb WO D8h D9h Channel 4–7 DMA Clear Byte Pointer Undefined WO DAh DBh Channel 4–7 DMA Master Clear Undefined WO DCh DDh Channel 4–7 DMA Clear Mask Undefined WO DEh DFh Channel 4–7 DMA Write All Mask 0Fh R/W Table 10-2. DMA Registers (Sheet 2 of 2) Port Alias Register Name Default Type

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 363 LPC Interface Bridge Registers (D31:F0)

10.2.1 DMABASE_CA—DMA B ase and Current Address

Registers (LPC I/F—D31:F0) I/O Address: Ch. #0 = 00h; Ch. #1 = 02h Attribute: R/W Ch. #2 = 04h; Ch. #3 = 06h Size: 16 bit (per channel), Ch. #5 = C4h Ch. #6 = C8h but accessed in two 8-bit Ch. #7 = CCh; quantities Default Value: Undef Lockable: No Power Well: Core

10.2.2 DMABASE_CC—DMA Base and Current Count Registers

(LPC I/F—D31:F0) I/O Address: Ch. #0 = 01h; Ch. #1 = 03h Attribute: R/W Ch. #2 = 05h; Ch. #3 = 07h Size: 16-bit (per channel), Ch. #5 = C6h; Ch. #6 = CAh but accessed in two 8-bit Ch. #7 = CEh; quantities Default Value: Undefined Lockable: No Power Well: Core Bit Description 15:0 Base and Current Address — R/W. This register determines the address for the transfers to be performed. The address specified points to two separate registers. On writes, the value is stored in the Base Address register and copied to the Current Address register. On reads, the value is returned from the Current Address register. The address increments/decrements in the Current Address register after each transfer, depending on the mode of the transfer. If the channel is in auto-initialize mode, the Current Address register will be reloaded from the Base Address register after a terminal count is generated. For transfers to/from a 16-bit slave (channel’s 5-7), the address is shifted left one bit location. Bit 15 will be shifted into Bit 16. The register is accessed in 8 bit quantities. The byte is pointed to by the current byte pointer flip/flop. Before accessing an address register, the byte pointer flip/flop should be cleared to ensure that the low byte is accessed first Bit Description 15:0 Base and Current Count — R/W. This register determines the number of transfers to be performed. The address specified points to two separate registers. On writes, the value is stored in the Base Count register and copied to the Current Count register. On reads, the value is returned from the Current Count register. The actual number of transfers is one more than the number programmed in the Base Count Register (i.e., programming a count of 4h results in 5 transfers). The count is decrements in the Current Count register after each transfer. When the value in the register rolls from 0 to FFFFh, a terminal count is generated. If the channel is in auto-initialize mode, the Current Count register will be reloaded from the Base Count register after a terminal count is generated. For transfers to/from an 8-bit slave (channels 0–3), the count register indicates the number of bytes to be transferred. For transfers to/from a 16-bit slave (channels 5–7), the count register indicates the number of words to be transferred. The register is accessed in 8 bit quantities. The byte is pointed to by the current byte pointer flip/flop. Before accessing a count register, the byte pointer flip/flop should be cleared to ensure that the low byte is accessed first.

364 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

LPC Interface Bridge Registers (D31:F0)

10.2.3 DMAMEM_LP—DMA Memory Low Page Registers

(LPC I/F—D31:F0) I/O Address: Ch. #0 = 87h; Ch. #1 = 83h Ch. #5 = 8Bh; Ch. #6 = 89h Ch. #7 = 8Ah; Attribute: R/W Default Value: Undefined Size: 8-bit Lockable: No Power Well: Core

10.2.4 DMACMD—DMA Command Register (LPC I/F—D31:F0)

I/O Address: Ch. #0 –3 = 08h; Ch. #4–7 = D0h Attribute: WO Default Value: Undefined Size: 8-bit Lockable: No Power Well: Core Bit Description 7:0 DMA Low Page (ISA Address bits [23:16]) — R/W. This r egister works in conjunction with the DMA controller's Current Address Register to define the complete 24-bit address for the DMA channel. This register remains static throughout the DMA transfer. Bit 16 of this register is ignored when in 16 bit I/O count by words mode as it is replaced by the bit 15 shifted out from the current address register. Bit Description 7:5 Reserved. Must be 0. DMA Group Arbitration Priority — WO. Each channel group is indi vidually assigned either fixed or rotating arbitration priority. At part reset, each group is initialized in fixed priority. 0 = Fixed priority to the channel group 1 = Rotating priority to the group. 3 Reserved. Must be 0. DMA Channel Group Enable — WO. Both channel groups are enabled following part reset. 0 = Enable the DMA channel group. 1 = Disable. Disabling channel group 4–7 also di sables channel group 0–3, which is cascaded through channel 4. 1:0 Reserved. Must be 0.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 365 LPC Interface Bridge Registers (D31:F0)

10.2.5 DMASTA—DMA Status Register (LPC I/F—D31:F0)

I/O Address: Ch. #0 –3 = 08h; Ch. #4–7 = D0h Attribute: RO Default Value: Undefined Size: 8-bit Lockable: No Power Well: Core

10.2.6 DMA_WRSMSK—DMA Write Single Mask Register

(LPC I/F—D31:F0) I/O Address: Ch. #0 –3 = 0Ah; Ch. #4–7 = D4h Attribute: WO Default Value: 0000 01xx Size: 8-bit Lockable: No Power Well: Core Bit Description 7:4 Channel Request Status — RO. When a valid DMA reques t is pending for a channel, the corresponding bit is set to 1. When a DMA request is not pending for a particular channel, the corresponding bit is set to 0. The source of the DREQ may be hardware or a software request. Note that channel 4 is the cascade channel, so the request status of channel 4 is a logical OR of the request status for channels 0 through 3. 4 = Channel 0 5 = Channel 1 (5) 6 = Channel 2 (6) 7 = Channel 3 (7) 3:0 Channel Terminal Count Status — RO. When a channel reaches terminal count (TC), its status bit is set to 1. If TC has not been reached, the status bit is set to 0. Channel 4 is programmed for cascade, so the TC bit response for channel 4 is irrelevant: 0 = Channel 0 1 = Channel 1 (5) 2 = Channel 2 (6) 3 = Channel 3 (7) Bit Description 7:3 Reserved. Must be 0. Channel Mask Select — WO. 0 = Enable DREQ for the selected channel. The channel is selected through bits [1:0]. Therefore, only one channel can be masked / unmasked at a time. 1 = Disable DREQ for the selected channel. 1:0 DMA Channel Select — WO. These bits select the DMA Channel Mode Register to program. 00 = Channel 0 (4) 01 = Channel 1 (5) 10 = Channel 2 (6) 11 = Channel 3 (7)

366 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

LPC Interface Bridge Registers (D31:F0)

10.2.7 DMACH_MODE—DMA Channel Mode Register

(LPC I/F—D31:F0) I/O Address: Ch. #0 –3 = 0Bh; Ch. #4–7 = D6h Attribute: WO Default Value: 0000 00xx Size: 8-bit Lockable: No Power Well: Core

10.2.8 DMA Clear Byte Pointer Register (LPC I/F—D31:F0)

I/O Address: Ch. #0 –3 = 0Ch; Ch. #4–7 = D8h Attribute: WO Default Value: xxxx xxxx Size: 8-bit Lockable: No Power Well: Core Bit Description 7:6 DMA Transfer Mode — WO. Each DMA channel can be programmed in one of four different modes: 00 = Demand mode 01 = Single mode 10 = Reserved 11 = Cascade mode Address Increment/Decrement Select — WO. This bit controls address increment/decrement during DMA transfers. 0 = Address increment. (default after part reset or Master Clear) 1 = Address decrement. Autoinitialize Enable — WO. 0 = Autoinitialize feature is disabled and DMA transfers terminate on a terminal count. A part reset or Master Clear disables autoinitialization. 1 = DMA restores the Base Address and Count r egisters to the current registers following a terminal count (TC). 3:2 DMA Transfer Type — WO. These bits represent the direction of the DMA transfer. When the channel is programmed for cascade mode, (bits[7:6] = 11) the transfer type is irrelevant. 00 = Verify – No I/O or memory strobes generated 01 = Write – Data transferred from the I/O devices to memory 10 = Read – Data transferred from memory to the I/O device 11 = Illegal 1:0 DMA Channel Select — WO. These bits select the DMA Channel Mode Register that will be written by bits [7:2]. 00 = Channel 0 (4) 01 = Channel 1 (5) 10 = Channel 2 (6) 11 = Channel 3 (7) Bit Description 7:0 Clear Byte Pointer — WO. No specific pattern. Command enabled with a write to the I/O port address. Writing to this register initializes the byte pointer flip/flop to a known state. It clears the internal latch used to address the upper or lower byte of the 16-bit Address and Word Count Registers. The latch is also cleared by part reset and by the Master Clear command. This command precedes the first access to a 16-bit DMA controller register. The first access to a 16-bit register will then access the significant byte, and the second access automatically accesses the most significant byte.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 367 LPC Interface Bridge Registers (D31:F0)

10.2.9 DMA Master Clear Re gister (LPC I/F—D31:F0)

I/O Address: Ch. #0 –3 = 0Dh; Ch. #4–7 = DAh Attribute: WO Default Value: xxxx xxxx Size: 8-bit

10.2.10 DMA_CLMSK—DMA Clear Ma sk Register (LPC I/F—D31:F0)

I/O Address: Ch. #0 –3 = 0Eh; Ch. #4–7 = DCh Attribute: WO Default Value: xxxx xxxx Size: 8-bit Lockable: No Power Well: Core

10.2.11 DMA_WRMSK—DMA Write All Mask Register

(LPC I/F—D31:F0) I/O Address: Ch. #0 –3 = 0Fh; Ch. #4–7 = DEh Attribute: R/W Default Value: 0000 1111 Size: 8-bit Lockable: No Power Well: Core Bit Description 7:0 Master Clear — WO. No specific pattern. Enabled with a wr ite to the port. This has the same effect as the hardware Reset. The Command, Status, Request, and Byte Pointer flip/flop registers are cleared and the Mask Register is set. Bit Description 7:0 Clear Mask Register — WO. No specific pattern. Command enabled with a write to the port. Bit Description 7:4 Reserved. Must be 0. 3:0 Channel Mask Bits — R/W. This register permits all four channels to be simultaneously enabled/ disabled instead of enabling/disabling each channel individually, as is the case with the Mask Register – Write Single Mask Bit. In addition, this register has a read path to allow the status of the channel mask bits to be read. A channel's mask bit is automatically set to 1 when the Current Byte/ Word Count Register reaches terminal count (unless the channel is in auto-initialization mode). Setting the bit(s) to a 1 disables the corresponding DREQ(s). Setting the bit(s) to a 0 enables the corresponding DREQ(s). Bits [3:0] are set to 1 upon part reset or Master Clear. When read, bits [3:0] indicate the DMA channel [3:0] ([7:4]) mask status. Bit 0 = Channel 0 (4) 1 = Masked, 0 = Not Masked Bit 1 = Channel 1 (5) 1 = Masked, 0 = Not Masked Bit 2 = Channel 2 (6) 1 = Masked, 0 = Not Masked Bit 3 = Channel 3 (7) 1 = Masked, 0 = Not Masked NOTE: Disabling channel 4 also disables channels 0–3 due to the cascade of channel’s 0 – 3 through channel 4.

368 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

LPC Interface Bridge Registers (D31:F0)

10.3 Timer I/O Registers (LPC I/F—D31:F0)

Port Aliases Register Name Default Value Type 40h 50h Counter 0 Interval Time Status Byte Format 0XXXXXXXb RO Counter 0 Counter Access Port Undefined R/W 41h 51h Counter 1 Interval Time Status Byte Format 0XXXXXXXb RO Counter 1 Counter Access Port Undefined R/W 42h 52h Counter 2 Interval Time Status Byte Format 0XXXXXXXb RO Counter 2 Counter Access Port Undefined R/W 43h 53h Timer Control Word Undefined WO Timer Control Word Register XXXXXXX0b WO Counter Latch Command X0h WO

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 369 LPC Interface Bridge Registers (D31:F0)

10.3.1 TCW—Timer Control Word Register (LPC I/F—D31:F0)

I/O Address: 43h Attribute: WO Default Value: All bits undefined Size: 8 bits This register is programmed prior to any counter being accessed to specify counter modes. Following part reset, the control words for each register are undefined and each counter output is 0. Each timer must be programmed to bring it into a known state. There are two special commands that can be issued to the counters through this register, the Read Back Command and the Counter Latch Command. When these commands are chosen, several bits within this register are redefined. These register formats are described below: Bit Description 7:6 Counter Select — WO. The Counter Selection bits select the counter the control word acts upon as shown below. The Read Back Command is selected when bits[7:6] are both 1. 00 = Counter 0 select 01 = Counter 1 select 10 = Counter 2 select 11 = Read Back Command 5:4 Read/Write Select — WO. These bits are the read/write control bits. The actual counter programming is done through the counter port (40h for counter 0, 41h for counter 1, and 42h for counter 2). 00 = Counter Latch Command 01 = Read/Write Least Significant Byte (LSB) 10 = Read/Write Most Significant Byte (MSB) 11 = Read/Write LSB then MSB 3:1 Counter Mode Selection — WO. These bits select one of six possible modes of operation for the selected counter. Binary/BCD Countdown Select — WO. 0 = Binary countdown is used. The largest possible binary count is 216 1 = Binary coded decimal (BCD) count is used. The largest possible BCD count is 104 Bit Value Mode 000b Mode 0 Out signal on end of count (=0) 001b Mode 1 Hardware retriggerable one-shot x10b Mode 2 Rate generator (divide by n counter) x11b Mode 3 Square wave output 100b Mode 4 Software triggered strobe 101b Mode 5 Hardware triggered strobe

370 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

LPC Interface Bridge Registers (D31:F0) RDBK_CMD—Read Back Command (LPC I/F—D31:F0) The Read Back Command is used to determine the count value, programmed mode, and current states of the OUT pin and Null count flag of the selected counter or counters. Status and/or count may be latched in any or all of the counters by selecting the counter during the register write. The count and status remain latched until read, and further latch commands are ignored until the count is read. Both count and status of the selected counters may be latched simultaneously by setting both bit 5 and bit 4 to 0. If both are latched, the first read operation from that counter returns the latched status. The next one or two reads, depending on whether the counter is programmed for one or two byte counts, returns the latched count. Subsequent reads return an unlatched count. LTCH_CMD—Counter Latch Command (LPC I/F—D31:F0) The Counter Latch Command latches the current count value. This command is used to insure that the count read from the counter is accurate. The count value is then read from each counter's count register through the Counter Ports Access Ports Register (40h for counter 0, 41h for counter 1, and 42h for counter 2). The count must be read according to the programmed format, i.e., if the counter is programmed for two byte counts, two bytes must be read. The two bytes do not have to be read one right after the other (read, write, or programming operations for other counters may be inserted between the reads). If a counter is latched once and then latched again before the count is read, the second Counter Latch Command is ignored. Bit Description 7:6 Read Back Command. Must be 11 to select the Read Back Command Latch Count of Selected Counters. 0 = Current count value of the se lected counters will be latched 1 = Current count will not be latched Latch Status of Selected Counters. 0 = Status of the selected counters will be latched 1 = Status will not be latched 3 Counter 2 Select. 1 = Counter 2 count and/or status will be latched 2 Counter 1 Select. 1 = Counter 1 count and/or status will be latched 1 Counter 0 Select. 1 = Counter 0 count and/or status will be latched. 0 Reserved. Must be 0. Bit Description 7:6 Counter Selection. These bits select the counter for latching. If “11” is written, then the write is interpreted as a read back command. 00 = Counter 0 01 = Counter 1 10 = Counter 2 5:4 Counter Latch Command. 00 = Selects the Counter Latch Command. 3:0 Reserved. Must be 0.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 371 LPC Interface Bridge Registers (D31:F0)

10.3.2 SBYTE_FMT—Interval Time r Status Byte Format Register

(LPC I/F—D31:F0) I/O Address: Counter 0 = 40h, Counter 1 = 41h, Attribute: RO Counter 2 = 42h Size: 8 bits per counter Default Value: Bits[6:0 ] undefined, Bit 7=0 Each counter's status byte can be read following a Read Back Command. If latch status is chosen (bit 4=0, Read Back Command) as a read back option for a given counter, the next read from the counter's Counter Access Ports Register (40h for counter 0, 41h for counter 1, and 42h for counter 2) returns the status byte. The status byte returns the following: Bit Description Counter OUT Pin State — RO. 0 = OUT pin of the counter is also a 0 1 = OUT pin of the counter is also a 1 Count Register Status — RO. This bit indicates when the last count written to the Count Register (CR) has been loaded into the counting element (CE). The exact time this happens depends on the counter mode, but until the count is loaded into the counting element (CE), the count value will be incorrect. 0 = Count has been transferred from CR to CE and is available for reading. 1 = Null Count. Count has not been transferred from CR to CE and is not yet available for reading. 5:4 Read/Write Selection Status — RO. These bits reflect the read/write selection made through bits[5:4] of the control register. The binary codes returned during the status read match the codes used to program the counter read/write selection. 00 = Counter Latch Command 01 = Read/Write Least Significant Byte (LSB) 10 = Read/Write Most Significant Byte (MSB) 11 = Read/Write LSB then MSB 3:1 Mode Selection Status — RO. These bits return the count er mode programming. The binary code returned matches the code used to program the counter mode, as listed under the bit function above. 000 = Mode 0 — Out signal on end of count (=0) 001 = Mode 1 — Hardware retriggerable one-shot x10 = Mode 2 — Rate generator (divide by n counter) x11 = Mode 3 — Square wave output 100 = Mode 4 — Software triggered strobe 101 = Mode 5 — Hardware triggered strobe Countdown Type Status — RO. This bit reflects the current countdown type. 0 = Binary countdown 1 = Binary Coded Decimal (BCD) countdown.

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10.3.3 Counter Access Ports Register (LPC I/F—D31:F0)

I/O Address: Counter 0 – 40h, Counter 1 – 41h, Attribute: R/W Counter 2 – 42h Default Value: All bits undefined Size: 8 bit 10.4 8259 Interrupt Controller (PIC) Registers (LPC I/F—D31:F0)

10.4.1 Interrupt Controller I/O MAP (LPC I/F—D31:F0)

The interrupt controller registers are located at 20h and 21h for the master controller (IRQ 0–7), and at A0h and A1h for the slave controller (IRQ 8–13). These registers have multiple functions, depending upon the data written to them. Table 10-3 shows the different register possibilities for each address. Note: Refer to note addressing active-low interrupt sources in 8259 Interrupt Controllers section (Chapter 5.9). Bit Description 7:0 Counter Port — R/W. Each counter port address is used to program the 16-bit Count Register. The order of programming, either LSB only, MSB only, or LSB then MSB, is defined with the Interval Counter Control Register at port 43h. The counter port is also used to read the current count from the Count Register, and return the status of the counter programming following a Read Back Command. Table 10-3. PIC Registers (LPC I/F—D31:F0) Port Aliases Register Name Default Value Type 20h 24h, 28h, 2Ch, 30h, 34h, 38h, 3Ch Master PIC ICW1 Init. Cmd Word 1 Undefined WO Master PIC OCW2 Op Ctrl Word 2 001XXXXXb WO Master PIC OCW3 Op Ctrl Word 3 X01XXX10b WO 21h 25h, 29h, 2Dh, 31h, 35h, 39h, 3Dh Master PIC ICW2 Init. Cmd Word 2 Undefined WO Master PIC ICW3 Init. Cmd Word 3 Undefined WO Master PIC ICW4 Init. Cmd Word 4 01h WO Master PIC OCW1 Op Ctrl Word 1 00h R/W A0h A4h, A8h, ACh, B0h, B4h, B8h, BCh Slave PIC ICW1 Init. Cmd Word 1 Undefined WO Slave PIC OCW2 Op Ctrl Word 2 001XXXXXb WO Slave PIC OCW3 Op Ctrl Word 3 X01XXX10b WO A1h A5h, A9h, ADh, B1h, B5h, B9h, BDh Slave PIC ICW2 Init. Cmd Word 2 Undefined WO Slave PIC ICW3 Init. Cmd Word 3 Undefined WO Slave PIC ICW4 Init. Cmd Word 4 01h WO Slave PIC OCW1 Op Ctrl Word 1 00h R/W 4D0h – Master PIC Edge/Level Triggered 00h R/W 4D1h – Slave PIC Edge/Level Triggered 00h R/W

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 373 LPC Interface Bridge Registers (D31:F0)

10.4.2 ICW1—Initialization Command Word 1 Register

(LPC I/F—D31:F0) Offset Address: Master Controller – 20h Attribute: WO Slave Controller – A0h Size: 8 bit /controller Default Value: All bits undefined A write to Initialization Command Word 1 starts the interrupt controller initialization sequence, during which the following occurs: 1. The Interrupt Mask register is cleared. 2. IRQ7 input is assigned priority 7. 3. The slave mode address is set to 7. 4. Special mask mode is cleared and Status Read is set to IRR. Once this write occurs, the controller expects writes to ICW2, ICW3, and ICW4 to complete the initialization sequence. Bit Description 7:5 ICW/OCW Select — WO. These bits are MCS-85 specific, and not needed. 000 = Should be programmed to “000” 4 ICW/OCW Select — WO. 1 = This bit must be a 1 to select ICW1 and enable the ICW2, ICW3, and ICW4 sequence. 3 Edge/Level Bank Select (LTIM) — WO. Disabled. Replaced by the edge/level triggered control registers (ELCR, D31:F0:4D0h, D31:F0:4D1h). 2 ADI — WO. 0 = Ignored for the ICH6. Should be programmed to 0. 1 Single or Cascade (SNGL) — WO. 0 = Must be programmed to a 0 to indicate two controllers operating in cascade mode. 0 ICW4 Write Required (IC4) — WO. 1 = This bit must be programmed to a 1 to indicate that ICW4 needs to be programmed.

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10.4.3 ICW2—Initialization Command Word 2 Register

(LPC I/F—D31:F0) Offset Address: Master Controller – 21h Attribute: WO Slave Controller – A1h Size: 8 bit /controller Default Value: All bits undefined ICW2 is used to initialize the interrupt controller with the five most significant bits of the interrupt vector address. The value programmed for bits[7:3] is used by the processor to define the base address in the interrupt vector table for the interrupt routines associated with each IRQ on the controller. Typical ISA ICW2 values are 08h for the master controller and 70h for the slave controller.

10.4.4 ICW3—Master Controlle r Initialization Command

Word 3 Register (LPC I/F—D31:F0) Offset Address: 21h Attribute: WO Default Value: All bits undefined Size: 8 bits Bit Description 7:3 Interrupt Vector Base Address — WO. Bits [7:3] define the base address in the interrupt vector table for the interrupt routines associated with each interrupt request level input. 2:0 Interrupt Request Level — WO. When writing ICW2, these bits should all be 0. During an interrupt acknowledge cycle, these bits are programmed by the interrupt controller with the interrupt to be serviced. This is combined with bits [7:3] to form the interrupt vector driven onto the data bus during the second INTA# cycle. The code is a three bit binary code: Code Master Interrupt Slave Interrupt 000b IRQ0 IRQ8 001b IRQ1 IRQ9 010b IRQ2 IRQ10 011b IRQ3 IRQ11 100b IRQ4 IRQ12 101b IRQ5 IRQ13 110b IRQ6 IRQ14 111b IRQ7 IRQ15 Bit Description 7:3 0 = These bits must be programmed to 0. Cascaded Interrupt Controller IRQ Connection — WO. This bit indicates that the slave controller is cascaded on IRQ2. When IRQ8#–IRQ15 is asserted, it goes through the slave controller’s priority resolver. The slave controller’s INTR output onto IRQ2. IRQ2 then goes through the master controller’s priority solver. If it wins, the INTR signal is asserted to the processor, and the returning interrupt acknowledge returns the interrupt vector for the slave controller. 1 = This bit must always be programmed to a 1. 1:0 0 = These bits must be programmed to 0.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 375 LPC Interface Bridge Registers (D31:F0)

10.4.5 ICW3—Slave Controlle r Initialization Command

Word 3 Register (LPC I/F—D31:F0) Offset Address: A1h Attribute: WO Default Value: All bits undefined Size: 8 bits

10.4.6 ICW4—Initialization Command Word 4 Register

(LPC I/F—D31:F0) Offset Address: Master Controller – 021h Attribute: WO Slave Controller – 0A1h Size: 8 bits Default Value: 01h Bit Description 7:3 0 = These bits must be programmed to 0. 2:0 Slave Identification Code — WO. These bits are compared agai nst the slave identification code broadcast by the master controller from the trailing edge of the first internal INTA# pulse to the trailing edge of the second internal INTA# pulse. These bits must be programmed to 02h to match the code broadcast by the master controller. When 02h is broadcast by the master controller during the INTA# sequence, the slave controller assumes responsibility for broadcasting the interrupt vector. Bit Description 7:5 0 = These bits must be programmed to 0. Special Fully Nested Mode (SFNM) — WO. 0 = Should normally be disabled by writing a 0 to this bit. 1 = Special fully nested mode is programmed. 3 Buffered Mode (BUF) — WO. 0 = Must be programmed to 0 for the ICH6. This is non-buffered mode. 2 Master/Slave in Buffered Mode — WO. Not used. 0 = Should always be programmed to 0. Automatic End of Interrupt (AEOI) — WO. 0 = This bit should normally be programmed to 0. This is the normal end of interrupt. 1 = Automatic End of Interrupt (AEOI) mode is programmed. Microprocessor Mode — WO. 1 = Must be programmed to 1 to indicate that the controller is operating in an Intel Architecture-based system.

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10.4.7 OCW1—Operational Control Word 1 (Interrupt Mask)

Register (LPC I/F—D31:F0) Offset Address: Master Controller – 021h Attribute: R/W Slave Controller – 0A1h Size: 8 bits Default Value: 00h

10.4.8 OCW2—Operational Control Word 2 Register

(LPC I/F—D31:F0) Offset Address: Master Controller – 020h Attribute: WO Slave Controller – 0A0h Size: 8 bits Default Value: Bit[4:0]=undefined, Bit[7:5]=001 Following a part reset or ICW initialization, the controller enters the fully nested mode of operation. Non-specific EOI without rotation is the default. Both rotation mode and specific EOI mode are disabled following initialization. Bit Description 7:0 Interrupt Request Mask — R/W. When a 1 is written to any bi t in this register, the corresponding IRQ line is masked. When a 0 is written to any bit in this register, the corresponding IRQ mask bit is cleared, and interrupt requests will again be accepted by the controller. Masking IRQ2 on the master controller will also mask the interrupt requests from the slave controller. Bit Description 7:5 Rotate and EOI Codes (R, SL, EOI) — WO. These three bits control the Rotate and End of Interrupt modes and combinations of the two. 000 = Rotate in Auto EOI Mode (Clear) 001 = Non-specific EOI command 010 = No Operation 011 = *Specific EOI Command 100 = Rotate in Auto EOI Mode (Set) 101 = Rotate on Non-Specific EOI Command 110 = *Set Priority Command 111 = *Rotate on Specific EOI Command *L0 – L2 Are Used 4:3 OCW2 Select — WO. When selecting OCW2, bits 4:3 = “00” 2:0 Interrupt Level Select (L2, L1, L0) — WO. L2, L1, and L0 determine the interrupt level acted upon when the SL bit is active. A simple binary code, outlined below, selects the channel for the command to act upon. When the SL bit is inactive, these bits do not have a defined function; programming L2, L1 and L0 to 0 is sufficient in this case. Code Interrupt Level Code Interrupt Level 000b IRQ0/8 000b IRQ4/12 001b IRQ1/9 001b IRQ5/13 010b IRQ2/10 010b IRQ6/14 011b IRQ3/11 011b IRQ7/15

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 377 LPC Interface Bridge Registers (D31:F0)

10.4.9 OCW3—Operational Control Word 3 Register

(LPC I/F—D31:F0) Offset Address: Master Controller – 020h Attribute: WO Slave Controller – 0A0h Size: 8 bits Default Value: Bit[6,0]= 0, Bit[7,4:2]=undefined, Bit[5,1]=1 Bit Description 7 Reserved. Must be 0. Special Mask Mode (SMM) — WO. 1 = The Special Mask Mode can be used by an interr upt service routine to dynamically alter the system priority structure while the routine is executing, through selective enabling/disabling of the other channel's mask bits. Bit 5, the ESMM bit, must be set for this bit to have any meaning. Enable Special Mask Mode (ESMM) — WO. 0 = Disable. The SMM bit becomes a “don't care”. 1 = Enable the SMM bit to set or reset the Special Mask Mode. 4:3 OCW3 Select — WO. When selecting OCW3, bits 4:3 = 01 Poll Mode Command — WO. 0 = Disable. Poll Command is not issued. 1 = Enable. The next I/O read to the interrupt c ontroller is treated as an interrupt acknowledge cycle. An encoded byte is driven onto the data bus, representing the highest priority level requesting service. 1:0 Register Read Command — WO. These bits provide control for reading the In-Service Register (ISR) and the Interrupt Request Register (IRR). When bit 1=0, bit 0 will not affect the register read selection. When bit 1=1, bit 0 selects the register status returned following an OCW3 read. If bit 0=0, the IRR will be read. If bit 0=1, the ISR will be read. Following ICW initialization, the default OCW3 port address read will be “read IRR”. To retain the current selection (read ISR or read IRR), always write a 0 to bit 1 when programming this register. The selected register can be read repeatedly without reprogramming OCW3. To select a new status register, OCW3 must be reprogrammed prior to attempting the read. 00 = No Action 01 = No Action 10 = Read IRQ Register 11 = Read IS Register

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10.4.10 ELCR1—Master Controller Edge/Level Triggered Register

(LPC I/F—D31:F0) Offset Address: 4D0h Attribute: R/W Default Value: 00h Size: 8 bits In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In level mode (bit[x] = 1), the interrupt is recognized by a high level. The cascade channel, IRQ2, the heart beat timer (IRQ0), and the keyboard controller (IRQ1), cannot be put into level mode. Bit Description IRQ7 ECL — R/W. 0 = Edge. 1 = Level. IRQ6 ECL — R/W. 0 = Edge. 1 = Level. IRQ5 ECL — R/W. 0 = Edge. 1 = Level. IRQ4 ECL — R/W. 0 = Edge. 1 = Level. IRQ3 ECL — R/W. 0 = Edge. 1 = Level. 2:0 Reserved. Must be 0.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 379 LPC Interface Bridge Registers (D31:F0)

10.4.11 ELCR2—Slave Controller Edge/Level Triggered Register

(LPC I/F—D31:F0) Offset Address: 4D1h Attribute: R/W Default Value: 00h Size: 8 bits In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In level mode (bit[x] = 1), the interrupt is recognized by a high level. The real time clock, IRQ8#, and the floating point error interrupt, IRQ13, cannot be programmed for level mode. Bit Description IRQ15 ECL — R/W. 0 = Edge 1 = Level IRQ14 ECL — R/W. 0 = Edge 1 = Level 5 Reserved. Must be 0. IRQ12 ECL — R/W. 0 = Edge 1 = Level IRQ11 ECL — R/W. 0 = Edge 1 = Level IRQ10 ECL — R/W. 0 = Edge 1 = Level IRQ9 ECL — R/W. 0 = Edge 1 = Level 0 Reserved. Must be 0.

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10.5 Advanced Programmable Interrupt Controller

(APIC)(D31:F0)

10.5.1 APIC Register Map (LPC I/F—D31:F0)

The APIC is accessed via an indirect addressing scheme. Two registers are visible by software for manipulation of most of the APIC registers. These registers are mapped into memory space. The registers are shown in Table 10-4. Table 10-5 lists the registers which can be accessed within the APIC via the Index Register. When accessing these registers, accesses must be done one DWord at a time. For example, software should never access byte 2 from the Data register before accessing bytes 0 and 1. The hardware will not attempt to recover from a bad programming model in this case.

10.5.2 IND—Index Regi ster (LPC I/F—D31:F0)

Memory Address FEC0_0000h Attribute: R/W Default Value: 00h Size: 8 bits The Index Register will select which APIC indirect register to be manipulated by software. The selector values for the indirect registers are listed in Table 10-5. Software will program this register to select the desired APIC internal register Table 10-4. APIC Direct Registers (LPC I/F—D31:F0) Address Mnemonic Register Name Size Type FEC0_0000h IND Index 8 bits R/W FEC0_0010h DAT Data 32 bits R/W FECO_0040h EOIR EOI 32 bits WO Table 10-5. APIC Indirect Registers (LPC I/F—D31:F0) Index Mnemonic Register Name Size Type

00 ID Identification 32 bits R/W

01 VER Version 32 bits RO

02–0F — Reserved — RO 10–11 REDIR_TBL0 Redirection Table 0 64 bits R/W, RO 12–13 REDIR_TBL1 Redirection Table 1 64 bits R/W, RO 3E–3F REDIR_TBL23 Redirection Table 23 64 bits R/W, RO 40–FF — Reserved — RO Bit Description 7:0 APIC Index — R/W. This is an 8-bit pointer into the I/O APIC register table.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 381 LPC Interface Bridge Registers (D31:F0)

10.5.3 DAT—Data Regis ter (LPC I/F—D31:F0)

Memory Address FEC0_0010h Attribute: R/W Default Value: 00000000h Size: 32 bits This is a 32-bit register specifying the data to be read or written to the register pointed to by the Index register. This register can only be accessed in DWord quantities.

10.5.4 EOIR—EOI Regist er (LPC I/F—D31:F0)

Memory Address FEC0_0040h Attribute: WO Default Value: N/A Size: 32 bits The EOI register is present to provide a mechanism to maintain the level triggered semantics for level-triggered interrupts issued on the parallel bus. When a write is issued to this register, the I/O APIC will check the lower 8 bits written to this register, and compare it with the vector field for each entry in the I/O Redirection Table. When a match is found, the Remote_IRR bit (Index Offset 10h, bit 14) for that I/O Redirection Entry will be cleared. Note: If multiple I/O Redirection entries, for any reason, assign the same vector for more than one interrupt input, each of those entries will have the Remote_IRR bit reset to 0. The interrupt which was prematurely reset will not be lost because if its input remained active when the Remote_IRR bit is cleared, the interrupt will be reissued and serviced at a later time. Note: Only bits 7:0 are actually used. Bits 31:8 are ignored by the ICH6. Note: To provide for future expansion, the processor should always write a value of 0 to Bits 31:8. Bit Description 7:0 APIC Data — R/W. This is a 32-bit register for the data to be read or written to the APIC indirect register (Figure 10-5) pointed to by the Index register (Memory Address FEC0_0000h). Bit Description 31:8 Reserved. To provide for future expansion, the processor should always write a value of 0 to Bits 31:8. 7:0 Redirection Entry Clear — WO. When a write is issued to this register, the I/O APIC will check this field, and compare it with the vector field for each entry in the I/O Redirection Table. When a match is found, the Remote_IRR bit for that I/O Redirection Entry will be cleared.

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10.5.5 ID—Identification Register (LPC I/F—D31:F0)

Index Offset: 00h Attribute: R/W Default Value: 00000000h Size: 32 bits The APIC ID serves as a physical name of the APIC. The APIC bus arbitration ID for the APIC is derived from its I/O APIC ID. This register is reset to 0 on power-up reset.

10.5.6 VER—Version Regi ster (LPC I/F—D31:F0)

Index Offset: 01h Attribute: RO Default Value: 00170020h Size: 32 bits Each I/O APIC contains a hardwired Version Register that identifies different implementation of APIC and their versions. The maximum redirection entry information also is in this register, to let software know how many interrupt are supported by this APIC. Bit Description 31:28 Reserved 27:24 APIC ID — R/W. Software must program this value before using the APIC. 23:16 Reserved 15 Scratchpad Bit. 14:0 Reserved Bit Description 31:24 Reserved 23:16 Maximum Redirection Entries — RO. This is the entry number (0 being the lowest entry) of the highest entry in the redirection table. It is equal to the number of interrupt input pins minus one and is in the range 0 through 239. In the ICH6 this field is hardwired to 17h to indicate 24 interrupts. 15 PRQ — RO. This bit indicate that the IOxAPIC does not implement the Pin Assertion Register. 14:8 Reserved 7:0 Version — RO. This is a version number that identifies the implementation version.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 383 LPC Interface Bridge Registers (D31:F0)

10.5.7 REDIR_TBL—Redirectio n Table (LPC I/F—D31:F0)

Index Offset: 10h –11h (vector 0) through Attribute: R/W, RO 3E–3Fh (vector 23) Default Value: Bit 16 = 1,. Size: 64 bits each, (accessed as All other bits undefined two 32 bit quantities) The Redirection Table has a dedicated entry for each interrupt input pin. The information in the Redirection Table is used to translate the interrupt manifestation on the corresponding interrupt pin into an APIC message. The APIC will respond to an edge triggered interrupt as long as the interrupt is held until after the acknowledge cycle has begun. Once the interrupt is detected, a delivery status bit internally to the I/O APIC is set. The state machine will step ahead and wait for an acknowledgment from the APIC unit that the interrupt message was sent. Only then will the I/O APIC be able to recognize a new edge on that interrupt pin. That new edge will only result in a new invocation of the handler if its acceptance by the destination APIC causes the Interrupt Request Register bit to go from 0 to 1. (In other words, if the interrupt was not already pending at the destination.) Bit Description 63:56 Destination — R/W. If bit 11 of this entry is 0 (Physical), then bits 59:56 specifies an APIC ID. In this case, bits 63:59 should be programmed by software to 0. If bit 11 of this entry is 1 (Logical), then bits 63:56 specify the logical destination address of a set of processors. 55:48 Extended Destination ID (EDID) — RO. These bits are sent to a local APIC only when in Processor System Bus mode. They become bits 11:4 of the address. 47:17 Reserved Mask — R/W. 0 = Not masked: An edge or level on this interrupt pi n results in the delivery of the interrupt to the destination. 1 = Masked: Interrupts are not delivered nor held pending. Setting this bit after the interrupt is accepted by a local APIC has no effect on that interrupt. This behavior is identical to the device withdrawing the interrupt before it is posted to the processor. It is software's responsibility to deal with the case where the mask bit is set after the interrupt message has been accepted by a local APIC unit but before the interrupt is dispensed to the processor. Trigger Mode — R/W. This field indicates the type of signal on the interrupt pin that triggers an interrupt. 0 = Edge triggered. 1 = Level triggered. Remote IRR — R/W. This bit is used for level tri ggered interrupts; its meaning is undefined for edge triggered interrupts. 0 = Reset when an EOI message is received from a local APIC. 1 = Set when Local APIC/s accept the le vel interrupt sent by the I/O APIC. Interrupt Input Pin Polarity — R/W. This bit specifies the polarity of each interrupt signal connected to the interrupt pins. 0 = Active high. 1 = Active low. Delivery Status — RO. This field contains the current status of the delivery of this interrupt. Writes to this bit have no effect. 0 = Idle. No activity for this interrupt. 1 = Pending. Interrupt has been injected, but delivery is not complete.

384 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

LPC Interface Bridge Registers (D31:F0) NOTE: Delivery Mode encoding: 000 = Fixed. Deliver the signal on the INTR signal of all processor cores listed in the destination. Trigger Mode can be edge or level. 001 = Lowest Priority. Deliver the signal on the INTR signal of the processor core that is executing at the lowest priority among all the processors listed in the specified destination. Trigger Mode can be edge or level. 010 = SMI (System Management Interrupt). Requires the interrupt to be programmed as edge triggered. The vector information is ignored but must be programmed to all 0’s for future compatibility: not supported 011 = Reserved 100 = NMI. Deliver the signal on the NMI signal of all processor cores listed in the destination. Vector information is ignored. NMI is treated as an edge triggered interrupt even if it is programmed as level triggered. For proper operation this redirection table entry must be programmed to edge triggered. The NMI delivery mode does not set the RIRR bit. If the redirection table is incorrectly set to level, the loop count will continue counting through the redirection table addresses. Once the count for the NMI pin is reached again, the interrupt will be sent again: not supported 101 = INIT. Deliver the signal to all processor cores listed in the destination by asserting the INIT signal. All addressed local APICs will assume their INIT state. INIT is always treated as an edge triggered interrupt even if programmed as level triggered. For proper operation this redirection table entry must be programmed to edge triggered. The INIT delivery mode does not set the RIRR bit. If the redirection table is incorrectly set to level, the loop count will continue counting through the redirection table addresses. Once the count for the INIT pin is reached again, the interrupt will be sent again: not supported 110 = Reserved 111 = ExtINT. Deliver the signal to the INTR signal of all processor cores listed in the destination as an interrupt that originated in an externally connected 8259A compatible interrupt controller. The INTA cycle that corresponds to this ExtINT delivery will be routed to the external controller that is expected to supply the vector. Requires the interrupt to be programmed as edge triggered. Destination Mode — R/W. This field determines the in terpretation of the Destination field. 0 = Physical. Destination APIC ID is identified by bits 59:56. 1 = Logical. Destinations are ident ified by matching bit 63:56 with the Logical Destination in the Destination Format Register and Logical Destination Register in each Local APIC. 10:8 Delivery Mode — R/W. This field specifies how the APIC s listed in the destination field should act upon reception of this signal. Certain Delivery Modes will only operate as intended when used in conjunction with a specific trigger mode. These encodings are listed in the note below: 7:0 Vector — R/W. This field contains the interrupt ve ctor for this interrupt. Values range between 10h and FEh. Bit Description

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10.6 Real Time Clock Registers (LPC I/F—D31:F0)

10.6.1 I/O Register Addr ess Map (LPC I/F—D31:F0)

The RTC internal registers and RAM are organized as two banks of 128 bytes each, called the standard and extended banks. The first 14 bytes of the standard bank contain the RTC time and date information along with four registers, A–D, that are used for configuration of the RTC. The extended bank contains a full 128 bytes of battery backed SRAM, and will be accessible even when the RTC module is disabled (via the RTC configuration register). Registers A–D do not physically exist in the RAM. All data movement between the host processor and the real-time clock is done through registers mapped to the standard I/O space. The register map appears in Table 10-6. NOTES: 1. I/O locations 70h and 71h are the standard legacy location for the real-time clock. The map for this bank is shown in Table 10-7. Locations 72h and 73h are for accessing the extended RAM. The extended RAM bank is also accessed using an indexed scheme. I/O address 72h is used as the address pointer and I/O address 73h is used as the data register. Index addresses above 127h are not valid. If the extended RAM is not needed, it may be disabled. 2. Software must preserve the value of bit 7 at I/O addresses 70h and 74h. When writing to this address, software must first read the value, and then write the same value for bit 7 during the sequential address write. Note that port 70h is not directly readable. The only way to read this register is through Alt Access mode. Although RTC Index bits 6:0 are readable from port 74h, bit 7 will always return 0. If the NMI# enable is not changed during normal operation, software can alternatively read this bit once and then retain the value for all subsequent writes to port 70h. Table 10-6. RTC I/O Registers (LPC I/F—D31:F0) I/O Locations If U128E bit = 0 Function 70h and 74h Also alias to 72h and 76h Real-T ime Clock (Standard RAM) Index Register 71h and 75h Also alias to 73h and 77h Real-Time Clock (Standard RAM) Target Register 72h and 76h Extended RAM Index Register (if enabled) 73h and 77h Extended RAM Target Register (if enabled)

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10.6.2 Indexed Registers (LPC I/F—D31:F0)

The RTC contains two sets of indexed registers that are accessed using the two separate Index and Target registers (70/71h or 72/73h), as shown in Table 10-7. Table 10-7. RTC (Standard) RAM Bank (LPC I/F—D31:F0) Index Name 00h Seconds 01h Seconds Alarm 02h Minutes 03h Minutes Alarm 04h Hours 05h Hours Alarm 06h Day of Week 07h Day of Month 08h Month 09h Year 0Ah Register A 0Bh Register B 0Ch Register C 0Dh Register D 0Eh–7Fh 114 Bytes of User RAM

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 387 LPC Interface Bridge Registers (D31:F0)

10.6.2.1 RTC_REGA—Register A (LPC I/F—D31:F0)

RTC Index: 0A Attribute: R/W Default Value: Undefined Size: 8-bit Lockable: No Power Well: RTC This register is used for general configuration of the RTC functions. None of the bits are affected by RSMRST# or any other ICH6 reset signal. Bit Description Update In Progress (UIP) — R/W. This bit may be monitored as a status flag. 0 = The update cycle will not start for at least 488 µs. The time, calendar, and alarm information in RAM is always available when the UIP bit is 0. 1 = The update is soon to occur or is in progress. 6:4 Division Chain Select (DV[2:0]) — R/W. These three bits control the divider chain for the oscillator, and are not affected by RSMRST# or any other reset signal. DV2 corresponds to bit 6. 010 = Normal Operation 11X = Divider Reset 101 = Bypass 15 stages (test mode only) 100 = Bypass 10 stages (test mode only) 011 = Bypass 5 stages (test mode only) 001 = Invalid 000 = Invalid 3:0 Rate Select (RS[3:0]) — R/W. These bits selects one of 13 taps of the 15 stage divider chain. The selected tap can generate a periodic interrupt if the PIE bit is set in Register B. Otherwise this tap will set the PF flag of Register C. If the periodic interrupt is not to be used, these bits should all be set to 0. RS3 corresponds to bit 3. 0000 = Interrupt never toggles 0001 = 3.90625 ms 0010 = 7.8125 ms 0011 = 122.070 µs 0100 = 244.141 µs 0101 = 488.281 µs 0110 = 976.5625 µs 0111 = 1.953125 ms 1000 = 3.90625 ms 1001 = 7.8125 ms 1010 = 15.625 ms 1011 = 31.25 ms 1100 = 62.5 ms 1101 = 125 ms 1110 = 250 ms 1111= 500 ms

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10.6.2.2 RTC_REGB—Register B (General Configuration)

(LPC I/F—D31:F0) RTC Index: 0Bh Attribute: R/W Default Value: U0U00UUU (U: Undefined) Size: 8-bit Lockable: No Power Well: RTC Bit Description Update Cycle Inhibit (SET) — R/W. This bit enables/Inhibits the update cycles. This bit is not affected by RSMRST# nor any other reset signal. 0 = Update cycle occurs normally once each second. 1 = A current update cycle will abort and subs equent update cycles will not occur until SET is returned to 0. When set is one, the BIOS may initialize time and calendar bytes safely. NOTE: This bit should be set then cleared early in BIOS POST after each powerup directly after coin-cell battery insertion. Periodic Interrupt Enable (PIE) — R/W. This bit is cleared by RSMRST#, but not on any other reset. 0 = Disable. 1 = Enable. Allows an interrupt to occur with a ti me base set with the RS bits of register A. Alarm Interrupt Enable (AIE) — R/W. This bit is cleared by RTCRST#, but not on any other reset. 0 = Disable. 1 = Enable. Allows an interrupt to occur when th e AF is set by an alarm match from the update cycle. An alarm can occur once a second, one an hour, once a day, or one a month. Update-Ended Interrupt Enable (UIE) — R/W. This bit is cleared by RSMRST#, but not on any other reset. 0 = Disable. 1 = Enable. Allows an interrupt to occur when the update cycle ends. Square Wave Enable (SQWE) — R/W. This bit serves no function in the ICH6. It is left in this register bank to provide compatibility with the Motorola 146818B. The ICH6 has no SQW pin. This bit is cleared by RSMRST#, but not on any other reset. Data Mode (DM) — R/W. This bit specifies either binary or BCD data representation. This bit is not affected by RSMRST# nor any other reset signal. 0 = BCD 1 = Binary Hour Format (HOURFORM) — R/W. This bit indicates the hour byte format. This bit is not affected by RSMRST# nor any other reset signal. 0 = Twelve-hour mode. In twelve-hour mode, the seventh bit represents AM as 0 and PM as one. 1 = Twenty-four hour mode. Daylight Savings Enable (DSE) — R/W. This bit triggers two special hour updates per year. The days for the hour adjustment are those specified in United States federal law as of 1987, which is different than previous years. This bit is not affected by RSMRST# nor any other reset signal. 0 = Daylight Savings Time updates do not occur. 1 = a) Update on the first Sunday in April, where time increments from 1:59:59 AM to 3:00:00 AM. b) Update on the last Sunday in October when the time first reaches 1:59:59 AM, it is changed to 1:00:00 AM. The time must increment normally for at least two update cycles (seconds) previous to these conditions for the time change to occur properly.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 389 LPC Interface Bridge Registers (D31:F0)

10.6.2.3 RTC_REGC—Register C (Flag Register)

(LPC I/F—D31:F0) RTC Index: 0Ch Attribute: RO Default Value: 00U00000 (U: Undefined) Size: 8-bit Lockable: No Power Well: RTC Writes to Register C have no effect.

10.6.2.4 RTC_REGD—Register D (Flag Register)

(LPC I/F—D31:F0) RTC Index: 0Dh Attribute: R/W Default Value: 10UUUUUU (U: Undefined) Size: 8-bit Lockable: No Power Well: RTC Bit Description 7 Interrupt Request Flag (IRQF) — RO. IRQF = (PF * PIE) + (AF * AI E) + (UF *UFE). This bit also causes the RTC Interrupt to be asserted. This bit is cleared upon RSMRST# or a read of Register C. Periodic Interrupt Flag (PF) — RO. This bit is cleared upon RSMRST# or a read of Register C. 0 = If no taps are specified via the RS bits in Register A, this flag will not be set. 1 = Periodic interrupt Flag will be 1 when the tap specified by the RS bits of register A is 1. Alarm Flag (AF) — RO. 0 = This bit is cleared upon RTCRST# or a read of Register C. 1 = Alarm Flag will be set after all Alarm values match the current time. Update-Ended Flag (UF) — RO. 0 = The bit is cleared upon RSMRST# or a read of Register C. 1 = Set immediately following an update cycle for each second. 3:0 Reserved. Will always report 0. Bit Description Valid RAM and Time Bit (VRT) — R/W. 0 = This bit should always be written as a 0 for write cycle, however it will return a 1 for read cycles. 1 = This bit is hardwired to 1 in the RTC power well. 6 Reserved. This bit always returns a 0 and should be set to 0 for write cycles. 5:0 Date Alarm — R/W. These bits store the date of month alarm value. If set to 000000b, then a don’t care state is assumed. The host must configure the date alarm for these bits to do anything, yet they can be written at any time. If the date alarm is not enabled, these bits will return 0’s to mimic the functionality of the Motorola 146818B. These bits are not affected by any reset assertion.

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10.7 Processor Interface Registers (LPC I/F—D31:F0)

Table 10-8 is the register address map for the processor interface registers.

10.7.1 NMI_SC—NMI Status and Control Register

(LPC I/F—D31:F0) I/O Address: 61h Attribute: R/W, RO Default Value: 00h Size: 8-bit Lockable: No Power Well: Core Table 10-8. Processor Interface PCI Register Address Map (LPC I/F—D31:F0) Offset Mnemonic Register Name Default Type 61h NMI_SC NMI Status and Control 00h R/W, RO 70h NMI_EN NMI Enable 80h R/W (special) 92h PORT92 Fast A20 and Init 00h R/W F0h COPROC_ERR Coprocessor Error 00h WO CF9h RST_CNT Reset Control 00h R/W Bit Description SERR# NMI Source Status (SERR#_NMI_STS) — RO. 1 = Bit is set if a PCI agent detected a system error and pulses the PCI SERR# line and if bit 2 (PCI_SERR_EN) is cleared. This interrupt source is enabled by setting bit 2 to 0. To reset the interrupt, set bit 2 to 1 and then set it to 0. When writing to port 61h, this bit must be 0. NOTE: This bit is set by any of the ICH6 internal sources of SERR; this includes SERR assertions forwarded from the secondary PCI bus, errors on a PCI Express* port, or other internal functions that generate SERR#. IOCHK# NMI Source Status (IOCHK_NMI_STS) — RO. 1 = Bit is set if an LPC agent (via SERIRQ) as serted IOCHK# and if bit 3 (IOCHK_NMI_EN) is cleared. This interrupt source is enabled by setting bit 3 to 0. To reset the interrupt, set bit 3 to 1 and then set it to 0. When writing to port 61h, this bit must be a 0. Timer Counter 2 OUT Status (TMR2_OUT_STS) — RO. This bit reflects the current state of the 8254 counter 2 output. Counter 2 must be programmed following any PCI reset for this bit to have a determinate value. When writing to port 61h, this bit must be a 0. Refresh Cycle Toggle (REF_TOGGLE) — RO. This signal toggles from ei ther 0 to 1 or 1 to 0 at a rate that is equivalent to when refresh cycles would occur. When writing to port 61h, this bit must be a 0. IOCHK# NMI Enable (IOCHK_NMI_EN) — R/W. 0 = Enabled. 1 = Disabled and cleared. PCI SERR# Enable (PCI_SERR_EN) — R/W. 0 = SERR# NMIs are enabled. 1 = SERR# NMIs are disabled and cleared. Speaker Data Enable (SPKR_DAT_EN) — R/W. 0 = SPKR output is a 0. 1 = SPKR output is equivalent to the Counter 2 OUT signal value. Timer Counter 2 Enable (TIM_CNT2_EN) — R/W. 0 = Disable 1 = Enable

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 391 LPC Interface Bridge Registers (D31:F0)

10.7.2 NMI_EN—NMI Enable (and Real Time Clock Index)

Register (LPC I/F—D31:F0) I/O Address: 70h Attri bute: R/W (special) Default Value: 80h Size: 8-bit Lockable: No Power Well: Core Note: The RTC Index field is write-only for normal operation. This field can only be read in Alt-Access Mode. Note, however, that this register is aliased to Port 74h (documented in), and all bits are readable at that address.

10.7.3 PORT92—Fast A20 and In it Register (LPC I/F—D31:F0)

I/O Address: 92h Attribute: R/W Default Value: 00h Size: 8-bit Lockable: No Power Well: Core Bits Description NMI Enable (NMI_EN) — R/W (special). 0 = Enable NMI sources. 1 = Disable All NMI sources. 6:0 Real Time Clock Index Address (RTC_INDX) — R/W (special). This data goes to the RTC to select which register or CMOS RAM address is being accessed. Bit Description 7:2 Reserved Alternate A20 Gate (ALT_A20_GATE) — R/W. This bit is Or’d with the A20GATE input signal to generate A20M# to the processor. 0 = A20M# signal can potentially go active. 1 = This bit is set when INIT# goes active. 0 INIT_NOW — R/W. When this bit transitions from a 0 to a 1, the ICH6 will force INIT# active for 16 PCI clocks.

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10.7.4 COPROC_ERR—Coprocessor Error Register

(LPC I/F—D31:F0) I/O Address: F0h Attribute: WO Default Value: 00h Size: 8-bits Lockable: No Power Well: Core

10.7.5 RST_CNT—Reset Control Register (LPC I/F—D31:F0)

I/O Address: CF9h Attribute: R/W Default Value: 00h Size: 8-bit Lockable: No Power Well: Core Bits Description 7:0 Coprocessor Error (COPROC_ERR) — WO. Any value written to this register will cause IGNNE# to go active, if FERR# had generated an internal IRQ13. For FERR# to generate an internal IRQ13, the COPROC_ERR_EN bit (Device 31:Function 0, Offset D0, Bit 13) must be 1. Bit Description 7:4 Reserved Full Reset (FULL_RST) — R/W. This bit is used to determine the states of SLP_S3#, SLP_S4#, and SLP_S5# after a CF9 hard reset (SYS_RST =1 and RST_CPU is set to 1), after PWROK going low (with RSMRST# high), or after two TCO timeouts. 0 = ICH6 will keep SLP_S3#, SLP_S4# and SLP_S5# high. 1 = ICH6 will drive SLP_S3#, SLP_S4# and SLP_S5# low for 3 – 5 seconds. NOTE: When this bit is set, it also causes the full power cycle (SLP_S3/4/5# assertion) in response to SYSRESET#, PWROK#, and Watchdog timer reset sources. 2 Reset CPU (RST_CPU) — R/W. When this bit transitions from a 0 to a 1, it initiates a hard or soft reset, as determined by the SYS_RST bit (bit 1 of this register). System Reset (SYS_RST) — R/W. This bit is used to determine a hard or soft reset to the processor. 0 = When RST_CPU bit goes from 0 to 1, the ICH6 performs a soft reset by activating INIT# for 16 PCI clocks. 1 = When RST_CPU bit goes from 0 to 1, the ICH6 performs a hard reset by activating PLTRST# and SUS_STAT# active for about 5-6 milliseconds, however the SLP_S3#, SLPS4# and SLP_S5# will NOT go active. The ICH6 main power well is reset when this bit is 1. It also resets the resume well bits (except for those noted throughout the Datasheet).

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 393 LPC Interface Bridge Registers (D31:F0)

10.8 Power Management Registers (PM—D31:F0)

The power management registers are distributed within the PCI Device 31: Function 0 space, as well as a separate I/O range. Each register is described below. Unless otherwise indicate, bits are in the main (core) power well. Bits not explicitly defined in each register are assumed to be reserved. When writing to a reserved bit, the value should always be 0. Software should not attempt to use the value read from a reserved bit, as it may not be consistently 1 or 0.

10.8.1 Power Management PC I Configuration Registers

(PM—D31:F0) Table 10-9 shows a small part of the configuration space for PCI Device 31: Function 0. It includes only those registers dedicated for power management. Some of the registers are only used for Legacy Power management schemes. Table 10-9. Power Management PCI Register Address Map (PM—D31:F0) Offset Mnemonic Register Name Default Type A0h GEN_PMCON_1 General Power Management Configuration 1 0000h R/W, RO, R/WO A2h GEN_PMCON_2 General Power Management Configuration 2 00h R/W, R/WC A4h GEN_PMCON_3 General Power Management Configuration 3 00h R/W, R/WC A9h Cx-STATE_CNF Cx State Configuration (Mobile Only). 00h R/W AAh C4-TIMING_CNT C4 Timing Control (Mobile Only). 00h R/W ABh BM_BREAK_EN BM_BREAK_EN 00h R/W ADh MSC_FUN Miscellaneous Functionality 00h R/W B8–BBh GPI_ROUT GPI Route Control 00000000h R/W

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10.8.1.1 GEN_PMCON_1—General PM Configuration 1 Register

(PM—D31:F0) Offset Address: A0h Att ribute: R/W, RO, R/WO Default Value: 0000h Size: 16-bit Lockable: No Usage: ACPI, Legacy Power Well: Core Bit Description 15:11 Reserved BIOS_PCI_EXP_EN — R/W. This bit acts as a global enable for the SCI associated with the PCI Express* ports. 0 = The various PCI Express ports and (G)MCH cannot cause the PCI_EXP_STS bit to go active. 1 = The various PCI Express ports and (G)MCH c an cause the PCI_EXP_STS bit to go active. PWRBTN_LVL — RO. This bit indicates the current state of the PWRBTN# signal. 0 = Low. 1 = High. 8R e s e r v e d (Desktop Only) Reserved (Mobile Only) Enter C4 When C3 Invoked (C4onC3_EN) — R/W. If this bit is set, then when software does a LVL3 read, the ICH6 transitions to the C4 state. 6 i64_EN. Software sets this bit to indicate that the processor is an IA_64 processor, not an IA_32 processor. This may be used in various state machines where there are behavioral differences. CPU SLP# Enable (CPUSLP_EN) — R/W. 0 = Disable. 1 = Enables the CPUSLP# signal to go active in the S1 state. This reduces the processor power. NOTE: CPUSLP# will go active during Intel SpeedStep® technology transitions and on entry to C3 and C4 states even if this bit is not set. SMI_LOCK — R/WO. When this bit is set, writes to the GLB_SMI_EN bit (PMBASE + 30h, bit 0) will have no effect. Once the SMI_LOCK bit is set, writes of 0 to SMI_LOCK bit will have no effect (i.e., once set, this bit can only be cleared by PLTRST#). 3:2 (Desktop Only) Reserved (Mobile Only) Intel SpeedStep Enable (SS_EN) — R/W. 0 = Intel SpeedStep technology logic is disabl ed and the SS_CNT register will not be visible (reads to SS_CNT will return 00h and writes will have no effect). 1 = Intel SpeedStep technology logic is enabled. (Mobile Only) PCI CLKRUN# Enable (CLKRUN_EN) — R/W. 0 = Disable. ICH6 drives the CLKRUN# signal low. 1 = Enable CLKRUN# logic to control the system PCI clock via the CLKRUN# and STP_PCI# signals. NOTE: when the SLP_EN# bit is set, the ICH6 drives the CLKRUN# signal low regardless of the state of the CLKRUN_EN bit. This ensures that the PCI and LPC clocks continue running during a transition to a sleep state. 1:0 Periodic SMI# Rate Select (PER_SMI_SEL) — R/W. Set by software to control the rate at which periodic SMI# is generated. 00 = 1 minute 01 = 32 seconds 10 = 16 seconds 11 = 8 seconds

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 395 LPC Interface Bridge Registers (D31:F0)

10.8.1.2 GEN_PMCON_2—General PM Configuration 2 Register

(PM—D31:F0) Offset Address: A2h Attribute: R/W, R/WC Default Value: 00h Size: 8-bit Lockable: No Usage: ACPI, Legacy Power Well: Resume Bit Description DRAM Initialization Bit — R/W. This bit does not effect hardware functionality in any way. BIOS is expected to set this bit prior to starting the DRAM initialization sequence and to clear this bit after completing the DRAM initialization sequence. BIOS can detect that a DRAM initialization sequence was interrupted by a reset by reading this bit during the boot sequence.

• If the bit is 1, then the DRAM initialization was interrupted.
• This bit is reset by the assertion of the RSMRST# pin. 6:5 CPU PLL Lock Time (CPLT) — R/W. This field indicates the amount of time that the processor needs to lock its PLLs. This is used wherever timing t270 (Chapter 22) applies. 00 = min 30.7 µs (Default) 01 = min 61.4 µs 10 = min 122.8 µs 11 = min 245.6 µs It is the responsibility of the BIOS to program the correct value in this field prior to the first transition to C3 or C4 states (or performing Intel SpeedStep® technology transitions). NOTE: The new DPSLP-TO-SLP bits (D31:F0:AAh, bits 1:0) act as an override to these bits. NOTE: These bits are not cleared by any type of reset except RSMRST# or a CF9 write System Reset Status (SRS) — R/WC. Software clears this bit by writing a 1 to it. 0 = SYS_RESET# button Not pressed. 1 = ICH6 sets this bit when the SYS_RESET# button is pressed. BIOS is expected to read this bit and clear it, if it is set. NOTE: This bit is also reset by RSMRST# and CF9h resets. CPU Thermal Trip Status (CTS) — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set when PLTRST# is inactive and THRMTRIP# goes active while the system is in an S0 or S1 state. NOTES: 1. This bit is also reset by RSMRST#, and CF9h resets. It is not reset by the shutdown and reboot associated with the CPUTHRMTRIP# event. 2. The CF9h reset in the description refers to CF9h type core well reset which includes SYS_RST#, PWROK/VRMPWRGD low, SMBus hard reset, TCO Timeout. This type of reset will clear CTS bit.

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LPC Interface Bridge Registers (D31:F0) NOTE: VRMPWROK is sampled using the RTC clock. Therefore, low times that are less than one RTC clock period may not be detected by the ICH6. Minimum SLP_S4# Assertion Width Violation Status — R/WC. 0 = Software clears this bi t by writing a 1 to it. 1 = Hardware sets this bit when the SLP_S4# assertion width is less than the time programmed in the SLP_S4# Minimum Assertion Width field (D31:F0:Offset A4h:bits 5:4). The ICH6 begins the timer when SLP_S4# is asserted during S4/S5 entry, or when the RSMRST# input is de- asserted during G3 exit. Note that this bit is functional regardless of the value in the SLP_S4# Assertion Stretch Enable (D31:F0:Offset A4h:bit 3). NOTE: This bit is reset by the assertion of the RSMRST# pin, but can be set in some cases before the default value is readable. CPU Power Failure (CPUPWR_FLR) — R/WC. 0 = Software (typically BIOS) clears this bit by writing a 0 to it. 1 = Indicates that the VRMPWRGD signal from the processor’s VRM went low while the system was in an S0 or S1 state. PWROK Failure (PWROK_FLR) — R/WC. 0 = Software clears this bit by writing a 1 to it, or when the system goes into a G3 state. 1 = This bit will be set any time PWROK goes low, w hen the system was in S0, or S1 state. The bit will be cleared only by software by writing a 1 to this bit or when the system goes to a G3 state. NOTE: See Chapter 5.14.11.3 for more details about the PWROK pin functionality. NOTE: In the case of true PWROK failure, PWROK will go low first before the VRMPWRGD. Bit Description

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 397 LPC Interface Bridge Registers (D31:F0)

10.8.1.3 GEN_PMCON_3—General PM Configuration 3 Register

(PM—D31:F0) Offset Address: A4h Attribute: R/W, R/WC Default Value: 00h Size: 8-bit Lockable: No Usage: ACPI, Legacy Power Well: RTC NOTE: RSMRST# is sampled using the RTC clock. Therefore, low times that are less than one RTC clock period may not be detected by the ICH6. Bit Description 7:6 SWSMI_RATE_SEL — R/W. This field indicates w hen the SWSMI timer will time out. Valid values are: 00 = 1.5 ms ± 0.6 ms 01 = 16 ms ± 4 ms 10 = 32 ms ± 4 ms 11 = 64 ms ± 4 ms These bits are not cleared by any type of reset except RTCRST#. 5:4 SLP_S4# Minimum Assertion Width — R/W. This field indicates the minimum assertion width of the SLP_S4# signal to guarantee that the DRAMs have been safely power-cycled. Valid values are: 11 = 1 to 2 seconds 10 = 2 to 3 seconds 01 = 3 to 4 seconds 00 = 4 to 5 seconds This value is used in two ways: 1. If the SLP_S4# assertion width is ever shorter than this time, a status bit is set for BIOS to read when S0 is entered. 2. If enabled by bit 3 in this register, the hardware will prevent the SLP_S4# signal from de- asserting within this minimum time period after asserting. RTCRST# forces this field to the conservative default state (00b) SLP_S4# Assertion Stretch Enable — R/W. 0 = The SLP_S4# minimum assertion time is 1 to 2 RTCCLK. 1 = The SLP_S4# signal minimally assert for the ti me specified in bits 5:4 of this register. This bit is cleared by RTCRST# RTC Power Status (RTC_PWR_STS) — R/W. This bit is set when RTCRST# indicates a weak or missing battery. The bit is not cleared by any type of reset. The bit will remain set until the software clears it by writing a 0 back to this bit position. Power Failure (PWR_FLR) — R/WC. This bit is in the RTC well, and is not cleared by any type of reset except RTCRST#. 0 = Indicates that the trickle current has not failed since the last time the bit was cleared. Software clears this bit by writing a 1 to it. 1 = Indicates that the trickle current (from the main battery or trickle supply) was removed or failed. NOTE: Clearing CMOS in an ICH-based platform can be done by using a jumper on RTCRST# or GPI, or using SAFEMODE strap. Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low. AFTERG3_EN — R/W. This bit determines what state to go to when power is re-applied after a power failure (G3 state). This bit is in the RTC well and is not cleared by any type of reset except writes to CF9h or RTCRST#. 0 = System will return to S0 state (boot) after power is re-applied. 1 = System will return to the S5 state (except if it was in S4, in which case it will return to S4). In the S5 state, the only enabled wake event is the Power Button or any enabled wake event that was preserved through the power failure. NOTE: Bit will be set when THRMTRIP#-based shutdown occurs.

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10.8.1.4 Cx-STATE_CNF—Cx Stat e Configuration Register

(PM—D31:F0) (Mobile Only) Offset Address: A9h Attribute: R/W Default Value: 00h Size: 8-bit Lockable: No Usage: ACPI, Legacy Power Well: Core This register is used to enable new C-state related modes. Bit Description 7 SCRATCHPAD (SP) — R/W. 6:5 Reserved Popdown Mode Enable (PDME) — R/W. This bit is used in conjunction with the PUME bit (D31:F0:A9h, bit 3). If PUME is 0, then this bit must also be 0. 0 = The ICH6 will not attempt to automatically return to a previous C3 or C4 state. 1 = When this bit is a 1 and Intel ® ICH6 observes that there are no bus master requests, it can return to a previous C3 or C4 state. NOTE: This bit is separate from the PUME bit to cover cases where latency issues permit POPUP but not POPDOWN. Popup Mode Enable (PUME) — R/W. When this bit is a 0, the I CH6 behaves like ICH5, in that bus master traffic is a break event, and it will return from C3/C4 to C0 based on a break event. See Chapter 5.14.5 for additional details on this mode. 0 = The ICH6 will treat Bus master traffic a break event, and will return from C3/C4 to C0 based on a break event. 1 = When this bit is a 1 and ICH6 observes a bus mast er request, it will take the system from a C3 or C4 state to a C2 state and auto enable bus masters. This will let snoops and memory access occur. Report Zero for BM_STS (BM_STS_ZERO_EN) — R/W. 0 = The ICH6 sets BM_STS (PMBASE + 00h, bit 4) if there is bus master activity from PCI, PCI Express* and internal bus masters. 1 = When this bit is a 1, ICH6 will not set the BM_S TS if there is bus master activity from PCI, PCI Express and internal bus masters. NOTES: 1. If the BM_STS bit is already set when the BM_STS_ZERO_EN bit is set, the BM_STS bit will remain set. Software will still need to clear the BM_STS bit. 2. It is expected that if the PUME bit (this register, bit 3) is set, the BM_STS_ZERO_EN bit should also be set. Setting one without the other would mainly be for debug or errata workaround. 3. BM_STS will be set by LPC DMA or LPC masters, even if BM_STS_ZERO_EN is set. 1:0 Reserved

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 399 LPC Interface Bridge Registers (D31:F0)

10.8.1.5 C4-TIMING_CNT—C4 Ti ming Control Register

(PM—D31:F0) (Mobile Only) Offset Address: AAh Attribute: R/W Default Value: 00h Size: 8-bit Lockable: No Usage: ACPI, Legacy Power Well: Core This register is used to enable C-state related modes. Bit Description 7:4 Reserved 3:2 DPRSLPVR to STPCPU — R/W. This field selects the amount of time that the ICH6 waits for from the de-assertion of DPRSLPVR to the de-assertion of STP_CPU#. This provides a programmable time for the processor’s voltage to stabilize when exiting from a C4 state. This thus changes the value for t266. 1:0 DPSLP-TO-SLP — R/W. This field selects the DPSLP# de-assertion to CPU_SLP# de-assertion time (t270). Normally this value is determined by the CPU_PLL_LOCK_TIME field in the GEN_PMCON_2 register. When this field is non-zero, then the values in this register have higher priority. It is software’s responsibility to program these fields in a consistent manner. Bits t266 min t266max Comment 00b 95 µs 101 µs Default 01b 22 µs 28 µs Value used for “Fast” VRMs 10b Reserved 11b Reserved Bits t270 00b Use value is CPU_PLL_LOCK_TIME field (default is 30 µs) 01b 20 µs 10b 15 µs 11b 10 µs

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10.8.1.6 BM_BREAK_EN Register (PM—D31:F0) (Mobile Only)

Offset Address: ABh Attribute: R/W Default Value: 00h Size: 8-bit Lockable: No Usage: ACPI, Legacy Power Well: Core Bit Description IDE_BREAK_EN — R/W. 0 = Parallel IDE or Serial ATA traf fic will not act as a break event. 1 = Parallel IDE or Serial ATA traffic acts as a break event, even if the BM_STS-ZERO_EN and POPUP_EN bits are set. Parallel IDE or Serial ATA master activity will cause BM_STS to be set and will cause a break from C3/C4. PCIE_BREAK_EN — R/W. 0 = PCI Express* traffic will not act as a break event. 1 = PCI Express traffic acts as a break event, even if the BM_STS-ZERO_EN and POPUP_EN bits are set. PCI Express master activity will cause BM_STS to be set and will cause a break from C3/C4. PCI_BREAK_EN — R/W. 0 = PCI traffic will not act as a break event. 1 = PCI traffic acts as a break event, even if the BM_STS-ZERO_EN and POPUP_EN bits are set. PCI master activity will cause BM_STS to be set and will cause a break from C3/C4. 4:3 Reserved EHCI_BREAK_EN — R/W. 0 = EHCI traffic will not act as a break event. 1 = EHCI traffic acts as a break event, even if the BM_STS-ZERO_EN and POPUP_EN bits are set. EHCI master activity will cause BM_STS to be set and will cause a break from C3/C4. UHCI_BREAK_EN — R/W. 0 = UHCI traffic will not act as a break event. 1 = USB traffic from any of the internal UHCIs acts as a break event, even if the BM_STS- ZERO_EN and POPUP_EN bits are set. UHCI master activity will cause BM_STS to be set and will cause a break from C3/C4. ACAZ_BREAK_EN — R/W. 0 = AC ‘97 or Intel High Definition Audio traffic will not act as a break event. 1 = AC ‘97 or Intel High Definition Audio traffic acts as a break event, even if the BM_STS- ZERO_EN and POPUP_EN bits are set. AC ‘97 or Intel High Definition Audio master activity will cause BM_STS to be set and will cause a break from C3/C4.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 401 LPC Interface Bridge Registers (D31:F0)

10.8.1.7 MSC_FUN—Miscellane ous Functionality Register

(PM—D31:F0) Offset Address: ADh Attribute: R/W Default Value: 00h Size: 8-bit Power Well: Resume

10.8.1.8 GPI_ROUT—GPI Rout ing Control Register

(PM—D31:F0) Offset Address: B8h – BBh Attribute: R/W Default Value: 00000000h Size: 32-bit Lockable: No Power Well: Resume Bit Description 7:6 Reserved LPC Generic Range 2 Bit 5 Mask (LGR5M) — R/W. 0 = The existing LPC Generic I/O decode range 2 decodes bit 5 as defined in the D31:F0h:88h register description. 1 = The LPC Generic I/O decode range 2 forces an address match on bit 5. NOTE: If this bit is set, LGR4M (bit 4 of this register) must also be set. LPC Generic Range 2 Bit 4 Mask (LGR4M) — R/W. 0 = The existing LPC Generic I/O decode range 2 decodes bit 4 as defined in the D31:F0h:88h register description. 1 = The LPC Generic I/O decode range 2 forces an address match on bit 4. 3R e s e r v e d 2 Top Swap Status (TSS) — RO. This bit provides a r ead-only path to view the state of the Top Swap bit that is in the Chipset Configuration Registers:Offset 3414h:bit 0. 1:0 USB Transient Disconnect Detect (TDD) — R/W: This field prevents a short Single-Ended Zero (SE0) condition on the USB ports from being interpreted by the UHCI host controller as a disconnect. BIOS should set to 11b. Bit Description 31:30 GPI15 Route — R/W. See bits 1:0 for description. Same pattern for GPI14 through GPI3 5:4 GPI2 Route — R/W. See bits 1:0 for description. 3:2 GPI1 Route — R/W. See bits 1:0 for description. 1:0 GPI0 Route — R/W. GPI[15:0] can be routed to cause an SMI or SCI when the GPI[n]_STS bit is set. If the GPIO is not set to an input, this field has no effect. If the system is in an S1–S5 state and if the GPE0_EN bit is also set, then the GPI can cause a Wake event, even if the GPI is NOT routed to cause an SMI# or SCI. 00 = No effect. 01 = SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) 10 = SCI (if corresponding GPE0_EN bit is also set) 11 = Reserved Software must set this bit field to generate the appropriate type of system interrupt, depending on how the SCI_EN bit is set. For example, if the SCI_EN bit is set, then this field must be programmed to 00b or 10b. If the SCI_EN bit is cleared, then this field must be programmed to 00b or 01b. Software must also update this field if the SCI_EN bit is changed.

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LPC Interface Bridge Registers (D31:F0) Note: GPIOs that are not implemented will not have the corresponding bits implemented in this register.

10.8.2 APM I/O Decode

Table 10-10 shows the I/O registers associated with APM support. This register space is enabled in the PCI Device 31: Function 0 space (APMDEC_EN), and cannot be moved (fixed I/O location).

10.8.2.1 APM_CNT—Advanced Power Management Control Port

I/O Address: B2h Attribute: R/W Default Value: 00h Size: 8-bit Lockable: No Usage: Legacy Only Power Well: Core

10.8.2.2 APM_STS—Advanced Powe r Management Status Port

I/O Address: B3h Attribute: R/W Default Value: 00h Size: 8-bit Lockable: No Usage: Legacy Only Power Well: Core Table 10-10. APM Register Map Address Mnemonic Register Name Default Type B2h APM_CNT Advanced Power Management Control Port 00h R/W B3h APM_STS Advanced Power Management Status Port 00h R/W Bit Description 7:0 This field is used to pass an APM command between the OS and the SMI handler. Writes to this port not only store data in the APMC register, but also generates an SMI# when the APMC_EN bit is set. Bit Description 7:0 This field is used to pass data between the OS and the SMI handler. Basically, this is a scratchpad register and is not affected by any other register or function (other than a PCI reset).

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 403 LPC Interface Bridge Registers (D31:F0)

10.8.3 Power Management I/O Registers

Table 10-11 shows the registers associated with ACPI and Legacy power management support. These registers are enabled in the PCI Device 31: Function 0 space (PM_IO_EN), and can be moved to any I/O location (128-byte aligned). The registers are defined to be compliant with the ACPI 2.0 specification, and use the same bit names. Note: All reserved bits and registers will always return 0 when read, and will have no effect when written. Table 10-11. ACPI and Legacy I/O Register Map PMBASE + Offset Mnemonic Register Name ACPI Pointer Default Type 00–01h PM1_STS PM1 Status PM1a_EVT_BLK 0000h R/WC 02–03h PM1_EN PM1 Enable PM1a_EVT_BLK+2 0000h R/W 04–07h PM1_CNT PM1 Control PM1a_CNT_BLK 00000000h R/W, WO 08–0Bh PM1_TMR PM1 Timer PMTMR_BLK xx000000h RO 10h–13h PROC_CNT Processor Control P_BLK 00000000h R/W, RO, WO 14h LV2 Level 2 P_BLK+4 00h RO 15h–16h — Reserved (Desktop Only) — — — 15h LV3 Level 3 (Mobile Only) P_BLK+5 00h RO 16h LV4 Level 4 (Mobile Only) P_BLK+6 00h RO 20h — Reserved (Desktop Only) — — — 20h PM2_CNT PM2 Control (Mobile Only) PM2a_CNT_BLK 00h R/W 28–2Bh GPE0_STS General Purpose Event 0 Status GPE0_BLK 00000000h R/W, R/WC 2C–2Fh GPE0_EN General Purpose Event 0 Enables GPE0_BLK+4 00000000h R/W 30–33h SMI_EN SMI# Control and Enable 00000000h R/W, WO, R/W (special) 34–37h SMI_STS SMI Status 00000000h R/WC, RO 38–39h ALT_GP_SMI_EN Alternate GPI SMI Enable 0000h R/W 3A–3Bh ALT_GP_SMI_STS Alternate GPI SMI Status 0000h R/WC 44–45h DEVACT_STS Device Activity Status 0000h R/WC 46h–4Fh — Reserved 50h — Reserved (Desktop Only) 50h SS_CNT Intel SpeedStep ® Technology Control (Mobile Only) 01h R/W (special) 54h–57h C3_RES (Mobile Only) C3-Residency Register — 00000000h RO, R/W 60h–7Fh — Reserved for TCO — — —

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10.8.3.1 PM1_STS—Power Mana gement 1 Status Register

I/O Address: PMBASE + 00h (ACPI PM1a_EVT_BLK) Attribute: R/WC Default Value: 0000h Size: 16-bit Lockable: No Usage: ACPI or Legacy Power Well: Bits 0 –7: Core, Bits 8–15: Resume, except Bit 11 in RTC If bit 10 or 8 in this register is set, and the corresponding _EN bit is set in the PM1_EN register, then the ICH6 will generate a Wake Event. Once back in an S0 state (or if already in an S0 state when the event occurs), the ICH6 will also generate an SCI if the SCI_EN bit is set, or an SMI# if the SCI_EN bit is not set. Note: Bit 5 does not cause an SMI# or a wake event. Bit 0 does not cause a wake event but can cause an SMI# or SCI. Bit Description Wake Status (WAK_STS) — R/WC. This bit is not affected by hard resets caused by a CF9 write, but is reset by RSMRST#. 0 = Software clears this bit by writing a 1 to it. 1 = Set by hardware when the system is in one of the sleep states (via the SLP_EN bit) and an enabled wake event occurs. Upon setting this bit, the ICH6 will transition the system to the ON state. If the AFTERG3_EN bit is not set and a power failure (such as removed batteries) occurs without the SLP_EN bit set, the system will return to an S0 state when power returns, and the WAK_STS bit will not be set. If the AFTERG3_EN bit is set and a power failure occurs without the SLP_EN bit having been set, the system will go into an S5 state when power returns, and a subsequent wake event will cause the WAK_STS bit to be set. Note that any subsequent wake event would have to be caused by either a Power Button press, or an enabled wake event that was preserved through the power failure (enable bit in the RTC well).

14 Reserved

13:12 Reserved Power Button Override Status (PRBTNOR_STS) — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set any time a Power Button Overri de occurs (i.e., the power button is pressed for at least 4 consecutive seconds), or due to the corresponding bit in the SMBus slave message. The power button override causes an unconditional transition to the S5 state, as well as sets the AFTERG# bit. The BIOS or SCI handler clears this bit by writing a 1 to it. This bit is not affected by hard resets via CF9h writes, and is not reset by RSMRST#. Thus, this bit is preserved through power failures. Note that if this bit is still asserted when the global SCI_EN is set then an SCI will be generated. RTC Status (RTC_STS) — R/WC. This bit is not affected by hard resets caused by a CF9 write, but is reset by RSMRST#. 0 = Software clears this bit by writing a 1 to it. 1 = Set by hardware when the RTC generates an alarm (assertion of the IRQ8# signal). Additionally if the RTC_EN bit (PMBASE + 02h, bit 10) is set, the setting of the RTC_STS bit will generate a wake event. 9R e s e r v e d

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 405 LPC Interface Bridge Registers (D31:F0) Power Button Status (PWRBTN__STS) — R/WC. This bit is not affected by hard resets caused by a CF9 write. 0 = If the PWRBTN# signal is held low for more than 4 seconds, the hardware clears the PWRBTN_STS bit, sets the PWRBTNOR_STS bit, and the system transitions to the S5 state with only PWRBTN# enabled as a wake event. This bit can be cleared by software by writing a one to the bit position. 1 = This bit is set by hardware when the PW RBTN# signal is asserted Low, independent of any other enable bit. In the S0 state, while PWRBTN_EN and PWRBTN_STS are both set, an SCI (or SMI# if SCI_EN is not set) will be generated. In any sleeping state S1–S5, while PWRBTN_EN (PMBASE + 02h, bit 8) and PWRBTN_STS are both set, a wake event is generated. NOTE: If the PWRBTN_STS bit is cleared by software while the PWRBTN# signal is sell asserted, this will not cause the PWRBN_STS bit to be set. The PWRBTN# signal must go inactive and active again to set the PWRBTN_STS bit. 7:6 Reserved Global Status (GBL _STS) — R/WC. 0 = The SCI handler should then clear this bit by writing a 1 to the bit location. 1 = Set when an SCI is generated due to BIOS wanting the attention of the SCI handler. BIOS has a corresponding bit, BIOS_RLS, which will cause an SCI and set this bit. (Desktop Only) Reserved (Mobile Only) Bus Master Status (BM_STS) — R/WC. This bit will not c ause a wake event, SCI or SMI#. 0 = Software clears this bit by writing a 1 to it. 1 = Set by the ICH6 when a bus master requests a ccess to main memory. Bus master activity is detected by any of the PCI Requests being active, any internal bus master request being active, the BMBUSY# signal being active, or REQ-C2 message received while in C3 or C4 state. NOTES: 1. If the BM_STS_ZERO_EN bit is set, then this bit will generally report as a 0. LPC DMA and bus master activity will always set the BM_STS bit, even if the BM_STS_ZERO_EN bit is set. 3:1 Reserved Timer Overflow Status (TMROF_STS) — R/WC. 0 = The SCI or SMI# handler clears this bit by writing a 1 to the bit location. 1 = This bit gets set any time bit 22 of the 24-bit timer goes high (bits are numbered from 0 to 23). This will occur every 2.3435 seconds. When the TMROF_EN bit (PMBASE + 02h, bit 0) is set, then the setting of the TMROF_STS bit will additionally generate an SCI or SMI# (depending on the SCI_EN). Bit Description

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10.8.3.2 PM1_EN—Power Management 1 Enable Register

I/O Address: PMBASE + 02h (ACPI PM1a_EVT_BLK + 2) Attribute: R/W Default Value: 0000h Size: 16-bit Lockable: No Usage: ACPI or Legacy Power Well: Bits 0 –7: Core, Bits 8–9, 11–15: Resume, Bit 10: RTC Bit Description 13:11 Reserved RTC Event Enable (RTC_EN) — R/W. This bit is in the RTC well to allow an RTC event to wake after a power failure. This bit is not cleared by any reset other than RTCRST# or a Power Button Override event. 0 = No SCI (or SMI#) or wake event is generated then RTC_STS (PMBASE + 00h, bit 10) goes active. 1 = An SCI (or SMI#) or wake event will occu r when this bit is set and the RTC_STS bit goes active. 9 Reserved. Power Button Enable (PWRBTN_EN) — R/W. This bit is used to enable the setting of the PWRBTN_STS bit to generate a power management event (SMI#, SCI). PWRBTN_EN has no effect on the PWRBTN_STS bit (PMBASE + 00h, bit 8) being set by the assertion of the power button. The Power Button is always enabled as a Wake event. 0 = Disable. 1 = Enable. 7:6 Reserved. Global Enable (GBL_EN) — R/W. When both the GBL_EN and the GBL_STS bit (PMBASE + 00h, bit 5) are set, an SCI is raised. 0 = Disable. 1 = Enable SCI on GBL_STS going active. 4:1 Reserved. Timer Overflow Interrupt Enable (TMROF_EN) — R/W. Works in conjunction with the SCI_EN bit (PMBASE + 04h, bit 0) as described below: TMROF_EN SCI_EN Effect when TMROF_STS is set

0 X No SMI# or SCI

10 S M I #

11 S C I

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 407 LPC Interface Bridge Registers (D31:F0)

10.8.3.3 PM1_CNT—Power Management 1 Control

I/O Address: PMBASE + 04h (ACPI PM1a_CNT_BLK) Attribute: R/W, WO Default Value: 00000000h Size: 32-bit Lockable: No Usage: ACPI or Legacy Power Well: Bits 0 –7: Core, Bits 8–12: RTC, Bits 13–15: Resume Bit Description 31:14 Reserved. 13 Sleep Enable (SLP_EN) — WO. Setting this bit causes the system to sequence into the Sleep state defined by the SLP_TYP field. 12:10 Sleep Type (SLP_TYP) — R/W. This 3-bit field defines the ty pe of Sleep the system should enter when the SLP_EN bit is set to 1. These bits are only reset by RTCRST#. 9:3 Reserved. Global Release (GBL_RLS) — WO. 0 = This bit always reads as 0. 1 = ACPI software writes a 1 to this bit to ra ise an event to the BIOS. BIOS software has a corresponding enable and status bits to control its ability to receive ACPI events. (Desktop Only) Reserved (Mobile Only) Bus Master Reload (BM_RLD) — R/W. This bit is treated as a sc ratchpad bit. This bit is reset to 0 by PLTRST# 0 = Bus master requests will not cause a break from the C3 state. 1 = Enable Bus Master requests (internal, external or BMBUSY#) to cause a break from the C3 state. If software fails to set this bit before going to C3 state, ICH6 will still return to a snoopable state from C3 or C4 states due to bus master activity. SCI Enable (SCI_EN) — R/W. Selects the SCI interrupt or the SMI# interrupt for various events including the bits in the PM1_STS register (bit 10, 8, 0), and bits in GPE0_STS. 0 = These events will generate an SMI#. 1 = These events will generate an SCI. Code Master Interrupt 000b ON: Typically maps to S0 state. 001b Asserts STPCLK#. Puts processor in Stop-Grant state. Optional to assert CPUSLP# to put processor in sleep state: Typically maps to S1 state. 010b Reserved 011b Reserved 100b Reserved 101b Suspend-To-RAM. Assert SLP_S3#: Typically maps to S3 state. 110b Suspend-To-Disk. Assert SLP_S3#, and SL P_S4#: Typically maps to S4 state. 111b Soft Off. Assert SLP_S3#, SLP_S4#, and SLP_S5#: Typically maps to S5 state.

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10.8.3.4 PM1_TMR—Power Management 1 Timer Register

I/O Address: PMBASE + 08h (ACPI PMTMR_BLK) Attribute: RO Default Value: xx000000h Size: 32-bit Lockable: No Usage: ACPI Power Well: Core

10.8.3.5 PROC_CNT—Processor Control Register

I/O Address: PMBASE + 10h (ACPI P_BLK) Attribute: R/W, RO, WO Default Value: 00000000h Size: 32-bit Lockable: No (bits 7:5 are write once) Usage: ACPI or Legacy Power Well: Core Bit Description 31:24 Reserved 23:0 Timer Value (TMR_VAL) — RO. Returns the running count of the PM timer. This counter runs off a 3.579545 MHz clock (14.31818 MHz divided by 4). It is reset to 0 during a PCI reset, and then continues counting as long as the system is in the S0 state. After an S1 state, the counter will not be reset (it will continue counting from the last value in S0 state. Anytime bit 22 of the timer goes HIGH to LOW (bits referenced from 0 to 23), the TMROF_STS bit (PMBASE + 00h, bit 0) is set. The High-to-Low transition will occur every 2.3435 seconds. If the TMROF_EN bit (PMBASE + 02h, bit 0) is set, an SCI interrupt is also generated. Bit Description 31:18 Reserved Throttle Status (THTL_STS) — RO. 0 = No clock throttling is occurrin g (maximum processor performance). 1 = Indicates that the clock state machine is th rottling the processor performance. This could be due to the THT_EN bit or the FORCE_THTL bit being set. 16:9 Reserved Force Thermal Throttling (FORCE_THTL) — R/W. Software can set this bit to force the thermal throttling function. 0 = No forced throttling. 1 = Throttling at the duty cycle specified in TH RM_DTY starts immediately, and no SMI# is generated.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 409 LPC Interface Bridge Registers (D31:F0) 7:5 THRM_DTY — WO. This write-once fiel d determines the duty cycle of the throttling when the FORCE_THTL bit is set. The duty cycle indicates the approximate percentage of time the STPCLK# signal is asserted while in the throttle mode. The STPCLK# throttle period is 1024 PCICLKs. Note that the throttling only occurs if the system is in the C0 state. If in the C2, C3, or C4 state, no throttling occurs. Once the THRM_DTY field is written, any subsequent writes will have no effect until PLTRST# goes active. THTL_EN — R/W. When set and the system is in a C0 state, it enables a processor-controlled STPCLK# throttling. The duty cycle is selected in the THTL_DTY field. 0 = Disable 1 = Enable 3:1 THTL_DTY — R/W. This field determines the duty cycl e of the throttling when the THTL_EN bit is set. The duty cycle indicates the approximate percentage of time the STPCLK# signal is asserted (low) while in the throttle mode. The STPCLK# throttle period is 1024 PCICLKs. THRM_DTY Throttle Mode PCI Clocks 000b 50% (Default) 512 001b 87.5% 896 010b 75.0% 768 011b 62.5% 640 100b 50% 512 101b 37.5% 384 110b 25% 256 111b 12.5% 128 THTL_DTY Throttle Mode PCI Clocks 000b 50% (Default) 512 001b 87.5% 896 010b 75.0% 768 011b 62.5% 640 100b 50% 512 101b 37.5% 384 110b 25% 256 111b 12.5% 128

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10.8.3.6 LV2 — Level 2 Register

I/O Address: PMBASE + 14h (ACPI P_BLK+4) Attribute: RO Default Value: 00h Size: 8-bit Lockable: No Usage: ACPI or Legacy Power Well: Core NOTE: This register should not be used by Intel iA64 processors or systems with more than 1 logical processor, unless appropriate semaphoring software has been put in place to ensure that all threads/processors are ready for the C2 state when the read to this register occurs

10.8.3.7 LV3—Level 3 Register (Mobile Only)

I/O Address: PMBASE + 15h ( ACPI P_BLK + 5) Attribute: RO Default Value: 00h Size: 8-bit Lockable: No Usage: ACPI or Legacy Power Well: CoreNOTE: If the C4onC3_EN bit is set, reads this register will initiate a LVL4 transition rather than a LVL3 transition. In the event that software attempts to simultaneously read the LVL2 and LVL3 registers (which is illegal), the ICH6 will ignore the LVL3 read, and only perform a C2 transition. NOTE: This register should not be used by iA64 processors or systems with more than 1 logical processor, unless appropriate semaphoring software has been put in place to ensure that all threads/processors are ready for the C3 state when the read to this register occurs.

10.8.3.8 LV4—Level 4 Register (Mobile Only)

I/O Address: PMBASE + 16h ( ACPI P_BLK + 6) Attribute: RO Default Value: 00h Size: 8-bit Lockable: No Usage: ACPI or Legacy Power Well: Core NOTE: This register should not be used by iA64 processors or systems with more than 1 logical processor, unless appropriate semaphoring software has been put in place to ensure that all threads/processors are ready for the C4 state when the read to this register occurs. Bit Description 7:0 Reads to this register return all 0s, writes to this register have no effect. Reads to this register generate a “enter a level 2 power state” (C2) to the clock control logic. This will cause the STPCLK# signal to go active, and stay active until a break event occurs. Throttling (due either to THTL_EN or FORCE_THTL) will be ignored. Bit Description 7:0 Reads to this register return all 0s, writes to this register have no effect. Reads to this register generate a “enter a C3 power state” to the clock control logic. The C3 state persists until a break event occurs. Bit Description 7:0 Reads to this register return all 0s, writes to this register have no effect. Reads to this register generate a “enter a C4 power state” to the clock control logic. The C4 state persists until a break event occurs.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 411 LPC Interface Bridge Registers (D31:F0)

10.8.3.9 PM2_CNT—Power Manageme nt 2 Control (Mobile Only)

I/O Address: PMBASE + 20h (ACPI PM2_BLK) Attribute: R/W Default Value: 00h Size: 8-bit Lockable: No Usage: ACPI Power Well: Core

10.8.3.10 GPE0_STS—General Pur pose Event 0 Status Register

I/O Address: PMBASE + 28h (ACPI GPE0_BLK) Attribute: R/W, R/WC Default Value: 00000000h Size: 32-bit Lockable: No Usage: ACPI Power Well: Resume This register is symmetrical to the General Purpose Event 0 Enable Register. Unless indicated otherwise below, if the corresponding _EN bit is set, then when the _STS bit get set, the ICH6 will generate a Wake Event. Once back in an S0 state (or if already in an S0 state when the event occurs), the ICH6 will also generate an SCI if the SCI_EN bit is set, or an SMI# if the SCI_EN bit (PMBASE + 04h, bit 0) is not set. Bits 31:16 are reset by a CF9h write; bits 15:0 are not. All are reset by RSMRST#. Bit Description 7:1 Reserved Arbiter Disable (ARB_DIS) — R/W. This bit is essentially just a scratchpad bit for legacy software compatibility. Software typically sets this bit to 1 prior to entering a C3 or C4 state. When a transition to a C3 or C4 state occurs, ICH6 will automatically prevent any internal or external non-Isoch bus masters from initiating any cycles up to the (G)MCH. This blocking starts immediately upon the ICH6 sending the Go-C3 message to the (G)MCH. The blocking stops when the Ack-C2 message is received. Note that this is not really blocking, in that messages (such as from PCI Express*) are just queued and held pending. Bit Description 31:16 GPIn_STS — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = These bits are set any time the corres ponding GPIO is set up as an input and the corresponding GPIO signal is high (or low if the corresponding GP_INV bit is set). If the corresponding enable bit is set in the GPE0_EN register, then when the GPI[n]_STS bit is set:

• If the system is in an S1–S5 state, the event will also wake the system.
• If the system is in an S0 state (or upon waki ng back to an S0 state), a SCI will be caused depending on the GPI_ROUT bits (D31:F0:B8h, bits 31:30) for the corresponding GPI. NOTE: Mapping is as follows: bit 31 corresponds to GPI[15] ... and bit 16 corresponds to GPI:[0].

USB4_STS — R/W. 0 = Disable. 1 = Set by hardware and can be reset by writing a one to this bit position or a resume well reset. This bit is set when USB UHCI controller #4 needs to cause a wake. Additionally if the USB4_EN bit is set, the setting of the USB4_STS bit will generate a wake event.

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LPC Interface Bridge Registers (D31:F0) PME_B0_STS — R/W. This bit will be set to 1 by t he ICH6 when any internal device with PCI Power Management capabilities on bus 0 asserts the equivalent of the PME# signal. Additionally, if the PME_B0_EN bit is set, and the system is in an S0 state, then the setting of the PME_B0_STS bit will generate an SCI (or SMI# if SCI_EN is not set). If the PME_B0_STS bit is set, and the system is in an S1–S4 state (or S5 state due to SLP_TYP and SLP_EN), then the setting of the PME_B0_STS bit will generate a wake event, and an SCI (or SMI# if SCI_EN is not set) will be generated. If the system is in an S5 state due to power button override, then the PME_B0_STS bit will not cause a wake event or SCI. The default for this bit is 0. Writing a 1 to this bit position clears this bit. USB3_STS — R/W. 0 = Disable. 1 = Set by hardware and can be reset by writing a one to this bit position or a resume well reset. This bit is set when USB UHCI controller #3 needs to cause a wake. Additionally if the USB3_EN bit is set, the setting of the USB3_STS bit will generate a wake event. PME_STS — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Set by hardware when the PME# signal goes ac tive. Additionally, if the PME_EN bit is set, and the system is in an S0 state, then the setting of the PME_STS bit will generate an SCI or SMI# (if SCI_EN is not set). If the PME_EN bit is set, and the system is in an S1–S4 state (or S5 state due to setting SLP_TYP and SLP_EN), then the setting of the PME_STS bit will generate a wake event, and an SCI will be generated. If the system is in an S5 state due to power button override or a power failure, then PME_STS will not cause a wake event or SCI. (Desktop Only) Reserved (Mobile Only) BATLOW_STS — R/WC. (Mobile Only) Software clears this bit by writing a 1 to it. 0 = BATLOW# Not asserted 1 = Set by hardware when the BATLOW# signal is asserted. PCI_EXP_STS — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Set by hardware to indicate that:

• The PME event message was received on one or more of the PCI Express* ports
• An Assert PMEGPE message received from the (G)MCH via DMI NOTES: 1. The PCI WAKE# pin has no impact on this bit. 2. If the PCI_EXP_STS bit went active due to an Assert PMEGPE message, then a de-assert PMEGPE message must be received prior to the software write in order for the bit to be cleared. 3. If the bit is not cleared and the corresponding PCI_EXP_EN bit is set, the level-triggered SCI will remain active. 4. A race condition exists where the PCI Express device sends another PME message because the PCI Express device was not serviced within the time when it must resend the message. This may result in a spurious interrupt, and this is comprehended and approved by the PCI Express* Specification, Revision 1.0a. The window for this race condition is approximately 95- 105 milliseconds. RI_STS — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Set by hardware when the RI# input signal goes active. Bit Description

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 413 LPC Interface Bridge Registers (D31:F0) SMBus Wake Status (SMB_WAK_STS) — R/WC. The SMBus controller can independently cause an SMI# or SCI, so this bit does not need to do so (unlike the other bits in this register). Software clears this bit by writing a 1 to it. 0 = Wake event Not caused by the ICH6’s SMBus logic. 1 = Set by hardware to indicate that the wake ev ent was caused by the ICH6’s SMBus logic.This bit will be set by the WAKE/SMI# command type, even if the system is already awake. The SMI handler should then clear this bit. NOTES: 1. This bit is set by the SMBus slave command 01h (Wake/SMI#) even when the system is in the S0 state. Therefore, to avoid an instant wake on subsequent transitions to sleep states, software must clear this bit after each reception of the Wake/SMI# command or just prior to entering the sleep state. 2. If SMB_WAK_STS is set due to SMBus slave receiving a message, it will be cleared by internal logic when a THRMTRIP# event happens or a Power Button Override event. However, THRMTRIP# or Power Button Override event will not clear SMB_WAK_STS if it is set due to SMBALERT# signal going active. 3. The SMBALERT_STS bit (D31:F3:I/O Offset 00h:Bit 5) should be cleared by software before the SMB_WAK_STS bit is cleared. TCOSCI_STS — R/WC. Software clears this bit by writing a 1 to it. 0 = TOC logic did Not cause SCI. 1 = Set by hardware when the TCO logic causes an SCI. AC97_STS — R/WC. This bit will be set to 1 when the codecs are attempting to wake the system and the PME events for the codecs are armed for wakeup. A PME is armed by programming the appropriate PMEE bit in the Power Management Control and Status register at bit 8 of offset 54h in each AC ’97 function. 0 = Software clears this bit by writing a 1 to it. 1 = Set by hardware when the codecs are attemp ting to wake the system. The AC97_STS bit gets set only from the following two cases: 1.The PMEE bit for the function is set, and o The AC-link bit clock has been shut and the routed ACZ_SDIN line is high (for audio, if routing is disabled, no wake events are allowed. 2.For modem, if audio routing is disabled, then the wake event is an OR of all ACZ_SDIN lines. If routing is enabled, then the wake event for modem is the remaining non-routed ACZ_SDIN line), or o GPI Status Change Interrupt bit (NABMBAR + 30h, bit 0) is 1. NOTE: This bit is not affected by a hard reset caused by a CF9h write. NOTE: This bit is also used for Intel High Definition Audio when ICH6 is configured to use the Intel High Definition Audio host controller rather than the AC97 host controller. USB2_STS — R/WC. Software clears this bit by writing a 1 to it. 0 = USB UHCI controller 2 does Not need to cause a wake. 1 = Set by hardware when USB UHCI controller 2 needs to cause a wake. Wake event will be generated if the corresponding USB2_EN bit is set. USB1_STS — R/WC. Software clears this bit by writing a 1 to it. 0 = USB UHCI controller 1 does Not need to cause a wake. 1 = Set by hardware when USB UHCI controller 1 needs to cause a wake. Wake event will be generated if the corresponding USB1_EN bit is set.

2 Reserved

HOT_PLUG_STS — R/WC. 0 = This bit is cleared by writ ing a 1 to this bit position. 1 = When a PCI Express* Hot-Plug event occurs. Th is will cause an SCI if the HOT_PLUG_EN bit is set in the GEP0_EN register. Thermal Interrupt Status (THRM_STS) — R/WC. Software clears this bit by writing a 1 to it. 0 = THRM# signal Not driven active as defined by the THRM_POL bit 1 = Set by hardware anytime the THRM# signal is driven active as defined by the THRM_POL bit. Additionally, if the THRM_EN bit is set, then the setting of the THRM_STS bit will also generate a power management event (SCI or SMI#). Bit Description

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LPC Interface Bridge Registers (D31:F0)

10.8.3.11 GPE0_EN—General Purp ose Event 0 Enables Register

I/O Address: PMBASE + 2Ch (ACPI GPE0_BLK + 4) Attribute: R/W Default Value: 00000000h Size: 32-bit Lockable: No Usage: ACPI Power Well: Bits 0–7, 9, 12, 14–31 Resume, Bits 8, 10–11, 13 RTC This register is symmetrical to the General Purpose Event 0 Status Register. All the bits in this register should be cleared to 0 based on a Power Button Override or processor Thermal Trip event. The resume well bits are all cleared by RSMRST#. The RTC sell bits are cleared by RTCRST#. Bit Description 31:16 GPIn_EN — R/W. These bits enable the corresponding GPI[n]_STS bits being set to cause a SCI, and/or wake event. These bits are cleared by RSMRST#. NOTE: Mapping is as follows: bit 31 corresponds to GPI[15] ... and bit 16 corresponds to GPI[0]. USB4_EN — R/W. 0 = Disable. 1 = Enable the setting of the USB4_STS bit to generate a wake event. The USB4_STS bit is set anytime USB UHCI controller #4 signals a wake event. Break events are handled via the USB interrupt. PME_B0_EN — R/W. 0 = Disable 1 = Enables the setting of the PME_B0_STS bit to generate a wake event and/or an SCI or SMI#. PME_B0_STS can be a wake event from the S1–S4 states, or from S5 (if entered via SLP_TYP and SLP_EN) or power failure, but not Power Button Override. This bit defaults to NOTE: It is only cleared by Software or RTCRST#. It is not cleared by CF9h writes. USB3_EN — R/W. 0 = Disable. 1 = Enable the setting of the USB3_STS bit to generate a wake event. The USB3_STS bit is set anytime USB UHCI controller #3 signals a wake event. Break events are handled via the USB interrupt. PME_EN — R/W. 0 = Disable. 1 = Enables the setting of the PME_STS to generate a wake event and/or an SCI. PME# can be a wake event from the S1 – S4 state or from S5 (if entered via SLP_EN, but not power button override). (Desktop Only) Reserved (Mobile Only) BATLOW_EN — R/W. (Mobile Only) 0 = Disable. 1 = Enables the BATLOW# signal to cause an SMI# or SCI (depending on the SCI_EN bit) when it goes low. This bit does not prevent the BATLOW# signal from inhibiting the wake event. PCI_EXP_EN — R/W. 0 = Disable SCI generation upon PCI_EXP_STS bit being set. 1 = Enables ICH6 to cause an SCI when PCI_EXP_STS bit is set. This is used to allow the PCI Express* ports, including the link to the (G)MCH, to cause an SCI due to wake/PME events.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 415 LPC Interface Bridge Registers (D31:F0) RI_EN — R/W. The value of this bit will be maintained through a G3 state and is not affected by a hard reset caused by a CF9h write. 0 = Disable. 1 = Enables the setting of the RI_STS to generate a wake event. TCOSCI_EN — R/W. 0 = Disable. 1 = Enables the setting of the TCOSCI_STS to generate an SCI. AC97_EN — R/W. 0 = Disable. 1 = Enables the setting of the AC97_STS to generate a wake event. NOTE: This bit is also used for Intel High Definition Audio when the Intel High Definition Audio host controller is enabled rather than the AC97 host controller. USB2_EN — R/W. 0 = Disable. 1 = Enables the setting of the USB2_STS to generate a wake event. USB1_EN — R/W. 0 = Disable. 1 = Enables the setting of the USB1_STS to generate a wake event. THRM#_POL — R/W. This bit controls the polarity of the THRM# pin needed to set the THRM_STS bit. 0 = Low value on the THRM# signal will set the THRM_STS bit. 1 = HIGH value on the THRM# signal will set the THRM_STS bit. HOT_PLUG_EN — R/W. 0 = Disables SCI generation upon the HOT_PLUG_STS bit being set. 1 = Enables the ICH6 to cause an SCI when the HOT_PLUG_STS bit is set. This is used to allow the PCI Express ports to cause an SCI due to hot-plug events. THRM_EN — R/W. 0 = Disable. 1 = Active assertion of the THRM# signal (as defined by the THRM_POL bit) will set the THRM_STS bit and generate a power management event (SCI or SMI). Bit Description

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LPC Interface Bridge Registers (D31:F0)

10.8.3.12 SMI_EN—SMI Cont rol and Enable Register

I/O Address: PMBASE + 30h Attribute: R/W, R/W (special), WO Default Value: 00000000h Size: 32 bit Lockable: No Usage: ACPI or Legacy Power Well: Core Note: This register is symmetrical to the SMI status register. Bit Description 31:19 Reserved INTEL_USB2_EN — R/W. 0 = Disable 1 = Enables Intel-Specific USB2 SMI logic to cause SMI#. LEGACY_USB2_EN — R/W. 0 = Disable 1 = Enables legacy USB2 logic to cause SMI#. 16:15 Reserved PERIODIC_EN — R/W. 0 = Disable. 1 = Enables the ICH6 to generate an SMI# when the PERIODIC_STS bit (PMBASE + 34h, bit 14) is set in the SMI_STS register (PMBASE + 34h). TCO_EN — R/W. 0 = Disables TCO logic generating an SMI#. Note that if the NMI2SMI_EN bit is set, SMIs that are caused by re-routed NMIs will not be gated by the TCO_EN bit. Even if the TCO_EN bit is 0, NMIs will still be routed to cause SMIs. 1 = Enables the TCO logic to generate SMI#. NOTE: This bit cannot be written once the TCO_LOCK bit is set.

12 Reserved

MCSMI_ENMicrocontroller SMI Enable (MCSMI_EN) — R/W. 0 = Disable. 1 = Enables ICH6 to trap accesses to the mi crocontroller range (62h or 66h) and generate an SMI#. Note that “trapped’ cycles will be claimed by the ICH6 on PCI, but not forwarded to LPC. 10:8 Reserved BIOS Release (BIOS_RLS) — WO. 0 = This bit will always return 0 on reads . Writes of 0 to this bit have no effect. 1 = Enables the generation of an SCI interrupt for ACPI software when a one is written to this bit position by BIOS software. NOTE: GBL_STS being set will cause an SCI, even if the SCI_EN bit is not set. Software must take great care not to set the BIOS_RLS bit (which causes GBL_STS to be set) if the SCI handler is not in place. Software SMI# Timer Enable (SWSMI_TMR_EN) — R/W. 0 = Disable. Clearing the SWSMI_TMR_EN bit before the timer expires will reset the timer and the SMI# will not be generated. 1 = Starts Software SMI# Timer. When the SWSMI timer expires (the timeout period depends upon the SWSMI_RATE_SEL bit setting), SWSMI_TMR_STS is set and an SMI# is generated. SWSMI_TMR_EN stays set until cleared by software. APMC_EN — R/W. 0 = Disable. Writes to the APM_CNT register will not cause an SMI#. 1 = Enables writes to the APM_CNT register to cause an SMI#.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 417 LPC Interface Bridge Registers (D31:F0) SLP_SMI_EN — R/W. 0 = Disables the generation of SMI# on SLP_EN. Note that this bit must be 0 before the software attempts to transition the system into a sleep state by writing a 1 to the SLP_EN bit. 1 = A write of 1 to the SLP_EN bit (bit 13 in PM1_CNT register) will generate an SMI#, and the system will not transition to the sleep state based on that write to the SLP_EN bit. LEGACY_USB_EN — R/W. 0 = Disable. 1 = Enables legacy USB ci rcuit to cause SMI#. BIOS_EN — R/W. 0 = Disable. 1 = Enables the generation of SMI# when ACPI software writes a 1 to the GBL_RLS bit (D31:F0:PMBase + 04h:bit 2). Note that if the BIOS_STS bit (D31:F0:PMBase + 34h:bit 2), which gets set when software writes 1 to GBL_RLS bit, is already a 1 at the time that BIOS_EN becomes 1, an SMI# will be generated when BIOS_EN gets set. End of SMI (EOS) — R/W (special). This bit controls the arbitration of the SMI signal to the processor. This bit must be set for the ICH6 to assert SMI# low to the processor after SMI# has been asserted previously. 0 = Once the ICH6 asserts SMI# low, the EOS bit is automatically cleared. 1 = When this bit is set to 1, SMI# signal will be de-asserted for 4 PCI clocks before its assertion. In the SMI handler, the processor should clear all pending SMIs (by servicing them and then clearing their respective status bits), set the EOS bit, and exit SMM. This will allow the SMI arbiter to re-assert SMI upon detection of an SMI event and the setting of a SMI status bit. NOTE: ICH6 is able to generate 1st SMI after reset even though EOS bit is not set. Subsequent SMI require EOS bit is set. GBL_SMI_EN — R/W. 0 = No SMI# will be generated by ICH6. This bit is reset by a PCI reset event. 1 = Enables the generation of SMI# in the system upon any enabled SMI event. NOTE: When the SMI_LOCK bit is set, this bit cannot be changed. Bit Description

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LPC Interface Bridge Registers (D31:F0)

10.8.3.13 SMI_STS—SM I Status Register

I/O Address: PMBASE + 34h Attribute: RO, R/WC Default Value: 00000000h Size: 32-bit Lockable: No Usage: ACPI or Legacy Power Well: Core Note: If the corresponding _EN bit is set when the _STS bit is set, the ICH6 will cause an SMI# (except bits 8–10 and 12, which do not need enable bits since they are logic ORs of other registers that have enable bits). The ICH6 uses the same GPE0_EN register (I/O address: PMBase+2Ch) to enable/disable both SMI and ACPI SCI general purpose input events. ACPI OS assumes that it owns the entire GPE0_EN register per ACPI spec. Problems arise when some of the general- purpose inputs are enabled as SMI by BIOS, and some of the general purpose inputs are enabled for SCI. In this case ACPI OS turns off the enabled bit for any GPIx input signals that are not indicated as SCI general-purpose events at boot, and exit from sleeping states. BIOS should define a dummy control method which prevents the ACPI OS from clearing the SMI GPE0_EN bits. Bit Description 31:20 Reserved MONITOR_STS — RO. This bit will be set if the Trap/SMI logic has caused the SMI. This will occur when the processor or a bus master accesses an assigned register (or a sequence of accesses). 20 PCI_EXP_SMI_STS — RO. PCI Express* SMI event occurred. This could be due to a PCI Express PME event or Hot-Plug event.

19 Reserved

INTEL_USB2_STS — RO. This non-sticky read-only bit is a logical OR of each of the SMI status bits in the Intel-Specific USB2 SMI Status Register ANDed with the corresponding enable bits. This bit will not be active if the enable bits are not set. Writes to this bit will have no effect. LEGACY_USB2_STS — RO. This non-sticky read-only bit is a l ogical OR of each of the SMI status bits in the USB2 Legacy Support Register ANDed with the corresponding enable bits. This bit will not be active if the enable bits are not set. Writes to this bit will have no effect. SMBus SMI Status (SMBus_SMI_STS) — R/WC. Software clears this bit by writing a 1 to it. 0 = This bit is set from the 64 kHz clock domain us ed by the SMBus. Software must wait at least 15.63 us after the initial assertion of this bit before clearing it. 1 = Indicates that the SMI# was caused by: 1. The SMBus Slave receiving a message that an SMI# should be caused, or 2. The SMBALERT# signal goes active and the SMB_SMI_EN bit is set and the SMBALERT_DIS bit is cleared, or 3. The SMBus Slave receiving a Host Notify message and the HOST_NOTIFY_INTREN and the SMB_SMI_EN bits are set, or 4. The ICH6 detecting the SMLINK_SLAVE_SMI command while in the S0 state. SERIRQ_SMI_STS — RO. 0 = SMI# was not caused by the SERIRQ decoder. 1 = Indicates that the SMI# was caused by the SERIRQ decoder. NOTE: This is not a sticky bit PERIODIC_STS — R/WC. Software clears this bit by writing a 1 to it. 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set at the rate determined by the PER_SMI_SEL bits. If the PERIODIC_EN bit (PMBASE + 30h, bit 14) is also set, the ICH6 generates an SMI#. TCO_STS — R/WC. Software clears this bit by writing a 1 to it. 0 = SMI# not caused by TCO logic. 1 = Indicates the SMI# was caused by the TCO logic. Note that this is not a wake event.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 419 LPC Interface Bridge Registers (D31:F0) Device Monitor Status (DEVMON_STS) — RO. 0 = SMI# not caused by Device Monitor. 1 = Set if bit 0 of the DEVACT_STS register (PM BASE + 44h) is set. The bit is not sticky, so writes to this bit will have no effect. Microcontroller SMI# Status (MCSMI_STS) — R/WC. Software clears this bit by writing a 1 to it. 0 = Indicates that there has been no access to the power management microcontroller range (62h or 66h). 1 = Set if there has been an access to the power management microcontroller range (62h or 66h) and the Microcontroller Decode Enable #1 bit in the LPC Bridge I/O Enables configuration register is 1 (D31:F0:Offset 82h:bit 11). Note that this implementation assumes that the Microcontroller is on LPC. If this bit is set, and the MCSMI_EN bit is also set, the ICH6 will generate an SMI#. GPE0_STS — RO. This bit is a logical OR of the bits in the ALT_GP_SMI_STS register that are also set up to cause an SMI# (as indicated by the GPI_ROUT registers) and have the corresponding bit set in the ALT_GP_SMI_EN register. Bits that are not routed to cause an SMI# will have no effect on this bit. 0 = SMI# was not generated by a GPI assertion. 1 = SMI# was generated by a GPI assertion. GPE0_STS — RO. This bit is a logical OR of the bits 14:10, 8:2, and 0 in the GPE0_STS register (PMBASE + 28h) that also have the corresponding bit set in the GPE0_EN register (PMBASE + 2Ch). 0 = SMI# was not generated by a GPE0 event. 1 = SMI# was generated by a GPE0 event. PM1_STS_REG — RO. This is an ORs of the bits in the ACPI PM1 Status Register (offset PMBASE+00h) that can cause an SMI#. 0 = SMI# was not generated by a PM1_STS event. 1 = SMI# was generated by a PM1_STS event. SWSMI_TMR_STS — R/WC. Software clears this bit by writing a 1 to it. 0 = Software SMI# Timer has Not expired. 1 = Set by the hardware when the Software SMI# Timer expires. APM_STS — R/WC. Software clears this bit by writing a 1 to it. 0 = No SMI# generated by write access to APM Control register with APMCH_EN bit set. 1 = SMI# was generated by a write access to the APM Control register with the APMC_EN bit set. SLP_SMI_STS — R/WC. Software clears this bit by writing a 1 to the bit location. 0 = No SMI# caused by write of 1 to SLP_ EN bit when SLP_SMI_EN bit is also set. 1 = Indicates an SMI# was caused by a write of 1 to SLP_EN bit when SLP_SMI_EN bit is also set. LEGACY_USB_STS — RO. This bit is a logical OR of eac h of the SMI status bits in the USB Legacy Keyboard/Mouse Control Registers ANDed with the corresponding enable bits. This bit will not be active if the enable bits are not set. 0 = SMI# was not generated by USB Legacy event. 1 = SMI# was generated by USB Legacy event. BIOS_STS — R/WC. 0 = No SMI# generated due to ACPI software requesting attention. 1 = This bit gets set by hardware when a 1 is written by software to the GBL_RLS bit (D31:F0:PMBase + 04h:bit 2). When both the BIOS_EN bit (D31:F0:PMBase + 30h:bit 2) and the BIOS_STS bit are set, an SMI# will be generated. The BIOS_STS bit is cleared when software writes a 1 to its bit position. 1:0 Reserved Bit Description

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LPC Interface Bridge Registers (D31:F0)

10.8.3.14 ALT_GP_SMI_EN—Altern ate GPI SMI Enable Register

I/O Address: PMBASE +38h Attribute: R/W Default Value: 0000h Size: 16-bit Lockable: No Usage: ACPI or Legacy Power Well: Resume

10.8.3.15 ALT_GP_SMI_STS—Alterna te GPI SMI Status Register

I/O Address: PMBASE +3Ah Attribute: R/WC Default Value: 0000h Size: 16-bit Lockable: No Usage: ACPI or Legacy Power Well: Resume Bit Description 15:0 Alternate GPI SMI Enable — R/W. These bits are used to enable the corresponding GPIO to cause an SMI#. For these bits to have any effect, the following must be true.

• The corresponding bit in the ALT_GP_SMI_EN register is set.
• The corresponding GPI must be routed in the GPI_ROUT register to cause an SMI.
• The corresponding GPIO must be implemented. NOTE: Mapping is as follows: bit 15 corresponds to GPI[15] ... bit 0 corresponds to GPI[0]. Bit Description 15:0 Alternate GPI SMI Status — R/WC. These bits report the status of the corresponding GPIs. 0 = Inactive. Software clears this bit by writing a 1 to it. 1 = Active These bits are sticky. If the following conditions are true, then an SMI# will be generated and the GPE0_STS bit set:
• The corresponding bit in the ALT_GPI_SMI_EN register (PMBASE + 38h) is set
• The corresponding GPI must be routed in the GPI_ROUT register to cause an SMI.
• The corresponding GPIO must be implemented. All bits are in the resume well. Default for these bits is dependent on the state of the GPI pins.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 421 LPC Interface Bridge Registers (D31:F0)

10.8.3.16 DEVACT_STS — Device Activity Status Register

I/O Address: PMBASE +44h Attribute: R/WC Default Value: 0000h Size: 16-bit Lockable: No Usage: Legacy Only Power Well: Core Each bit indicates if an access has occurred to the corresponding device’s trap range, or for bits 6:9 if the corresponding PCI interrupt is active. This register is used in conjunction with the Periodic SMI# timer to detect any system activity for legacy power management. The periodic SMI# timer indicates if it is the right time to read the DEV ACT_STS register (PMBASE + 44h). Note: Software clears bits that are set in this register by writing a 1 to the bit position. Bit Description 15:13 Reserved KBC_ACT_STS — R/WC. KBC (60/64h). 0 = Indicates that there has been no access to this device’s I/O range. 1 = This device’s I/O range has been accessed. Clear this bit by writing a 1 to the bit location. 11:10 Reserved PIRQDH_ACT_STS — R/WC. PIRQ[D or H]. 0 = The corresponding PCI interrupts have not been active. 1 = At least one of the corresponding PC I interrupts has been active. Clear this bit by writing a 1 to the bit location. PIRQCG_ACT_STS — R/WC. PIRQ[C or G]. 0 = The corresponding PCI interrupts have not been active. 1 = At least one of the corresponding PC I interrupts has been active. Clear this bit by writing a 1 to the bit location. PIRQBF_ACT_STS — R/WC. PIRQ[B or F]. 0 = The corresponding PCI interrupts have not been active. 1 = At least one of the corresponding PC I interrupts has been active. Clear this bit by writing a 1 to the bit location. PIRQAE_ACT_STS — R/WC. PIRQ[A or E]. 0 = The corresponding PCI interrupts have not been active. 1 = At least one of the corresponding PC I interrupts has been active. Clear this bit by writing a 1 to the bit location. 5:1 Reserved IDE_ACT_STS — R/WC. IDE Primary Drive 0 and Drive 1. 0 = Indicates that there has been no access to this device’s I/O range. 1 = This device’s I/O range has been accessed. The enable bit is in the ATC register (D31:F1:Offset C0h). Clear this bit by writing a 1 to the bit location.

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10.8.3.17 SS_CNT— Intel SpeedStep ® Technology

Control Register (Mobile Only) I/O Address: PMBASE +50h Attribute: R/W (special) Default Value 01h Size: 8-bit Lockable: No Usage: ACPI/Legacy Power Well: Core Note: Writes to this register will initiate an Intel SpeedStep technology transition that involves a temporary transition to a C3-like state in which the STPCLK# signal will go active. An Intel SpeedStep technology transition always occur on writes to the SS_CNT register, even if the value written to SS_STATE is the same as the previous value (after this “transition” the system would still be in the same Intel SpeedStep technology state). If the SS_EN bit is 0, then writes to this register will have no effect and reads will return 0.

10.8.3.18 C3_RES— C3 Residen cy Register (Mobile Only)

I/O Address: PMBASE +5 4h Attribute: RW/RO Default Value 00000000h Size: 32-bit Lockable: No Usage: ACPI/Legacy Power Well: Core Software may only write this register during system initialization to set the state of the C3_RESIDENCY_MODE bit. It must not be written while the timer is in use. Bit Description 7:1 Reserved SS_STATE (Intel SpeedStep® technology State) — R/W (Special). When this bit is read, it returns the last value written to this register. By convention, this will be the current Intel SpeedStep technology state. Writes to this register causes a change to the Intel SpeedStep technology state indicated by the value written to this bit. If the new value for SS_STATE is the same as the previous value, then transition will still occur. 0 = High power state. 1 = Low power state NOTE: This is only a convention because the transition is the same regardless of the value written to this bit. Bit Description C3_RESEDENCY_MODE — RW. When this bit is 0, the C3_RESIDENCY counter field will automatically clear upon entry into the C3 or C4 state. When this bit is 1, the C3_RESIDENCY counter will not automatically clear upon entry into the C3 or C4 state. 30:24 Reserved 23:0 C3_RESIDENCY — RO. The value in this field increments at the same rate as the Power Management Timer. If the C3_RESEDENCY_MODE bit is clear, this field automatically resets to 0 at the point when the Lvl3 or Lvl4 read occurs. If the C3_RESIDENCY_MODE bit is set, the register does not reset when the Lvl3 or Lvl4 read occurs. In either mode, it increments while STP_CPU# is active (i.e. the processor is in a C3 or C4 state). This field will roll over in the same way as the PM Timer, however the most significant bit is NOT sticky. Software is responsible for reading this field before performing the Lvl3/4 transition. Software must also check for rollover if the maximum time in C3/C4 could be exceeded.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 423 LPC Interface Bridge Registers (D31:F0)

10.9 System Management TCO Registers (D31:F0)

The TCO logic is accessed via registers mapped to the PCI configuration space (Device 31:Function 0) and the system I/O space. For TCO PCI Configuration registers, see LPC Device 31:Function 0 PCI Configuration registers. TCO Register I/O Map The TCO I/O registers reside in a 32-byte range pointed to by a TCOBASE value, which is, PMBASE + 60h in the PCI configuration space. The following table shows the mapping of the registers within that 32-byte range. Each register is described in the following sections.

10.9.1 TCO_RLD—TCO Timer Reload and Current Value Register

I/O Address: TCOBASE +00h Attribute: R/W Default Value: 0000h Size: 16-bit Lockable: No Power Well: Core Table 10-12. TCO I/O Register Address Map TCOBASE + Offset Mnemonic Register Name Default Type 00h–01h TCO_RLD TCO Timer Reload and Current Value 0000h R/W 02h TCO_DAT_IN TCO Data In 00h R/W 03h TCO_DAT_OUT TCO Data Out 00h R/W 04h–05h TCO1_STS TCO1 Status 0000h R/WC, RO 06h–07h TCO2_STS TCO2 Status 0000h R/W, R/WC 08h–09h TCO1_CNT TCO1 Control 0000h R/W, R/W (special), R/WC 0Ah–0Bh TCO2_CNT TCO2 Control 0008h R/W 0Ch–0Dh TCO_MESSAGE1, TCO_MESSAGE2 TCO Message 1 and 2 00h R/W 0Eh TCO_WDCNT Watchdog Control 00h R/W 0Fh — Reserved — — 10h SW_IRQ_GEN Software IRQ Generation 11h R/W 11h — Reserved — — 12h–13h TCO_TMR TCO Timer Initial Value 0004h R/W 14h–1Fh — Reserved — — Bit Description 15:10 Reserved 9:0 TCO Timer Value — R/W. Reading this register will return the current count of the TCO timer. Writing any value to this register will reload the timer to prevent the timeout.

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10.9.2 TCO_DAT_IN—TCO Data In Register

I/O Address: TCOBASE +02h Attribute: R/W Default Value: 00h Size: 8-bit Lockable: No Power Well: Core

10.9.3 TCO_DAT_OUT—TCO Data Out Register

I/O Address: TCOBASE +03h Attribute: R/W Default Value: 00h Size: 8-bit Lockable: No Power Well: Core

10.9.4 TCO1_STS—TCO1 Status Register

I/O Address: TCOBASE + 04h Attribute: R/WC, RO Default Value: 0000h Size: 16-bit Lockable: No Power Well: Core (Except bit 7, in RTC) Bit Description 7:0 TCO Data In Value — R/W. This data register field is used for passing commands from the OS to the SMI handler. Writes to this register will cause an SMI and set the SW_TCO_SMI bit in the TCO1_STS register (D31:F0:04h). Bit Description 7:0 TCO Data Out Value — R/W. This data register field is used for passing commands from the SMI handler to the OS. Writes to this register will set the TCO_INT_STS bit in the TCO_STS register. It will also cause an interrupt, as selected by the TCO_INT_SEL bits. Bit Description 15:13 Reserved DMISERR_STS — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = ICH6 received a DMI special cycle message vi a DMI indicating that it wants to cause an SERR#. The software must read the (G)MCH to determine the reason for the SERR#. DMISMI_STS — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = ICH6 received a DMI special cycle message via DMI indicating that it wants to cause an SMI. The software must read the (G)MCH to determine the reason for the SMI. DMISCI_STS — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = ICH6 received a DMI special cycle message via DM I indicating that it wants to cause an SCI. The software must read the (G)MCH to determine the reason for the SCI.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 425 LPC Interface Bridge Registers (D31:F0) BIOSWR_STS — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = ICH6 sets this bit and generates and SMI# to indicate an illegal attempt to write to the BIOS. This occurs when either: a) The BIOSWP bit is changed from 0 to 1 and the BLD bit is also set, or b) any write is attempted to the BIOS and the BIOSWP bit is also set. NOTE: On write cycles attempted to the 4 MB lower alias to the BIOS space, the BIOSWR_STS will not be set. NEWCENTURY_STS — R/WC. This bit is in the RTC well. 0 = Cleared by writing a 1 to the bit position or by RTCRST# going active. 1 = This bit is set when the Year byte (RTC I/O sp ace, index offset 09h) rolls over from 99 to 00. Setting this bit will cause an SMI# (but not a wake event). NOTE: The NEWCENTURY_STS bit is not valid when the RTC battery is first installed (or when RTC power has not been maintained). Software can determine if RTC power has not been maintained by checking the RTC_PWR_STS bit (D31:F0:A4h, bit 2), or by other means (such as a checksum on RTC RAM). If RTC power is determined to have not been maintained, BIOS should set the time to a legal value and then clear the NEWCENTURY_STS bit. The NEWCENTURY_STS bit may take up to 3 RTC clocks for the bit to be cleared after a 1 is written to the bit to clear it. After writing a 1 to this bit, software should not exit the SMI handler until verifying that the bit has actually been cleared. This will ensure that the SMI is not re-entered. 6:4 Reserved TIMEOUT — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Set by ICH6 to indicate that the SMI was caused by the TCO timer reaching 0. TCO_INT_STS — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = SMI handler caused the interrupt by writi ng to the TCO_DAT_OUT register (TCOBASE + 03h). SW_TCO_SMI — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Software caused an SMI# by writing to the TCO_DAT_IN register (TCOBASE + 02h). NMI2SMI_STS — RO. 0 = Cleared by clearing the associated NMI status bit. 1 = Set by the ICH6 when an SMI# occurs becaus e an event occurred that would otherwise have caused an NMI (because NMI2SMI_EN is set). Bit Description

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10.9.5 TCO2_STS—TCO2 Status Register

I/O Address: TCOBASE +06h Attribute: R/W, R/WC Default Value: 0000h Size: 16-bit Lockable: No Power Well: Resume (Except Bit 0, in RTC) Bit Description 15:5 Reserved SMLink Slave SMI Status (SMLINK_SLV_SMI_STS) — R/WC. Allow the software to go directly into pre-determined sleep state. This avoids race conditions. Software clears this bit by writing a 1 to it. 0 = The bit is reset by RSMRST#, but not due to the PCI Reset associated with exit from S3–S5 states. 1 = ICH6 sets this bit to 1 when it receives t he SMI message on the SMLink's Slave Interface. 3R e s e r v e d BOOT_STS — R/WC. 0 = Cleared by ICH6 based on RSMRST# or by software writing a 1 to this bit. Note that software should first clear the SECOND_TO_STS bit before writing a 1 to clear the BOOT_STS bit. 1 = Set to 1 when the SECOND_TO_STS bit goes from 0 to 1 and the processor has not fetched the first instruction. If rebooting due to a second TCO timer timeout, and if the BOOT_STS bit is set, the ICH6 will reboot using the ‘safe’ multiplier (1111). This allows the system to recover from a processor frequency multiplier that is too high, and allows the BIOS to check the BOOT_STS bit at boot. If the bit is set and the frequency multiplier is 1111, then the BIOS knows that the processor has been programmed to an illegal multiplier. SECOND_TO_STS — R/WC. 0 = Software clears this bit by writing a 1 to it, or by a RSMRST#. 1 = ICH6 sets this bit to 1 to indicate that the TIMEOUT bit had been (or is currently) set and a second timeout occurred before the TCO_RLD register was written. If this bit is set and the NO_REBOOT configuration bit is 0, then the ICH6 will reboot the system after the second timeout. The reboot is done by asserting PLTRST#. Intruder Detect (INTRD_DET) — R/WC. 0 = Software clears this bit by writing a 1 to it, or by RTCRST# assertion. 1 = Set by ICH6 to indicate that an intrusion was detected. This bit is set even if the system is in G3 state. NOTES: 1. This bit has a recovery time. After writing a 1 to this bit position (to clear it), the bit may be read back as a 1 for up 65 microseconds before it is read as a 0. Software must be aware of this recovery time when reading this bit after clearing it. 2. If the INTRUDER# signal is active when the software attempts to clear the INTRD_DET bit, the bit will remain as a 1, and the SMI# will be generated again immediately. The SMI handler can clear the INTRD_SEL bits (TCOBASE + 0Ah, bits 2:1), to avoid further SMIs. However, if the INTRUDER# signals goes inactive and then active again, there will not be further SMI’s (because the INTRD_SEL bits would select that no SMI# be generated). 3. If the INTRUDER# signal goes inactive some point after the INTRD_DET bit is written as a 1, then the INTRD_DET signal will go to a 0 when INTRUDER# input signal goes inactive. Note that this is slightly different than a classic sticky bit, since most sticky bits would remain active indefinitely when the signal goes active and would immediately go inactive when a 1 is written to the bit

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 427 LPC Interface Bridge Registers (D31:F0)

10.9.6 TCO1_CNT—TCO 1 Control Register

I/O Address: TCOBASE +08h Attribut e: R/W, R/W (special), R/WC Default Value: 0000h Size: 16-bit Lockable: No Power Well: Core Bit Description 15:13 Reserved TCO_LOCK — R/W (special). When set to 1, this bit prevents writes from changing the TCO_EN bit (in offset 30h of Power Management I/O space). Once this bit is set to 1, it can not be cleared by software writing a 0 to this bit location. A core-well reset is required to change this bit from 1 to 0. This bit defaults to 0. TCO Timer Halt (TCO_TMR_HLT) — R/W. 0 = The TCO Timer is enabled to count. 1 = The TCO Timer will halt. It will not count, and thus cannot reach a value that will cause an SMI# or set the SECOND_TO_STS bit. When set, this bit will prevent rebooting and prevent Alert On LAN event messages from being transmitted on the SMLINK (but not Alert On LAN* heartbeat messages). SEND_NOW — R/W (special). 0 = The ICH6 will clear this bit when it has comp leted sending the message. Software must not set this bit to 1 again until the ICH6 has set it back to 0. 1 = Writing a 1 to this bit will cause the ICH6 to send an Alert On LAN Event message over the SMLINK interface, with the Software Event bit set. Setting the SEND_NOW bit causes the ICH6 integrated LAN controller to reset, which can have unpredictable side-effects. Unless software protects against these side effects, software should not attempt to set this bit. NMI2SMI_EN — R/W. 0 = Normal NMI functionality. 1 = Forces all NMIs to instead cause SMIs. Th e functionality of this bit is dependent upon the settings of the NMI_EN bit and the GBL_SMI_EN bit as detailed in the following table: NMI_NOW — R/WC. 0 = Software clears this bit by writing a 1 to it. The NMI handler is expected to clear this bit. Another NMI will not be generated until the bit is cleared. 1 = Writing a 1 to this bit causes an NMI. This allows the BIOS or SMI handler to force an entry to the NMI handler. 7:0 Reserved NMI_EN GBL_SMI_EN Description 0b 0b No SMI# at all because GBL_SMI_EN = 0 0b 1b SMI# will be caused due to NMI events 1b 0b No SMI# at all because GBL_SMI_EN = 0 1b 1b No SMI# due to NMI because NMI_EN = 1

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10.9.7 TCO2_CNT—TCO2 Control Register

I/O Address: TCOBASE +0Ah Attribute: R/W Default Value: 0008h Size: 16-bit Lockable: No Power Well: Resume

10.9.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers

I/O Address: TCOBASE +0Ch (Message 1) Attribute: R/W TCOBASE +0Dh (Message 2) Default Value: 00h Size: 8-bit Lockable: No Power Well: Resume Bit Description 15:6 Reserved 5:4 OS_POLICY — R/W. OS-based software writes to these bits to select the policy that the BIOS will use after the platform resets due the WDT. The following convention is recommended for the BIOS and OS: 00 = Boot normally 01 = Shut down 10 = Don’t load OS. Hold in pre-boot state and use LAN to determine next step 11 = Reserved NOTE: These are just scratchpad bits. They should not be reset when the TCO logic resets the platform due to Watchdog Timer. GPI11_ALERT_DISABLE — R/W. At reset (via RSMRST# asserted) this bit is set and GPI[11] alerts are disabled. 0 = Enable. 1 = Disable GPI[11]/SMBALERT# as an alert s ource for the heartbeats and the SMBus slave. 2:1 INTRD_SEL — R/W. This field selects the action to take if the INTRUDER# signal goes active. 00 = No interrupt or SMI# 01 = Interrupt (as selected by TCO_INT_SEL). 10 = SMI 11 = Reserved 0R e s e r v e d Bit Description 7:0 TCO_MESSAGE[n] — R/W. The value written into this regi ster will be sent out via the SMLINK interface in the MESSAGE field of the Alert On LAN message. BIOS can write to this register to indicate its boot progress which can be monitored externally

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 429 LPC Interface Bridge Registers (D31:F0)

10.9.9 TCO_WDCNT—TCO Watchdog Control Register

Offset Address: TCOBASE + 0Eh Attribute: R/W Default Value: 00h Size: 8 bits Power Well: Resume

10.9.10 SW_IRQ_GEN—Software IRQ Generation Register

Offset Address: TCOBASE + 10h Attribute: R/W Default Value: 11h Size: 8 bits Power Well: Core

10.9.11 TCO_TMR—TCO Timer Initial Value Register

I/O Address: TCOBASE +12h Attribute: R/W Default Value: 0004h Size: 16-bit Lockable: No Power Well: Core Bit Description 7:0 Watchdog Status (WDSTATUS) — R/W. The value written to this register will be sent in the Alert On LAN message on the SMLINK interface. It can be used by the BIOS or system management software to indicate more details on the boot progress. This register will be reset to the default of 00h based on RSMRST# (but not PCI reset). Bit Description 7:2 Reserved IRQ12_CAUSE — R/W. The state of this bit is logically ANDed with the IRQ12 signal as received by the ICH6’s SERIRQ logic. This bit must be a 1 (default) if the ICH6 is expected to receive IRQ12 assertions from a SERIRQ device. IRQ1_CAUSE — R/W. The state of this bit is logically ANDed with the IRQ1 signal as received by the ICH6’s SERIRQ logic. This bit must be a 1 (default) if the ICH6 is expected to receive IRQ1 assertions from a SERIRQ device. Bit Description 15:10 Reserved 9:0 TCO Timer Initial Value — R/W. Value that is loaded into the timer each time the TCO_RLD register is written. Values of 0000h or 0001h will be ignored and should not be attempted. The timer is clocked at approximately 0.6 seconds, and thus allows timeouts ranging from 1.2 second to 613.8 seconds. Note: The timer has an error of ± 1 tick (0.6s). The TCO Timer will only count down in the S0 state.

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10.10 General Purpose I/O Registers (D31:F0)

The control for the general purpose I/O signals is handled through a separate 64-byte I/O space. The base offset for this space is selected by the GPIOBASE register.

10.10.1 GPIO Register I/O Address Map

Table 10-13. Registers to Control GPIO Address Map GPIOBASE + Offset Mnemonic Register Name Default Access General Registers 00–03h GPIO_USE_SEL GPIO Use Select 1BA83180h R/W 04–07h GP_IO_SEL GPIO Input/Output Select E400 FFFFh R/W 08–0Bh — Reserved — — 0C–0Fh GP_LVL GPIO Level for Input or Output FF3F0000h R/W 10–13h — Reserved — — Output Control Registers 14–17h — Reserved — — 18–1Bh GPO_BLINK GPIO Blink Enable 00040000h R/W 1C–1Fh — Reserved — — Input Control Registers 20–2Bh — Reserved — — 2C–2Fh GPI_INV GPIO Signal Invert 00000000h R/W 30–33h GPIO_USE_SEL2 GPIO Use Select 2 [63:32] 00000006h R/W 34–37h GP_IO_SEL2 GPIO Input/Output Select 2 [63:32] 00000300h R/W 38–3Bh GP_LVL2 GPIO Level for Input or Output 2 [63:32] 00030207h R/W

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 431 LPC Interface Bridge Registers (D31:F0)

10.10.2 GPIO_USE_SEL—GPIO Use Select Register

Offset Address: GPIOBASE + 00h Attribute: R/W Default Value: 1BA83180h Size: 32-bit Lockable: No Power Well: Core for 0:7, 12, 16:21, 23, 26, 29:31 Resume for 8:11, 13:15, 25, 27, 28

10.10.3 GP_IO_SEL—GPIO Input/Output Select Register

Offset Address: GPIO BASE +04h Attribute: R/W Default Value: E400FFFFh Size: 32-bit Lockable: No Power Well: Resume Bit Description 31:29 26, 15:14, 11:9, 5:0 GPIO_USE_SEL[31:29, 26, 15:14, 11:9, 5:0] — R/W. Each bit in this register enables the corresponding GPIO (if it exists) to be used as a GPIO, rather than for the native function. 0 = Signal used as native function. 1 = Signal used as a GPIO. NOTES: 1. The following bit is not implemented because there is no corresponding GPIO: 22. 2. The following bits are always 1 because they are unmultiplexed: 7, 8, 12:13, 19, 21, 23:25, 27:28 3. The following bits are not implemented because they are determined by the Desktop/Mobile configuration: 6, 18, 20 4. Bit 16 is not implemented because GPO selection will be controlled by Bit 0 (REQ/GNT pair) 5. Bit 17 is not implemented because GPO selection will be controlled by Bit 1 (REQ/GNT pair) 6. If GPIO[n] does not exist, then the bit in this register will always read as 0 and writes will have no effect. 7. After a full reset (RSMRST#) all multiplexed signals in the resume and core wells are configured as their native function rather than as a GPIO. After just a PLTRST#, the GPIO in the core well are configured as their native function. 8. When configured to GPIO mode, the multiplexing logic should present the inactive state to native logic that uses the pin as an input. Bit Description 31:29 Always 1. These GPIs are fixed as inputs. 28:27 GP_IO_SEL[28:27] — R/W. When set to a 1, the corr esponding GPIO signal (if enabled in the GPIO_USE_SEL register) is programmed as an input. When set to 0, the GPIO signal is programmed as an output. 0 = Output. The corresponding GPIO signal is an output. 1 = Input. The corresponding GPIO signal is an input. 26 Always 1. This GPI is fixed as an input. 25:24 GP_IO_SEL[25:24] — R/W. When set to a 1, the corr esponding GPIO signal (if enabled in the GPIO_USE_SEL register) is programmed as an input. When set to 0, the GPIO signal is programmed as an output. 0 = Output. The corresponding GPIO signal is an output. 1 = Input. The corresponding GPIO signal is an input. 21:16 Always 0. The GPOs are fixed as outputs. 15:0 Always 1. These GPIs are fixed as inputs.

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10.10.4 GP_LVL—GPIO Level for Input or Output Register

Offset Address: GPIOB ASE +0Ch Attribute: R/W Default Value: FF3F0000h Size: 32-bit Lockable: No Power Well: See bit descriptions Bit Description 31:29 GP_LVL[31:29] — R/W. These bits correspond to input-only GPI in the core well. The corresponding GP_LVL bit reflects the state of the input signal (1 = high, 0 = low). Writes to these bits will have no effect. Since these bits correspond to GPI that are in the core well, these bits will be reset by PLTRST#. 0 = Low 1 = High 28:27 GP_LVL[28:27] — R/W. If GPIO[n] is programmed to be an output (via the corresponding bit in the GP_IO_SEL register), then the corresponding GP_LVL[n] bit can be updated by software to drive a high or low value on the output pin. 1 = high, 0 = low. If GPIO[n] is programmed as an input, then the corresponding GP_LVL bit reflects the state of the input signal (1 = high, 0 = low.). Writes will have no effect. Since these bits correspond to GPIO that are in the Resume well, these bits will be reset by RSMRST# and also by a write to the CF9h register. 0 = Low 1 = High GP_LVL[26] — R/W. This bit corresponds to an input-only GPI in the core well. The corresponding GP_LVL bit reflects the state of the input signal (1 = high, 0 = low). Writes to this bit will have no effect. Since this bit correspond to a GPI that is in the core well, this bit will be reset by PLTRST#. 0 = Low 1 = High 25:24 GP_LVL[25:24] — R/W. If GPIO[n] is programmed to be an output (via the corresponding bit in the GP_IO_SEL register), then the corresponding GP_LVL[n] bit can be updated by software to drive a high or low value on the output pin. 1 = high, 0 = low. If GPIO[n] is programmed as an input, then the corresponding GP_LVL bit reflects the state of the input signal (1 = high, 0 = low.). Writes will have no effect. Since these bits correspond to GPIO that are in the Resume well, these bits will be reset by RSMRST# and also by a write to the CF9h register. 0 = Low 1 = High 23:16 GP_LVL[23:16] — R/W. These bits can be updated by software to drive a high or low value on the output pin. These bits correspond to GPIO that are in the core well, and will be reset to their default values by PLTRST#. 0 = Low 1 = High 15:0 Reserved. (These bits are not needed, as the level of general purpose inputs can be read through the registers in the ACPI I/O space).

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 433 LPC Interface Bridge Registers (D31:F0)

10.10.5 GPO_BLINK—GPO Blink Enable Register

Offset Address: GPIO BASE +18h Attribute: R/W Default Value: 0004 0000h Size: 32-bit Lockable: No Power Well: See bit description NOTE: (Desktop Only) GPIO18 will blink by default immediately after reset. This signal could be connected to an LED to indicate a failed boot (by programming BIOS to clear GP_BLINK18 after successful POST). Bit Description 28:27, 25 GP_BLINK[28:27, 25] — R/W. The setting of this bit has no effect if the corresponding GPIO signal is programmed as an input. 0 = The corresponding GPIO will function normally. 1 = If the corresponding GPIO is programmed as an output, the output signal will blink at a rate of approximately once per second. The high and low times have approximately 0.5 seconds each. The GP_LVL bit is not altered when this bit is set. The value of the corresponding GP_LVL bit remains unchanged during the blink process, and does not effect the blink in any way. The GP_LVL bit is not altered when programmed to blink. It will remain at its previous value. These bits correspond to GPIO in the Resume well. These bits revert to the default value based on RSMRST# or a write to the CF9h register (but not just on PLTRST#). 19:18 (Desktop Only) GP_BLINK[n] — R/W. The setting of these bits will have no effect if the corresponding GPIO is programmed as an input. These bits correspond to GPIO that are in the Core well, and will be reset to their default values by PLTRST#. 0 = The corresponding GPIO will function normally. 1 = If the corresponding GPIO is programmed as an output, the output signal will blink at a rate of approximately once per second. The high and low times are approximately 0.5 seconds each. The GP_LVL bit is not altered when this bit is set. (Mobile Only) GP_BLINK[n] — R/W. The setting of these bits will have no effect if the corresponding GPIO is programmed as an input. These bits correspond to GPIO that are in the Core well, and will be reset to their default values by PLTRST#. 0 = The corresponding GPIO will function normally. 1 = If the corresponding GPIO is programmed as an output, the output signal will blink at a rate of approximately once per second. The high and low times are approximately 0.5 seconds each. The GP_LVL bit is not altered when this bit is set.

434 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

LPC Interface Bridge Registers (D31:F0)

10.10.6 GPI_INV—GPIO Signal Invert Register

Offset Address: GPIOB ASE +2Ch Attribute: R/W Default Value: 00000000h Size: 32-bit Lockable: No Power Well: See bit description Bit Description 31:16 Reserved 15:13 GP_INV[n] — R/W. These bits are used to allow both active-low and active-high inputs to cause SMI# or SCI. Note that in the S0 or S1 state, the input signal must be active for at least two PCI clocks to ensure detection by the ICH6. In the S3, S4 or S5 states the input signal must be active for at least 2 RTC clocks to ensure detection. The setting of these bits has no effect if the corresponding GPIO is programmed as an output. These bits correspond to GPI that are in the resume well, and will be reset to their default values by RSMRST# or by a write to the CF9h register. 0 = The corresponding GPI_STS bit is set when the I CH6 detects the state of the input pin to be high. 1 = The corresponding GPI_STS bit is set when the I CH6 detects the state of the input pin to be low. GP_INV[n] — R/W. These bits are used to allow both active-low and active-high inputs to cause SMI# or SCI. Note that in the S0 or S1 state, the input signal must be active for at least two PCI clocks to ensure detection by the ICH6. These bits correspond to GPI that are in the core well, and will be reset to their default values by PLTRST#. 0 = The corresponding GPI_STS bit is set when the I CH6 detects the state of the input pin to be high. 1 = The corresponding GPI_STS bit is set when the I CH6 detects the state of the input pin to be low. 11:8 GP_INV[n] — R/W. These bits are used to allow both active-low and active-high inputs to cause SMI# or SCI. Note that in the S0 or S1 state, the input signal must be active for at least two PCI clocks to ensure detection by the ICH6. In the S3, S4 or S5 states the input signal must be active for at least 2 RTC clocks to ensure detection. The setting of these bits has no effect if the corresponding GPIO is programmed as an output. These bits correspond to GPI that are in the resume well, and will be reset to their default values by RSMRST# or by a write to the CF9h register. 0 = The corresponding GPI_STS bit is set when the I CH6 detects the state of the input pin to be high. 1 = The corresponding GPI_STS bit is set when the I CH6 detects the state of the input pin to be low. 7:0 GP_INV[n] — R/W. These bits are used to allow both active-low and active-high inputs to cause SMI# or SCI. Note that in the S0 or S1 state, the input signal must be active for at least two PCI clocks to ensure detection by the ICH6. The setting of these bits will have no effect if the corresponding GPIO is programmed as an output. These bits correspond to GPI that are in the core well, and will be reset to their default values by PLTRST#. 0 = The corresponding GPI_STS bit is set when the I CH6 detects the state of the input pin to be high. 1 = The corresponding GPI_STS bit is set when the I CH6 detects the state of the input pin to be low.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 435 LPC Interface Bridge Registers (D31:F0)

10.10.7 GPIO_USE_SEL2—GPIO Use Select 2 Register[63:32]

Offset Address: GPIO BASE +30h Attribute: R/W Default Value: 00000006h Size: 32-bit Lockable: No Power Well: Processor I/O for 17, Core for 16:0

10.10.8 GP_IO_SEL2—GPIO Input/ Output Select 2 Register[63:32]

Offset Address: GPIO BASE +34h Attribute: R/W Default Value: 00000300h Size: 32-bit Lockable: No Power Well: Core Bit Description 17, 9:8 GPIO_USE_SEL2[49, 41:40] — R/W. Each bit in this register enables the corresponding GPIO (if it exists) to be used as a GPIO, rather than for the native function. 0 = Signal used as native function. 1 = Signal used as a GPIO. After a full reset (RSMRST#) all multiplexed signals in the resume and core wells are configured as a GPIO rather than as their native function. After just a PLTRST#, the GPIO in the core well are configured as GPIO. NOTES: 1. The following bits are not implemented because there is no corresponding GPIO: 3:7, 10:15, 18:31. 2. The following bits are always 1 because they are unmultiplexed: 1:2 3. Bit 16 is not implemented because the GPIO selection will be controlled by Bit 8 (REQ/GNT pair) 4. If GPIO[n] does not exist, then the bit in this register will always read as 0 and writes will have no effect. 5. The following bits are not implemented because they are determined by the Desktop/Mobile configuration: 0 Bit Description 31:18 Always 0. No corresponding GPIO. 17:16 Always 0. Outputs. 15:10 Always 0. No corresponding GPIO. 9:8 Always 0. Inputs. 7:3 Always 0. No corresponding GPIO. 2:0 GP_IO_SEL2[34:32] — R/W. 0 = GPIO signal is programmed as an output. 1 = Corresponding GPIO signal (if enabled in the GP IO_USE_SEL2 register) is programmed as an input.

436 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

LPC Interface Bridge Registers (D31:F0)

10.10.9 GP_LVL2—GPIO Level for In put or Output 2 Register[63:32]

Offset Address: GPIOB ASE +38h Attribute: R/W Default Value: 00030207h Size: 32-bit Lockable: No Power Well: See below Bit Description 31:18 Reserved. Read-only 0 17:16 GP_LVL[49:48] — R/W. The corresponding GP_LVL[n] bit can be updated by software to drive a high or low value on the output pin. Since these bits correspond to GPIO that are in the processor I/ O and core well, respectively, these bits will be reset by PLTRST#. 0 = low 1 = high 15:10 Reserved. Read-only 0 9:8 GP_LVL[41:40] — R/W. The corresponding GP_LVL[n] bit re flects the state of the input signal. Writes will have no effect. Since these bits correspond to GPIO that are in the core well, these bits will be reset by PLTRST#. 0 = low 1 = high 7:3 Reserved. Read-only 0 2:0 GP_LVL[34:32] — R/W. If GPIOn is programmed to be an output (via the corresponding bit in the GP_IO_SEL register), then the corresponding GP_LVL[n] bit can be updated by software to drive a high or low value on the output pin. If GPIOn is programmed as an input, then the corresponding GP_LVL bit reflects the state of the input signal (1 = high, 0 = low). Writes will have no effect. 0 = low 1 = high Since these bits correspond to GPIO that are in the core well, these bits will be reset by PLTRST#.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 437 IDE Controller Registers (D31:F1)

11 IDE Controller Registers (D31:F1)

11.1 PCI Configuration Registers (IDE—D31:F1)

Note: Address locations that are not shown should be treated as Reserved (See Section 6.2 for details). All of the IDE registers are in the core well. None of the registers can be locked. NOTE: The ICH6 IDE controller is not arbitrated as a PCI device; therefore, it does not need a master latency Table 11-1. IDE Controller PCI Register Address Map (IDE-D31:F1) Offset Mnemonic Register Name Default Type 00–01h VID Vendor Identification 8086h RO 02–03h DID Device Identification 266Fh RO 04–05h PCICMD PCI Command 00h R/W, RO 06–07h PCISTS PCI Status 0280h R/W, RO 08h RID Revision Identification See register description. RO 09h PI Programming Interface 8Ah R/W, RO 0Ah SCC Sub Class Code 01h RO 0Bh BCC Base Class Code 01h RO 0Ch CLS Cache Line Size 00h RO 0Dh PMLT Primary Master Latency Timer 00h RO 10–13h PCMD_BAR Primary Command Block Base Address 00000001h R/W, RO 14–17h PCNL_BAR Primary Control Block Base Address 00000001h R/W, RO 18–1Bh SCMD_BAR Secondary Command Block Base Address 00000001h R/W, RO 1C–1Fh SCNL_BAR Secondary Control Block Base Address 00000001h R/W, RO 20–23h BM_BASE Bus Master Base Address 00000001h R/W, RO 2C–2Dh IDE_SVID Subsystem Vendor ID 00h R/WO 2E–2Fh IDE_SID Subsystem ID 0000h R/WO 3C INTR_LN Interrupt Line See register description. R/W 3D INTR_PN Interrupt Pin 01h RO 40–41h IDE_TIMP Primary IDE Timing 0000h R/W 42–43h IDE_TIMS Secondary IDE Timing 0000h R/W 44h SLV_IDETIM Slave IDE Timing 00h R/W 48h SDMA_CNT Synchronous DMA Control 00h R/W 4A–4Bh SDMA_TIM Synchronous DMA Timing 0000h R/W 54h IDE_CONFIG IDE I/O Configuration 00000000h R/W C0h ATC APM Trapping Control 00h R/W C4h ATS APM Trapping Status 00h R/WC

438 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

IDE Controller Registers (D31:F1) timer.

11.1.1 VID—Vendor Identification Register (IDE—D31:F1)

Offset Address: 00 –01h Attribute: RO Default Value: 8086h Size: 16-bit Lockable: No Power Well: Core

11.1.2 DID—Device Identifi cation Register (IDE—D31:F1)

Offset Address: 02 –03h Attribute: RO Default Value: 266Fh Size: 16-bit Lockable: No Power Well: Core Bit Description 15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h Bit Description 15:0 Device ID — RO. This is a 16-bit value assigned to the ICH6 IDE controller.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 439 IDE Controller Registers (D31:F1)

11.1.3 PCICMD—PCI Command Register (IDE—D31:F1)

Address Offset: 04h –05h Attribute: RO, R/W Default Value: 00h Size: 16 bits Bit Description 15:11 Reserved Interrupt Disable (ID) — R/W. 0 = Enables the IDE controller to assert IN TA# (native mode) or IRQ14/15 (legacy mode). 1 = Disable. The interrupt will be de-asserted. 9 Fast Back to Back Enable (FBE) — RO. Reserved as 0. 8 SERR# Enable (SERR_EN) — RO. Reserved as 0. 7 Wait Cycle Control (WCC) — RO. Reserved as 0. 6 Parity Error Response (PER) — RO. Reserved as 0. 5 VGA Palette Snoop (VPS) — RO. Reserved as 0. 4 Postable Memory Write Enable (PMWE) — RO. Reserved as 0. 3 Special Cycle Enable (S CE) — RO. Reserved as 0. Bus Master Enable (BME) — R/W. Controls the ICH6’s ability to act as a PCI master for IDE Bus Master transfers. Memory Space Enable (MSE) — R/W. 0 = Disables access. 1 = Enables access to the IDE Expansion memory range. The EXBAR register (Offset 24h) must be programmed before this bit is set. NOTE: BIOS should set this bit to a 1. I/O Space Enable (IOSE) — R/W. This bit controls acce ss to the I/O space registers. 0 = Disables access to the Legacy or Native IDE ports (both Primary and Secondary) as well as the Bus Master I/O registers. 1 = Enable. Note that the Base Address regi ster for the Bus Master registers should be programmed before this bit is set. NOTES: 1. Separate bits are provided (IDE Decode Enable, in the IDE Timing register) to independently disable the Primary or Secondary I/O spaces. 2. When this bit is 0 and the IDE controller is in Native Mode, the Interrupt Pin Register (see Section 11.1.19) will be masked (the interrupt will not be asserted). If an interrupt occurs while the masking is in place and the interrupt is still active when the masking ends, the interrupt will be allowed to be asserted.

440 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

IDE Controller Registers (D31:F1)

11.1.4 PCISTS — PCI Stat us Register (IDE—D31:F1)

Address Offset: 06 –07h Attribute: R/WC, RO Default Value: 0280h Size: 16 bits Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no effect. Bit Description 15 Detected Parity Error (DPE) — RO. Reserved as 0. 14 Signaled System Error (SSE) — RO. Reserved as 0. Received Master Abort (RMA) — R/WC. 0 = Master abort Not generated by Bus Master IDE interface function. 1 = Bus Master IDE interface function, as a master, generated a master abort. 12 Reserved as 0 — RO. 11 Reserved as 0 — RO. 10:9 DEVSEL# Timing Status (DEV_STS) — RO. 01 = Hardwired; however, the ICH6 does not have a real DEVSEL# signal associated with the IDE unit, so these bits have no effect. 8 Data Parity Error Detected (DPED) — RO. Reserved as 0. 7 Fast Back to Back Capable (FB2BC) — RO. Reserved as 1. 6 User Definable Features (UDF) — RO. Reserved as 0. 5 66MHz Capable (66MHZ_CAP) — RO. Reserved as 0. Interrupt Status (INTS) — RO . This bit is independent of the state of the Interrupt Disable bit in the command register. 0 = Interrupt is cleared. 1 = Interrupt/MSI is asserted. NOTE: This bit will read ‘1’ after Power On Reset when no parallel ATA drive is attached. This is the intended behavior. 2:0 Reserved

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 441 IDE Controller Registers (D31:F1)

11.1.5 RID—Revision Identifi cation Register (IDE—D31:F1)

Offset Address: 08h Attribute: RO Default Value: See bit description Size: 8 bits

11.1.6 PI—Programming Inter face Register (IDE—D31:F1)

Address Offset: 09h Attribute: RO, R/W Default Value: 8Ah Size: 8 bits

11.1.7 SCC—Sub Class Code Register (IDE—D31:F1)

Address Offset: 0Ah Attribute: RO Default Value: 01h Size: 8 bits Bit Description 7:0 Revision ID — RO. Refer to the Intel® I/O Controller Hub 6 (ICH6) Family Specification Update for the value of the Revision ID Register Bit Description

7 This read-only bit is a 1 to indicate that the ICH6 supports bus master operation

6:4 Reserved. Hardwired to 000b. 3 SOP_MODE_CAP — RO. This read-only bit is a 1 to indica te that the secondary controller supports both legacy and native modes. SOP_MODE_SEL — R/W. This read/write bit determines the mode that the secondary IDE channel is operating in. 0 = Legacy-PCI mode (default) 1 = Native-PCI mode 1 POP_MODE_CAP — RO. This read-only bit is a 1 to indica te that the primary controller supports both legacy and native modes. POP_MODE_SEL — R/W. This read/write bits determines the mode that the primary IDE channel is operating in. 0 = Legacy-PCI mode (default) 1 = Native-PCI mode Bit Description 7:0 Sub Class Code (SCC) — RO. 01h = IDE device, in the context of a mass storage device.

442 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

IDE Controller Registers (D31:F1)

11.1.8 BCC—Base Class Code Register (IDE—D31:F1)

Address Offset: 0Bh Attribute: RO Default Value: 01h Size: 8 bits

11.1.9 CLS—Cache Line Size Register (IDE—D31:F1)

Address Offset: 0Ch Attribute: RO Default Value: 00h Size: 8 bits

11.1.10 PMLT—Primary Master Latency Timer Register

(IDE—D31:F1) Address Offset: 0Dh Attribute: RO Default Value: 00h Size: 8 bits

11.1.11 PCMD_BAR—Primary Command Block Base Address

Register (IDE—D31:F1) Address Offset: 10h –13h Attribute: R/W, RO Default Value: 00000001h Size: 32 bits NOTE: This 8-byte I/O space is used in native mode for the Primary Controller’s Command Block. Bit Description 7:0 Base Class Code (BCC) — RO. 01 = Mass storage device Bit Description 7:0 Cache Line Size (CLS) — RO. 00h = Hardwired. The IDE controller is implemented internally so this register has no meaning. Bit Description 7:0 Master Latency Timer Count (MLTC) — RO. 00h = Hardwired. The IDE controller is implemented internally, and is not arbitrated as a PCI device, so it does not need a Master Latency Timer. Bit Description 31:16 Reserved 15:3 Base Address — R/W. Base address of the I/O sp ace (8 consecutive I/O locations). 2:1 Reserved 0 Resource Type Indicator (RTE) — RO. Hardwired to 1 indicating a request for I/O space.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 443 IDE Controller Registers (D31:F1)

11.1.12 PCNL_BAR—Primary Co ntrol Block Base Address

Register (IDE—D31:F1) Address Offset: 14h –17h Attribute: R/W, RO Default Value: 00000001h Size: 32 bits NOTE: This 4-byte I/O space is used in native mode for the Primary Controller’s Command Block.

11.1.13 SCMD_BAR—Secondary Command Block Base Address

Register (IDE D31:F1) Address Offset: 18h –1Bh Attribute: R/W, RO Default Value: 00000001h Size: 32 bits NOTE: This 4-byte I/O space is used in native mode for the Secondary Controller’s Command Block.

11.1.14 SCNL_BAR—Secondary Control Block Base Address

Register (IDE D31:F1) Address Offset: 1Ch –1Fh Attribute: R/W, RO Default Value: 00000001h Size: 32 bits NOTE: This 4-byte I/O space is used in native mode for the Secondary Controller’s Command Block. Bit Description 31:16 Reserved 15:2 Base Address — R/W. Base address of the I/O sp ace (4 consecutive I/O locations).

0 Resource Type Indicator (RTE)

— RO. Hardwired to 1 indica ting a request for I/O space. Bit Description 31:16 Reserved 15:3 Base Address — R/W. Base address of the I/O sp ace (8 consecutive I/O locations). 2:1 Reserved 0 Resource Type Indicator (RTE) — RO. Hardwired to 1 indica ting a request for I/O space. Bit Description 31:16 Reserved 15:2 Base Address — R/W. Base address of the I/O sp ace (4 consecutive I/O locations). — RO. Hardwired to 1 indica ting a request for I/O space.

444 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

IDE Controller Registers (D31:F1)

11.1.15 BM_BASE — Bus Master Base Address Register

(IDE—D31:F1) Address Offset: 20h –23h Attribute: R/W, RO Default Value: 00000001h Size: 32 bits The Bus Master IDE interface function uses Base Address register 5 to request a 16-byte I/O space to provide a software interface to the Bus Master functions. Only 12 bytes are actually used (6 bytes for primary, 6 bytes for secondary). Only bits [15:4] are used to decode the address.

11.1.16 IDE_SVID — Subsystem Vendor Identification

(IDE—D31:F1) Address Offset: 2Ch –2Dh Attribute: R/WO Default Value: 00h Size: 16 bits Lockable: No Power Well: Core

11.1.17 IDE_SID — Subsystem Identification Register

(IDE—D31:F1) Address Offset: 2Eh –2Fh Attribute: R/WO Default Value: 0000h Size: 16 bits Lockable: No Power Well: Core Bit Description 31:16 Reserved 15:4 Base Address — R/W. This field provides the base addre ss of the I/O space (16 consecutive I/O locations). 3:1 Reserved 0 Resource Type Indicator (RTE) — RO. Hardwired to 1 indicating a request for I/O space. Bit Description 15:0 Subsystem Vendor ID (SVID) — R/WO. The SVID register, in combination with the Subsystem ID (SID) register, enables the operating system (OS) to distinguish subsystems from each other. Software (BIOS) sets the value in this register. After that, the value can be read, but subsequent writes to this register have no effect. The value written to this register will also be readable via the corresponding SVID registers for the USB#1, USB#2, and SMBus functions. Bit Description 15:0 Subsystem ID (SID) — R/WO. The SID register, in combinati on with the SVID register, enables the operating system (OS) to distinguish subsystems from each other. Software (BIOS) sets the value in this register. After that, the value can be read, but subsequent writes to this register have no effect. The value written to this register will also be readable via the corresponding SID registers for the USB#1, USB#2, and SMBus functions.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 445 IDE Controller Registers (D31:F1)

11.1.18 INTR_LN—Interrupt Li ne Register (IDE—D31:F1)

Address Offset: 3Ch Attribute: R/W Default Value: 00h Size: 8 bits

11.1.19 INTR_PN—Interrupt Pin Register (IDE—D31:F1)

Address Offset: 3Dh Attribute: RO Default Value: See Register Description Size: 8 bits

11.1.20 IDE_TIMP — IDE Primary Timing Register (IDE—D31:F1)

Address Offset: 40 –41h Attribute: R/W Default Value: 0000h Size: 16 bits This register controls the timings driven on the IDE cable for PIO and 8237 style DMA transfers. It also controls operation of the buffer for PIO transfers. Bit Description 7:0 Interrupt Line (INT_LN) — R/W. This field is used to communicate to software the interrupt line that the interrupt pin is connected to. Bit Description 7:0 Interrupt Pin — RO. This field reflects the value of D31IP.PIP (Chipset Configuration Registers:Offset 3100h:bits 7:4). Bit Description IDE Decode Enable (IDE) — R/W. The IDE I/O Space Enable bit (D31:F1:04h, bit 0) in the Command register must be set in order for this bit to have any effect. 0 = Disable. 1 = Enables the ICH6 to decode the Comm and (1F0–1F7h) and Control (3F6h) Blocks. This bit also effects the memory decode range for IDE Expansion. Drive 1 Timing Register Enable (SITRE) — R/W. 0 = Use bits 13:12, 9:8 for both drive 0 and drive 1. 1 = Use bits 13:12, 9:8 for drive 0, and use the Slave IDE Timing register for drive 1 13:12 IORDY Sample Point (ISP) — R/W. The setting of these bits det ermine the number of PCI clocks between IDE IOR#/IOW# assertion and the first IORDY sample point. 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = Reserved 11:10 Reserved 9:8 Recovery Time (RCT) — R/W. The setting of these bits det ermines the minimum number of PCI clocks between the last IORDY sample point and the IOR#/IOW# strobe of the next cycle. 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clock

446 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

IDE Controller Registers (D31:F1) Drive 1 DMA Timing Enable (DTE1) — R/W. 0 = Disable. 1 = Enable the fast timing mode for DMA transfers only for this drive. PIO transfers to the IDE data port will run in compatible timing. Drive 1 Prefetch/Posting Enable (PPE1) — R/W. 0 = Disable. 1 = Enable Prefetch and posting to the IDE data port for this drive. Drive 1 IORDY Sample Point Enable (IE1) — R/W. 0 = Disable IORDY sampling for this drive. 1 = Enable IORDY sampling for this drive. Drive 1 Fast Timing Bank (TIME1) — R/W. 0 = Accesses to the data port will use compatible timings for this drive. 1 = When this bit = 1 and bit 14 = 0, accesses to the data port will use bits 13:12 for the IORDY sample point, and bits 9:8 for the recovery time. When this bit = 1 and bit 14 = 1, accesses to the data port will use the IORDY sample point and recover time specified in the slave IDE timing register. Drive 0 DMA Timing Enable (DTE0) — R/W. 0 = Disable 1 = Enable fast timing mode for DMA transfers only for this drive. PIO transfers to the IDE data port will run in compatible timing. Drive 0 Prefetch/Posting Enable (PPE0) — R/W. 0 = Disable prefetch and posting to the IDE data port for this drive. 1 = Enable prefetch and posting to the IDE data port for this drive. Drive 0 IORDY Sample Point Enable (IE0) — R/W. 0 = Disable IORDY sampling is disabled for this drive. 1 = Enable IORDY sampling for this drive. Drive 0 Fast Timing Bank (TIME0) — R/W. 0 = Accesses to the data port will use compatible timings for this drive. 1 = Accesses to the data port will use bits 13:12 for the IORDY sample point, and bits 9:8 for the recovery time Bit Description

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 447 IDE Controller Registers (D31:F1)

11.1.21 IDE_TIMS — IDE Secondary Timing Register

(IDE—D31:F1) Address Offset: 42 –43h Attribute: R/W Default Value: 0000h Size: 16 bits

11.1.22 SLV_IDETIM—Slave (Dri ve 1) IDE Timing Register

(IDE—D31:F1) Address Offset: 44h Attribute: R/W Default Value: 00h Size: 8 bits Bit Description IDE Decode Enable (IDE) — R/W. This bit enables/disables the Secondary decode. The IDE I/O Space Enable bit (D31:F1:04h, bit 0) in the Command register must be set in order for this bit to have any effect. Additionally, separate configuration bits are provided (in the IDE I/O Configuration register) to individually disable the secondary IDE interface signals, even if the IDE Decode Enable bit is set. 0 = Disable. 1 = Enables the ICH6 to decode the associ ated Command Blocks (170–177h) and Control Block (376h). Accesses to these ranges return 00h, as the secondary channel is not implemented. 14:12 No Operation (NOP) — R/W. These bits are read/write for l egacy software compatibility, but have no functionality in the ICH6 since a secondary channel does not exist. 10:0 No Operation (NOP) — R/W. These bits are read/write for l egacy software compatibility, but have no functionality in the ICH6 since a secondary channel does not exist. Bit Description 7:4 No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility, but have no functionality in the ICH6. 3:2 Primary Drive 1 IORDY Sample Point (PISP1) — R/W. This field determines the number of PCI clocks between IOR#/IOW# assertion and the first IORDY sample point, if the access is to drive 1 data port and bit 14 of the IDE timing register for primary is set. 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = Reserved 1:0 Primary Drive 1 Recovery Time (PRCT1) — R/W. This field determines the minimum number of PCI clocks between the last IORDY sample point and the IOR#/IOW# strobe of the next cycle, if the access is to drive 1 data port and bit 14 of the IDE timing register for primary is set. 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clocks

448 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

IDE Controller Registers (D31:F1)

11.1.23 SDMA_CNT—Synchronous DMA Control Register

(IDE—D31:F1) Address Offset: 48h Attribute: R/W Default Value: 00h Size: 8 bits Bit Description 7:4 Reserved 3:2 No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility, but have no functionality in the ICH6. Primary Drive 1 Synchronous DMA Mode Enable (PSDE1) — R/W. 0 = Disable (default) 1 = Enable Synchronous DMA mode for primary channel drive 1. Primary Drive 0 Synchronous DMA Mode Enable (PSDE0) — R/W. 0 = Disable (default) 1 = Enable Synchronous DMA mode for primary channel drive 0.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 449 IDE Controller Registers (D31:F1)

11.1.24 SDMA_TIM—Synchronous DMA Timing Register

(IDE—D31:F1) Address Offset: 4A –4Bh Attribute: R/W Default Value: 0000h Size: 16 bits Note: For FAST_PCB1 = 1 (133 MHz clk) in bits [13:12, 9:8, 5:4, 1:0], refer to Section 5.16.4 for details. Bit Description 15:14 Reserved 13:12 No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility, but have no functionality in the ICH6. 11:10 Reserved 9:8 No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility, but have no functionality in the ICH6. 7:6 Reserved 5:4 Primary Drive 1 Cycle Time (PCT1) — R/W. For Ultra ATA mode, the setting of these bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also determined by the setting of these bits. 3:2 Reserved 1:0 Primary Drive 0 Cycle Time (PCT0) — R/W. For Ultra ATA mode, the setting of these bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also determined by the setting of these bits. PCB1 = 0 (33 MHz clk) PCB1 = 1 (66 MHz clk) FAST_PCB1 = 1 (133 MHz clk) 00 = CT 4 clocks, RP 6 clocks 00 = Reserved 00 = Reserved 01 = CT 3 clocks, RP 5 clocks 01 = CT 3 clocks , RP 8 clocks 01 = CT 3 clocks, RP 16 clocks 10 = CT 2 clocks, RP 4 clocks 10 = CT 2 clocks, RP 8 clocks 10 = Reserved 11 = Reserved 11 = Reserved 11 = Reserved PCB1 = 0 (33 MHz clk) PCB1 = 1 (66 MHz clk) FAST_PCB1 = 1 (133 MHz clk) 00 = CT 4 clocks, RP 6 clocks 00 = Reserved 00 = Reserved 01 = CT 3 clocks, RP 5 clocks 01 = CT 3 clocks , RP 8 clocks 01 = CT 3 clocks, RP 16 clocks 10 = CT 2 clocks, RP 4 clocks 10 = CT 2 clocks, RP 8 clocks 10 = Reserved 11 = Reserved 11 = Reserved 11 = Reserved

450 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

IDE Controller Registers (D31:F1)

11.1.25 IDE_CONFIG—IDE I/O Configuration Register

(IDE—D31:F1) Address Offset: 54h Attribute: R/W Default Value: 00000000h Size: 32 bits Bit Description 31:24 Reserved 23:20 Miscellaneous Scratchpad (MS) — R/W. Previously defined as a sc ratchpad bit to indicate to a driver that ATA-100 is supported. This is not used by software as all they needed to know was located in bits 7:4. See the definition of those bits. 19:18 No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility, but have no functionality in the ICH6. 17:16 SIG_MODE — R/W. These bits are used to control mode of the IDE signal pins for swap bay support. If the PRS bit (Chipset Configuration Registers:Offset 3414h:bit 1) is 1, the reset states of bits 17:16 will be 01 (tri-state) instead of 00 (normal). 00 = Normal (Enabled) 01 = Tri-state (Disabled) 10 = Drive low (Disabled) 11 = Reserved 15:14 No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility, but have no functionality in the ICH6. Fast Primary Drive 1 Base Clock (FAST_PCB1) — R/W. This bit is used in conjunction with the PCT1 bits to enable/disable Ultra ATA/100 timings for the Primary Slave drive. 0 = Disable Ultra ATA/100 timing for the Primary Slave drive. 1 = Enable Ultra ATA/100 timing for the Primary Sl ave drive (overrides bit 1 in this register). Fast Primary Drive 0 Base Clock (FAST_PCB0) — R/W. This bit is used in conjunction with the PCT0 bits to enable/disable Ultra ATA/100 timings for the Primary Master drive. 0 = Disable Ultra ATA/100 timing for the Primary Master drive. 1 = Enable Ultra ATA/100 timing for the Primary Mast er drive (overrides bit 0 in this register). 11:8 Reserved 7 No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility, but have no functionality in the ICH6. 6 No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility, but have no functionality in the ICH6. Primary Slave Channel Cable Reporting — R/W. BIOS should program this bit to tell the IDE driver which cable is plugged into the channel. 0 = 40 conductor cable is present. 1 = 80 conductor cable is present. 4 Primary Master Channel Cable Reporting — R/W. Same description as bit 5 3:2 No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility, but have no functionality in the ICH6. Primary Drive 1 Base Clock (PCB1) — R/W. 0 = 33 MHz base clock fo r Ultra ATA timings. 1 = 66 MHz base clock for Ultra ATA timings Primary Drive 0 Base Clock (PCB0) — R/W. 0 = 33 MHz base clock fo r Ultra ATA timings. 1 = 66 MHz base clock for Ultra ATA timings

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 451 IDE Controller Registers (D31:F1)

11.1.26 ATC—APM Trapping Co ntrol Register (IDE—D31:F1)

Address Offset: C0h Attribute: R/W Default Value: 00h Size: 8 bits

11.1.27 ATS—APM Trapping Status Register (IDE—D31:F1)

Address Offset: C4h Attribute: R/WC Default Value: 00h Size: 8 bits

11.2 Bus Master IDE I/O Registers (IDE—D31:F1)

The bus master IDE function uses 16 bytes of I/O space, allocated via the BMIBA register, located in Device 31:Function 1 Configuration space, offset 20h. All bus master IDE I/O space registers can be accessed as byte, word, or DWord quantities. Reading reserved bits returns an indeterminate, inconsistent value, and writes to reserved bits have no affect (but should not be attempted). The description of the I/O registers is shown in Table 11-2. Bit Description 7:2 Reserved 1 Slave Trap (PST) — R/W. This bit enables trapping and SM I# assertion on legacy I/O accesses to 1F0h–1F7h and 3F6h. The active device must be the slave device for the trap and/or SMI# to occur. 0 Master Trap (PMT) — R/W. This bit enables trapping and SMI# assertion on legacy I/O accesses to 1F0h–1F7h and 3F6h. The active device must be master device for the trap and/or SMI# to occur. Bit Description 7:2 Reserved 1 Slave Trap Status (PSTS) — R/WC. This bit indicates that a trap occurred to the slave device 0 Master Trap Status (PMTS) — R/WC. This bit indicates that a trap occurred to the master device Table 11-2. Bus Master IDE I/O Registers BMIBASE + Offset Mnemonic Register Name Default Type

00 BMICP Bus Master IDE Command Primary 00h R/W

01 — Reserved 00h RO

02 BMISP Bus Master IDE Status Primary 00h R/WC

03 — Reserved 00h RO 04–07 BMIDP Bus Master IDE Descriptor Table Pointer Primary xxxxxxxxh R/W

452 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

IDE Controller Registers (D31:F1)

11.2.1 BMICP—Bus Master IDE Command Register

(IDE—D31:F1) Address Offset: BMIBASE + 00h Attribute: R/W Default Value: 00h Size: 8 bits Bit Description 7:4 Reserved. Returns 0. Read / Write Control (RWC) — R/W. This bit sets the direction of the bus master transfer: This bit must NOT be changed when the bus master function is active. 0 = Memory reads 1 = Memory writes 2:1 Reserved. Returns 0. Start/Stop Bus Master (START) — R/W. 0 = All state information is lost when this bit is cleared. Master mode operation cannot be stopped and then resumed. If this bit is reset while bus master operation is still active (i.e., the Bus Master IDE Active bit (BMIBASE + 02h, bit 0) of the Bus Master IDE Status register for that IDE channel is set) and the drive has not yet finished its data transfer (the Interrupt bit (BMIBASE + 02h, bit 2) in the Bus Master IDE Status register for that IDE channel is not set), the bus master command is said to be aborted and data transferred from the drive may be discarded instead of being written to system memory. 1 = Enables bus master operation of the controll er. Bus master operation does not actually start unless the Bus Master Enable bit (D31:F1:04h, bit 2) in PCI configuration space is also set. Bus master operation begins when this bit is detected changing from 0 to 1. The controller will transfer data between the IDE device and memory only when this bit is set. Master operation can be halted by writing a 0 to this bit. NOTE: This bit is intended to be cleared by software after the data transfer is completed, as indicated by either the Bus Master IDE Active bit being cleared or the Interrupt bit of the Bus Master IDE Status register for that IDE channel being set, or both. Hardware does not clear this bit automatically.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 453 IDE Controller Registers (D31:F1)

11.2.2 BMISP—Bus Master IDE Status Register (IDE—D31:F1)

Address Offset: BMIB ASE + 02h Attribute: R/WC Default Value: 00h Size: 8 bits

11.2.3 BMIDP—Bus Master IDE Desc riptor Table Pointer Register

(IDE—D31:F1) Address Offset: BMIBASE + 04h Attribute: R/W Default Value: All bits undefined Size: 32 bits Bit Description PRD Interrupt Status (PRDIS) — R/WC. 0 = When this bit is cleared by so ftware, the interrupt is cleared. 1 = Set when the host controller completes execution of a PRD that has its Interrupt bit (bit 2 of this register) set. Drive 1 DMA Capable — R/W. 0 = Not Capable. 1 = Capable. Set by device dependent code (BIOS or devic e driver) to indicate that drive 1 for this channel is capable of DMA transfers, and that the controller has been initialized for optimum performance. The ICH6 does not use this bit. It is intended for systems that do not attach BMIDE to the PCI bus. Drive 0 DMA Capable — R/W. 0 = Not Capable 1 = Capable. Set by device dependent code (BIOS or devic e driver) to indicate that drive 0 for this channel is capable of DMA transfers, and that the controller has been initialized for optimum performance. The ICH6 does not use this bit. It is intended for systems that do not attach BMIDE to the PCI bus. 4:3 Reserved. Returns 0. Interrupt — R/WC. Software can use this bit to determine if an IDE device has asserted its interrupt line (IDEIRQ). 0 = Software clears this bit by writi ng a 1 to it. If this bit is cleared while the interrupt is still active, this bit will remain clear until another assertion edge is detected on the interrupt line. 1 = Set by the rising edge of the IDE interrupt line, regardless of whether or not the interrupt is masked in the 8259 or the internal I/O APIC. When this bit is read as 1, all data transferred from the drive is visible in system memory. Error — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set when the controller encounters a target abort or master abort when transferring data on PCI. Bus Master IDE Active (ACT) — RO. 0 = This bit is cleared by the ICH6 when the last transfer for a region is performed, where EOT for that region is set in the region descriptor. It is also cleared by the ICH6 when the Start bit is cleared in the Command register. When this bit is read as 0, all data transferred from the drive during the previous bus master command is visible in system memory, unless the bus master command was aborted. 1 = Set by the ICH6 when the Start bit is written to the Command register. Bit Description 31:2 Address of Descriptor Table (ADDR) — R/W. This field corresponds to A[31:2]. The Descriptor Table must be DWord-aligned. The Descriptor Table must not cross a 64-K boundary in memory. 1:0 Reserved

454 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

IDE Controller Registers (D31:F1)

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 455 SATA Controller Registers (D31:F2)

12 SATA Controller Registers

(D31:F2)

12.1 PCI Configuration Registers (SATA–D31:F2)

Note: Address locations that are not shown should be treated as Reserved. All of the SATA registers are in the core well. None of the registers can be locked. Table 12-1. SATA Controller PCI Register Address Map (SATA–D31:F2) (Sheet 1 of 2) Offset Mnemonic Register Name Default Type 00–01h VID Vendor Identification 8086h RO 02–03h DID Device Identification 2651h ICH6 2652h ICH6R 2653h ICH6-M RO 04–05h PCICMD PCI Command 0000h R/W, RO 06–07h PCISTS PCI Status 02B0h R/WC, RO 08h RID Revision Identification See register description. RO 09h PI Programming Interface See register description. See register

description

0Ah SCC Sub Class Code See register 0Bh BCC Base Class Code 01h RO 0Dh PMLT Primary Master Latency Timer 00h RO 10–13h PCMD_BAR Primary Command Block Base Address 00000001h R/W, RO 14–17h PCNL_BAR Primary Control Block Base Address 00000001h R/W, RO 18–1Bh SCMD_BAR Secondary Command Block Base Address 00000001h R/W, RO 1C–1Fh SCNL_BAR Secondary Control Block Base Address 00000001h R/W, RO 20–23h BAR Legacy Bus Master Base Address 00000001h R/W, RO 24–27h ABAR AHCI Base Address 00000000h See register 2C–2Dh SVID Subsystem Vendor Identification 0000h R/WO 2E–2Fh SID Subsystem Identification 0000h R/WO 34h CAP Capabilities Pointer 70h RO 3C INT_LN Interrupt Line 00h R/W 3D INT_PN Interrupt Pin See register description. RO 40–41h IDE_TIMP Primary IDE Timing 0000h R/W 42–43h IDE_TIMS Secondary IDE Timing 0000h R/W

456 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

SATA Controller Registers (D31:F2) NOTE: The ICH6 SATA controller is not arbitrated as a PCI device, therefore it does not need a master latency timer.

12.1.1 VID—Vendor Identificati on Register (SATA—D31:F2)

Offset Address: 00 –01h Attribute: RO Default Value: 8086h Size: 16 bit Lockable: No Power Well: Core 44h SIDETIM Slave IDE Timing 00h R/W 48h SDMA_CNT Synchronous DMA Control 00h R/W 4A–4Bh SDMA_TIM Synchronous DMA Timing 0000h R/W 54–57h IDE_CONFIG IDE I/O Configuration 00000000h R/W 70–71h PID PCI Power Management Capability ID 0001h RO 72–73h PC PCI Power Management Capabilities 4002h RO 74–75h PMCS PCI Power Management Control and Status 0000h R/W, RO, R/WC 90h MAP Address Map 00h R/W 92–93h PCS Port Control and Status 0000h R/W, RO, R/WC 94-97h SIR SATA Initialization Register 00000000h R/W A0h SIRI SATA Indexed Registers Index 00h R/W A4h STRD SATA Indexed Register Data XXXXXXXXh R/W C0h ATC APM Trapping Control 00h R/W C4 ATS ATM Trapping Status 00h R/WC D0–D3h SP Scratch Pad 00000000h R/W E0h– E3h BFCS BIST FIS Control/Status 00000000h R/W, R/WC E4h– E7h BFTD1 BIST FIS Transmit Data, DW1 00000000h R/W E8h– EBh BFTD2 BIST FIS Transmit Data, DW2 00000000h R/W Table 12-1. SATA Controller PCI Register Address Map (SATA–D31:F2) (Sheet 2 of 2) Offset Mnemonic Register Name Default Type Bit Description 15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 457 SATA Controller Registers (D31:F2)

12.1.2 DID—Device Identific ation Register (SATA—D31:F2)

Offset Address: 02 –03h Attribute: RO Default Value: ICH6: 2651h Size: 16 bit ICH6R: 2652h ICH6-M: 2653h Lockable: No Power Well: Core12.1.3 PCICMD—PCI Command Register (SATA–D31:F2) Address Offset: 04h –05h Attribute: RO, R/W Default Value: 0000h Size: 16 bits Bit Description 15:0 Device ID — RO. This is a 16-bit valu e assigned to the ICH6 SATA controller. Bit Description 15:11 Reserved Interrupt Disable — R/W. This bit disables pin-based INTx# interrupts. This bit has no effect on MSI operation. 0 = Internal INTx# messages are generated if there is an interrupt and MSI is not enabled. 1 = Internal INTx# messages will not be generated. 9 Fast Back to Back Enable (FBE) — RO. Reserved as 0. 8 SERR# Enable (SERR_EN) — RO. Reserved as 0. 7 Wait Cycle Control (WCC) — RO. Reserved as 0. Parity Error Response (PER) — R/W. 0 = Disabled. SATA controller will not generate PERR# when a data parity error is detected. 1 = Enabled. SATA controller will generate PERR# when a data parity error is detected. 5 VGA Palette Snoop (VPS) — RO. Reserved as 0. 4 Postable Memory Write Enable (PMWE) — RO. Reserved as 0. 3 Special Cycle Enable (SCE) — RO. Reserved as 0. Bus Master Enable (BME) — R/W. This bit controls the ICH6’s ability to act as a PCI master for IDE Bus Master transfers. This bit does not impact the generation of completions for split transaction commands. Memory Space Enable (MSE) — R/W / RO. This bit controls access to the SATA controller’s target memory space (for AHCI). (ICH6-M/ICH6R only) NOTE: When MAP .MV (offset 90:bits 1:0) is not 00h, this register is Read Only (RO). Software is responsible for clearing this bit before entering combined mode. For ICH6, this bit is RO ‘0’, unless the SCRAE bit (offset 94h:bit 9) is set. I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers. 0 = Disables access to the Legacy or Native IDE ports (both Primary and Secondary) as well as the Bus Master I/O registers. 1 = Enable. Note that the Base Address register for the Bus Master registers should be programmed before this bit is set.

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SATA Controller Registers (D31:F2)

12.1.4 PCISTS — PCI Status Register (SATA–D31:F2)

Address Offset: 06 –07h Attribute: R/WC, RO Default Value: 02B0h Size: 16 bits Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no effect.

12.1.5 RID—Revision Identifi cation Register (SATA—D31:F2)

Offset Address: 08h Attribute: RO Default Value: See bit description Size: 8 bits Bit Description Detected Parity Error (DPE) — R/WC. 0 = No parity error detected by SATA controller. 1 = SATA controller detects a parity error on its interface. 14 Signaled System Error (SSE) — RO. Reserved as 0. Received Master Abort (RMA) — R/WC. 0 = Master abort Not generated. 1 = SATA controller, as a master, generated a master abort. 12 Reserved as 0 — RO. 11 Signaled Target Abort (STA) — RO. Reserved as 0. 10:9 DEVSEL# Timing Status (DEV_STS) — RO. 01 = Hardwired; Controls the device select time for the SATA controller’s PCI interface. Data Parity Error Detected (DPED) — RO. For ICH6, this bit can only be set on read completions received from SiBUS where there is a parity error. 1 = SATA controller, as a master, either detects a parity error or sees the parity error line asserted, and the parity error response bit (bit 6 of the command register) is set. Fast Back to Back Capable (FB2BC) — RO. Reserved as 1. 6 User Definable Features (UDF) — RO. Reserved as 0. 5 66MHz Capable (66MHZ_CAP) — RO. Reserved as 1. Capabilities List (CAP_LIST) — RO. This bit indicates the presence of a capabilities list. The minimum requirement for the capabilities list must be PCI power management for the SATA controller. Interrupt Status (INTS) — RO. Reflects the state of INTx# messages. 0 = Interrupt is cleared (independent of the state of Interrupt Disable bit in the command register [offset 04h]). 1 = Interrupt is to be asserted 2:0 Reserved Bit Description 7:0 Revision ID — RO. Refer to the Intel® I/O Controller Hub 6 (ICH6) Family Specification Update for the value of the Revision ID Register

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 459 SATA Controller Registers (D31:F2)

12.1.6 PI—Programming Inter face Register (SATA–D31:F2)

12.1.6.1 When Sub Class Code Register (D31:F2:Offset 0Ah) = 01h

Address Offset: 09h Attribute: R/W, RO Default Value: See bit description Size: 8 bits

12.1.6.2 When Sub Class Code Register (D31:F2:Offset 0Ah) = 04h

Address Offset: 09h Attribute: RO Default Value: 00h Size: 8 bits Bit Description 6:4 Reserved. Will always return 0. Secondary Mode Native Capable (SNC) — RO. 0 = Secondary controller only supports legacy mode. 1 = Secondary controller supports both legacy and native modes. When MAP.MV (D31:F2:Offset 90:bits 1:0) is any value other than 00b, this bit reports as a 0. When MAP.MV is 00b, this bit reports as a 1. Secondary Mode Native Enable (SNE) — R/W / RO. This bit determines the mode that the secondary channel is operating in. 0 = Secondary controller operating in legacy (compatibility) mode 1 = Secondary controller operating in native PCI mode. When MAP .MV (D31:F2:Offset 90:bits 1:0) is any value other than 00b, this bit is read-only (RO). Software is responsible for clearing this bit before entering combined mode. When MAP.MV is 00b, this bit is read/write (R/W). If this bit is set by software, then the PNE bit (bit 0 of this register) must also be set by software. While in theory these bits can be programmed separately, such a configuration is not supported by hardware. Primary Mode Native Capable (PNC) — RO. 0 = Primary controller only supports legacy mode. 1 = Primary controller suppor ts both legacy and native modes. When MAP.MV (D31:F2:Offset 90:bits 1:0) is any value other than 00b, this bit reports as a 0. When MAP.MV is 00b, this bit reports as a 1 Primary Mode Native Enable (PNE) — R/W / RO. This bit determines the mode that the primary channel is operating in. 0 = Primary controller operating in legacy (compatibility) mode. 1 = Primary controller operating in native PCI mode. When MAP .MV (D31:F2:Offset 90:bits 1:0) is any value other than 00b, this bit is read-only (RO). Software is responsible for clearing this bit before entering combined mode. When MAP.MV is 00b, this bit is read/write (R/W). If this bit is set by software, then the SNE bit (bit 2 of this register) must also be set by software. While in theory these bits can be programmed separately, such a configuration is not supported by hardware. Bit Description 7:0 Interface (IF) — RO. When configured as RAID, this register becomes read only 0.

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SATA Controller Registers (D31:F2)

12.1.6.3 When Sub Class Code Regist er (D31:F2:Offset 0Ah) = 06h

Address Offset: 09h Attribute: RO Default Value: 01h Size: 8 bits

12.1.7 SCC—Sub Class Code Register (SATA–D31:F2)

Address Offset: 0Ah Attribute: See bit description Default Value: See bit description Size: 8 bits

12.1.8 BCC—Base Class Code Register

(SATA–D31:F2SATA–D31:F2) Address Offset: 0Bh Attribute: RO Default Value: 01h Size: 8 bits Bit Description 7:0 Interface (IF) — RO. This field indicates the SATA Controller supports AHCI, rev 1.0. Bit Description 7:0 Sub Class Code (SCC). This field specifies the sub-class code of the controller, per the table below: Intel® ICH6 Only: ICH6-M Only: ICH6R Only: SCC Register Attribute Scc Register Value RO 01h (IDE Controller) MAP.USCC (D31:F2:Offset 90h:bit 7) SCC Register Attribute SCC Register Value 0b RO 01h (IDE Controller) 1b RO 06h (SATA Controller) MAP.USCC (D31:F2:Offset 90h:bit 7) SCC Register Attribute SCC Default Register Value X R/WO 04h (RAID Controller) Bit Description 7:0 Base Class Code (BCC) — RO. 01h = Mass storage device

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 461 SATA Controller Registers (D31:F2)

12.1.9 PMLT—Primary Master Latency Timer Register

(SATA–D31:F2) Address Offset: 0Dh Attribute: RO Default Value: 00h Size: 8 bits

12.1.10 PCMD_BAR—Primary Co mmand Block Base Address

Register (SATA–D31:F2) Address Offset: 10h –13h Attribute: R/W, RO Default Value: 00000001h Size: 32 bits NOTE: This 8-byte I/O space is used in native mode for the Primary Controller’s Command Block.

12.1.11 PCNL_BAR—Primary Contro l Block Base Address Register

(SATA–D31:F2) Address Offset: 14h –17h Attribute: R/W, RO Default Value: 00000001h Size: 32 bits NOTE: This 4-byte I/O space is used in native mode for the Primary Controller’s Command Block. Bit Description 7:0 Master Latency Timer Count (MLTC) — RO. The SATA controller is implemented internally, and is not arbitrated as a PCI device, so it does not need a Master Latency Timer. 00h = Hardwired. Bit Description 31:16 Reserved 15:3 Base Address — R/W. This field provides the base address of the I/O space (8 consecutive I/O locations). 2:1 Reserved 0 Resource Type Indicator (RTE) — RO. Hardwired to 1 to indi cate a request for I/O space. Bit Description 31:16 Reserved 15:2 Base Address — R/W. This field provides the base address of the I/O space (4 consecutive I/O locations). 0 Resource Type Indicator (RTE) — RO. Hardwire d to 1 to indicate a request for I/O space.

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SATA Controller Registers (D31:F2)

12.1.12 SCMD_BAR—Secondary Command Block Base Address

Register (IDE D31:F1) Address Offset: 18h –1Bh Attribute: R/W, RO Default Value: 00000001h Size: 32 bits NOTE: This 4-byte I/O space is used in native mode for the Secondary Controller’s Command Block.

12.1.13 SCNL_BAR—Secondary Control Block Base Address

Register (IDE D31:F1) Address Offset: 1Ch –1Fh Attribute: R/W, RO Default Value: 00000001h Size: 32 bits NOTE: This 4-byte I/O space is used in native mode for the Secondary Controller’s Command Block.

12.1.14 BAR — Legacy Bus Mast er Base Address Register

(SATA–D31:F2) Address Offset: 20h –23h Attribute: R/W, RO Default Value: 00000001h Size: 32 bits The Bus Master IDE interface function uses Base Address register 5 to request a 16-byte I/O space to provide a software interface to the Bus Master functions. Only 12 bytes are actually used (6 bytes for primary, 6 bytes for secondary). Only bits [15:4] are used to decode the address. Bit Description 31:16 Reserved 15:3 Base Address — R/W. This field provides the base addre ss of the I/O space (8 consecutive I/O locations). 2:1 Reserved 0 Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O space. Bit Description 31:16 Reserved 15:2 Base Address — R/W. This field provides the base addre ss of the I/O space (4 consecutive I/O locations). 1R e s e r v e d 0 Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O space. Bit Description 31:16 Reserved 15:4 Base Address — R/W. This field provides the base addre ss of the I/O space (16 consecutive I/O locations). 3:1 Reserved 0 Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O space.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 463 SATA Controller Registers (D31:F2)

12.1.15 ABAR — AHCI Base Address Register

(SATA–D31:F2)

12.1.15.1 Intel ® ICH6 Only

Address Offset: 24h–27h Attribute: RO Default Value: 00000000h Size: 32 bits Note: For ICH6, this register is Reserved and Read Only, unless the SCRAE bit (offset 94h:bit 9) is set, in which case the register follows the definition given in Section 12.1.15.2.

12.1.15.2 Intel ® ICH6R / ICH6-M Only

Address Offset: 24h –27h Attribute: R/W, RO Default Value: 00000000h Size: 32 bits This register allocates space for the memory registers defined in Section 12.3. NOTES: 1. When the MAP.MV register is programmed for combined mode (00b), this register is RO. Software is responsible for clearing this bit before entering combined mode. 2. The ABAR register must be set to a value of 0001_0000h or greater.

12.1.16 SVID—Subsystem Vendor Identification Register

(SATA–D31:F2) Address Offset: 2Ch –2Dh Attribute: R/WO Default Value: 0000h Size: 16 bits Lockable: No Power Well: Core Bit Description 31:0 Reserved Bit Description 31:10 Base Address (BA) — R/W. Base address of register memory space (aligned to 1 KB) 9:4 Reserved 3 Prefetchable (PF) — RO. This bit indica tes that this range is not pre-fetchable 2:1 Type (TP) — RO. This bit indicates that this range can be mapped anywhere in 32-bit address space. 0 Resource Type Indicator (RTE) — RO. Hardwired to 0 to indicate a request for register memory space. Bit Description 15:0 Subsystem Vendor ID (SVID) — R/WO. Value is written by BIOS . No hardware action taken on this value.

464 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

SATA Controller Registers (D31:F2)

12.1.17 SID—Subsystem Identifi cation Register (SATA–D31:F2)

Address Offset: 2Eh –2Fh Attribute: R/WO Default Value: 0000h Size: 16 bits Lockable: No Power Well: Core12.1.18 CAP—Capabilities Poin ter Register (SATA–D31:F2) Address Offset: 34h Attribute: RO Default Value: 70h Size: 8 bits

12.1.19 INT_LN—Interrupt Line Register (SATA–D31:F2)

Address Offset: 3Ch Attribute: R/W Default Value: 00h Size: 8 bits

12.1.20 INT_PN—Interrupt Pi n Register (SATA–D31:F2)

Address Offset: 3Dh Attribute: RO Default Value: See Register Description Size: 8 bits Bit Description 15:0 Subsystem ID (SID) — R/WO. Value is written by BIOS. No hardware action taken on this value. Bit Description 7:0 Capabilities Pointer (CAP_PTR) — RO. This field indi cates that the first capability pointer offset is 70h, the PCI Power Management capability. Bit Description 7:0 Interrupt Line — R/W. This field is used to communicate to software the interrupt line that the interrupt pin is connected to. Bit Description 7:0 Interrupt Pin — RO. This reflects the value of D31IP.SIP (Chipset Configuration Registers:Offset 3100h:bits 11:8).

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 465 SATA Controller Registers (D31:F2)

12.1.21 IDE_TIM — IDE Timing Register (SATA–D31:F2)

Address Offset: Primary: 40 –41h Attribute: R/W Secondary: 42–43h Default Value: 0000h Size: 16 bits This register controls the timings driven on the IDE cable for PIO and 8237 style DMA transfers. It also controls operation of the buffer for PIO transfers. Note: This register is R/W to maintain software compatibility and enable parallel ATA functionality when the PCI functions are combined. These bits have no effect on SATA operation unless otherwise noted. Bit Description IDE Decode Enable (IDE) — R/W. Individually enable/disabl e the Primary or Secondary decode. 0 = Disable. 1 = Enables the Intel ® ICH6 to decode the associated Command Blocks (1F0–1F7h for primary, 170–177h for secondary) and Control Block (3F6h for primary and 376h for secondary). This bit effects the IDE decode ranges for both legacy and native-Mode decoding. NOTE: This bit affects SATA operation in both combined and non-combined ATA modes. See Section 5.17 for more on ATA modes of operation. Drive 1 Timing Register Enable (SITRE) — R/W. 0 = Use bits 13:12, 9:8 for both drive 0 and drive 1. 1 = Use bits 13:12, 9:8 for drive 0, and us e the Slave IDE Timing register for drive 1 13:12 IORDY Sample Point (ISP) — R/W. The setting of these bits determines the number of PCI clocks between IDE IOR#/IOW# assertion and the first IORDY sample point. 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = Reserved 11:10 Reserved 9:8 Recovery Time (RCT) — R/W. The setting of these bits determines the minimum number of PCI clocks between the last IORDY sample point and the IOR#/IOW# strobe of the next cycle. 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clock Drive 1 DMA Timing Enable (DTE1) — R/W. 0 = Disable. 1 = Enable the fast timing mode for DMA transfers onl y for this drive. PIO transfers to the IDE data port will run in compatible timing. Drive 1 Prefetch/Posting Enable (PPE1) — R/W. 0 = Disable. 1 = Enable Prefetch and posting to the IDE data port for this drive. Drive 1 IORDY Sample Point Enable (IE1) — R/W. 0 = Disable IORDY sampling for this drive. 1 = Enable IORDY sampling for this drive.

466 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

SATA Controller Registers (D31:F2) Drive 1 Fast Timing Bank (TIME1) — R/W. 0 = Accesses to the data port will us e compatible timings for this drive. 1 = When this bit =1 and bit 14 = 0, accesses to the data port will use bits 13:12 for the IORDY sample point, and bits 9:8 for the recovery time. When this bit = 1 and bit 14 = 1, accesses to the data port will use the IORDY sample point and recover time specified in the slave IDE timing register. Drive 0 DMA Timing Enable (DTE0) — R/W. 0 = Disable 1 = Enable fast timing mode for DMA transfers only for this drive. PIO transfers to the IDE data port will run in compatible timing. Drive 0 Prefetch/Posting Enable (PPE0) — R/W. 0 = Disable prefetch and posting to the IDE data port for this drive. 1 = Enable prefetch and posting to the IDE data port for this drive. Drive 0 IORDY Sample Point Enable (IE0) — R/W. 0 = Disable IORDY sampling is disabled for this drive. 1 = Enable IORDY sampling for this drive. Drive 0 Fast Timing Bank (TIME0) — R/W. 0 = Accesses to the data port will us e compatible timings for this drive. 1 = Accesses to the data port will use bits 13:12 for the IORDY sample point, and bits 9:8 for the recovery time Bit Description

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 467 SATA Controller Registers (D31:F2)

12.1.22 SIDETIM—Slave IDE Ti ming Register (SATA–D31:F2)

Address Offset: 44h Attribute: R/W Default Value: 00h Size: 8 bits Note: This register is R/W to maintain software compatibility and enable parallel ATA functionality when the PCI functions are combined. These bits have no effect on SATA operation unless otherwise noted. Bit Description 7:6 Secondary Drive 1 IORDY Sample Point (SISP1) — R/W. This field determines the number of PCI clocks between IDE IOR#/IOW# assertion and the first IORDY sample point, if the access is to drive 1 data port and bit 14 of the IDE timing register for secondary is set. 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = Reserved 5:4 Secondary Drive 1 Recovery Time (SRCT1) — R/W. This field determines the minimum number of PCI clocks between the last IORDY sample point and the IOR#/IOW# strobe of the next cycle, if the access is to drive 1 data port and bit 14 of the IDE timing register for secondary is set. 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clocks 3:2 Primary Drive 1 IORDY Sample Point (PISP1) — R/W. This field determines the number of PCI clocks between IOR#/IOW# assertion and the first IORDY sample point, if the access is to drive 1 data port and bit 14 of the IDE timing register for primary is set. 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = Reserved 1:0 Primary Drive 1 Recovery Time (PRCT1) — R/W. This field determines the minimum number of PCI clocks between the last IORDY sample point and the IOR#/IOW# strobe of the next cycle, if the access is to drive 1 data port and bit 14 of the IDE timing register for primary is set. 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clocks

468 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

SATA Controller Registers (D31:F2)

12.1.23 SDMA_CNT—Synchronous DMA Control Register

(SATA–D31:F2) Address Offset: 48h Attribute: R/W Default Value: 00h Size: 8 bits Note: This register is R/W to maintain software compatibility and enable parallel ATA functionality when the PCI functions are combined. These bits have no effect on SATA operation unless otherwise noted. Bit Description 7:4 Reserved Secondary Drive 1 Synchronous DMA Mode Enable (SSDE1) — R/W. 0 = Disable (default) 1 = Enable Synchronous DMA mode for secondary channel drive 1 Secondary Drive 0 Synchronous DMA Mode Enable (SSDE0) — R/W. 0 = Disable (default) 1 = Enable Synchronous DMA mode for secondary drive 0. Primary Drive 1 Synchronous DMA Mode Enable (PSDE1) — R/W. 0 = Disable (default) 1 = Enable Synchronous DMA mode for primary channel drive 1 Primary Drive 0 Synchronous DMA Mode Enable (PSDE0) — R/W. 0 = Disable (default) 1 = Enable Synchronous DMA mode for primary channel drive 0

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 469 SATA Controller Registers (D31:F2)

12.1.24 SDMA_TIM—Synchronous DMA Timing Register

(SATA–D31:F2) Address Offset: 4A –4Bh Attribute: R/W Default Value: 0000h Size: 16 bits Note: This register is R/W to maintain software compatibility and enable parallel ATA functionality when the PCI functions are combined. These bits have no effect on SATA operation, unless otherwise noted. Bit Description 15:14 Reserved 13:12 Secondary Drive 1 Cycle Time (SCT1) — R/W. For Ultra ATA mode. The setting of these bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also determined by the setting of these bits. 11:10 Reserved 9:8 Secondary Drive 0 Cycle Time (SCT0) — R/W. For Ultra ATA mode. The setting of these bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also determined by the setting of these bits. 7:6 Reserved 5:4 Primary Drive 1 Cycle Time (PCT1) — R/W. For Ultra ATA mode, the setting of these bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also determined by the setting of these bits. 3:2 Reserved 1:0 Primary Drive 0 Cycle Time (PCT0) — R/W. For Ultra ATA mode, the setting of these bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also determined by the setting of these bits. SCB1 = 0 (33 MHz clk) SCB1 = 1 (66 MHz clk) FAST_SCB1 = 1 (133 MHz clk) 00 = CT 4 clocks, RP 6 clocks 00 = Reserved 00 = Reserved 01 = CT 3 clocks, RP 5 clocks 01 = CT 3 clocks , RP 8 clocks 01 = CT 3 clocks, RP 16 clocks 10 = CT 2 clocks, RP 4 clocks 10 = CT 2 clocks, RP 8 clocks 10 = Reserved 11 = Reserved 11 = Reserved 11 = Reserved SCB1 = 0 (33 MHz clk) SCB1 = 1 (66 MHz clk) FAST_SCB1 = 1 (133 MHz clk) 00 = CT 4 clocks, RP 6 clocks 00 = Reserved 00 = Reserved 01 = CT 3 clocks, RP 5 clocks 01 = CT 3 clocks , RP 8 clocks 01 = CT 3 clocks, RP 16 clocks 10 = CT 2 clocks, RP 4 clocks 10 = CT 2 clocks, RP 8 clocks 10 = Reserved 11 = Reserved 11 = Reserved 11 = Reserved PCB1 = 0 (33 MHz clk) PCB1 = 1 (66 MHz clk) FAST_PCB1 = 1 (133 MHz clk) 00 = CT 4 clocks, RP 6 clocks 00 = Reserved 00 = Reserved 01 = CT 3 clocks, RP 5 clocks 01 = CT 3 clocks , RP 8 clocks 01 = CT 3 clocks, RP 16 clocks 10 = CT 2 clocks, RP 4 clocks 10 = CT 2 clocks, RP 8 clocks 10 = Reserved 11 = Reserved 11 = Reserved 11 = Reserved PCB1 = 0 (33 MHz clk) PCB1 = 1 (66 MHz clk) FAST_PCB1 = 1 (133 MHz clk) 00 = CT 4 clocks, RP 6 clocks 00 = Reserved 00 = Reserved 01 = CT 3 clocks, RP 5 clocks 01 = CT 3 clocks , RP 8 clocks 01 = CT 3 clocks, RP 16 clocks 10 = CT 2 clocks, RP 4 clocks 10 = CT 2 clocks, RP 8 clocks 10 = Reserved 11 = Reserved 11 = Reserved 11 = Reserved

470 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

SATA Controller Registers (D31:F2)

12.1.25 IDE_CONFIG—IDE I/O Configuration Register

(SATA–D31:F2) Address Offset: 54h –57h Attribute: R/W Default Value: 00000000h Size: 32 bits Note: This register is R/W to maintain software compatibility and enable parallel ATA functionality when the PCI functions are combined. These bits have no effect on SATA operation, unless otherwise noted. Bit Description 31:24 Reserved 23:20 Scratchpad (SP2). Intel ® ICH6 does not perform any actions on these bits. 19:18 SEC_SIG_MODE — R/W. These bits are used to control mode of the Secondary IDE signal pins for swap bay support. If the SRS bit (Chipset Configuration Registers:Offset 3414h:bit 1) is 1, the reset states of bits 19:18 will be 01 (tri-state) instead of 00 (normal). 00 = Normal (Enabled) 01 = Tri-state (Disabled) 10 = Drive low (Disabled) 11 = Reserved 17:16 PRIM_SIG_MODE — R/W. These bits are used to control m ode of the Primary IDE signal pins for mobile swap bay support. If the PRS bit (Chipset Configuration Registers:Offset 3414h:bit 1) is 1, the reset states of bits 17:16 will be 01 (tri-state) instead of 00 (normal). 00 = Normal (Enabled) 01 = Tri-state (Disabled) 10 = Drive low (Disabled) 11 = Reserved Fast Secondary Drive 1 Base Clock (FAST_SCB1) — R/W. This bit is used in conjunction with the SCT1 bits (D31:F2:4Ah, bits 13:12) to enable/disable Ultra ATA/100 timings for the Secondary Slave drive. 0 = Disable Ultra ATA/100 timing for the Secondary Slave drive. 1 = Enable Ultra ATA/100 timing for t he Secondary Slave drive (overrides bit 3 in this register). Fast Secondary Drive 0 Base Clock (FAST_SCB0) — R/W. This bit is used in conjunction with the SCT0 bits (D31:F2:4Ah, bits 9:8) to enable/disable Ultra ATA/100 timings for the Secondary Master drive. 0 = Disable Ultra ATA/100 timing for the Secondary Master drive. 1 = Enable Ultra ATA/100 timing for t he Secondary Master drive (overrides bit 2 in this register). Fast Primary Drive 1 Base Clock (FAST_PCB1) — R/W. This bit is used in conjunction with the PCT1 bits (D31:F2:4Ah, bits 5:4) to enable/disable Ultra ATA/100 timings for the Primary Slave drive. 0 = Disable Ultra ATA/100 timing for the Primary Slave drive. 1 = Enable Ultra ATA/100 timing for the Primary Slav e drive (overrides bit 1 in this register). Fast Primary Drive 0 Base Clock (FAST_PCB0) — R/W. This bit is used in conjunction with the PCT0 bits (D31:F2:4Ah, bits 1:0) to enable/disable Ultra ATA/100 timings for the Primary Master drive. 0 = Disable Ultra ATA/100 timing for the Primary Master drive. 1 = Enable Ultra ATA/100 timing for the Primary Mast er drive (overrides bit 0 in this register). 11:8 Reserved 7:4 Scratchpad (SP1). ICH6 does not perform any action on these bits.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 471 SATA Controller Registers (D31:F2)

12.1.26 PID—PCI Power Manageme nt Capability Identification

Register (SATA–D31:F2) Address Offset: 70 –71h Attribute: RO Default Value: 0001h Size: 16 bits

12.1.27 PC—PCI Power Manageme nt Capabilities Register

(SATA–D31:F2) Address Offset: 72 –73h Attribute: RO Default Value: 4002h Size: 16 bits f Secondary Drive 1 Base Clock (SCB1) — R/W. 0 = 33 MHz base clock for Ultra ATA timings. 1 = 66 MHz base clock for Ultra ATA timings Secondary Drive 0 Base Clock (SCBO) — R/W. 0 = 33 MHz base clock for Ultra ATA timings. 1 = 66 MHz base clock for Ultra ATA timings Primary Drive 1 Base Clock (PCB1) — R/W. 0 = 33 MHz base clock for Ultra ATA timings. 1 = 66 MHz base clock for Ultra ATA timings Primary Drive 0 Base Clock (PCB0) — R/W. 0 = 33 MHz base clock for Ultra ATA timings. 1 = 66 MHz base clock for Ultra ATA timings Bit Description Bits Description 15:8 Next Capability (NEXT) — RO . Indicates that this is the last item in the list. 7:0 Capability ID (CID) — RO. Indicates that this pointer is a PCI power management. Bits Description 15:11 PME Support (PME_SUP) — RO. This field i ndicates PME# can be generated from the D3HOT state in the SATA host controller. 10 D2 Support (D2_SUP) — RO. Hardwired to 0. The D2 state is not supported 9 D1 Support (D1_SUP) — RO. Hardwired to 0. The D1 state is not supported 8:6 Auxiliary Current (AUX_CUR) — RO. PME# from D3 COLD state is not supported, therefore this field is 000b. 5 Device Specific Initialization (DSI) — RO. Hard wired to 0 to indicate that no device-specific initialization is required. 3 PME Clock (PME_CLK) — RO. Hardwired to 0 to indi cate that PCI clock is not required to generate PME#. 2:0 Version (VER) — RO. Hardwired to 010 to indica tes support for Revision 1.1 of the PCI Power Management Specification.

472 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

SATA Controller Registers (D31:F2)

12.1.28 PMCS—PCI Power Mana gement Control and Status

Register (SATA–D31:F2) Address Offset: 74 –75h Attribute: RO , R/W, R/WC Default Value: 0000h Size: 16 bits

12.1.29 MAP—Address Map Register (SATA–D31:F2)

Address Offset: 90h Attribute: R/W Default Value: 00h Size: 8 bits Bits Description 15 PME Status (PMES) — R/WC. Bit is set when a PME event is to be requested, and if this bit and PMEE is set, a PME# will be generated from the SATA controller 14:9 Reserved 8 PME Enable (PMEE) — R/W. When set, the SATA controller generates PME# form D3 HOT on a wake event. 7:2 Reserved 1:0 Power State (PS) — R/W. These bits are used both to determine the current power state of the SATA controller and to set a new power state. 00 = D0 state 11 = D3 HOT state When in the D3HOT state, the controller’s configuration space is available, but the I/O and memory spaces are not. Additionally, interrupts are blocked. Bits Description Use SATA Class Code (USCC) — R/W. ICH6 / ICH6R Only: Reserved. Software must not set this bit. ICH6-M Only: 0 =Subclass code reported in SCC (D31:F2:Offset 0Ah) is 01h (IDE Controller). 1 =Subclass code reported in SCC is 06h (SATA controller). 6:2 Reserved. 1:0 Map Value — R/W. Map Value (MV): The value in the bits below indicate the address range the SATA ports responds to, and whether or not the PATA and SATA functions are combined. When in combined mode, the AHCI memory space is not available and AHCI may not be used. 00 = Non-combined. P0 is primary master, P2 is the primary slave. P1 is secondary master, P3 is the secondary slave (desktop only). P0 is primary master, P2 is the primary slave (mobile only). 01 = Combined. IDE is primary. P1 is secondary master, P3 is the secondary slave. (desktop only) 10 = Combined. P0 is primary master. P2 is primary slave. IDE is secondary 11 = Reserved

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 473 SATA Controller Registers (D31:F2)

12.1.30 PCS—Port Control and St atus Register (SATA–D31:F2)

Address Offset: 92h –93h Attribute: R/W, R/WC, RO Default Value: 0000h Size: 16 bits This register is only used in systems that do not support AHCI. In AHCI enabled systems, bits[3:0] must always be set (ICH6R only) / bits[2,0] must always be set (ICH6-M only), and the status of the port is controlled through AHCI memory space. Bits Description 15:8 Reserved. (Desktop Only) Port 3 Present (P3P) — RO. The status of this bit may change at any time. This bit is cleared when the port is disabled via P3E. This bit is not cleared upon surprise removal of a device. 0 = No device detected. 1 = The presence of a device on Port 3 has been detected. (Mobile Only) Reserved Port 2 Present (P2P) — RO. The status of this bit may change at any time. This bit is cleared when the port is disabled via P2E. This bit is not cleared upon surprise removal of a device. 0 = No device detected. 1 = The presence of a device on Port 2 has been detected. (Desktop Only) Port 1 Present (P1P) — RO. The status of this bit may change at any time. This bit is cleared when the port is disabled via P1E. This bit is not cleared upon surprise removal of a device. 0 = No device detected. 1 = The presence of a device on Port 1 has been detected. (Mobile Only) Reserved Port 0 Present (P0P) — RO. The status of this bit may change at any time. This bit is cleared when the port is disabled via P0E. This bit is not cleared upon surprise removal of a device. 0 = No device detected. 1 = The presence of a device on Port 0 has been detected. (Desktop Only) Port 3 Enabled (P3E) — R/W. 0 = Disabled. The port is in the ‘off’ state and cannot detect any devices. 1 = Enabled. The port can transition between the on, partial, and slumber states and can detect devices. NOTE: This bit takes precedence over P3CMD.SUD (offset ABAR+298h:bit 1) (Mobile Only) Reserved Port 2 Enabled (P2E) — R/W. 0 = Disabled. The port is in the ‘off’ state and cannot detect any devices. 1 = Enabled. The port can transition between the on, partial, and slumber states and can detect devices. NOTE: This bit takes precedence over P2CMD.SUD (offset ABAR+218h:bit 1) (Desktop Only) Port 1 Enabled (P1E) — R/W. 0 = Disabled. The port is in the ‘off’ state and cannot detect any devices. 1 = Enabled. The port can transition between the on, partial, and slumber states and can detect devices. NOTE: This bit takes precedence over P1CMD.SUD (offset ABAR+198h:bit 1)

474 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

SATA Controller Registers (D31:F2)

12.1.31 SIR - SATA Initialization Register

Address Offset: 94h Attribute: R/W Default Value: 00000000h Size: 32 bits (Mobile Only) Reserved Port 0 Enabled (P0E) — R/W. 0 = Disabled. The port is in the ‘off’ state and cannot detect any devices. 1 = Enabled. The port can transition between the on, partial, and slumber states and can detect devices. NOTE: This bit takes precedence over P0CMD.SUD (offset ABAR+118h:bit 1) Bits Description Bit Description 31:28 Reserved 27:24 (Desktop Only) Reserved 27:24 (Mobile Only) SATA Initialization Field 3 (SIF3) — R/W. BIOS shall always program this field to the value 0Ah. All other values are reserved. 23 SATA Initialization Field 2 (SIF2) — R/W. BIOS shall always program this register to the value 1b. All other values are reserved. 22:10 Reserved SCR Access Enable (SCRAE) — R/W. In non-AHCI mode, this bi t allows access to the SATA SCR registers (SStatus, SControl, and SError registers). 0 = The ABAR (Dev31:F2:Offset 24h) register and MSE bit field (Dev31:F2:Offset 04h:bit 1) remain as defined. 1 = The ABAR (Dev31:F2:Offset 24h) register and MSE bit field (Dev31:F2:Offset 04h:bit 1) are forced to be read/write. NOTES: 1. Using this mode only allows access to AHCI registers PxSSTS, PxSCRTL, PxSERR. All other AHCI space is reserved when this bit is set. 2. Proper use of this bit requires:

• ABAR must be programmed to a valid BAR; MSE must be set before software can access AHCI space.
• The Port Implemented bit (D31:F2, Offset ABAR+0Ch) for the corresponding port has to be set to allow access to the AHCI port specific PxSSTS, PxSCRTL, and PxSERR registers. 8:0 SATA Initialization Field 1 (SIF1) — R/W. BIOS shall always program this register to the value 182h. All other values are reserved.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 475 SATA Controller Registers (D31:F2)

12.1.32 SIRI—SATA Indexed Registers Index

Address Offset: A0h Attribute: R/W Default Value: 00h Size: 8 bits

12.1.33 STRD—SATA Indexed Register Data

Address Offset: A4h Attribute: R/W Default Value: XXXXXXXXh Size: 32 bits Bit Description 6:2 Index (IDX) — R/W. This field is a 5-bit index pointer into the SATA Indexed Register space. Data is written into and read from the SIRD register (D31:F2:A4h). 1:0 Reserved Table 12-1. SATA Indexed Registers Index Name 00h–03h SATA TX Termination Test Register 1 (STTT1) 04h–17h Reserved 18h–1Bh SATA Initialization Register 18 (SIR18) 1Ch–1Fh SATA Test Mode Enable Register (STME) 20h–27h Reserved 28h–2Bh SATA Initialization Register 28 (SIR28) 2Bh–73h Reserved 74h–77h SATA TX Termination Test Register 2 (STTT2) 78h–83h Reserved 84h–87h SATA Initialization Register 84 (SIR84) 88h–FFh Reserved Bit Description 31:0 Data (DTA) — R/W. This field is a 32-bit data value that is written to the register pointed to by SIRI (D31:F2;A0h) or read from the register pointed to by SIRI.

476 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

SATA Controller Registers (D31:F2)

12.1.34 STTT1—SATA Indexe d Registers Index 00h

(SATA TX Termination Test Register 1) Address Offset: Index 00h - 03h Attribute: R/W Default Value: 00000000h Size: 32 bits Bit Description 31:2 Reserved. Port 1 TX Termination Test Enable — R/W: 0 = Port 1 TX termination port testing is disabled. 1 = Setting this bit will enable testing of Port 1 TX termination. NOTE: This bit only to be used for system board testing. Port 0 TX Termination Test Enable — R/W: 0 = Port 0 TX termination port testing is disabled. 1 = Setting this bit will enable testing of Port 0 TX termination. NOTE: This bit only to be used for system board testing.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 477 SATA Controller Registers (D31:F2)

12.1.35 SIR18—SATA Indexed Registers Index 18h

(SATA Initialization Register 18h) Address Offset: Index 18h - 01Bh Attribute: R/W Default Value: 0000025Bh Size: 32 bits

12.1.36 STME—SATA Indexed Registers Index 1Ch

(SATA Test Mode Enable Register) Address Offset: Index 1Ch - 1Fh Attribute: R/W Default Value: 00000000h Size: 32 bits

12.1.37 SIR28—SATA Indexed Registers Index 28h

(SATA Initialization Register 28h) Address Offset: Index 28h - 2Bh Attribute: R/W Default Value: 00CC2080h Size: 32 bits Bit Description 31:6 Reserved. 5:0 BIOS programs this field to 101101b. Bit Description 31:19 Reserved. SATA Test Mode Enable Bit — R/W: 0 = Entrance to Intel ICH6 SATA test modes are disabled. 1 = This bit allows entrance to Intel ICH6 SATA test modes when set. Note: This bit only to be used for system board testing. 17:0 Reserved. Bit Description 31:23 Reserved. 22 BIOS leaves this bit at default. 21:19 Reserved 18 BIOS leaves this bit at default. 17:0 Reserved.

478 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

SATA Controller Registers (D31:F2)

12.1.38 STTT2—SATA Indexe d Registers Index 74h

(SATA TX Termination Test Register 2) Address Offset: Index 74h - 77h Attribute: R/W Default Value: 00000000h Size: 32 bits Bit Description 31:18 Reserved. Port 3 TX Termination Test Enable — R/W: 0 = Port 3 TX termination port testing is disabled. 1 = Setting this bit will enable testing of Port 3 TX termination. NOTE: This bit only to be used for system board testing. Port 2 TX Termination Test Enable — R/W: 0 = Port 2TX termination port testing is disabled. 1 = Setting this bit will enable testing of Port 2TX termination. NOTE: This bit only to be used for system board testing. 15:0 Reserved.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 479 SATA Controller Registers (D31:F2)

12.1.39 SIR84—SATA Indexed Registers Index 84h

(SATA Initialization Register 84h) Address Offset: Index 84h - 87h Attribute: R/W Default Value: 0000001Bh Size: 32 bits

12.1.40 ATC—APM Trapping Cont rol Register (SATA–D31:F2)

Address Offset: C0h Attribute: R/W Default Value: 00h Size: 8 bits Bit Description 31:6 Reserved. 5:0 BIOS programs this field to 101101b. Bit Description 7:4 Reserved Secondary Slave Trap (SST) — R/W. This bit enables trapping and SMI# assertion on legacy I/O accesses to 170h–177h and 376h. The active device on the secondary interface must be device 1 for the trap and/or SMI# to occur. Secondary Master Trap (SPT) — R/W. This bit enables trapping and SMI# assertion on legacy I/O accesses to 170h–177h and 376h. The active device on the secondary interface must be device 0 for the trap and/or SMI# to occur. Primary Slave Trap (PST) — R/W. This bit enables trapping and SMI# assertion on legacy I/O accesses to 1F0h–1F7h and 3F6h. The active device on the primary interface must be device 1 for the trap and/or SMI# to occur. Primary Master Trap (PMT) — R/W. This bit enables trapping an d SMI# assertion on legacy I/O accesses to 1F0h–1F7h and 3F6h. The active device on the primary interface must be device 0 for the trap and/or SMI# to occur.

480 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

SATA Controller Registers (D31:F2)

12.1.41 ATS—APM Trapping Stat us Register (SATA–D31:F2)

Address Offset: C4h Attribute: R/WC Default Value: 00h Size: 8 bits

12.1.42 SP—Scratch Pad Re gister (SATA–D31:F2)

Address Offset: D0h Attribute: R/W Default Value: 00000000h Size: 32 bits

12.1.43 BFCS—BIST FIS Control/Status Register (SATA–D31:F2)

Address Offset: E0h –E3h Attribute: R/W, R/WC Default Value: 00000000h Size: 32 bits Bit Description 7:4 Reserved 3 Secondary Slave Trap (SST) — R/WC. This bit indicates that a trap occurred to the secondary slave device. 2 Secondary Master Trap (SPT) — R/WC. This bit indicates that a trap occurred to the secondary master device. 1 Primary Slave Trap (PST) — R/WC. This bit indicates that a trap occurred to the primary slave device. 0 Primary Master Trap (PMT) — R/WC. This bit indicates that a trap occurred to the primary master device. Bit Description 31:0 Data (DT) — R/W. This is a read/write register that is available for software to use. No hardware action is taken on this register. Bits Description 31:14 Reserved (Desktop Only) Port 3 BIST FIS Initiate (P3BFI) — R/W. When a rising edge is detected on this bit field, the ICH6 initiates a BIST FIS to the device on Port 3, using the parameters specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS will only be initiated if a device on Port 3 is present and ready (not partial/slumber state). After a BIST FIS is successfully completed, software must disable and re-enable the port using the PxE bits at offset 92h prior to attempting additional BIST FISes or to return the ICH6 to a normal operational mode. If the BIST FIS fails to complete, as indicated by the BFF bit in the register, then software can clear then set the P3BFI bit to initiate another BIST FIS. This can be retried until the BIST FIS eventually completes successfully. (Mobile Only) Reserved. Port 2 BIST FIS Initiate (P2BFI) — R/W. When a rising edge is detected on this bit field, the ICH6 initiates a BIST FIS to the device on Port 2, using the parameters specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS will only be initiated if a device on Port 2 is present and ready (not partial/slumber state). After a BIST FIS is successfully completed, software must disable and re-enable the port using the PxE bits at offset 92h prior to attempting additional BIST FISes or to return the ICH6 to a normal operational mode. If the BIST FIS fails to complete, as indicated by the BFF bit in the register, then software can clear then set the P2BFI bit to initiate another BIST FIS. This can be retried until the BIST FIS eventually completes successfully.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 481 SATA Controller Registers (D31:F2) BIST FIS Successful (BFS) — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set any time a BIST FIS transmitt ed by ICH6 receives an R_OK completion status from the device. NOTE: This bit must be cleared by software prior to initiating a BIST FIS. BIST FIS Failed (BFF) — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set any time a BIST FIS transmitt ed by ICH6 receives an R_ERR completion status from the device. NOTE: This bit must be cleared by software prior to initiating a BIST FIS. (Desktop Only) Port 1 BIST FIS Initiate (P1BFI) — R/W. When a rising edge is detect ed on this bit field, the ICH6 initiates a BIST FIS to the device on Port 1, using the parameters specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS will only be initiated if a device on Port 1 is present and ready (not partial/slumber state). After a BIST FIS is successfully completed, software must disable and re-enable the port using the PxE bits at offset 92h prior to attempting additional BIST FISes or to return the ICH6 to a normal operational mode. If the BIST FIS fails to complete, as indicated by the BFF bit in the register, then software can clear then set the P1BFI bit to initiate another BIST FIS. This can be retried until the BIST FIS eventually completes successfully. (Mobile Only) Reserved. Port 0 BIST FIS Initiate (P0BFI) — R/W. When a rising edge is detect ed on this bit field, the ICH6 initiates a BIST FIS to the device on Port 0, using the parameters specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS will only be initiated if a device on Port 0 is present and ready (not partial/slumber state). After a BIST FIS is successfully completed, software must disable and re-enable the port using the PxE bits at offset 92h prior to attempting additional BIST FISes or to return the ICH6 to a normal operational mode. If the BIST FIS fails to complete, as indicated by the BFF bit in the register, then software can clear then set the P0BFI bit to initiate another BIST FIS. This can be retried until the BIST FIS eventually completes successfully. 7:2 BIST FIS Parameters. These 6 bits form the contents of the upper 6 bits of the BIST FIS Pattern Definition in any BIST FIS transmitted by the ICH6. This field is not port specific — its contents will be used for any BIST FIS initiated on port 0, port 1, port 2 or port 3. The specific bit definitions are: Bit 7: T – Far End Transmit mode Bit 6: A – Align Bypass mode Bit 5: S – Bypass Scrambling Bit 4: L – Far End Retimed Loopback Bit 3: F – Far End Analog Loopback Bit 2: P – Primitive bit for use with Transmit mode 1:0 Reserved Bits Description

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12.1.44 BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2)

Address Offset: E4h –E7h Attribute: R/W Default Value: 00000000h Size: 32 bits

12.1.45 BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2)

Address Offset: E8h –EBh Attribute: R/W Default Value: 00000000h Size: 32 bits Bits Description 31:0 BIST FIS Transmit Data 1 — R/W. The data programmed into this register will form the contents of the second DWord of any BIST FIS initiated by the ICH6. This register is not port specific — its contents will be used for BIST FIS initiated on any port. Although the 2nd and 3rd DWs of the BIST FIS are only meaningful when the “T” bit of the BIST FIS is set to indicate “Far-End Transmit mode”, this register’s contents will be transmitted as the BIST FIS 2nd DW regardless of whether or not the “T” bit is indicated in the BFCS register (D31:F2:E0h). Bits Description 31:0 BIST FIS Transmit Data 2 — R/W. The data programmed into this register will form the contents of the third DWord of any BIST FIS initiated by the ICH6. This register is not port specific — its contents will be used for BIST FIS initiated on any port. Although the 2nd and 3rd DWs of the BIST FIS are only meaningful when the “T” bit of the BIST FIS is set to indicate “Far-End Transmit mode”, this register’s contents will be transmitted as the BIST FIS 3rd DW regardless of whether or not the “T” bit is indicated in the BFCS register (D31:F2:E0h).

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 483 SATA Controller Registers (D31:F2)

12.2 Bus Master IDE I/O Registers (D31:F2)

The bus master IDE function uses 16 bytes of I/O space, allocated via the BAR register, located in Device 31:Function 2 Configuration space, offset 20h. All bus master IDE I/O space registers can be accessed as byte, word, or DWord quantities. Reading reserved bits returns an indeterminate, inconsistent value, and writes to reserved bits have no affect (but should not be attempted). These registers are only used for legacy operation. Software must not use these registers when running AHCI. The description of the I/O registers is shown in Table 12-2. Table 12-2. Bus Master IDE I/O Register Address Map BAR+ Offset Mnemonic Register Default Type

00 BMICP Command Register Primary 00h R/W

01 — Reserved — RO

02 BMISP Bus Master IDE Status Register Primary 00h R/W, R/WC,

03 — Reserved — RO 04–07 BMIDP Bus Master IDE Descriptor Table Pointer Primary xxxxxxxxh R/W

08 BMICS Command Register Secondary 00h R/W

09 — Reserved — RO 0A BMISS Bus Master IDE Status Register Secondary 00h R/W, R/WC, RO 0B — Reserved — RO 0C–0F BMIDS Bus Master IDE Descriptor Table Pointer Secondary xxxxxxxxh R/W

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SATA Controller Registers (D31:F2)

12.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F2)

Address Offset: Primary: BAR + 00h Attribute: R/W Secondary: BAR + 08h Default Value: 00h Size: 8 bits Bit Description 7:4 Reserved. Returns 0. Read / Write Control (RWC) — R/W. This bit sets the direction of the bus master transfer: This bit must NOT be changed when the bus master function is active. 0 = Memory reads 1 = Memory writes 2:1 Reserved. Returns 0. Start/Stop Bus Master (START) — R/W. 0 = All state information is lost when this bit is cleared. Master mode operation cannot be stopped and then resumed. If this bit is reset while bus master operation is still active (i.e., the Bus Master IDE Active bit (D31:F2:BAR + 02h, bit 0) of the Bus Master IDE Status register for that IDE channel is set) and the drive has not yet finished its data transfer (the Interrupt bit in the Bus Master IDE Status register for that IDE channel is not set), the bus master command is said to be aborted and data transferred from the drive may be discarded instead of being written to system memory. 1 = Enables bus master operation of the controll er. Bus master operation does not actually start unless the Bus Master Enable bit (D31:F1:04h, bit 2) in PCI configuration space is also set. Bus master operation begins when this bit is detected changing from 0 to 1. The controller will transfer data between the IDE device and memory only when this bit is set. Master operation can be halted by writing a 0 to this bit. NOTE: This bit is intended to be cleared by software after the data transfer is completed, as indicated by either the Bus Master IDE Active bit being cleared or the Interrupt bit of the Bus Master IDE Status register for that IDE channel being set, or both. Hardware does not clear this bit automatically. If this bit is cleared to 0 prior to the DMA data transfer being initiated by the drive in a device to memory data transfer, then the ICH6 will not send DMAT to terminate the data transfer. SW intervention (e.g. sending SRST) is required to reset the interface in this condition.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 485 SATA Controller Registers (D31:F2)

12.2.2 BMIS[P,S]—Bus Maste r IDE Status Register (D31:F2)

Address Offset: Primary: BAR + 02h Attribute: R/W, R/WC, RO Secondary: BAR + 0Ah Default Value: 00h Size: 8 bits

12.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer

Register (D31:F2) Address Offset: Primary: BAR + 04h–07h Attribute: R/W Secondary: BAR + 0Ch–0Fh Default Value: All bits undefined Size: 32 bits Bit Description PRD Interrupt Status (PRDIS) — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set when the host controller exec ution of a PRD that has its PRD_INT bit set. Drive 1 DMA Capable — R/W. 0 = Not Capable. 1 = Capable. Set by device dependent code (BIOS or devic e driver) to indicate that drive 1 for this channel is capable of DMA transfers, and that the controller has been initialized for optimum performance. The Intel® ICH6 does not use this bit. It is intended for systems that do not attach BMIDE to the PCI bus. Drive 0 DMA Capable — R/W. 0 = Not Capable 1 = Capable. Set by device dependent code (BIOS or devic e driver) to indicate that drive 0 for this channel is capable of DMA transfers, and that the controller has been initialized for optimum performance. The ICH6 does not use this bit. It is intended for systems that do not attach BMIDE to the PCI bus. 4:3 Reserved. Returns 0. Interrupt — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Set when a device FIS is received with the ‘I’ bit set, provided that software has not disabled interrupts via the nIEN bit of the Device Control Register (see chapter 5 of the Serial ATA Specification, Revision 1.0a). Error — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set when the controller encounters a target abort or master abort when transferring data on PCI. Bus Master IDE Active (ACT) — RO. 0 = This bit is cleared by the ICH6 when the last transfer for a region is performed, where EOT for that region is set in the region descriptor. It is also cleared by the ICH6 when the Start Bus Master bit (D31:F2:BAR+ 00h, bit 0) is cleared in the Command register. When this bit is read as a 0, all data transferred from the drive during the previous bus master command is visible in system memory, unless the bus master command was aborted. 1 = Set by the ICH6 when the Start bit is written to the Command register. Bit Description 31:2 Address of Descriptor Table (ADDR) — R/W. The bits in this field correspond to A[31:2]. The Descriptor Table must be dword-aligned. The Descriptor Table must not cross a 64-K boundary in memory. 1:0 Reserved

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SATA Controller Registers (D31:F2)

12.3 AHCI Registers (D31:F2)

Note: These registers are AHCI-specific and available only on ICH6R and ICH6-M when properly configured. The Serial ATA Status, Control, and Error registers are special exceptions and may be accessed on all ICH6 components if properly configured; see Section 12.1.31 for details. The memory mapped registers within the SATA controller exist in non-cacheable memory space. Additionally, locked accesses are not supported. If software attempts to perform locked transactions to the registers, indeterminate results may occur. Register accesses shall have a maximum size of 64-bits; 64-bit access must not cross an 8-byte alignment boundary. The registers are broken into two sections – generic host control and port control. The port control registers are the same for all ports, and there are as many registers banks as there are ports.

12.3.1 AHCI Generic Host Co ntrol Registers (D31:F2)

Table 12-3. AHCI Register Address Map ABAR + Offset Mnemonic Register 00h–1Fh GHC Generic Host Control 20h–FFh — Reserved 100h–17Fh P0PCR Port 0 port control registers 180h–1FFh P1PCR Port 1 port control registers (Desktop Only) Registers are not available and software must not read or write registers. (Mobile Only) 200h–27Fh P2PCR Port 2 port control registers 280h–2FFh P3PCR Port 3 port control registers (Desktop Only) Registers are not available and software must not read or write registers. (Mobile Only) 300h–3FFh — Reserved Table 12-4. Generic Host Controller Register Address Map ABAR + Offset Mnemonic Register Default Type 00h–03h CAP Host Capabilities C6027F03h R/WO, RO 04h–07h GHC Global ICH6 Control 00000000h R/W 08h–0Bh IS Interrupt Status 00000000h R/WC, RO 0Ch–0Fh PI Ports Implemented 00000000h R/WO, RO 10h–13h VS AHCI Version 00010000h RO

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 487 SATA Controller Registers (D31:F2)

12.3.1.1 CAP—Host Capabili ties Register (D31:F2)

Address Offset: ABAR + 00h–03h Attribute: R/WO, RO Default Value: C6027F03h Size: 32 bits All bits in this register that are R/WO are reset only by PLTRST#. Bit Description Supports 64-bit Addressing (S64A) — RO. This bit indicates that the SATA controller can access 64-bit data structures. The 32-bit upper bits of the port DMA Descriptor, the PRD Base, and each PRD entry are read/write. Supports Command Queue Acceleration (SCQA) — RO. Hardwired to 1 to indicate that the SATA controller supports SATA command queuing via the DMA Setup FIS. The Intel® ICH6 handles DMA Setup FISes natively, and can handle auto-activate optimization through that FIS. 29 Supports Cold Presence Detect (SCD) — RO. Cold presence detect not supported. Supports Interlock Switch (SIS) — R/WO. This bit indicates whet her the SATA controller supports interlock switches on its ports for use in Hot-Plug operations. This value is loaded by platform BIOS prior to OS initialization. If this bit is set, BIOS must also map the SATAGP pins to the SATA controller through GPIO space. Supports Staggered Spin-up (SSS) — R/WO. This bit indicates whether the SATA controller supports staggered spin-up on its ports, for use in balancing power spikes. This value is loaded by platform BIOS prior to OS initialization. 0 = Staggered spin-up not supported. 1 = Staggered spin-up supported. Supports Aggressive Link Power Management (SALP) — R/W. 0 = Indicates that the SATA controller does not s upport auto-generating link requests to the partial or slumber states when there are no commands to process. 1 = Indicates that the SATA controller supports auto-generating link requests to the partial or slumber states when there are no commands to process. Note: For only B-1 step devices, BIOS must clear this bit. 25 Supports Activity LED (SAL) — RO. This field indicates that t he SATA controller supports a single output pin (SATALED#) which indicates activity. 24 Supports Raw FIS Mode (SRM) — RO. The SATA controller does not support raw FIS mode. 23:20 Interface Speed Support (ISS) — RO. This field indicates the maximum speed the SATA controller can support on its ports. 0h =1.5 Gb/s. 19 Supports Non-Zero DMA Offsets (SNZO) — RO . Reserved, as per the AHCI Revision 1.0 specification 18 Supports Port Selector Acceleration — RO. Port Selectors not supported. 17 Supports Port Multiplier (PMS) — R/WO. ICH6 does not support port multiplier. BIOS/SW shall write this bit to ‘0’ during AHCI initalization. 16 Supports Port Multiplier FIS Based Switching (PMFS) — RO. Reserved, as per the AHCI Revision 1.0 specification. 15 Reserved. Returns 0. 14 Slumber State Capable (SSC) — RO. The SATA controller supports the slumber state. 13 Partial State Capable (PSC) — RO. The SA TA controller supports the partial state. 12:8 Number of Command Slots (NCS) — RO. Hardwired to 1Fh to indicate support for 32 slots. 7:5 Reserved. Returns 0. 4:0 Number of Ports (NPS) — RO. Hardwired to 3h to i ndicate support for 4 ports. Note that the number of ports indicated in this field may be more than the number of ports indicated in the PI (ABAR + 0Ch) register.

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SATA Controller Registers (D31:F2)

12.3.1.2 GHC—Global ICH6 C ontrol Register (D31:F2)

Address Offset: ABAR + 04h–07h Attribute: R/W Default Value: 00000000h Size: 32 bits Bit Description AHCI Enable (AE) — R/W. When set, this bit indicates that an AHCI driver is loaded and the controller will be talked to via AHCI mechanisms. This can be used by an ICH6 that supports both legacy mechanisms (such as SFF-8038i) and AHCI to know when the controller will not be talked to as legacy. When set, software will only talk to the ICH6 using AHCI. The ICH6 will not have to allow command processing via both AHCI and legacy mechanisms. When cleared, software will only talk to the ICH6 using legacy mechanisms. Software shall set this bit to 1 before accessing other AHCI registers. 30:2 Reserved. Returns 0. Interrupt Enable (IE) — R/W. This global bit enables interrupts from the ICH6. 0 = All interrupt sources from all ports are disabled. 1 = Interrupts are allowed from the AHCI controller. HBA Reset (HR) — R/W. Resets ICH6 AHCI controller. 0 = No effect 1 = When set by SW, this bit causes an internal reset of the ICH6 AHCI controller. All state machines that relate to data transfers and queuing return to an idle condition, and all ports are re-initialized via COMRESET. NOTE: For further details, consult section 12.3.3 of the Serial ATA Advanced Host Controller Interface specification.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 489 SATA Controller Registers (D31:F2)

12.3.1.3 IS—Interrupt Stat us Register (D31:F2)

Address Offset: ABAR + 08h –0Bh Attribute: R/WC, RO Default Value: 00000000h Size: 32 bits This register indicates which of the ports within the controller have an interrupt pending and require service. Bit Description 31:4 Reserved. Returns 0. (Mobile Only) Reserved. Returns 0. (Desktop Only) Interrupt Pending Status Port[3] (IPS[3]) — R/WC . 0 = No interrupt pending. 1 = Port 3 has an interrupt pending. Software can us e this information to determine which ports require service after an interrupt. Interrupt Pending Status Port[2] (IPS[2]) — R/WC 0 = No interrupt pending. 1 = Port 2 has an interrupt pending. Software can us e this information to determine which ports require service after an interrupt. (Mobile Only) Reserved. Returns 0. (Desktop Only) Interrupt Pending Status Port[1] (IPS[1]) — R/WC . 0 = No interrupt pending. 1 = Port 1has an interrupt pending. Software can use this information to determine which ports require service after an interrupt. Interrupt Pending Status Port[0] (IPS[0]) — R/WC . 0 = No interrupt pending. 1 = Port 0 has an interrupt pending. Software can us e this information to determine which ports require service after an interrupt.

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12.3.1.4 PI—Ports Implemen ted Register (D31:F2)

Address Offset: ABAR + 0C h–0Fh Attribute: R/WO, RO Default Value: 00000000h Size: 32 bits This register indicates which ports are exposed to the ICH6. It is loaded by platform BIOS. It indicates which ports that the device supports are available for software to use. For ports that are not available, software must not read or write to registers within that port.

12.3.1.5 VS—AHCI Version (D31:F2)

Address Offset: ABAR + 10h–13h Attribute: RO Default Value: 00010000h Size: 32 bits This register indicates the major and minor version of the AHCI specification. It is BCD encoded. The upper two bytes represent the major version number, and the lower two bytes represent the minor version number. Example: Version 3.12 would be represented as 00030102h. The current version of the specification is 1.0 (00010000h). Bit Description 31:4 Reserved. Returns 0. (Desktop Only) Ports Implemented Port 3 (PI3) — R/WO. 0 = The port is not implemented. 1 = The port is implemented. (Mobile Only) Ports Implemented Port 3 (PI3) — RO. 0 = The port is not implemented. Ports Implemented Port 2 (PI2)— R/WO. 0 = The port is not implemented. 1 = The port is implemented. (Desktop Only) Ports Implemented Port 1 (PI1) — R/WO. 0 = The port is not implemented. 1 = The port is implemented. (Mobile Only) Ports Implemented Port 1 (PI1) — RO. 0 = The port is not implemented. Ports Implemented Port 0 (PI0) — R/WO . 0 = The port is not implemented. 1 = The port is implemented. Bit Description 31:16 Major Version Number (MJR) — RO. This field indicates the major version is 1 15:0 Minor Version Number (MNR) — RO. This field indicates the minor version is 0.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 491 SATA Controller Registers (D31:F2)

12.3.2 Port Registers (D31:F2)

Table 12-5. Port [3:0] DMA Register Address Map ABAR + Offset Mnemonic Register 100–103h P0CLB Port 0 Command List Base Address 104–107h P0CLBU Port 0 Command List Base Address Upper 32-Bits 108–10Bh P0FB Port 0 FIS Base Address 10C–10Fh P0FBU Port 0 FIS Base Address Upper 32-Bits 110–113h P0IS Port 0 Interrupt Status 114–117h P0IE Port 0 Interrupt Enable 118–11Ch P0CMD Port 0 Command 11C–11Fh — Reserved 120–123h P0TFD Port 0 Task File Data 124–127h P0SIG Port 0 Signature 128–12Bh P0SSTS Port 0 Serial ATA Status 12C–12Fh P0SCTL Port 0 Serial ATA Control 130–133h P0SERR Port 0 Serial ATA Error 134–137h P0SACT Port 0 Serial ATA Active 138–13Bh P0CI Port 0 Command Issue 13C–17Fh — Reserved 180–1FFh (Mobile Only) — Reserved Registers are not available and software must not read from or write to registers. 180–183h P1CLB Port 1 Command List Base Address 184–187h P1CLBU Port 1 Command List Base Address Upper 32-Bits 188–18Bh P1FB Port 1 FIS Base Address 18C–18Fh P1FBU Port 1 FIS Base Address Upper 32-Bits 190–193h P1IS Port 1 Interrupt Status 194–197h P1IE Port 1 Interrupt Enable 198–19Ch P1CMD Port 1 Command 19C–19Fh — Reserved 1A0–1A3h P1TFD Port 1 Task File Data 1A4–1A7h P1SIG Port 1 Signature 1A8–1ABh P1SSTS Port 1 Serial ATA Status 1AC–1AFh P1SCTL Port 1 Serial ATA Control 1B0–1B3h P1SERR Port 1 Serial ATA Error 1B4–1B7h P1SACT Port 1 Serial ATA Active 1B8–1BBh P1CI Port 1 Command Issue 1BC–1FFh — Reserved

492 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

SATA Controller Registers (D31:F2) 200–203h P2CLB Port 2 Command List Base Address 204–207h P2CLBU Port 2 Command List Base Address Upper 32-Bits 208–20Bh P2FB Port 2 FIS Base Address 20C–20Fh P2FBU Port 2 FIS Base Address Upper 32-Bits 210–213h P2IS Port 2 Interrupt Status 214–217h P2IE Port 2 Interrupt Enable 218–21Ch P2CMD Port 2 Command 21C–21Fh — Reserved 220–223h P2TFD Port 2 Task File Data 224–227h P2SIG Port 2 Signature 228–22Bh P2SSTS Port 2 Serial ATA Status 22C–22Fh P2SCTL Port 2 Serial ATA Control 230–233h P2SERR Port 2 Serial ATA Error 234–237h P2SACT Port 2 Serial ATA Active 238–23Bh P2CI Port 2 Command Issue 23C–27Fh — Reserved 280–2FFh (Mobile Only) — Reserved Registers are not available and software must not read from or write to registers. 280–283h P3CLB Port 3 Command List Base Address 284–287h P3CLBU Port 3 Command List Base Address Upper 32-Bits 288–28Bh P3FB Port 3 FIS Base Address 28C–28Fh P3FBU Port 3 FIS Base Address Upper 32-Bits 290–293h P3IS Port 3 Interrupt Status 294–297h P3IE Port 3 Interrupt Enable 298–29Ch P3CMD Port 3 Command 19C–19Fh — Reserved 2A0–2A3h P3TFD Port 3 Task File Data 2A4–2A7h P3SIG Port 3 Signature 2A8–2ABh P3SSTS Port 3 Serial ATA Status 2AC–2AFh P3SCTL Port 3 Serial ATA Control 2B0–2B3h P3SERR Port 3 Serial ATA Error 2B4–2B7h P3SACT Port 3 Serial ATA Active 2B8–2BBh P3CI Port 3 Command Issue 2BC–2FFh — Reserved Table 12-5. Port [3:0] DMA Register Address Map ABAR + Offset Mnemonic Register

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 493 SATA Controller Registers (D31:F2)

12.3.2.1 PxCLB—Port [3:0] Comma nd List Base Address Register

(D31:F2) Address Offset: Port 0: ABAR + 100h Attribute: R/W, RO Port 1: ABAR + 180h (Desktop Only) Port 2: ABAR + 200h Port 3: ABAR + 280h (Desktop Only) Default Value: Undefined Size: 32 bits

12.3.2.2 PxCLBU—Port [3:0] Comma nd List Base Address Upper

32-Bits Register (D31:F2) Address Offset: Port 0: ABAR + 104h Attribute: R/W Port 1: ABAR + 184h (Desktop Only) Port 2: ABAR + 204h Port 3: ABAR + 284h (Desktop Only) Default Value: Undefined Size: 32 bits

12.3.2.3 PxFB—Port [3:0] FIS Ba se Address Register (D31:F2)

Address Offset: Port 0: ABAR + 108h Attribute: R/W, RO Port 1: ABAR + 188h (Desktop Only) Port 2: ABAR + 208h Port 3: ABAR + 288h (Desktop Only) Default Value: Undefined Size: 32 bits Bit Description 31:10 Command List Base Address (CLB) — R/W . This field indicates the 32-bit base for the command list for this port. This base is used when fetching commands to execute. The structure pointed to by this address range is 1 KB in length. This address must be 1-KB aligned as indicated by bits 31:10 being read/write. Note that these bits are not reset on a HBA reset. 9:0 Reserved — RO Bit Description 31:0 Command List Base Address Upper (CLBU) — R/W . This field indicates the upper 32-bits for the command list base address for this port. This base is used when fetching commands to execute. Note that these bits are not reset on a HBA reset. Bit Description 31:8 FIS Base Address (FB) — R/W . This field indicates the 32-bit base for received FISes. The structure pointed to by this address range is 256 bytes in length. This address must be 256-byte aligned, as indicated by bits 31:3 being read/write. Note that these bits are not reset on a HBA reset. 7:0 Reserved — RO

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SATA Controller Registers (D31:F2)

12.3.2.4 PxFBU—Port [3:0] FI S Base Address Upper 32-Bits

Register (D31:F2) Address Offset: Port 0: ABAR + 10Ch Attribute: R/W Port 1: ABAR + 18Ch Port 2: ABAR + 20Ch Port 3: ABAR + 28Ch Default Value: Undefined Size: 32 bits

12.3.2.5 PxIS—Port [3 :0] Interrupt Status Register (D31:F2)

Address Offset: Port 0: ABAR + 110h Attribute: R/WC, RO Port 1: ABAR + 190h (Desktop Only) Port 2: ABAR + 210h Port 3: ABAR + 290h (Desktop Only) Default Value: 00000000h Size: 32 bits Bit Description 31:3 Command List Base Address Upper (CLBU) — R/W . This field indicates the upper 32-bits for the received FIS base for this port. Note that these bits are not reset on a HBA reset. 2:0 Reserved Bit Description 31 Cold Port Detect Status (CPDS) — RO . Cold presence not supported. 30 Task File Error Status (TFES) — R/WC. This bit is set whenever the status register is updated by the device and the error bit (PxTFD.bit 0) is set. Host Bus Fatal Error Status (HBFS) — R/WC . This bit indicates that the Intel® ICH6 encountered an error that it cannot recover from due to a bad software pointer. In PCI, such an indication would be a target or master abort. 28 Host Bus Data Error Status (HBDS) — R/WC . Indicates that the ICH6 encountered a data error (uncorrectable ECC / parity) when reading from or writing to system memory. 27 Interface Fatal Error Status (IFS) — R/WC . Indicates that the ICH6 encountered an error on the SATA interface which caused the transfer to stop. 26 Interface Non-fatal Error Status (INFS) — R/WC. Indicates that the ICH6 encountered an error on the SATA interface but was able to continue operation.

25 Reserved

24 Overflow Status (OFS) — R/WC . Indicates that the ICH6 received more bytes from a device than was specified in the PRD table for the command. Incorrect Port Multiplier Status (IPMS) — R/WC. Indicates that the ICH6 received a FIS from a device whose Port Multiplier field did not match what was expected. NOTE: Port Multiplier not supported by ICH6. PhyRdy Change Status (PRCS) — RO. When set to 1 indicates the internal PhyRdy signal changed state. This bit reflects the state of PxSERR.DIAG.N. Unlike most of the other bits in the register, this bit is RO and is only cleared when PxSERR.DIAG.N is cleared. Note that the internal PhyRdy signal also transitions when the port interface enters partial or slumber power management states. Partial and slumber must be disabled when Surprise Removal Notification is desired, otherwise the power management state transitions will appear as false insertion and removal events. 21:8 Reserved

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 495 SATA Controller Registers (D31:F2) Device Interlock Status (DIS) — R/WC. When set, indicates that a platform interlock switch has been opened or closed, which may lead to a change in the connection state of the device.This bit is only valid in systems that support an interlock switch (CAP.SIS [ABAR+00:bit 28] set). For systems that do not support an interlock switch, this bit will always be 0. Port Connect Change Status (PCS) — RO . This bit reflects the state of PxSERR.DIAG.X. (ABAR+130h/1D0h/230h/2D0h, bit 26) Unlike other bits in this register, this bit is only cleared when PxSERR.DIAG.X is cleared. 0 = No change in Current Connect Status. 1 = Change in Current Connect Status. 5 Descriptor Processed (DPS) — R/WC . A PRD with the I bit set has transferred all its data. Unknown FIS Interrupt (UFS) — RO . When set to ‘1’ indicates that an unknown FIS was received and has been copied into system memory. This bit is cleared to ‘0’ by software clearing the PxSERR.DIAG.F (ABAR+130h/1D0h/230h/2D0h, bit 25) bit to ‘0’. Note that this bit unknown FIS is detected, whereas this bit is set when the FIS is posted to memory. Software should wait to act on an unknown FIS until this bit is set to ‘1’ or the two bits may become out of sync. 3 Set Device Bits Interrupt (SDBS) — R/WC . A Set Device Bits FIS has been received with the I bit set and has been copied into system memory. 2 DMA Setup FIS Interrupt (DSS) — R/WC . A DMA Setup FIS has been received with the I bit set and has been copied into system memory. 1 PIO Setup FIS Interrupt (PSS) — R/WC . A PIO Setup FIS has been received with the I bit set, it has been copied into system memory, and the data related to that FIS has been transferred. 0 Device to Host Register FIS Interrupt (DHRS) — R/WC . A D2H Register FIS has been received with the I bit set, and has been copied into system memory. Bit Description

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SATA Controller Registers (D31:F2)

12.3.2.6 PxIE—Port [3 :0] Interrupt Enable Register (D31:F2)

Address Offset: Port 0: ABAR + 114h Attribute: R/W, RO Port 1: ABAR + 194h (Desktop Only) Port 2: ABAR + 214h Port 3: ABAR + 294h (Desktop Only) Default Value: 00000000h Size: 32 bits This register enables and disables the reporting of the corresponding interrupt to system software. When a bit is set (‘1’) and the corresponding interrupt condition is active, then an interrupt is generated. Interrupt sources that are disabled (‘0’) are still reflected in the status registers. Bit Description 31 Cold Presence Detect Enable (CPDE) — RO. Cold Presence Detect not supported. 30 Task File Error Enable (TFEE) — R/W . When set, and GHC.IE and PxTFD.STS.ERR (due to a reception of the error register from a received FIS) are set, the Intel® ICH6 will generate an interrupt. 29 Host Bus Fatal Error Enable (HBFE) — R/W . When set, and GHC.IE and PxS.HBFS are set, the ICH6 will generate an interrupt. 28 Host Bus Data Error Enable (HBDE) — R/W . When set, and GHC.IE and PxS.HBDS are set, the ICH6 will generate an interrupt. 27 Host Bus Data Error Enable (HBDE) — R/W. When set, GHC.IE is set, and PxIS.HBDS is set, the ICH6 will generate an interrupt. 26 Interface Non-fatal Error Enable (INFE) — R/W. When set, GHC.IE is set, and PxIS.INFS is set, the ICH6 will generate an interrupt.

25 Reserved - Should be written as 0

24 Overflow Error Enable (OFE) — R/W . When set, and GHC.IE and PxS.OFS are set, the ICH6 will generate an interrupt. Incorrect Port Multiplier Enable (IPME) — R/W. When set, and GHC.IE and PxIS.IPMS are set, the ICH6 will generate an interrupt. NOTE: Should be written as 0. Port Multiplier not supported by ICH6. 22 PhyRdy Change Interrupt Enable (PRCE) — R/W. When set, and GHC.IE is set, and PxIS.PRCS is set, the ICH6 shall generate an interrupt. 21:8 Reserved - Should be written as 0 Device Interlock Enable (DIE) — R/W. When set, and PxIS.DIS is set, the ICH6 will generate an interrupt. For systems that do not support an interlock switch, this bit shall be a read-only 0. 6 Port Change Interrupt Enable (PCE) — R/W . When set, and GHC.IE and PxS.PCS are set, the ICH6 will generate an interrupt. 5 Descriptor Processed Interrupt Enable (DPE) — R/W . When set, and GHC.IE and PxS.DPS are set, the ICH6 will generate an interrupt 4 Unknown FIS Interrupt Enable (UFIE) — R/W . When set, and GHC.IE is set and an unknown FIS is received, the ICH6 will generate this interrupt. 3 Set Device Bits FIS Interrupt Enable (SDBE) — R/W . When set, and GHC.IE and PxS.SDBS are set, the ICH6 will generate an interrupt. 2 DMA Setup FIS Interrupt Enable (DSE) — R/W . When set, and GHC.IE and PxS.DSS are set, the ICH6 will generate an interrupt. 1 PIO Setup FIS Interrupt Enable (PSE) — R/W . When set, and GHC.IE and PxS.PSS are set, the ICH6 will generate an interrupt. 0 Device to Host Register FIS Interrupt Enable (DHRE) — R/W . When set, and GHC.IE and PxS.DHRS are set, the ICH6 will generate an interrupt.

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 497 SATA Controller Registers (D31:F2)

12.3.2.7 PxCMD—Port [3:0] Command Register (D31:F2)

Address Offset: Port 0: ABAR + 118h Attribute: R/W, RO, R/WO Port 1: ABAR + 198h (Desktop Only) Port 2: ABAR + 218h Port 3: ABAR + 298h (Desktop Only) Default Value: 0000w00wh Size: 32 bits where w = 00?0b (for ?, see bit description) Bit Description 31:28 Interface Communication Control (ICC) — R/W . This is a four bit field which can be used to control reset and power states of the interface. Writes to this field will cause actions on the interface, either as primitives or an OOB sequence, and the resulting status of the interface will be reported in the PxSSTS register (Address offset Port 0:ABAR+124h, Port 1: ABAR+1A4h, Port 2: ABAR+224h, Port 3: ABAR+2A4h). When system software writes a non-reserved value other than No-Op (0h), the ICH6 will perform the action and update this field back to Idle (0h). If software writes to this field to change the state to a state the link is already in (e.g. interface is in the active state and a request is made to go to the active state), the ICH6 will take no action and return this field to Idle. NOTE: When the ALPE bit (bit 26) is set, then this register should not be set to 02h or 06h. Aggressive Slumber / Partial (ASP) — R/W . When set, and the ALPE bit (bit 26) is set, the ICH6 will aggressively enter the slumber state when it clears the PxCI register and the PxSACT register is cleared. When cleared, and the ALPE bit is set, the ICH6 will aggressively enter the partial state when it clears the PxCI register and the PxSACT register is cleared. Aggressive Link Power Management Enable (ALPE) — R/W . When set, the ICH6 will aggressively enter a lower link power state (partial or slumber) based upon the setting of the ASP bit (bit 27). Drive LED on ATAPI Enable (DLAE) — R/W . When set, the ICH6 will drive the LED pin active for ATAPI commands (PxCLB[CHz.A] set) in addition to ATA commands. When cleared, the ICH6 will only drive the LED pin active for ATA commands. See Section 5.17.5 for details on the activity LED. HDevice is ATAPI (ATAPI) — R/W. When set, the connected device is an ATAPI device. This bit is used by the ICH6 to control whether or not to generate the desktop LED when commands are active. See Section 5.17.5 for details on the activity LED. 23:20 Reserved Value Definition Fh–7h Reserved Slumber: This will cause the Intel® ICH6 to request a transition of the interface to the slumber state. The SATA device may reject the request and the interface will remain in its current state 5h–3h Reserved Partial: This will cause the ICH6 to request a transition of the interface to the partial state. The SATA device may reject the request and the interface will remain in its current state. 1h Active: This will cause the ICH6 to request a transition of the interface into the active No-Op / Idle: When software reads this value, it indicates the ICH6 is not in the process of changing the interface state or sending a device reset, and a new link command may be issued.

498 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

SATA Controller Registers (D31:F2) Interlock Switch Attached to Port (ISP) — R/WO. When interlock switches are supported in the platform (CAP .SIS [ABAR+00h:bit 28] set), this indicates whether this particular port has an interlock switch attached. This bit can be used by system software to enable such features as aggressive power management, as disconnects can always be detected regardless of PHY state with an interlock switch. When this bit is set, it is expected that HPCP (bit 18) in this register is also set. The ICH6 takes no action on the state of this bit – it is for system software only. For example, if this bit is cleared, and an interlock switch toggles, the ICH6 still treats it as a proper interlock switch event. Note that these bits are not reset on a HBA reset. Hot Plug Capable Port (HPCP) — R/WO. 0 = Port is not capable of Hot-Plug. 1 = Port is Hot-Plug capable. This indicates whether the platform exposes this port to a device which can be Hot-Plugged. SATA by definition is hot-pluggable, but not all platforms are constructed to allow the device to be removed (it may be screwed into the chassis, for example). This bit can be used by system software to indicate a feature such as "eject device" to the end-user. The ICH6 takes no action on the state of this bit - it is for system software only. For example, if this bit is cleared, and a Hot-Plug event occurs, the ICH6 still treats it as a proper Hot-Plug event. Note that these bits are not reset on a HBA reset. Port Multiplier Attached (PMA) — RO / R/W. When this bit is set, a port multiplier is attached to the ICH6 for this port. When cleared, a port multiplier is not attached to this port. This bit is RO 0 when CAP.PMS (offset ABAR+00h:bit 17) = 0 and R/W when CAP.PMS = 1. NOTE: Port Multiplier not supported by ICH6. 16 Port Multipler FIS Based Switching Enable (PMFSE) — RO. The ICH6 does not support FIS-based switching. Controller Running (CR) — RO. When this bit is set, the DMA engines for a port are running. See section 5.2.2 of the Serial ATA AHCI Specification for details on when this bit is set and cleared by the ICH6. FIS Receive Running (FR) — RO. When set, the FIS Receive DMA engine for the port is running. See section 12.2.2 of the Serial ATA AHCI Specification for details on when this bit is set and cleared by the ICH6. Interlock Switch State (ISS) — RO. For systems that support interlock switches (via CAP.SIS [ABAR+00h:bit 28]), if an interlock switch exists on this port (via ISP in this register), this bit indicates the current state of the interlock switch. A 0 indicates the switch is closed, and a 1 indicates the switch is opened. For systems that do not support interlock switches, or if an interlock switch is not attached to this port, this bit reports 0. 12:8 Current Command Slot (CCS) — RO . This field indicates the current command slot the ICH6 is processing. This field is valid when the ST bit is set in this register, and is constantly updated by the ICH6. This field can be updated as soon as the ICH6 recognizes an active command slot, or at some point soon after when it begins processing the command. This field is used by software to determine the current command issue location of the ICH6. In queued mode, software shall not use this field, as its value does not represent the current command being executed. Software shall only use PxCI and PxSACT when running queued commands. 7:5 Reserved FIS Receive Enable (FRE) — R/W. When set, the ICH6 may post received FISes into the FIS receive area pointed to by PxFB (ABAR+108h/188h/208h/288h) and PxFBU (ABAR+10Ch/18Ch/ 20Ch/28Ch). When cleared, received FISes are not accepted by the ICH6, except for the first D2H (device-to-host) register FIS after the initialization sequence. System software must not set this bit until PxFB (PxFBU) have been programmed with a valid pointer to the FIS receive area, and if software wishes to move the base, this bit must first be cleared, and software must wait for the FR bit (bit 14) in this register to be cleared. 3 Port Selector Activate (PSA) — RO. Port Selector not supported. Defaults to 0. Bit Description

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 499 SATA Controller Registers (D31:F2)

12.3.2.8 PxTFD—Port [3 :0] Task File Data Register (D31:F2)

Address Offset: Port 0: ABAR + 120h Attribute: RO Port 1: ABAR + 1A0h (Desktop Only) Port 2: ABAR + 220h Port 3: ABAR + 2A0h (Desktop Only) Default Value: 0000007Fh Size: 32 bits This is a 32-bit register that copies specific fields of the task file when FISes are received. The FISes that contain this information are: D2H Register FIS PIO Setup FIS Set Device Bits FIS 2 Power On Device (POD) — RO . Cold presence detect not supported. Defaults to 1. Spin-Up Device (SUD) — R/W / RO This bit is R/W and defaults to 0 for systems that support staggered spin-up (R/W when CAP.SSS (ABAR+00h:bit 27) is 1). Bit is RO 1 for systems that do not support staggered spin-up (when CAP.SSS is 0). 0 = No action. 1 = On an edge detect from 0 to 1, the ICH6 st arts a COMRESET initialization sequence to the device. Start (ST) — R/W . When set, the ICH6 may process the command list. When cleared, the ICH6 may not process the command list. Whenever this bit is changed from a 0 to a 1, the ICH6 starts processing the command list at entry 0. Whenever this bit is changed from a 1 to a 0, the PxCI register is cleared by the ICH6 upon the ICH6 putting the controller into an idle state. Refer to section 12.2.1 of the Serial ATA AHCI Specification for important restrictions on when ST can be set to 1. Bit Description Bit Description 31:16 Reserved 15:8 Error (ERR) — RO . Contains the latest copy of the task file error register. 7:0 Status (STS) — RO . Contains the latest copy of the task file status register. Fields of note in this register that affect AHCI. Bit Field Definition

7 BSY Indicates the interface is busy

6:4 N/A Not applicable

3 DRQ Indicates a data transfer is requested

2:1 N/A Not applicable

0 ERR Indicates an error during the transfer

500 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

SATA Controller Registers (D31:F2)

12.3.2.9 PxSIG—Port [3:0] Si gnature Register (D31:F2)

Address Offset: Port 0: ABAR + 124h Attribute: RO Port 1: ABAR + 1A4h (Desktop Only) Port 2: ABAR + 224h Port 3: ABAR + 2A4h (Desktop Only) Default Value: FFFFFFFFh Size: 32 bits This is a 32-bit register which contains the initial signature of an attached device when the first D2H Register FIS is received from that device. It is updated once after a reset sequence. Bit Description 31:0 Signature (SIG) — RO . This field contains the signature received from a device on the first D2H register FIS. The bit order is as follows: Bit Field 31:24 LBA High Register 23:16 LBA Mid Register 15:8 LBA Low Register 7:0 Sector Count Register

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