N89027

89024 INTEL | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 30

Technical content

2400 BPS INTELLIGENT

Figure 1. System Block Diagram

41 Order Number: 270222-002

www.chipdocs.com Be sure to visit ChipDocs web site for more information.

a GENERAL DESCRIPTION is available in a standard 48 pin package. An option- al 68 pin version supports an external ROM for user The Intel 89024 chip set is a high performance and designed software. With this option, the signal pro- highly integrated modem, providing a complete sys- cessing algorithms resident in the 89026, can be tem in two chips. The system implements CCITT controlled by the customer designed external soft- V.22 bis 2400 bps, V.22 A & B/ Bell 212A 1200 bps, ware for proprietary modem control and call prog- and V.21/Bell 103 300 bps full-duplex modem func- ress management applications. A block diagram of tions. In addition to supporting a strict implementa- 89026 is provided In Figure 2. tion of CCITT and Bell standards, a complete set of Hayes Smartmodem 2400 commands is also provid- This device contains a TTL compatible serial link to ed for modem configuration and user interface. DTE/DCE equipment, along with a full complement of V.24/RS-232-C control signals. Alternatively, a In stand-alone modem applications, the 89024 chip UART or USART may be used to directly transfer set along with a Data Access Arrangement (DAA) data to/from a microcomputer bus. The device sup- and RS-232 driver/receivers, represent the circuitry ports a complete set of Hayes compatible modem required for implementing an auto-dial, auto-answer, control commands. This compatibility facilitates 300 to 2400 bps, full duplex modem. communications between the 89024 and most PC software written for the Hayes Smartmodem 2400 In applications where user proprietary modem con- product. trol commands may be required, the user can re- place the 89024 internal command module with cus- In the transmit direction, the 89026 synthesizes tom proprietary software resident in the 89026 mi- DTMF tones and the 300 bps FSK modem signal crocontroller’s on-chip ROM or an external memory _prior to transmitting them to the 89027 as digitized device. amplitude samples. During 1200 and 2400 bps oper- ations, quadrature amplitude modulation (QAM) is The 89024 system consists of a 16 bit application used to send 2 or 4 bits of information at 600 baud specific processor (89026) and an analog front end _—_to the 89027. Since the QAM coding technique is device (89027). The 89026 processor executes all inherently a synchronous transmission mechanism, “Digital Signal Processing” algorithms for the mo- during a synchronous QAM transmission, the asyn- dem signals, as well as providing all modem control chronous data is synchronized by adding or deleting functions typically performed by an external proces- stop bits. Following the synchronization process, the sor. Tha analog front end provides the telephone 89026 transmits digitized phase and amplitude sam- line 2 wire to 4 wire interface, D/A conversion, and _ ples to the 89027 over a high speed serial link. most of the complex filtering functions required in QAM/PSK/FSK modems. Refer to Figure 1 for a In the receive direction, the information is received simplified block diagram of the system. by the 89026 from the 89027 as two signals which are 90 degrees phase shifted from each other. The chip set provides a comprehensive set of te- These analog signals are then digitized by the lephony functions designed to facilitate a simple in- 89026’s on-board A/D converter, and using DSP terface to the telephone network. software algorithms the signals are gain adjusted, adaptively equalized for telephone line delay and amplitude distortion, and demodulated. Following

89026 OVERVIEW the demodulation process by the 89026, the data is

unscrambled, and If necessary, returned to asyn- The 89026 processor performs most of modulation, chronous format. demodulation and user interface functions. This chip NOTICE: Hayes is a registered trademark of Hayes Microcomputer Products, Inc. ‘Smartcom Ii is a registered trademark of Hayes Microcomputer Products, Inc. Smartmodem 2400 is a trademark of Hayes Microcomputer Products, Inc. 4-2 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

0 Sh Le Psk ASYNC DATA PHASE H

Figure 2. 89026 Block Diagram www.chipdocs.com Be sure to visit ChipDocs web site for more information.

89027 OVERVIEW ters, combined with the necessary guard tone,

smoothed by a low pass filter, and transmitted to the The 69027 is a 28 pin CHMOS analog front end de- line. Prior to transmitting either FSK or QAM signals vice, which performs most of the complex filtering to the telephone line, the 89027 adjusts the signal functions required in modem transmitters and re- gain through a on-board programmable gain amplifi- ceivers. A general block diagram of this chip is pro- er. vided in Figure 3. Most of the analog signal process- . . . - ing functions in this chip’ are implemented with During the receive operation, the received QAM/ switched capacitor technology. The 89027 functions © PSK/FSK signals are passed through anti-alias fil- are controlled by the 89026, through a high speed ters, bandsplit fitters, automatic gain control and car- serial data link. tier detect circuits, a Hibert transform filter, and the output sent to the 89026 processor as analog sig- During FSK transmit operation, the 89027 receives nals. digitally synthesized mark and space sinusoid ampli- tude information from the 89026. The 89027 con- Other functions provided by the 89027 are: an on- verts the signal to its analog equivalent, filters it, and board 2 wire to 4 wire circuit with disable capability, transmits it to the telephone line. For QAM transmis- an audio monitor output with software configurable sion, the signal constellation points are transferred gain, and a programmable gain transmit signal. to the 89027. This information is modulated into an analog signal, passed through spectral shaping fil- po rrrcb ecco cre ec ene ee nce eee e ete ncn eee en een n nena nce eneeee enon: SDATA SERIAL ' 3 | wo eg a neg ed FILTER i : Wee > AMP at {| cncon — : ' BAND BAND HYBRID , H FILTER FILTER 4— HYB set} ‘ ' ‘ a [sneer oon Te 401 Hy FILTER H ' 'SMP/HOLD HILBERT ' ‘ : mr] [ ! T f OUTPUT LEVEL Yoo Yap AGND Vsg RST AV eg, Azz val 1X30 270222-8 . Figure 3. 89027 Block Diagram 4-4 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

1. transparent to the current 212A users. Similarly, a

and do not provide recognition of the ramota modem tion in services. adapt to remote modems without user intervention. Figure 4. Typical Modem Configuration www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Figure 5. Typical Telephone Line Interface With Bullt-In Hybrid plastic DIP, and the optional 68 pin device (for exter- names and a brief explanation of their function.

89026 PINOUT

www.chipdocs.com Be sure to visit ChipDocs web site for more information.

89026 PINOUT (Continued)

Symbol Function (89026) [inno [in a aaa TCL NVRAM Data I/O fe) 23 20 TCLO NVRAM SK Out 24 19 B/C 103/V.21 default option In 47 15 S/A NVRAM CE Out 22 21 o/s Oumb/Smart mode select In 32 6 CONFIG Custom Firmware Disable In 40 8 TXD Transmitted data from DTE In 6 27 RXD Received data to DTE Out 8 29 RTS Request to send from DTE In 24 22 CTs Clear to Send to DTE Out 20 23 DSR Data Set Ready to DTE Out 19 30 DCD Data Carrier Detect to DTE Out 18 31 DIR Data Terminal Ready from DTE In 4 25 RCLK Received clock to DTE Out 9 34 TCLK Transmit clock to DTE Out 7 28 XTCLK External timing clock from DTE In 5 26 SI Speed Indicator to DTE Out 17 32 ss Speed select from DTE(4) In 31 5 REMLB Remote Loopback Command from DTE In 30 7 TCLs Local Loopback Command from DTE In 29 4 Veo Positive power supply (+ 5V) +5V 38 1 Vep Ram back-up power +5V 46 14 VREF A/D converter reference +5V 45 13 Vssi Digitat ground GND ch 36 Vss2 Digital ground GND 37 68 AGND Analog ground AGND 44 12 Vess Back-bias generator output Out 12 37 EA External Memory enable In 2 ADO-AD15 External memory access address/data(5) VO 60-45 AA Auto answer, ring indicator Out 60 Sy Jack select Out 59 NMI Non-maskable Interrupt (Vgg)(1) In _ 3 x2 Crystal output (NC)(2) Out 35 66 CLKOUT Clock output (NC)(2) Out _ 65 TEST Factory test (Vcc)(3) In - 64 INST External memory instruction fetch Out - 63 ALE Address latch enable Out 34 62 RD External memory read Out 33 61 READY External memory ready (Voc)() In 16 43 BHE External memory bus high enable Out 15 41 WR External memory write Out 14 40 NOTES: 1. Pins marked with (Vgs) must be connected to Vss. 2. Pins marked with (NC) are to be left unconnected. 3. Pins marked with (Vcc) must be connected to Vc. 4. SS pin reserved for future use. 5. With internal ROM enabled, ADO-AD1 are used as AA and JS. 4-7 www.chipdocs.com Be sure to visit ChipDocs web site for more information. a

89027 PINOUT

[_symbor | __Funetion (89027) [Direction | Pino. | Voc Positive Power Supply (Digital) +5 28 VeB Negative Power Supply —5V 15 Vss Digital Ground DGND 24 AGND Analog Ground AGND 21 AVcc Positive Power Supply (Analog) +5 7 x1 Xtal Oscillator In x2 Xtal Oscillator Out CLKOUT 12.96 MHz Clock output to 89026 Out RST Chip reset (active low) 20 HYB Enable on-chip hybrid 10 AZ1 Auto-zero capacitor input 16 AZ2 Auto-zero capacitor input 17 SDATA Serial data from 89026 2 SCLK Serial clock from 89026 1 TSYNC Transmitter sync from 89026 3 STR Symbol timing to 89026 Out 27 ED Receiver energy detect to 89026 Out 18 | In phase received signal to 89026 Out 13 Q Quadrature-phase received signal to 89026 Out 14 AO1 Transmitter output Out 6 AO2 Receiver input In 12 AMP Output to monitor speaker Out 1 TXO Transmitter level control 9 ™1 Transmitter level control 8 TxX2 Transmitter ‘evel control 5 TX3 Transmitter {evel control 4 Unused pins:19, 22 must be left unconnected. 4-8 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

s intel 89024 T os 5 suk ay, Zs 8 cc soacda aps HEEGSE S oonnpnon Tse 8 26 cuxour ra aE mss 23Pxz . ms 24B Veg rags 2sPax2 sore 23x aos 2455 Woe 7 22FNc Noo Q7 3px cc mos P69027 2150 aGND mos NB9027 22 NC Tmo 9 20 Rst Tons 21 AGND vv 10 19 ne Hye C10 20 ast awe his =i amp Oh 11 19 nc 402} 12 t7Fiazz 1213 1415 161718 iis 16 azi Coocoooo 270222-3 270222-2

28 Pin Plastic Dip 28 Pin PLCC

Figure 6a. 89027 Packages soma: 7 as borst ge ey 2 3 q = Zigu be. g oe scurt2 oBsa okeSub is ghee SB 2 %e noonoononnoonanon omc 4 45D Vece O XTCLK ES 44D AGno ecto 6057 Ado mo é apr qu 59,9 apr jaxd7 abo AGND CJ 12 58—3 D2 roe aie Vrer C15 57F aps Conds Py 401 conric Yeo '4 58 AD4 TsyNc C10 spa ea soe q 4B a Vss 11 BV, Voss] 12 sve SOATA CY 17 S35) a07 eis 789026 5b oe, seuK 18 NB9026 523 08 wm 3sPax2 ToLo G19 51 aos aes sD teu GY 20 sof A010 Reapy C16 330 sAag2 49 Aort sda. 32 o/s ats C4 22 asp ani2 rod 18 nbs cs 2s 47 a013 oR 19 30 RewLe bali bad 46panis oS Cj 20 2s ico OTR E25 45Panis RISC 2t 28 SH XTCLK EY 26 44 SH e/t22 2br 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 ~~ UUUUUOUOUUOUUCOUUO ToL! G25 267 OH 2% Sie iQ /ZIS Sw RIEIZIE Wie = roo Cf 24 apm Big SI Sig 2 # BRIER 3 270222-4 270222-5

46 Pin Plastic Dip 68 Pin PLCC

Figure 6b. 89026 Packages OVERVIEW The reference manual also provides a full descrip- tion of all the “AT” commands and S-registers sup- The 89024 Reference Manual details design infor- ported by the 89024 Modem Chip Set. mation for the 89024 Modem Chip Set. It provides descriptions and specifications of the two chips comprising the 89024, the 89026 and the 89027. In ORDERING INFORMATION addition, it describes the control interface between . the two chips. Intel literature number: 296235-001 4-9 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

2400 BPS INTELLIGENT MODEM CHIP SET

Figure 1. 89024 System Block Diagram www.chipdocs.com Be sure to visit ChipDocs web site for more information.

GENERAL DESCRIPTION serial EEPROM, and RS-232 driver/receivers, repre- sent the circuitry required for implementing an auto- The Intel 89024 chip set is a highly integrated, high dial, auto-answer, 300 to 2400 bps, full duplex performance, intelligent modem, providing a com- Hayes compatible intelligent modem. plete system in two chips. The system conforms to the following CCITT and Bell standards: A complete set of Hayes Smartmodem 2400 com- © CCITT V.22 bis mands is provided for modem configuration and user 2400 bps sync and async intertace. Virtually all PC software written for the 1200 bps sync and async (fall-back) Hayes Smartmodem 2400 can also be used with this chip set. Alternatively, in applications where user * CCITT V.22A&B proprietary modem control commands and features 1200 bps syne and async are desired, the user can replace the 89024 internal 600 bps sync and async (fall-back) command module with custom proprietary software *@ CCITT V.21 resident in the 89026 microcontroller’s on-chip ROM 0 to 300 bps anisochronous or an external memory device. ° bead toe enc and async The 89024 has a set of default features. Upon power 300 bps fall-back mode up, the modem configuration will be in accordance with these default options, unless a different config- * BELL 103 uration has been saved in the external EEPROM 0 to 300 bps anisochronous with the &W command. The 89024 system consists of a 16 bit application The 89024 modem has built in auto-dialing and auto- Specific processor (89026) and an analog front end answering capabilities. It can automatically adapt to device (89027). The 89026 processor performs all _ the proper line signaling mode (Tone or Pulse), and “Digital Signal Processing” algorithm execution for to to the type (CCITT or Bell) and speed of the call- processing the modem signals, as well as providing ing or answering modem. It can also detect and ail modem contro! functions typically performed by _identify call set-up signals of telephone networks, al- an external processor. The analog front end pro- lowing unattended data call operation. vides for 2 wire and 4 wire telephone line interface, D/A conversion, and most of the complex filtering A full set of CCITT V.54 diagnostic loop-tast features functions required in QAM/PSK/FSK modems. Re- _ig supported. The chip set also provides a line signal fer to Figure 1 for a simplified block diagram of the for audio monitoring of call progress, a comprehen- system. sive set of DAA control lines for a simple interface to a the telephone network, and a full complement of In stand-alone modem applications, the 89024 chip TTL level RS-232/ V.24 handshake signals. set along with a Data Access Arrangement (DAA), a NOTICE: Hayes is a registered trademark of Hayes Microcomputer Products, Inc. Smartmodem 2400 is a trademark of Hayes Microcomputer Products, Inc. Smartcom II is a registered trademark of Hayes Microcomputer Products, Inc. 4-11 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

RIK )9 405) conFiG veo 14 sepa .

48 Pin Plastic DIP 68 Pin PLCC

Figure 2. Device Packages www.chipdocs.com Be sure to visit ChipDocs web site for more information.

CALL ESTABLISHMENT, dom tin intitle a disconnect only after a Y1 com- mand. optional disconnect requests originated TERMINATION AND RETRAIN by the remote modem, are of two types, (1) discon- The 89024 modem system incorporates all proto. ect when receiving long-space, and (2) disconnect cols and functions required for automatic (or manu- _— when received carrier is dropped. The modem chip- al) establishment, progress and termination of a _—_-set_ can also be configured to transmit ‘long-space’ data call. just before disconnection, in each of the aforemen- tioned cases. The modem chip-set has a built in auto-dialer, both DTMF and Pulse type, and is capable of automat © Because the CCITT and Bell modem connection cally adapting to the telephone dial type. The dialing protocols are quite different from each other and do sequence on the telephone fink conforms to the —_‘not provide recognition of remote modem type (i.e. CCITT V.25 recommendations. An exception to the _—‘V..22 bis to 212A), the Intel chip-set provides the ad- V.25 is that the interrupted calling tone will not be _ditional capability of identifying the remote modem transmitted by the calling modem, as is suggested in type. This feature is beneficial during the migration V.22 bis. phase of the technology from the 1200 bps to 2400 bps. In North America, where the installed base of The modem can detect the dial, busy and ringback © 1200 bps modems is mostly made-up of 212A type, signals at remote end, and will provide call progress _this feature allows a “Data Base Service Provider” messages to the user. The modem is capable of re- to easily upgrade the existing 212A modems to 2400 dialing the last number dialed, by one command. bps V.22 bis standard, transparently, to 212A users. Similarly, a user with a 89024 based modem system The modem when configured for auto-answer, will can automatically call data bases with either 212A or answer an incoming call, remain silent for the two _—‘V.22 bis modems, without concern over the differ- second billing delay interval, before transmitting the ence. This feature’s benefits are realized in smooth answer tones. Afterwards modem to modem identifi upgrading of data links, with minimum cost and re- cation and handshaking will proceed at a speed and duced disruption in services. Refer to Table 1 for a operating mode acceptable to both ends of the link. detailed description of remote modem compatibility. The data call can also be setup by manual dialing with the modems set to data mode, or by voice to SOFTWARE CONFIGURATION data transfer by means of mechanical switch (exclu COMMANDS sion key), using the SH pin. Once set to data mode, the modem handshaking will proceed before the This section lists the 89024 commands and registers modems will be ready to accept and exchange data. that may be used while configuring the modem. Commands instruct the modem to perform an ac- During data transmission, if one of the modems finds tion, the value in the associated registers determine that the received data is likely to have a high bit error how the commands are performed, and the result rate (indicated by a large mean square error in the | Codes returned by the modem tell the user about the adaptive equalizer), it initiates a retrain sequence. execution of the commands. This automatic retrain feature is only available at 2400 bps, and conforms to CCITT V.22 bis recom- The commands may be entered in a string, with or mendations. without spaces in between. Any spaces within or be- tween commands will be ignored by the modem. Disconnection of the data call can be initiated by the During the entry of any command, the ‘backspace’ DTE at the local end, or by the remote DTE, (if the | key (CNTRL H) can be used to correct any error. modem is configured to accept it). Whether DTR will Upper case or lower case characters can be used in initiate a disconnect, depends on the last &D com- the commands. Commands described in the foliow- mand. Receiving a jong space from a remote mo- ing paragraphs refer to asynchronous terminals us- ing ASCII codes. 4-13 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Table 1. Remote Modem Compatibility

89024 Bell Bell CCITT CCcITT CCITT CCITT

89024 Bell Bell CcITT ccitT ccitt ccitT

be obtained when a 89024 based modem is connected to other modems. www.chipdocs.com Be sure to visit ChipDocs web site for more information.

CONFIGURATION REGISTERS Dial Modifiers The modem stores all the configuration information P Pulse Dial . in a set of registers. Some registers are dedicated to R | Originate call in Answer Mode special command and function, and others are bit- T | Tone Dial mapped, with different commands sharing the regis- S | Dial a stored number ter space to store the command status. W | Wait for dial tone . Delay a dial sequence S* | Ring to Answer 5 Return to command state $1 | Ring Count. (Read Only) Initiate a flash S2 | Escape Code Character @ | Wait for quit $3 | Carriage Return Character If neither P or T is specified in the command S4 Line Feed Character string, the modem automatically selects the $5 | Back Space Character Proper dial mode. $6 | Wait for Dial Tone S7 Wait for Data Carrier Example: S8__ | Pause Time for the Comma Dial Modifier Terminal: AT &Z T 1 (602) 555-1212 $9 | Carrier Detect Response Time Modem: OK S10 | Lost Carrier to Hang Up Delay Result: Modem stores T16025551212 in the ex- S11 | Not Used ternal EEPROM. $12 | Escape Code Guard Time S13 | Not Used The number can be dialed from asynchronous mode $14 *| Bit Mapped Option Register by issuing the following command: S15 | Not Used Terminal: AT DS $16 | Modem Test Options Modem: 1716025551212 $17 | Not Used $18 * | Test Timer or by turning on DTR when in Synchronous Mode 2. $19 | Not Used Up to 33 symbols (dial digits and dial modifiers) may $20 | Not Used be stored. Spaces and other delimiters are ignored | pi - and do not need to be included in the count. If more S21 * | Bit Mapped Options Register than 33 symbols are supplied, the dial string will be S22 * | Bit Mapped Options Register truncated to 33 $23 * | Bit Mapped Options Register ° $24 | Not Used $25 * | Delay to DTR (Sync Only) APPLICATIONS OVERVIEW $26 * | RTS to CTS Delay (Half Dup.) $27 * | Bit Mapped Options Register The biock diagram of a stand-alone 300 to 2400 bps. Hayes compatible modem is depicted in Figure 3. NOTE: The DAA section shown in this diagram may be ob- * These S registers can be stored in the EEPROM. tained with FCC registration, or implemented using the suggested diagram in Figure 4. 4-15 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

SYSTEM COMPATIBILITY SPECIFICATIONS [Parameter | Specification Synchronous 2400 bps +0.01% V.22 bis 1200 bps +0.01% V.22 and 212A 600 bps +0.01 V.22 Asynchronous 2400, 1200, 600 bps, character asynchronous. 0 - 300 bps anisochronous. Asynchronous Speed Range +2.3% —2.5%, extended range option of CCITT standards in character asynchronous mode. Asynchronous Format 8,9,10,11 bits, including start, stop, parity. Synchronous Timing Source Internal, derived from the local oscillator. External, provided by DTE through XTCLK. Slave, derived from the received clock. Telephone Line Interface Two wire full duplex over public switched network or 4 wire leased lines. On-chip hybrid and billing delay timers. Output level —1 to —16 dBm Modulation V.22 bis, 16 point QAM at 600 baud. V.22 and 212A, 4 point QAM at 600 baud. V.21 and 103, binary phase coherent FSK Output Spectral Shaping Square root of 75% raised cosine, QAM/PSK. Transmit Carrier Frequencies V.22 bis, V.22, 212A Originate 1200 Hz + .01% Answer 2400 Hz + .01% V.21 at 300 bps Originate 'space’ 1180Hz + .01% Originate ‘mark’ 980 Hz + .01% Answer ‘space’ 1850 Hz + .01% Answer ‘mark’ 1650 Hz + .01% Bell 103 mode Originate ’space’ 1070 Hz + .01% Originate mark’ 1270 Hz + .01% Answer 'space’ 2020Hz + .01% Answer 'mark’ 2225 Hz + .01% Receive Carrier Frequencies V.22 bis, V.22, 212A Originate 2400 Hz + 7 Hz Answer 1200 Hz + 7 Hz v.21 Originate 'space’ 1850 Hz + 12Hz Originate ‘mark’ 1650 Hz + 12 Hz Answer 'space’ 1180 Hz + 12 Hz Answer ’mark’ 980 Hz + 12 Hz Bell 103 Originate ’space’ 2020 Hz + 12Hz Originate 'mark’ 2225 Hz + 12 Hz Answer ‘space’ 1070 Hz t 12 Hz Answer ’mark’ 1270 Hz + 12 Hz Receiver Sensitivity OFF to ON threshold — 44 dBm at AO2 pin ON to OFF threshold — 46 dBm at AO2 pin Line Equalization Fixed compromise equalization, transmit. Adaptive equalizer for PSK/QAM, receive. Diagnostics Available Local analog loopback. Local digital loopback. Remote digital loopback. Local interface loopback modem. Self Test Pattern Generator Alternate ‘ones’ and ‘zeros’ and error detector, to be used along with most loopbacks. A number indicating the bit errors detected is sent to DTE. 417 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

a TRANSMISSION PERFORMANCE SPECIFICATIONS Test condition: Unconditioned 3002 line, across the full dynamic range. The noise bandwidth is 3 KHz flat. Random Noise Bit Error rate of 1 in 100000 or better at 12 dB SNR at 300 bps, 5 dB SNR at 600 bps, 8 dB SNR at 1200 bps and 16 dB SNR at 2400 bps. FewenyOiees) | a7He | Phase Jitter(1) 2400 bps - 15° peak to peak, at up to 300 Hz. 600, 1200 bps - 45° peak to peak, at up to 300 Hz. NOTE: 1. There is no observable data errors for the received signals, for the above limits of line impairments. These impairments are applied one at a time in absence of noise. OTHER PERFORMANCE SPECIFICATIONS [Parameter | Min | Typ | Max | Units | Comments | DTMF Level [fo TT eam | atar Tone 2ndHarmonic Distortion |__| —=—«(|_—35 | dB | HYB enabled into 6000 DTMF Twist (Balance) A Default Duration Po ms Pulse Dialing Rate Pf to es PO Pulse Dialing Make/Break 39/61 % US 33/67 % UK, Hong Kong Pulse Interdigit Interval [ves fms Billing Delay interval a Guard Tone Frequency 540 Hz Amplitude -3 dB referenced to High channel transmit. Frequency 1800 Hz Amplitude 6 dB ‘ High Channel Transmit Amplitude referenced to Low channel, Guard Tone enabled. Guard Tone 2nd Harmonic Distortion Tone Detection 3 dB Point Passband Frequency Tone Detection OFF to —33 Into 6002. ON Threshold Tone Detection ON to Into 6002 OFF Threshold DialToneDetectDuraton | 30 | | | see [ Ringback Tone Detect Duration 0.75 Cadence 1.5 Off/On Ratio Busy Tone Detect Duration 0.2 Cadence 0.67 Off/On Ratio 4-18 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

89026 OVERVIEW In the transmit operation, the 89026 synthesizes

ples to 89027 over a high speed serial link. and if necessary, returned to asynchronous format. Figure 5. 89026 Block Diagram www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Function (89026) [inno CLKIN 12.96 MHz master clock from 89027 36 67 RST Chip reset (active low) 48 16 I In-phase received signal 43 W Q Quadrature-phase received signal 42 10 STR Symbol Timing from 89027 3 24 ED Energy Detect input 41 9 TSYNC Transmitter sync pulse to 89027 Out 10 35 SDATA Serial Data to 89027 Out 1 17 SCLK Serial Clock to 89027 Out 2 18 OF Off-Hook control to DAA Out 26 33 SH Switch-Hook from dataphone in 28 44 Ri Ring Indicator from DAA In 27 42 AR Aux Relay contro! to DAA Out 25 38 TCL1 NVRAM Data I/O. vo 23 20 TCLO NVRAM SK Out 24 19 B/C 103/V.21 default option In 47 15 S/A NVRAM CE Out 22 ral o/s Dumb/Smart mode select In 32 6 CONFIG Custom Firmware Disable In 40 8 TXD Transmitted data from DTE In 6 27 RXD Received data to DTE Out 8 29 RTS Request to send from DTE In 21 22 crs Clear to Send to DTE Out 20 23 DSR Data Set Ready to DTE Out 19 30 DCD Data Carrier Detect to DTE Out 18 31 DTR Data Terminal Ready from DTE In 4 25 RCLK Received clock to DTE Out 9 34 TCLK Transmit clock to DTE Out 7 28 XTCLK External timing clock from DTE In 5 26 si Speed Indicator to OTE Out 7 32 ss Speed select from DTE(4) in 31 5 EMLB Remote Loopback Command from DTE In 30 7 LCLLB Local Loopback Command from DTE In 29 4 Voc Positive power supply (+ 5V) +5V 38 1 Vpp Ram back-up power +5V 46 14 VREF A/D converter reference +5V 45 13 Vss1 Digital ground GND 1 36 Vss2 Digital ground GND 37 68 AGND Analog ground AGND 44 12 Veps Back-bias generator output Out 12 37 EA External Memory enable In 2 ADO-AD15 External memory access address/data(5) ie) 60-45 AA Auto Answer, Ring Indicator Out 60

3 Jack Select Out 59

www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Function (90028) [inno aepin | eepin | NMI No-maskable Interrupt(Vsg)(1) In - 3 x2 Crystal output(NC)(2) Out 35 66 CLKOUT Clk output (NC)(2) Out : 65 TEST Factory test(Voc)(9) In - 64 INST External memory instruction fetch Out - 63 ALE Address latch enable Out 34 62 RD External memory read Out 33 61 READY External memory ready(Vcc)(3) In 16 43 BHE External memory bus high enable Out 15 41 WR External memory write Out 14 40 NOTES: 1, Pins marked with (Vgs) must be connected to Vss. 2. Pins marked with (NC) are to be left unconnected. 3. Pins marked with (Vcc) must be connected to Vcc. 4. SS pin reserved for future use. 5. With internal ROM enabled, ADO-AD1 are used as AA and JS.

89026 PIN DESCRIPTION be

In async operation, DCD remains Low regardless of XTCLK data carrier (default), or it can be programmed to Transmitter timing from DTE, when external clock _indicate received carrier signal is within the required option is selected. timing and amplitude limits. In sync operation Low indicates the received carrier signal is within the re- TxD quired timing and amplitude limits. The serial data from DTE to be transmitted on the DSA line. A logic "high’ is mark. In synchronous mode, 89026 samples this data on the rising edges of Low indicates modem is off-hook, and it is in data TCLK. transmission mode, and the answer tone is being exchanged. CTS Low indicates modem is prepared TCLK to accept data. Clock output from 89026 as timing source for data ATS exchange from DTE to modem. Serial data is read on the rising edges of the TCLK. This output is High In async mode RTS is ignored, Under command in asynchronous mode. control, in sync mode RTS can be wrered, or the modem can respond with a Low on . RXD — The serial data to DTE. 'Mark’ is a loge, High. in OTR synchronous mode, the rising edge of occurs &D0 command will cause the modem to ignore DTA. in the middle of RXD. For &D1 the modem assumes the asynchronous command state on a Low to High transition of the RCLK OTR circuit. The &D2 commend does the same as Synchronous clock output. Rising edge of ACLK oc- &D1 except the state of will enable/disable curs in the middle of each RXD it. This pin remains auto answer. A Low to High transition of DTR after High in asynchronous mode. the &D3 command will cause the modem to assume the initialization state. Vees B/E gris Feats to AGND through @ | ow configures the modem to CCITT V.21. High will configure the modem to Bell 103, when at 300 bps i) speed. This pin only affects the modem in 300 bps ; operation. A Low indicates maintenance condition in the mo- dem. 4-21 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

TCL1, TCLO EMLB These pins are used as the serial clock and data for A logic Low on this pin initiates a remote loopback interface to an EEPROM. Refer to Figure 3. TCLO is condition. used to output a clock and serial data is read in on TCL1. si — Selects one of the two data rates or ranges of rates AR in the DTE to correspond to the rate in modem. Low This Auxiliary relay control is for switching a relay for selects the higher rate (2400 CCITT/1200 BELL) or voice or data calls. High is voice, Low is data. range of rates. High selects the Low rate or range of rates. Ri = A Low signal from DAA indicates line ringing. This 2/8 input is ignored when the modem is configured for A Low on this pin will indicate the smart mode which leased line. This signal should follow the ring ca- will respond to all commands. A High will ignore ail dence. commands. OH Vrer Low controls off hook. High indicates on hook. Voltage reference for the analog to digital converter When dialing, this control is used to pulse dial the should be connected to the 89027 AVcc. line. Vpp SH The internat RAM power down supply voltage to be Used as a telephone voice to data switch or vice connected to 5 Volts during normal operation. versa. Any logic level transition will toggle the mo- _ dem state. This input is ignored, if a software com- S/A mand attempts to switch the modem between voice ~— The function of this pin is re-defined as external and data. NVRAM CE. AK CONFIG Used as an indicator for Auto Answer status and —_—_L ow enables access to custom software modules. Ring indicator. Active low. [eu EA u High accesses internal memory. Low accesses 6x: A Low will set the modem in the local anslog loop- ternal memory. i back test mode. Logic Low levels applied simulta- neously to REMLB and [CLLB pins, sets the modem Is to the local digital loo) k. 19 the local ara! pbac| Low is used to pulse A and A1 leads to control a 1A2 Key System jack.

89026 ABSOLUTE MAXIMUM “Notice: Stresses above those listed under “Abso-

RATINGS* lute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and Voltage from Any Pin to tional sections of this specification is not implied. Ex- 9 ny _ posure to absolute maximum rating conditions for following tables are subject to change. 4-22 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Ambient Temperature UnderBis | 0 | 70 | Digital Supply Voltage [ars [ss Tv VREF Analog Supply Voltage 4,75 5.25 Vv Voo—.3 Vect.3 v FREQ CLKIN Frequency 12.96 Mhz = 0.01% +oo% |_| PowerDownSuppiyVotage | 475 | 825 | NOTE: Vpas should be connected to AGND through a 0.01 yF capacitor. AGND, Vgg and the 89027 Veg, AGND must be nominally at the same potential. DC CHARACTERISTICS [symbol] Parameter [ Min | Max [Unite] Comments Ni [npe vonage [os] +08] v [oct Input Low Voltage, AST [coal sor [ v [oO Vin input High Voltage Vec+.5} V_ | Except RST, NMI, CLKIN inputigh Voltage. RSTRising | 24 |Veors[ vV [| [Vie [Input high Vonage, RET rating | 24 |Voors| v | inputHigh Voltage, NMLCLKIN, | 24 [Voot5| V | Output Low Vottage r | 04s |_v_|Seenote 1. Output High Voltage [24| | _v_ [SeeNote. Vee Supply Current [| 200 | ma | All outputs disconnected lio | Vpp Supply Current | [1 | ma] Normal operation and Power-Down et [Var Supty Cure [stmt Input Leakage Current || #10 | pa | Vin = 0 to Veg See Note 3 [iin | Input High Current to EA [| 100 | pA |Vm=2.4v Input Low Current [| -100 | pa | Vi = 0.45V See Note 4 Input Low Current to AST [=e [ma [vusoaev Input Low Current S/A, 5H, RI, READY) | —50 | wA | Vu =0.45V Pin Capacitance (Any PintoVes) |_| 10 | pF [ime NOTES: 1. lo, = 0.36 mA for pins TCLO, TCL1, B/C, RTS, CTS, DSR, DCD, Si, AR, and OH. Also if ADO - AD15 are configured as 1/ O ports. lo. = 2.0 mA for TM, CLKOUT, ALE, BHE, RD, WA, RXD, TCLK, and ADO - AD15 when used as external memory bus. 2. lon = —20 pA for pine TCLO, TCL1, B/C, ATS, CTS, DSR, DCD, SI, AR, and OH. lo = ~200 pA for TM, CLKOUT, ALE, BHE, RD, WR, RXD, TCLK, and ADO - AD15 when used as external memory bus. ADO - AD15 when used as |/O ports, have open-drain outputs. 3. For pins DTR, XTCLK, TXD, D/5, SS, FEMS, LCLLB, CONFIG, ADO-AD15. 4. TCLO, TCL1, B/C, RTS. 5. Power must be applied to the device in the following sequence: Vgs first, then Voc. 4-23 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

AC CHARACTERISTICS (Vcc, Vpp = 4.75 to 5.25 Volts; Ta = 0°C to 70°C; CLKIN = 12.96 MHz) Test Conditions: Load capacitance on output pins = 80 pF Frequency = 12.96 MHz Timing Requirements |_Sympot [Parameter | min ax | Units |_Tavov | Address VaiidtoinputDatavaid || sToso—e0 | ns |_tatov | RO ActvetoinputDatavaid |_| aTowo~60 | ns | TRXOx | DataHoldatterAB Inaction) | of ns [__TAxDz | RD Inactotoinput DataFloat(t) | | Tose~20 | ns Timing Responses ae] |_Symbot | Parameter | in| Max [rerac | Gua Freuency Sito oom | [tose [auKnreiog a [cronon | o1kour peed) =|: Tone @) | Stowe | ne | [ Toc. [CLOUT High Time + tose-20 | Tosc+20 | rw | [Teun | cikourtowioaLerigh | -s_ | | ms | [TuLcH | “ALE Lowe cLKOUTHigh | Towe-0| Tosovao [ns | | Tut | AlePusewidth | Toso-25 | Tost [one | [_TaVIC | Addoss Soupiotnaciale | Tore | S| rw | [runt [enor ALE RD orWRactve | Toso-ao [Ss |_Tuax | Address HoidatterEndof ALE | Tosc-20 | [ns | _twiwH | WRpusewith | atoso-ap_ [ns Trowwx | ouputDatasotpioendotWR | atoso-eo | dt re |_Twxox | OutputDataHoldatterEndofWR | Toso-2s | ns [wth enotWRtonetate | arose | is [TTrunH [RB Puso wan —————SS*d atone) id | [_TRHLH | EndotABtonedale | Tose—a6 | |r| NOTES: (1) This specification is not tested, but is verified by design analysis and/or derived from other tested parameters. (2) CLKOUT is directly generated as a divide by 3 of the oscillator. The period will be 3Tosc + 10 nsec if Tose is constant and the rise and fall times on XTAL are less than 10 nsec. 4-24 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Figure 6. Bus Signal Timings www.chipdocs.com Be sure to visit ChipDocs web site for more information.

ceivers, A general block diagram of this chip is pro- fier. put sent to the 89026 processor as analog signals. transmits it to the telephone line. For QAM transmis- rable gain, and a programmable gain transmit signal. analog signal, passed through spectral shaping fil- PLCC packages. Figure 7. 89027 Block Diagram www.chipdocs.com Be sure to visit ChipDocs web site for more information.

a [__symbot__| Function (89027) [Direction | PinNo. | Veco Positive Power Supply (Digital) +5V 28 Ves Negative Power Supply -5V 15 Vss Digital Ground DGND 24 AGND Analog Ground AGND “21 AVcoc Positive Power Supply (Analog) +5 7 xt Xtal Oscillator In x2 Xtal Oscillator Out CLKOUT 12.96 MHz Clock output to 89026 Out RST Chip reset (active low) In 20 HYB Enable on-chip hybrid in 10 AZ1 Auto-zero capacitor Out 16 AZ2 Auto-zero capacitor In 17 SDATA Serial data from 89026 SCLK Serial clock from 89026 TSYNC Transmitter sync from 89026 STR Symbol timing to 89026 Out 27 —ED Receiver energy detect to 89026 Out 18 I In phase received signal to 89026 Out 13 Q Quadrature-phase received signal to 89026 Out 14 AOI Transmitter output 6 AO2 Receiver input 12 AMP. Output to monitor speaker "1 TXO Transmitter level control (LSB) 9 T™1 Transmitter level control 8 TxX2 Transmitter level control 5 TX3 Transmitter levet control (MSB) 4 Unused pins: 19, 22 must be left unconnected.

89027 Pinout Description AO1

Transmitter output. TX0-3 These four pins control the transmitted signal level. AO2 The output {evel can be adjusted from —1 dBm to . —16 dBm in 1 dB steps. Receiver input. HYB AMP This pin enables the on-chip hybrid. A line imped- This output can be used to monitor the call progress ance matching network must be connected between tones and operation of the line. AQ1 and AO2 when HYB is enabled. If HYB is dis- abled and an external 4W/2W hybrid is used, the hybrid receive path must be amplified by 6 dB. 4-27 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

All Input and Output Voltages NOTE: All Input and Output Voltages HYB, TXO-TX3 only. POWER DISSIPATION Ambient Temp = 0° to 70° C, Voc= AVoc= 5 + 5%, Vgg= AGND= 0. [_symoor [Parameter | min_ [Typ | Max | Unite |e | Voc Operating Current a ee ee ee |_tboi__ [Vee Operating Current a ee ee eee DC CHARACTERISTICS (Ta=0°C to 70°C, Voc = +5%, Vag = +5%, AGND = Vgg = OV), supply voltage must be at the same potential as the 89026 power supply. Typical Values are for Ta = 25°C and nominal power supply values. Power must be applied in the following sequence: Vss, AGND, Vga, Voc, and AVcc. Voc, AVcc and 89206 Vrer must be nominally at the same potential. Digital Inputs: TXO, TX1, TX2, TX3, HYB, RST Digital Outputs: CLKOUT [ symbol] Parameter | _Min_| typ | Max | units | TestConaition OuputLowvotage | || 0 |v | tole -1.6mA,1 TTL load OutputHigh Votage | 24 | | |v | ich < 60ua, 1 TTL toad [veer | cixourtowvotage |_| | oa | v | cr=eopr | 4-28 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Figure 8. Crystal Equivalent Circuit www.chipdocs.com Be sure to visit ChipDocs web site for more information.

1. For FSK, PSK, QAM xmit signal. HYB is enabled into a 6002 network and measured at AO2. Refer to Figure 9 for test

89027 E 6002

Figure 9. Transmitter Test Setup

89024 REFERENCE MANUAL The reference manual also provides a full descrip-

Ported by the 89024 Modem Chip Set. www.chipdocs.com Be sure to visit ChipDocs web site for more information.