8XC198 INTEL | Alldatasheet
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*Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. October 1992COPYRIGHT © INTEL CORPORATION, 1995 Order Number: 272034-003 8XC198 COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER
8 Kbytes of OTPROM
Y 8 Kbytes of On-Chip OTPROM or ROM Y 232 Byte Register File Y Register-to-Register Architecture Y 28 Interrupt Sources/16 Vectors Y 1.75 ms 16 x 16 Multiply (16 MHz) Y 3.0 ms 32/16 Divide (16 MHz) Y Powerdown and Idle Modes Y 16-Bit Watchdog Timer Y 8-Bit External Bus Y 16 MHz Standard Y Full Duplex Serial Port Y High Speed I/O Subsystem Y 16-Bit Timer Y 16-Bit Counter Y Pulse-Width-Modulated Output Y Four 16-Bit Software Timers Y 10-Bit A/D Converter with Sample/Hold Y Extended Temperature Available The 8XC198 family offers low-cost entry into Intel’s powerful MCS É-96 16-bit microcontroller architecture. Intel’s CHMOS process provides a high performance processor along with low power consumption. To further reduce power requirements, the processor can be placed into Idle or Powerdown Mode. The 8XC198 is the 8-bit bus version of the 8XC196KB. The prefixes mean: 80 (ROMless), 83 (ROM), 87 (OTP) One Time Programmable. The ROM and OTP are available in 8 Kbytes. Bit, byte, word and some 32-bit operations are available on the 8XC198. With a 16 MHz oscillator a 16-bit addition takes 0.50 ms, and the instruction times average 0.37 ms to 1.1 ms in typical applications. Four high-speed capture inputs are provided to record times when events occur. Six high-speed outputs are available for pulse or waveform generation. The high-speed output can also generate four software timers or start an A/D conversion. Events can be based on the timer or counter. Also provided on-chip are an A/D converter, serial port, watchdog timer and a pulse-width-modulated output signal. With the commercial (standard) temperature option, operational characteristics are guaranteed over the tem- perature range of 0 §Ct o a70§C. Wth the extended temperature range option, operational characteristics are guaranteed over the temperature range of b40§Ct o a85§C. MCSÉ-96 is a registered trademark of Intel Corporation.
office to determine the exact ordering code for the part desired. 240800) for a description of Intel’s thermal impedance test methodology. Figure 4. 52-Pin PLCC Package doesn’t use any of the programming pins.
N.C. means No Connect (do not connect these pins). Figure 5. 80-Pin QFP Package doesn’t use any of the programming pins.
VCC Main supply voltage (5V). VSS The PLCC package has 5 V SS pins and the QFP package has 12 V SS pins. All must be connected to digital ground. VREF Reference voltage for the A/D converter (5V). V REF is also the supply voltage to the analog portion of the A/D converter and the logic used to read Port 0. Must be connected for A/D and Port 0 to function. ANGND Reference ground for the A/D converter. Must be held at nominally the same potential as V SS. VPP Programming Voltage. Also, timing pin for the return from powerdown circuit. XTAL1 Input of the oscillator inverter and of the internal clock generator. XTAL2 Output of the oscillator inverter. RESET Reset input to and open-drain output from the chip. Input low for at least 4 state times to reset the chip. The subsequent low-to-high transition commences the 10-state Reset Sequence. INST Output high during an external memory read indicates the read is an instruction fetch. INST is valid throughout the bus cycle. INST is activated only during external memory accesses and output low for a data fetch. EA Input for memory select (External Access). EA equal to a TTL-high causes memory accesses to locations 2000H through 3FFFH to be directed to on-chip ROM/EPROM. EA equal to a TTL-low causes accesses to these locations to be directed to off-chip memory. ALE/ADV Address Latch Enable or Address Valid output, as selected by CCR. Both pin options provide a latch to demultiplex the address from the address/data bus. When the pin is ADV , it goes inactive high at the end of the bus cycle. ALE/ADV is activated only during external memory accesses. RD Read signal output to external memory. RD is activated only during external memory reads. WR Write output to external memory. WR will go low for every external write. READY Ready input to lengthen external memory cycles. When the external memory is not being used, READY has no effect. Internal control of the number of wait states inserted into a bus cycle held not ready is available through configuration of CCR. HSI Inputs to High Speed Input Unit. Four HSI pins are available: HSI.0, HSI.1, HSI.2 and HSO Outputs from High Speed Output Unit. Six HSO pins are available: HSO.0, HSO.1, HSI Unit. Port 0 4-bit high impedance input-only port. These pins can be used as digital inputs and/or as analog inputs to the on-chip A/D converter. These pins set the Programming Mode on the EPROM device.
PIN DESCRIPTIONS (Continued) Symbol Name and Function Port 2 Multi-functional port. All of its pins are shared with other functions in the 80C198. Ports 3 and 4 8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the multiplexed address/data bus which has strong internal pullups. Available as I/O only on the ROM and EPROM devices. TxD The TxD pin is used for serial port transmission in Modes 1, 2 and 3. In mode 0 the pin is used as the serial clock output. RxD Serial Port Receive pin used for serial port reception. In mode 0 the pin functions as input or output data. EXTINT A positive transition on the EXTINT pin will generate an external interrupt. T2CLK The T2CLK pin is the Timer2 clock input or the serial port baud rate generator input. T2RST A rising edge on the T2RST pin will reset Timer2. PWM The PWM output. PMODE Programming Mode Select. Determines the EPROM programming algorithm that is performed. PMODE is sampled after a chip reset and should be static while the part is operating. SID Slave ID Number. Used to assign each slave a pin of Port 3 or 4 to use for passing programming verification acknowledgement. PALE Programming ALE Input. Accepted by the 87C196KB when it is in Slave Programming Mode. Used to indicate that Ports 3 and 4 contain a command/ address. PROG Programming. Falling edge indicates valid data on PBUS and the beginning of programming. Rising edge indicates end of programming. PVAL Program Valid. This signal indicates the success or failure of programming in the Auto Programming Mode. A zero indicates successful programming. PVER Program Verification. Used in Slave Programming and Auto CLB Programming Modes. Signal is low after rising edge of PROG if the programming was not successful. AINC Auto Increment. Active low signal indicates that the auto increment mode is enabled. Auto Increment will allow reading or writing of sequential EPROM locations without address transactions across the PBUS for each read or write. PORTS 3 and 4 Address/Command/Data Bus. Used to pass commands, addresses, and data to and from slave mode 87C196KBs. Used by chips in Auto Programming Mode to(when programming) pass command, addresses and data to slaves. Also used in the Auto Programming Mode as a regular system bus to access external memory. Should have pullups to V CC (15 k X).
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS * Ambient Temperature under BiasÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b55§Ct o a125§C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b65§Ct o a150§C Voltage on V PP or EA to VSS or ANGND ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b0.3V to a13.0V Voltage on Any Other Pin to V SS ÀÀb0.5V to a7.0V Power Dissipation (1) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W NOTE: 1. Power dissipation is based on package heat transfer lim- itations, not device power consumption. NOTICE: This data sheet contains preliminary infor- mation on new products in production. It is valid for the devices indicated in the revision history. The specifications are subject to change without notice. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. OPERATING CONDITIONS (All characteristics in this data sheet apply to these operating conditions unless otherwise noted.) Symbol Description Min Max Units TA Ambient Temperature Under Bias 0 a70 §C VCC Digital Supply Voltage 4.50 5.50 V VREF Analog Supply Voltage 4.50 5.50 V FOSC Oscillator Frequency 16 MHz 3.5 16 MHz NOTE: ANGND and V SS should be nominally at the same potential. DC CHARACTERISTICS Symbol Description Min Max Units Test Conditions VIL Input Low Voltage b0.5 0.8 V VIH Input High Voltage (1) 0.2 V CC a 0.9 V CC a 0.5 V VIH1 Input High Voltage on XTAL1 0.7 V CC VCC a 0.5 V VIH2 Input High Voltage on RESET 2.6 V CC a 0.5 V VOL Output Low Voltage 0.3 V I OL e 200 mA
0.45 V I OL e 32 mA
1.5 V I OL e 7m A
VOH Output High Voltage V CC b 0.3 V I OH eb 200 mA (Standard Outputs) V CC b 0.7 V I OH eb 3.2 mA VCC b 1.5 V I OH eb 7m A ILI Input Leakage Current (Std. Inputs) g10 mA0 k VIN k VCC b 0.3V ILI1 Input Leakage Current (Port 0) a3 mA0 k VIN k VREF IIL1 Logical 0 Input Current in Reset b6m A V IN e 0.45 V (ALE, RD , INST) Hyst Hysteresis on RESET Pin 300 mV NOTE: 1. All pins except RESET and XTAL1.
- Standard Outputs include AD0–15, RD
RXD (in serial mode 0). The V OH specification is not valid for RESET. Ports 3 and 4 are open-drain outputs.
- Maximum current per pin must be externally limited to the following values if V OL is held above 0.45V or V OH is held
- Maximum current per bus pin (data and control) during normal operation is g3.2 mA.
- During normal (non-transient) conditions the following total current limits apply:
- Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature
Figure 8. I CC and I IDLE vs Frequency
Test Conditions: Capacitive load on all pins e 100 pF, Rise and fall times e 10 ns, F OSC e 12/16 MHz The system must meet these specifications to work with the 87C198: Symbol Description Min Max Units Notes TAVYV Address Valid to Ready Setup 2 T OSC b 75 ns TYLYH Non READY Time No upper limit ns TLLYX READY Hold after ALE Low T OSC b 15 2 T OSC b 40 ns (Note 1) TAVDV Address Valid to Input Data Valid 3 T OSC b 55 ns (Note 2) TRLDV RD Active to Input Data Valid T OSC b 23 ns (Note 2) TRHDZ End of RD to Input Data Float T OSC b 20 ns TRXDX Data Hold after RD Inactive 0 ns NOTES: 1. If max is exceeded, additional wait states will occur. 2. When using wait states, add 2 T OSC c n, where n e number of wait states.
Test Conditions: Capacitive load on all pins e 100 pF, Rise and fall times e 10 ns, F OSC e 12/16 MHz The 87C198 will meet these specifications: Symbol Description Min Max Units Notes FXTAL Frequency on XTAL1 12 MHz 3.5 12 MHz (Note 1) FXTAL Frequency on XTAL1 16 MHz 3.5 16 MHz (Note 1) TOSC 1/FXTAL 12 MHz 83.3 286 ns TOSC 1/FXTAL 16 MHz 62.5 286 ns TLHLH ALE Cycle Time 4 T OSC ns (Note 3) TLHLL ALE High Period T OSC b 10 T OSCa10 ns TAVLL Address Setup to ALE Falling Edge T OSC b 20 ns TLLAX Address Hold after ALE Falling Edge T OSC b 40 ns TLLRL ALE Falling Edge to RD Falling Edge T OSC b 35 ns TRLRH RD Low Period T OSC b 5T OSC a 25 ns (Note 3) TRHLH RD Rising Edge to ALE Rising Edge T OSC TOSC a 25 ns (Note 2) TRLAZ RD Low to Address Float 5 ns TLLWL ALE Falling Edge to WR Falling Edge T OSC b 10 ns TQVWH Data Stable to WR Rising Edge T OSC b 23 ns (Note 3) TWLWH WR Low Period T OSC b 15 T OSC a 5 ns (Note 3) TWHQX Data Hold after WR Rising Edge T OSC b 15 ns TWHLH WR Rising Edge to ALE Rising Edge T OSC b 15 T OSC a 10 ns (Note 2) TWHBX INST Hold after WR Rising Edge T OSC b 15 ns TLLBX INST Hold after ALE Rising Edge T OSC b 10 ns TRHBX INST Hold after RD Rising Edge T OSC b 10 ns TWHAX AD8–15 Hold after WR Rising Edge T OSC b 30 ns TRHAX AD8–15 Hold after RD Rising Edge T OSC b 25 ns NOTES: 1. Testing performed at 3.5 MHz. However, the part is static by design and will typically operate below 1 Hz. 2. Assuming back-to-back bus cycles. 3. When using wait states, add 2 T OSC c n, where n e number of wait states.
272034–23
READY Timings (One Wait State) 272034–24 EXTERNAL CLOCK DRIVE Symbol Parameter Min Max Units 1/TXLXL Oscillator Frequency 12 MHz 3.5 12.0 MHz 1/TXLXL Oscillator Frequency 16 MHz 3.5 16.0 MHz TXLXL Oscillator Period 12 MHz 83.3 286 ns TXLXL Oscillator Period 16 MHz 62.5 286 ns TXHXX High Time 21.25 ns TXLXX Low Time 21.25 ns TXLXH Rise Time 10 ns TXHXL Fall Time 10 ns EXTERNAL CLOCK DRIVE WAVEFORMS 272034–25 An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts-up. This is due to interaction between the amplifier and its feedback capacitance. Once the external signal meets the V IL and VIH specifications the capacitance will not exceed 20 pF.
EXTERNAL CRYSTAL CONNECTIONS 272034–32 NOTE: Keep oscillator components close to chip and use short direct traces to XTAL1, XTAL2 and V SS. When using crystals, C1 e 20 pF, C2 e 20 pF. When using ceramic resonators consult manufacturer for recom- mended capacitor values. EXTERNAL CLOCK CONNECTIONS 272034–33 NOTE: *Required if open collector TTL driver used. Not need- ed if CMOS driver is used.AC TESTING INPUT, OUTPUT WAVEFORMS 272034–26 AC Testing inputs are driven at 2.4V for a Logic ‘‘1’’ and 0.45V for a Logic ‘‘0’’ Timing measurements are made at 2.0V for a Logic ‘‘1’’ and 0.8V for a Logic ‘‘0’’. FLOAT WAVEFORMS 272034–27 For Timing Purposes a Port Pin is no Longer Floating when a 200 mV change from Load Voltage Occurs and Begins to Float when a 200 mV change from the Loaded V OH/VOL Level occurs IOL/IOH e g15 mA. EXPLANATION OF AC SYMBOLS Each symbol is two pairs of letters prefixed by ‘‘T’’ for time. The characters in a pair indicate a signal and its condition, respectively. Symbols represent the time between the two signal/condition points. Conditions: H - High L - Low V - Valid X - No Longer Valid Z - Floating Signals: A - Address D - DATA IN L - ALE/ADV Q - DATA OUT R- R D W- W R X - XTAL1 Y - READY
10-BIT AID CHARACTERISTICS At a clock speed of 6 MHz or less, the clock prescal- er should be disabled. This is accomplished by set- ting IOC2.4 e 1. At higher frequencies (greater than 6 MHz) the clock prescaler should be turned on (IOC2.4 e 0) to allow the comparator to settle. The table below shows two different clock speeds and their corresponding A/D conversion and sample times. State times are calculated as follows: state time e 2 fXTAL1 The converter is ratiometric, so the absolute accura- cy is directly dependent on the accuracy and stability of V REF.V REF must be close to V CC since it supplies both the resistor ladder and the digital section of the converter. See the MCS-96 A/D Converter Quick Reference for definition of A/D terms. Example Sample and Conversion Times AID Clock Clock Speed Sample Time Sample Time Conversion Conversion Prescaler (MHz) (States) at Clock Time Time at Clock Speed ( ms) (States) Speed ( ms) IOC2.4e0xON 16 15 1.875 156.5 19.6 IOC2.4e1xOFF 6 8 2.667 89.5 29.8 A/D CONVERTER SPECIFICATIONS Parameter Typical(1) Minimum Maximum Units * Notes Resolution 1024 1024 Levels 10 10 Bits Absolute Error 0 g3 LSBs Full Scale Error 0.25 g0.50 LSBs Zero Offset Error b0.25 g0.50 LSBs Non-Linearity Error 1.5 g2.5 0 g3 LSBs Differential Non-Linearity Error lb1 a2 LSBs Channel-to-Channel Matching g0.1 0 g1 LSBs Repeatability g0.25 LSBs Temperature Coefficients: Offset 0.009 LSB/ §C Full Scale 0.009 LSB/ §C Differential Non-Linearity 0.009 LSB/ §C Off Isolation b60 dB 2, 3 Feedthrough b60 dB 2 VCC Power Supply Rejection b60 dB 2 Input Series Resistance 750 1.2K X 4 DC Input Leakage 0 3.0 mA Sample Time: Prescaler On 15 States Prescaler Off 8 States Sampling Capacitor 3 pF NOTES: *An ‘‘LSB’’, as used here, has a value of approximately 5 mV. 1. Typical values are expected for most devices at 25 §C but are not tested or guaranteed. 2. DC to 100 KHz. 3. Multiplexer Break-Before-Make Guaranteed. 4. Resistance from device pin, through internal MUX, to sample capacitor.
EPROM PROGRAMMING OPERATING CONDITIONS Symbol Parameter Min Max Units TA Ambient Temperature during Programming 20 30 §C VCC,V PD,V REF(1) Supply Voltages during Programming 4.5 5.5 V VEA Programming Mode Supply Voltage 12.50 13.0 V (2) VPP EPROM Programming Supply Voltage 12.50 13.0 V (2) VSS, Digital and Analog Ground 0 0 V ANGND(3) FOSC Oscillator Frequency 16 MHz 6.0 16.0 MHz NOTES: 1. V CC,V PD and V REF should nominally be at the same voltage during programming. 2. V EA and V PP must never exceed the maximum voltage for any amount of time or the device may be damaged. 3. V SS and ANGND should nominally be at the same voltage (0V) during programming. AC EPROM PROGRAMMING CHARACTERISTICS Symbol Description Min Max Units TSHLL Reset High to First PALE Low 1100 T OSC TLLLH PALE Pulse Width 40 T OSC TAVLL Address Setup Time 0 T OSC TLLAX Address Hold Time 50 T OSC TLLVL PALE Low to PVER Low 60 T OSC TPLDV PROG Low to Word Dump Valid 50 T OSC TPHDX Word Dump Data Hold 50 T OSC TDVPL Data Setup Time 0 T OSC TPLDX Data Hold Time 50 T OSC TPLPH PROG Pulse Width 40 T OSC TPHLL PROG High to Next PALE Low 120 T OSC TLHPL PALE High to PROG Low 220 T OSC TPHPL PROG High to Next PROG Low 120 T OSC TPHIL PROG High to AINC Low 0 T OSC TILIH AINC Pulse Width 40 T OSC TILVH PVER Hold after AINC Low 50 T OSC TILPL AINC Low to PROG Low 170 T OSC TPHVL PROG High to PVER Low 90 T OSC DC EPROM PROGRAMMING CHARACTERISTICS Symbol Description Min Max Units IPP VPP Supply Current (When Programming) 100 mA
EPROM PROGRAMMING WAVEFORMS SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE 272034–28 SLAVE PROGRAMMING MODE IN WORD DUMP OR DATA VERIFY MODE WITH AUTO INCREMENT 272034–29
SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM MODE WITH REPEATED PROG PULSE AND AUTO INCREMENT 272034–30
AC CHARACTERISTICSÐSERIAL PORTÐSHIFT REGISTER MODE SERIAL PORT TIMINGÐSHIFT REGISTER MODE Symbol Parameter Min Max Units TXLXL Serial Port Clock Period (BRR t 8002H) 6 T OSC ns TXLXH Serial Port Clock Falling Edge 4 T OSC b 50 4 T OSC a 50 ns to Rising Edge (BRR t 8002H) TXLXL Serial Port Clock Period (BRR e 8001H) 4 T OSC ns TXLXH Serial Port Clock Falling Edge 2 T OSC b 50 2 T OSC a 50 ns to Rising Edge (BRR e 8001H) TQVXH Output Data Setup to Clock Rising Edge 2 T OSC b 50 ns TXHQX Output Data Hold after Clock Rising Edge 2 T OSC b 50 ns TXHQV Next Output Data Valid after Clock Rising Edge 2 T OSC a 50 ns TDVXH Input Data Setup to Clock Rising Edge T OSC a 50 ns TXHDX Input Data Hold after Clock Rising Edge 0 ns TXHQZ Last Clock Rising to Output Float 2 T OSC ns WAVEFORMÐSERIAL PORTÐSHIFT REGISTER MODE SERIAL PORT WAVEFORMÐSHIFT REGISTER MODE 272034–31
Devices marked with an ‘‘E’’, ‘‘F’’, or ‘‘G’’ have the following errata. 1. HIGH SPEED INPUTS The High Speed Input (HSI) has three deviations from the specifications. NOTE: ‘‘Events’’ are defined as one or more pin tran- sitions. ‘‘Entries’’ are defined as the recording of one or more events. A. The resolution is nine states instead of eight states. Events occurring on the same pin more frequently than once every nine states may be lost. B. A mismatch between the nine state HSI resolu- tion and the eight state hardware timer causes one time-tag value to be skipped every nine timer counts. Events may receive a time-tag one count later than expected. C. If the FIFO and Holding Register are empty, the first event will transfer into the Holding Register, leaving the FIFO empty again. The next event that occurs will be the first event loaded into the empty FIFO. If the first two events into an empty FIFO (not counting the Holding Register) occur coincident with each other, both are recorded as one entry with one time-tag. If the second event occurs within 9 states after the first, the events will be entered separately with time-tags at least one count apart. If the second event enters the FIFO coincident with the ‘‘skipped’’ time-tag situ- ation (see B above) the time-tags will be at least two counts apart. 2. CMPL with R0 Using CMPL with register 0 can set incorrect flags. Don’t use register 0 with the compare long instruc- tion. Use another long word register and set it equal to zero. See Techbit MC0692.
REVISION HISTORY
This data sheet (272034-003) is valid for devices marked with an ‘‘E’’, ‘‘F’’, or ‘‘G’’ at the end of the top side tracking number. Data sheets are changed as new device information becomes available. Verify with your local Intel sales office that you have the latest version before finalizing a design or ordering devices. The following differences exist between this data sheet and the previous version (-002). 1. This data sheet added the ROMless and ROM devices 80C198 and 83C198 respectively. 2. The description of the A/D converter prescalar bit was improved.