85C220 INTEL | Alldatasheet
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intel. 85C220/85C224-100, -80 AND -66 FAST REGISTERED SPEED Tey, Tso 8-MACROCELL PLDs These register optimized timing PLDs offer superior design features:
10 Dedicated and
= Low-Power, High-Performance Upgrade @ UP to 18 Inputs (1 for SSI/MSI Logic and Bipolar PALs* 8 1/0) and 8 Outputs High-Performance Systems @ Programmable “Security Bit” Allows = Replacement or Upgrade for 16V8/ Total Protection of Proprietary Designs 20V8 PAL and GAL Architecture @ 100% Generally Tested Logic Array @ 8 Macrocells with Independently Programmable I/O Architecture 85C220-100 AND 85C224-100 85C220-80 AND 85C224-80 @ 100 MHz Max Frequency (External @ Quarter Power (icc = 40 mA); Feedback); 5.5 ns (Max) Clock to Programmable Zero Power Mode Output; 4.5 ns (Min) Set-Up Time (50 »A Typical) @ Meets Critical Timing Requirements of @ 80 MHz Max Frequency (External Advanced Intel Microprocessor Feedback); 5.5 ns (Max) Clock to Systems Output; 7 ns (Min) Set-Up Time @ 7.5 ns (Max) Propagation Delay @ 10 ns Propagation Delay @ Typical Ic¢g = 90 mA @ High-Speed Upgrade to EP320, EP330, Available in 20-Pin and 28-Pin PLCC and 6C032 Packages @ Available in 300-mil 20-Pin and 24-Pin CerDIP/PDIP Packages, and 20-Pin and @ Low Power and Output Skew for Clock ” Device Applications 28-Pin PLCC Packages Inte!386™, i486™ and i860™ are trademarks of intel Corporation. *PAL is a registered trademark of Advanced Micro Devices. October 1993, 2-74 Order Number: 290224-005
we7t7 havo necde N85C224 OE. Figure 1. Pinout Diagrams
85C220/85C224-100, -80 AND -66 intel e INTRODUCTION ‘As shown in Figures 2 and 3, the 85C220/85C224 contains 10/14 dedicated inputs and 8 1/O pins. The Intel 85C220/85C224 8-micron CHMOS pPLD — Each I/O pin can be individually programmed to (Microcomputer Programmable Logic Device) is ca- function as an input, output, or bidirectional I/O pin. pable of implementing over 300 equivalent gates of Associated with each 1/O pin is a programmable user-customized logic functions through program- _ macrocell. ming. With its flexible 1/O architecture and fast speeds, this device has functional capabilities that Figures 4 and 5 show the structure of the 85C220/ ‘surpass those of typical programmable logic devic- 85C224 macrocell. Each macrocell includes a es. This device can be used to upgrade high-speed _p-term (product term) block with eight AND p-terms bipolar programmable logic devices and 74-series feeding the OR gate of the I/O control block and LS and CMOS SSI and MSI logic devices in bus con- one additional p-term controlling the output buffer. trol and state-machine applications for Advanced In- The logic array is 36 rows wide, allowing each tel Microprocessors, i486™, Intel386™, and Intel __p-term in the device to connect to the true or com- i8607™-based systems and other high-performance plement of each input and I/O feedback signal Processors. The 85C220/85C224 can also be used _Each intersecting point in the logic array is connect- as a direct, low-power replacement for almost all ed or not connected based on the value pro- high-speed 20-pin and 24-pin fuse-based program- grammed in the EPROM array. Initially (EPROM mable logic devices. erased state), all p-terms are connected to alll sig- nals. Connections are broken by programming the The 85C220/85C224 uses advanced EPROM cells appropriate EPROM cells. Connecting both the true as architecture and logic control memory elements. and complement of a signal for a given p-term re- Coupled with Intel's proprietary CHMOS IIE technol- moves that p-term from the SOP for the macrocell ogy, these devices offer a fast tep in combinatorial _(ie., that p-term is a “don't care”). mode, with current consumption much lower than bipolar devices of equivalent speed. The maximum Figure 6 shows the architecture of each macrocell’s “count” frequencies of 100 MHZ and 80 MHz are _!/O control block. The SOP input to the 1/O control ‘optimized for high-performance state machines typi. block can be inverted or non-inverted. The output cally encountered in bus control applications. can be registered or combinatorial. When registered EPROM technology allows these devices to be output is selected, feedback to the logic array 100% factory tested by programming and erasing all comes directly from the register (before the output the EPROM logic control elements. butfer). When combinatorial output is selected, teed- : back comes from the I/O pin (after the output buffer) The inherent speed of the device together with its and can be used for bidirectional I/O. The register is lower power demands and plastic package make the D-type register that clocks on the rising edge of 85C220/85C224 an ideal production vehicle for CLK. high-volume manufacturing of high-performance systems. The 85C220/85C224 will improve perform- ance and reliability, while decreasing system noise, 20-PIN AND 24-PIN PLD power consumption and heat generation. COMPATIBILITY The 85C220/85C224 is designed to be a logical su- ARCHITECTURE DESCRIPTION perset of most high-speed 20-pin and 24-pin bipolar PAL and GAL devices. The I/O and logic sections of The architecture of the 85C220/85C224 is based on _the device can be configured to emulate any of the the SOP (Sum of Products) PAL structure with apro- devices listed below. Designers can often replace grammable AND array feeding into a fixed OR array. multiple PALs with fewer 85C220/85C224 devices. Programmable macrocells allow the device to ac- Tables 1 and 2 include some of the devices with commodate both combinatorial and sequential logic which the 85C220/85C224 are compatible. functions, Each macrocell is individually programma- ble for combinatorial or registered output. An invert option on the SOP allows each output to be config- ured as an active-high or active-low output. 2-76 |
Table 1. Replacement/Upgrade Table 2. Replacement/Upgrade
Figure 2. 85C220 Global Architecture
Figure 3. 85C224 Global Architecture
Figure 4. 85C220 Macrocell Architecture
2 SS SS << an
Figure 5. 85C224 Macrocell Architecture
Figure 7. 85C220/85C224 Standby and Active Mode Transitions erasure time with this dosage is approximately 1 ming.
85C220/85C224-100, -80 AND -66 intel CHMOS IIIE EPROM process. Thus, each of the — PLDshell Plus software is a free design package that pins will not experierice latch-up with currents up to. accepts PALASM 2-compatible source _ files. +100 mA and voltages ranging from —0.5V to (Vcc PLDshell Plus software allows you to design in a fa- + 0.5V). The programming pin is designed to resist. —_miliar language and to functionally simulate your de- latch-up to the 13.5V maximum device limit. sign. You can also invoke third-party design pack- ages directly from the PLDshell Run menu. DESIGN RECOMMENDATIONS iPLS Il includes the LOC (Logic Optimizing Compiler) _ and APT (Advanced Programming Tool), For de- For proper operation, it is recommended that all in- tailed information on iPLS Il, refer to the iPLDS |! put and output pins be constrained to the voltage —_Data Sheet, order number: 290134. range GND < (Vix or Vout) < Vcc. All unused in- puts and I/Os should be tied high or low to minimize The following ADF primitives are supported by this power consumption (do not leave them floating). On device: the 85C224 PLCC package, the optional power pin INP RONF (pin 1) and optional ground pins (8, 15, and 22) may be connected to power and ground, respectively, to CONF RORF reduce output switching noise. A high-speed power COIF NORF supply decoupling capacitor of at least 0.2 pF must be connected directly between the Voc and GND pins. PROGRAMMING SUPPORT As with all CMOS devices, ESD handling procedures Programming for the 85C220 is supported by APT should be used with the devices to prevent damage —_ on the GUPI 20D20J Programming Adaptor using ei- to the devices during programming, assembly, and ther an iUP-PC Personal Programmer or an iUP- test. 200A/201A Universal Programmer. Programming for the 85C224 is supported by the same software/ platforms using the GUPI 24D28J Programming COMPILER SUPPORT Adaptor. The 85C220 and 85C224 are supported by Intel's 85C220/85C224 programming support is also pro- PLDshell Plus software as well as third-party logic vided by third-party programmer companies such as compilers such as ABEL*, CUPL", PLDDesigner’, —_Data I/O, Logical Devices, STAG, etc. Please refer Log/IC*, etc. to the “Programming Support” lists in the Program- ‘mable Logic handbook for complete information and vendor contacts.
ORDERING INFORMATION
tpp | Order Code Order Code ts | ats | | Sst | seit | rea | onatnarae | 100 | 16 | 75 | Nascz20-100 | Nes0224-100 "1 besc220-80 | Dasc224-80 Commercial P85C220-80 pesc224-80 | POP | N85C220-80 NasC224-80 PLCC 90.9 085C220-66 0e5C224-66 | +CerDIP Commercial Pasc220-66 | Pasceed66 | POP | N85C220-66 N85C224-66 PLCC Windowed CerDIP package allows UV erase. “ABEL is a trademark of Data !/O, Corporation. CUPL is a trademark of Logical Devices, Inc. PLDesigner is a trademark of MING, Inc. 2-84 |
intel ° 85C220/85C224-100, -80 AND -66 ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi- Supply Vol ” soy cations are subject to change without notice. Programming Supply Maximum Ratings” may cause permanent damage. Storage Temperature (Tsra) «...—65°C to +150°C Iravianart noni kcoiys Peratina Conditions Ambient Temperature (Tawa)() ..~ 10°C to + 85°C NOTES: 1. Voltages with respect to GND. Puts may undershoot to —2.0V or overshoot to +7.0V for periods of less than 20 ns under no load conditions. 3. Under bias. Extended Temperature versions are also available, . RECOMMENDED OPERATING CONDITIONS Supply Voltage Input Voltage ee ee Output Voltage a Operating Temperature | oo | +70 || Input Rise Time re ee ee D.C. CHARACTERISTICS (Ta, = 0°C to +70°C, Voc = 5.0V +5%) 85C220/85C224-100 [Symbot] Parameter [in [Typ | Max _[ unit] Test Conditions High Levelinputvotage | 20 | |Voo+os[ v [7 High Level Output Votage | 24 [ | ‘| _v_|vo= -4.0mADC.,Voc = Min LowLevelOutputVoitage | | | 048 | V | 1/0 = 24.0mADG. Voc = Min [i mputLeakage Curent [| | #10 | mA | Vog = Max, GND < Vin < Voc Output Leakage Current +10 | pA | Voc = Max, GND < Vout < Voc ['scf® | Output Shor Circuit Gurrent| —30| | 120 _| mA | Vog = Max, Vour = 05V Power Supply Current mA | Voc = Max, Vin = Voc or GND, No Load, fiy = 25 MHz, Device Prog. as an 8-Bit Counter [ote faa come | 2-85
85C220/85C224-100, -80 AND -66 intel 85C220/85C224-80 and -66 [symbot[ Parameter |_in [typ | Max | Unit] Test Conditions HighLevelinputvottage | 20 | | vooros| v | | LowLevelinputvotage [os] | os |v [oo High Level OutputVoltage [| 24 | | | Vv | Ip = —4.0mAD.C., Voc = Min LowLevelOutputVottage | | | 045 | V_| lo = 120mAD.C. Voc = Min [| inputLeakage Curent | [| #10 | na | Voc = Max, GND < Vin < Voo Output Leakage Current 10 | wa | Voc = Max, GND < Vour < Voc Output Short Grout Current | ~30 || —120 [ma | Voc = Max Vour = 05¥ Iga | Standby Current Voc = Max, Vin = Voc or GND, Standby Mode Power Supply Current (see mA | Voc = Max, Vin = Voc or loc vs Frequency Graph) GND, No Load, fin = 1 MHz, Device Prog. as an 8-Bit Counter, Non-Turbo Mode | [3s [so | ma | fy = 15 Miz, Active Mode | [4s | 60 | ma | fy = 80 Miz, Active Mode NOTES: 4. Absolute values with respect to device GND; all over and undershoots due to system or tester noise are included. 5. Maximum DC Io, for the device (all 8 outputs) is 64 mA. 6. Not more than 1 output should be tested at a time. Duration of that test should not exceed 1 second. 7. In Non-Turbo Mode (TURBO = OFF), device enters standby mode approximately 75 ns after the last input transition. A.C. TESTING LOAD CIRCUIT -80 and -66 -100 sv 3v ssa res oevice yo test eevee ost inst Rau (OwcLuoEs ste moog abe, (HeuUDKs ae vong se_oiunts ae = (290224-7 ~ 290224-21 Cy = 30pF 2-86 |
intel © 85C220/85C224-100, -80 AND -66 A.C. TESTING WAVEFORM—SYNCHRONOUS INPUTS AND OUTPUTS sev aux sv rest poms —= Yes sor ° ] oururs tn) —— rest powts 200224-8 AC. Testing: Inputs (including CLK) are driven at 3.0V for a Logic "1" and OV for a Logic “0”. Setup and hold input measurements relative to CLK are made at 2.0V on CLK (low-to-high transition). inputs are measured at 2.0V for a high CAPACITANCE (Ta = 0°C to + 70°C; Voc = 5.0V +5%)(8) [Symbol [Parameter [| Min | Typ [ Max [ unit [Conditions —_—_—| inputCapacitance | | 4 | 6 | pF | Viv= OV. = 10MHz WOCapacitance | | s | 8 | pF | Vour = 0v,t= 1.0MHz CtKCepacitance [| [6 | 8 | oF | Vour = 0v,t = 1.0Miz VepPin Capacitance [| 8 | 10 | pF | VpponPin11/13,1= 1.0MHz NOTES: 8. These values are evaluated during initial characterization and whenever design modifications occur that may affect capac- itance. A.C. CHARACTERISTICS (Ta = 0°C to +70°C, Voc = 5.0V +5%)(®) 85C220-100/ 85C220-80/ 850220-66/ 10) Symbol 85C224-100 85C224-80 85C224-66 Non Turbot | min | Typ | Max | Min | Typ | Max | Min [ Typ [ Max | tep(?) | Input or 70 75 to | 4 +20 to Output tpzx(12) | Input or 1/0 12 4 +20 to Output Enable tpxz(2) | Input or 1/0 4 +20 to Output Disable Tos Registered Output Skew Tos Comb. Output Skew NOTES: 9. Typical values are at Ta = +25°C, Voc = SV, Active Mode. 10. If device is operated in Standby Mode (Standby bit = Low) and the device is inactive for approximately 75 ns, increase time by amount shown for -80 and -66 only. 11. Measured with all eight outputs switching. 12. tpzx and tpxz are measured at +0.5V from steady state voltage as driven by specification output load. tpxz is measured with CL = 5 pF. Measured with all eight outputs switching. | 2-87
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intel ° 85C220/85C224-100, -80 AND -66 COMBINATORIAL MODE REGISTERED MODE tow INPUT OR 1/0 tent ten feo CLK COMBINATORIAL OUTPUT tsy won wrcomee REGISTERED OUTPUT Yeon veo rtoance ‘ex roooreus | KX _vavo ourrut se = VAUD ouTPuT cor : eooeet-10 85C220/85224 85C220/85C224 Icc vs Frequency tpp Derating vs Capacitive Loading ry a Pa a ste | iz gelent 1} & 4 on Km [td a Pe 2a > Habctortow Teck ners || ao 20) FAS (zeRo owen) —>—| ons (ee ‘0 = a a rs 0 20 40 60 80 100 30 pF 70pF 110 pF 150 pF 190 pF fo(un2) Capacitance wane e nee 100 soeenta12 cho 66 Conditions: ~ ~80 Ta = 70°C Conditions: Voc = 4.75V Ta = 25°C Voc = 5.25V INPUT/OUTPUT EQUIVALENT SCHEMATICS Yeo Yoo Yee «0 rok PROTECTION PULL-UP 1/0 PIN «so motarron PROGRAM /VERIFY Sean wus = ae Monee 290224-13 AND PROGRAM / | 2-89
85C220/85C224-100, -80 AND -66 intel 85C220/85C224 Output Drive Current in Relation to Voltage CE 59 bE . \\ of | ee Ce [— | a 2 oe ee ’ ain (ma) 1 500 |_| | | * I . it A) 100 oad ° 1 2 3 4 Ss Vo Output Voltage (V) 20022415 Conditions: Ta = +80°C Voc = 4.75V Power-Up Reset POWER-UP RESET CHARACTERISTICS Internal power-up reset circuits ensure that all tip- [Symbol Parameter | Value_| flops will be reset to a logic 0 after the device has [ter _| Power-Up Reset Time powered up. Because Voc rise can vary significantly from one application to another, Vo tise must be monotonic. POWER-UP RESET POWER (Wee) ji vx =— te — OUTPUT att tied) ox (>? f a 20022416 2-90 |
intel ° 85C220/85C224-100, -80 AND -66 PACKAGE/TECHNOLOGY SPECIFICATIONS [ __Beseription "| asczzo[escaza | ©jg—Junetion-to-Ambient | 68°C/W—CerDIP__ | 55°C/W—CerDIP Thermal Resistance 90°C/W—-PDIP 65°C/W—PDIP 90°C/W—PLCC 65°C—PLOG © je—Junction-to-Case 30°C/W—CerDIP__ | §5°C/W—CerDIP Thermal Resistance 25°C/W—PDIP 20°C/W—PDIP 25°C/W—PLOC 20°C/W—PLOC CHMOS INE, Px29.5 | CHMOS IIE, PX29.5 locHot—Ambient @70°C | 40ma(800ny) | locTypical—Ambient @25°C | 40ma(-80ony [| |
REVISION HISTORY
-004 to -005 Addition of specification for clock driver | 291