N8397JFL

Intel Corporation

COMMERCIAL/EXPRESS HMOS MICROCONTOLLER

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8097JF INTEL | Alldatasheet

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8797JF: an 8097JF with 16 Kbytes of On-Chip EPROM 8397JF: an 8097JF with 16 Kbytes of On-Chip ROM @ 232 Byte Register File @ High Speed I/O Subsystem @ 256 Bytes XRAM for Code @ Full Duplex Serial Port m@ 10-Bit A/D Converter with S/H ™@ Dedicated Baud Rate Generator @ Five 8-Bit I/O Ports @ 6.25 ys 16 x 16 Multiply @ 20 Interrupt Sources @ 6.25 us 32/16 Divide @ Pulse-Width Modulated Output @ 16-Bit Watchdog Timer @ ~ROM/EPROM Lock @ Four 16-Bit Software Timers @ Run-Time Programmable EPROM (OTP) @ Two 16-Bit Counter/Timers m Extended Temperature Available w Extended Burn-in Available The MCS 96 microcontroller family of 16-bit microcontrollers consists of many members, all of which are designed for high-speed control functions. The MCS-96 family members produced using Intel's HMOS-III Process are described in this data sheet. ‘The CPU supports bit, byte, and word operations. Thirty-two bit double-words are supported for a subset of the instruction set. With a 12 MHz input frequency the 8097JF can do a 16-bit addition in 1.0 1s and a 16 x 16-bit 4 multiply or 32/16 divide in 6.25 1s. Instruction execution times average 1 to 2 ps in typical applications. Four high-speed trigger inputs are provided to record the times at which external events occur. Six high-speed Pulse generator outputs are provided to trigger external events at preset times. The high-speed output unit can simultaneously perform software timer functions. Up to four 16-bit software timers can be in operation at once. The on-chip A/D converter includes a Sample and Hold, and converts up to 8 multiplexed analog input channels to 10-bit digital values. With a 12 MHz crystal, each conversion takes 22 us. Also provided on-chip are a serial port, a Watchdog Timer and a pulse-width modulated output signal. With the commercial (standard) temperature option, operational characteristics are guaranteed over the tem- perature range of 0°C to + 70°C. With the extended temperature range option, operational characteristics are guaranteed over the temperature range of — 40°C to + 85°C. Unless otherwise noted, the specifications are the same for both options. With the extended burn-in option, the burn-in is dynamic for a minimum time of 160 hours at 125°C with Voc = 5.5V + 0.5V, following the guidelines in MIL-STD-883, Method 1015. See the Packaging information for extended temperature and extended burn-in designators. Oona vee ae November 1994 4-45 Order Number: 270795-006 Ea 4826175 0144663 960 mm

1 Hi 1 [ower] H

Figure 1. 8X97JF Block Diagram Figure 2. 8X97JF Memory Map

Figure 5. 68-Pin PLCC Package

Figure 6. Shrink-DIP Package

[ symbot | Name and Function Main supply voltage (5V). Digital circuit ground (OV). There are two Vgg pins, both of which must be connected. Veo RAM standby supply voltage (5V). This voltage must be present during normal operation. ina Power Down condition (1.., Voc drops to zero), if RESET is activated before Voo drops below spec and Vpp continues to be held within spec., the top 16 bytes in the Register File will retain their contents. VREF Reference voltage for the A/D converter (5V). Ver is also the supply voltage to the analog portion of the A/D converter and the logic used to read Port 0. Must be connected to use A/D or Port 0. jAneno | Reference ground for the A/D converter. Must be held at nominally the same potential as Vgs. Ver Programming voltage for the EPROM devices. It should be + 12.75V for programming and will float to 5V otherwise. It should not be above Vcc for ROM or CPU devices. This pin must be left floating in the application circuit for EPROM devices. Input of the oscillator inverter and of the internal clock generator. Output of the oscillator inverter. CLKOUT* | Output of the internal clock generator. The frequency of CLKOUT is %4 the oscillator frequency. It has a 33% duty cycle. Reset input to the chip. Input low for a minimum of 10 XTAL1 cycles to reset the chip. The subsequent low-to-high transition re-synchronizes CLKOUT and commences a 10-state- time RESET sequence. BUSWIDTH" | Input for bus width selection. If CCR bit 1 is a one, this pin selects the bus width for the bus cycle in progress. if BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH is a 0 an 8-bit cycle occurs. If CCR bit 1 is a 0, the bus is always an 8-bit bus. If this pin is left unconnectad, it will rise to Voc. [NMI | Apositive transition causes a vector to external memory location O000H. INST* Output high during an external memory read indicates the read is an instruction fetch. INST is valid throughout the bus cycle. Input for memory select (External Access). EA equal to a TTL-high causes memory accesses to locations 2000H through 5FFF to be directed to on-chip ROM/EPROM. EA equal to a TTL-low causes accesses to these locations to be directed to off-chip memory. = +12.75V causes the device to enter the Programming Mode. ‘ALE/ADV | Address Latch Enable or Address Valid output, as selected by CCR. Both pin options provide alatch to demultiles the ‘address from the address/data bus. When the pin is it goes inactive high at the end of the bus cycle. ALE/ADV is activated only during external memory accesses. [| Read signal output to external memory. FID is activated only during external memory reads. WR/WAL Write and Write Low output to external memory, as selected by the CCA. WA will go low for every external write, while WRL will go low only for external writes where an even byte is being written. WA/WRL is activated only during external memory writes. BHE/WAH Bus High Enable or Write High output to external memory, as selected by the CCR. BHE wil go low for external writes tothe high byte ofthe data bus. WA will go low for external writes where an odd byte is being written. BHE/WRH is activated only during external memory writes. *Not available on Shrink-DIP Package 4-50 PRELIMINARY | MB 4426175 O144bb8 462

e PIN DESCRIPTIONS (Continued) [symbol _| Name and Function READY Ready input to lengthen external memory cycles. If the pin is low prior to the falling edge of CLKOUT, the memory controller goes into a wait mode until the next positive transition of CLKOUT occurs with READY high. When the external memory is not being used, READY has no effect. Internal contro! of the number of wait states inserted into a bus cycle held not ready is available in the CCA. Inputs to High Speed Input Unit. Four HS! pins are available: HSI.0, HSI.1, HSI.2 and HS13. Two of them (HSI.2 and HSI.3) are shared with the HSO Unit. Outputs from High Speed Output Unit. Six HSO pins are available: HSO.0, HSO.1, HSO.2, 8-bit high impedance input-only port. These pins can be used as digital inputs and/or as analog inputs to the on-chip A/D converter. | Pott __| @-bit quasi-bidirectional I/O port. 8-bit multi-functional port. Six of its pins are shared with other functions in the 8096JF, the remaining 2 are quasi-bidirectional. These pins are also used to input and output control signals on EPROM devices in Programming Mode. Ports 3 and 4 | 8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the multiplexed address/data bus, which has strong internal pull-ups. Ports 8 and 4 are also used as a command, address and data path by EPROM devices operating in the Programming Mode. | PMODE _| Determines the EPROM programming mode. A low signal in Auto Programming Mode indicates that programming is in progress. A high signal indicates programming is complete. A low signal in Auto Programming Mode indicates that the device programmed correctly. SALE A falling edge in Auto Programming Mode indicates that Ports 3 and 4 contain valid programming address/command information (output from master). SPROG A falling edge in Auto Programming Mode indicates that Ports 3 and 4 contain valid programming data (output from master). | SID___| Assigns a pin of Ports 3 and 4 to each slave to pass programming verification, PALE A falling edge in Slave Programming Mode and Auto Configuration Byte Programming Mode indicates that Ports 3 and 4 contain valid programming address/command information (input to slave). A falling edge in Slave Programming Mode indicates that Ports 3 and 4 contain valid Programming data (input to slave). A high signal in Slave Programming Mode and Auto Configuration Byte Programming Mode indicates the byte programmed correctly. | PVAL A high signal in Slave Programming Mode indicates the device programmed correctly, | A low signal in Slave Programming Mode indicates that the PROG pulse was applied for longer than allowed. RELI 451 | PRELIMINARY = gm 4926175 O144Rb9 379 mm

8X97JF I ntel ° ELECTRICAL CHARACTERISTICS NOTICE: This data sheet contains preliminary infor- ABSOLUTE MAXIMUM RATINGS* mation on new products in production. It is valid for the devices indicated in the revision history. The Ambient Temperature || specifications are subject to change without notice. These are stress ratings only. Operation beyond the vovs serAnGND -o3vte +13.0v “Operating Conditions” is not recommended and ex, ‘SS Saaeaneenaeee " tended exposure beyond the “Operating Conditions” Voltage from Any Other Pin to may affect device reliability. NOTES: 1. This includes Vpp and EA on ROM and CPU only devices. 2. Power dissipation is based on package heat transfer characteristics, not device power consump- tion. OPERATING CONDITIONS (All characteristics specified in this data sheet apply to these operating conditions unless otherwise noted.) ee ‘Ambient Temperature Under Bias Commercial Temp. | 0 | +70 | °C | [tr] “Ambient Temperature Under Bias Extended Teme, | 40 | +08 | *o | Digital Supply Voltage | «50 | sso |v | Analog Supply Voltage [450 [sso | v | rose | OseitorFroquncy —SSSSCSC~C~S~dtCi || Power-Down Supply Voltage [450 [550 | v_| NOTE: ANGND and Vgg should be nominally at the same potential. DC CHARACTERISTICS [toc __| Voc Supply Current Commercial Temp. [| 300 | ma _| atlOutputs [tcc | Voc Supply Curent Extended Temp. [| 230 ma_] Disconnected [oc | Voc Supply Curent (Ta = 70°C) [| 2a [ma Vpn Supply Current mA_ | Normal operation and Power-Down [eer | Vaer SupplyGurentGommercia temp. || @ | ma | | Input Low Voltage [=oafvos[ v [| InputLow Voltage, RESET CommercialTemp. | -os | ros v | | InputLow Votage, RESET Extended Ter. | os | ro7{ v |_| 4-62 NARY ME 4826175 0144670 O10 PRELIM |

DC CHARACTERISTICS (Continued) [symbol] Parameter | Min [Max _ [Unite] Test Conditions Input High Voltage (Except RESET, NMLxTAL1) | 20 |Voo+ os] v [| Input High Voltage, RESET Rising | 24 [voo+os| vf | to Input Leakage Current to each pin of +10 BA | Vin = 0 to Veo. HSI, P3, P4, and to P2.1 [Iu | DC input Leakage Current to each pin of PO [| [+3 | ua [Vin = 0t0 Voc [ix ___[Input igh Curent to EA | [100 | ua [Vin = 24v Me Input Low Current to each pin of P1, BA Vy = 0.45V and to P2.6, P2.7 Commercial Temp. Ie Input Low Current to each pin of P1, BA | Vi. = 0.45V and to P2.6, P2.7 Extended Temp. Input Low Current to RESET [-o.25| -2 | ma [Vi = 045v luz | Input Low Current P2.2, P2.3, P2.4, BA |Vi, = 0.45V READY, BUSWIDTH Vo. | Output Low Voltage on Quasi-Bidirectional V_ lot = 0.8 mA Port pins and P3, P4 when used as ports (Note 1) Voi: _ | Output Low Voltage on Quasi-Bidirectional 075 | V |lo. = 20maA Port pins and P3, P4 when used as ports (Notes 1, 2, 3) Vow2 | Output Low Voltage on Standard Output V flo. = 2.0mA pins, RESET and Bus/Control Pins (Notes 1, 2, 3) Vox | Output High Voltage on Quasi-Bidirectional 24 V_ lon = 20 mA pins (Note 1) Vox | Output High Voltage on Standard Output 24 V_ |lon = ~200 pA pins and Bus/Control pins (Note 1) [lors _| Output High Current on RESET [-so] [nA [Von = 24v Pin Capacitance (Any Pin to Vss) [ [10 _| oF |Frest = 1.0MHz NOTES: 1. Quasi-bidirectional pins include those on P1, for P2.6 and P2.7. Standard Output Pins include TXD, RXD (Mode 0 only), PWM and HSO pins. Bus/Control pins include CLKOUT, ALE, BHE, AD, WA, INST and ADO-15. : 2. Maximum current per pin must be externally limited to the following values if Vo, is held above 0.45V. lox on quasi-bidirectional pins and Ports 3 and 4 when used as ports: 4.0 mA Io. on standard output pins and RESET: 8.0 mA loc on Bus/Control pins: 2.0 mA 3.During normal (non-transient) operation the following limits apply: Total Io on Port 1 must not exceed 8.0 mA. Total lo, on P2.0, P2.6, RESET and all HSO pins must not exceed 15 mA. Total Io, on Port 3 must not exceed 10 mA. Total lo, on P2.5, P2.7, and Port 4 must not exceed 20 mA. PRELIMINARY 4-53 MH 4426175 O144b71 15?

8X97JF . intel ° AC CHARACTERISTICS Test Conditions: Load Capacitance on Output Pins = 80 pF TIMING REQUIREMENTS (The system must meet these specifications to work with the 8X97JF) READY HoldafterCLKOUTEdse | oo) | ns End of ALE/ADVtoREADY Valid | || 2 Tosco 70 | ns_| End of ALE/ADV to READY High 2Tosc +40 | 4Tosc-80 | ns | [Tuva | NonReadytime || tos Address ValidtotnputDataVaid | «| «STosc— 120% | ns | FD Active to Input Data Vaid [Tose = 100% | ns | Data Hold after RD inactive Poo Ts FDinactivetoinputDataFloat | 0 | Toso 25 | ns | Address ValidtoBUSWIDTH Valid | «| 2 Tosc 125 | ns | BUSWIDTHHoldatter ALE/ADVLow | Toso +40 | |r ALE/ADVLowtopuswioTHvaid | | Toso 100 | ns | NOTES: 1. If the 64-pin device is being used then this timing can be generated by assuming that the CLKOUT falling edge has occurred at 2 Togo + 55 (TLLCH(max) + eee after the falling edge of ALE. 2. The term “Address Valid” applies to ADO-15, and INST. 3. Pins not bonded out on 64-pin devices. 4. It wait states are used, add 3 Togc * N where N = number of wait states.

4.54 PRELIMINARY

8X97JF intel : WAVEFORM—SYSTEM BUS TIMINGS ow DLOLPLL Lyn Tone Toncu--} b+ Tosc-| . Thue i eocnout READY VALID ],"] @) oun Tuuw Tur Tune TLLae: 7 TRHL Loy ‘ Taye Te 10 {1008 oor) (oan) ; ie —~ THM WR, WAL, Tavis OR Nee 10 (Troma Xoo sd | wx — Town Tan sonnts vn 270795-18 NOTES: 1. 6-bit bus only. 2. 6-bit or 16-bit bus and write strobe mode selected. 3, When ADV selected. 4. 8 or 16-bit bus and no write strobe mode selected. WAVEFORM—BUSWIDTH* TIMINGS oo SLELELP LLL ecxour / \\ / \\ / \\ Tavov: auswors? [Xo neweeeeee, Tuev ALE / ADV Tuex- Tay 7708-19 ‘*Not available on 64-lead package.

4.56 PRELIMINARY

intel ° 8X97JF WAVEFORM—Tripy Power Supply Rise Time 5.5Vo¢ Vee 45Vo¢ ‘tort Time from Power Supply Rise to External Output Low va HOMO LTT Tt 72.0,°2.5 ——— r_| 2018H cca” [~ 2080H Tare 2 TORTAL CYOLES FimsT BUS FeTeH cvoLe ] PROGRAM EXTERNAL CLOCK DRIVE [-_symbor_ [Parameter [win [Max [Units | Ton | Oseitator Frequency [ef tae | Towox | Higntime fas rs | Touox | bowtie Toe | toon | isotime Pt ns L_tonon [atime Tt EXTERNAL CLOCK DRIVE WAVEFORMS ) Tonox ToLon Towot 28 25 Toox 25 os 08 | Toro. 270795-22 An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts-up. This is due to interaction between the amplifier and its feedback capacitance. Once the external signal meets the Vi_ and Vin Specifications the capacitance will not exceed 20 pF. | 4-57 PRELIMINARY MH 4826175 O144b75 bTe Ml

8X97UF intel ° EXTERNAL CRYSTAL CONNECTIONS EXTERNAL CLOCK CONNECTIONS et rau vee = BX9X 4K, Yss = Wi XTAL2- EXTERNAL 2 cxdeK Pot | >O rat Quartz Crystal or stock driver 8x9x Ceramic Revonotor ro connect —xTAL2 270708-5 NOTE: Keep oscillator components close to chip and use short, direct 270795-6 traces to XTALI, XTALZ and Vee. When using crystals, C1 = 30 pF and C2 = 30 pF. When using ceramic resonators, consult manufacturer for recommended capacitor values. ‘AC TESTING INPUT, OUTPUT WAVEFORMS FLOAT WAVEFORMS 24 “Loapto20v TIMING REFERENCE. vour020N ‘ ogee TST FONTS Viouo 0.20 Pownrs Vo*0.20V ry 270795-23 270795~24 oy For Timing Purposes a Port Pin is 90 Longer Floating when @ "4" and 0.8V for a Logic “0”. ‘when a 200 mV change from the Loaded VoH/Vo. Level occurs Toulon 2 £8 mA MINIMUM HARDWARE CONFIGURATION CIRCUITS Ye —onut Ye }—oncar sal yor Ls yer suo “eat a om se XTALS_XTALZ. am: vss? XTALL_XTALZ. cont oF oy oat 3008 hit nF oni 3068 ‘tht 130 9 Pont] ~ 270795-25 ~ 270795~26 4-58 PRELIMINARY MB 4826175 O144b7b S39 MM |

AC CHARACTERISTICS—SERIAL PORT—SHIFT REGISTER MODE SERIAL PORT TIMING—SHIFT REGISTER MODE Test Conditions: Load Capacitance = 80 pF | Tan | SeriiPonCockPeriod | Toso | |_| Serial Port Glock Falling Edge to Rising Edge | 4Tosc~ 50 | 4Tosc +50 | ns | Next Output Data Valid After Clock Rising Edge | | 2Tosc +80 | ns _| Input Data Setup to Clock Rising Edge | 2Tosc +200 | | ns | | Txiox | InoutDataHoldAterClockRisingedge || |_| WAVEFORM—SERIAL PORT—SHIFT REGISTER MODE SERIAL PORT WAVEFORM—SHIFT REGISTER MODE fac se i es ee ee ee ee ee Tor >| Taw Tov df Tex Tawar! r oun <2 XK F>K STK EK KX XD Tovne*| f+ Trwox a CD GD CD GD CD GD CD DCT) DDD CDE, 270795-21 PRELIMINARY 4-59 | ME 4826175 OL44b77 475 Ml

@X97JF intel. A/D CONVERTER SPECIFICATIONS The absolute conversion accuracy is dependent on the accuracy and stability of Vaer- See the MCS-96 A/D Converter Quick Reference for definitions of A/D Converter terms. [Parameter | Typical" [Minimum [Maximum | units'* | Notes | Resolution 1024 1024 Levels 10 10 Bits Absolute Error ee es Full Scale Error oszos || tgs | [Nontineaty | Tee ss | Differential Non-tinearty || t | te | uses || Channetto-Channei Matching | [| oT zt sas || Repeatabilty [so [oT ts | Temperature Coefficients: Offset 0.009 LSB/°C Full Scale 0.009 LSB/°c Differential Non-Linearity 0.009 LSB/°C Off isolation a es Feedthrough a Veo Power SupplyRejection | -eo [| ||| InputSeriesResistance || KT sk | | | Sample Delay [| stosc= 0 | stosc+s0 | ns | 2 | ‘Sample Time | t2tosc= 80 | 12 Tose +80 | ns || Sampling Capacitor a a NOTES: * These values are expected for most devices at 25°C. ** An “LSB”, as used here, is defined in the MCS-96 A/D Converter Quick Reference and has a value of approximately Smv. 1, DC to 100 KHz. 2. For starting the A/D with an HSO Command. 3. Multiplexer Break-Before-Make Guaranteed. 4, Resistance from device pin, through internal MUX, to sample capacitor. 4-60 PRELIMINARY MH 4826175 0144678 301 Me |

EPROM PROGRAMMING OPERATING CONDITIONS Ambient Temperature during Programming | 20 | 30 |__| Vee: Vp, Supply Voltages during Programming v Vaer() Froraring Mode Soy Volags | | 130 | va _| Fosat) Oscillator Frequency during Auto and Slave Programming Fosc(2) Oscillator Frequency during Run-Time MHz Programming NOTES: 1. Voc, Vpp and Ver should nominally be at the same voltage during programming. 2. Vea and Vpp must never exceed the maximum voltage for any amount of time or the device may be damaged. 8. Vgg and ANGND should nominally be at the same voltage (OV) during programming. AC EPROM PROGRAMMING CHARACTERISTICS ADDRESS/COMMANDValidtoPALELow [| 9 | | Toso | ADDRESS/COMMANDHoldAfterPALELow [| 60 | | Tose | Output Data Setup Before PROG Low poo fT Tose] | terox | OataHosaterPROGFaing || Toso | PALE Pulse With ee ee TPLPH PROG Pulse Width 250Tosc | 100 ps + . 144 Tose PALE High to PROG Low [a0 | Tose | PROG High to Next PALE Low : ee OGHgh | wT Tose | [Thaw | PROG Hin PVER/POO Vaid [eae || Tose | [Tue | PAE LowioPVER/POG Han | 100 | | Tose | PROG LowtoVERIFICATION/DUMP Data Valid | 100 | ———i|s ‘Toso _| | RESET HightoFFrstPALE Low (natstown) [| 2000 | | Tose | DC EPROM PROGRAMMING CHARACTERISTICS [_tee | Vee Supply Current Whenever Programming) | | 100 | ma 461 PRELIMINARY MB 4626175 O144b79 248 me

WAVEFORM—EPROM PROGRAMMING (OTP) Tam Tove pote Tax [> Truox PORTS 3,4 CoAtA) TPLPH — TPHLL PROG Tavut eee Tax TeLov TeHox ports 3,4 —{ RAND) ("Si WORD DUMP) ir es —_ | = PDO VALID YL vauio 270795-27 REVISION HISTORY 2. Added Vi.1 (Input Low Voltage, RESET) This data sheet (270795-006) is valid for devices The following differences exist between the -003 with a "B” at the end of the topside tracking number. data sheet and the -002 data sheet. Data sheets are changed as new device information 4. The raserved location section and the power sup- becomes available. Verity with your local Intel sales ply sequencing section has been deleted. This office that you have the latest version before finaliz- Information is in the Hardware Design Informa: ing a design or ordering devices. tion, , 4 2. The Software Reset Timing bug was removed we eet ce te pretius one 008. this -006 from the Functional Deviations. The RESET pin : will pull down for at least 2 states if a software 1. The loL/lon for float waveform testing changed reset or watchdog timer overflow occurs. from £15 mA to +8 mA (this data sheet). ‘olowing dit Differences between the -002 and -001 data sheets. ‘The following differences exist between “005 and 1. The TLLGV spec has been changed from Max = tthe E (extended temperature and b Toso ~ 75 ns to Max = Tog¢ = 100 ns. . The Express (extended temperature and burn-in options) were added to this data sheet. The The TOLLH spec has bean changad from Min = 8XOXJF EXPRESS data sheet (270796-001) is and Max Ae obselote. and Max = +15 ns, 3. The TXHQX spec has been changed from Min = 2. Changes were made to the format of the data c ba sheet and the SFR descriptions were removed. 2 Tosc ~ 50 ns to 2Tosc — 70 ns. No spec changes were made. 4. The TOLOX spec has been changed from Min = , 25 ns to Min = 30 ns. 3. Added Reserved Location 201CH errata. 5. Added “20” recommendation for reserved ad- The following differences exist between the -004 dress 2019H to EPROM specification. data sheet and the -003 data sheet. 6 Added errata. 1. The -003 data sheet was valid only for devices marked with an “A” at the end of the top side tracking number. 4-62 ME 4826175 OL44L80 TET PRELIMINARY |

intel ° 8X97JF 8X97JF ERRATA 3, RESERVED LOCATION 2019H . ; _ The 1990 Architectural Overview recommends Devices covered by this data sheet (see Revision that reserved location 2019H be filled with hex History) have the following errata. value FFH. The recommendation is now to fill 1. INDEXED, 3 OPERAND MULTIPLY 2019H with hex value 20H. The displacement portion of an indexed, three 4. RESERVED LOCATION 201CH ‘operand (byte or word) multiply may not be in the Reading reserved location 201CH, either intemal- range of 2004 thru 17FFH inclusive. If you must ly or externally, will return “201C” as data. use these displacements, execute an indexed, two operand multiply and a move if necessary. > seure PORT See se ial Port Flags—Reading SP_STAT may not 2. @X97JF HIGH SPEED INPUTS ; Sear the Tl or ft flag ft that flag was set within The High Speed Input (HSI) has three deviations ‘two state times prior to the read. In addition, the from the specifications. Note that “events” are parity error bit (RPE/RB8) may not be correct if it defined as one or more pin transitions. “Entries” is read within two state times after Ri is set. Use are defined as the recording of one or more the following code to replace ORB sp_image, events. SP_STAT. A. The resolution is nine states instead of eight SP_READ: LDB TEMP, SP_STAT states. Events occurring on the same pin ORB SP_IMAGE, TEMP more frequently than once every nine state JBS TEMP,5,SP-READ; if TI times may be lost. is set then read again B. A mismatch between the nine state HSI reso- JBS TEMP,6,SP_READ; if RI lution and the eight state hardware timer is set then read again causes one time-tag value to be skipped ev- ANDB SP_IMAGE,#7FH; clear ery nine timer counts. Events may receive a false RB8/RPE time tag one count later than expected. ORB SP_IMAGE, TEMP; load ©. If the FIFO and Holding Register are empty, correct RBG/RPE the first event will transfer into the Holding Register, leaving the FIFO empty again. The next event that occurs will be the first event loaded into the empty FIFO. If the first two events into any empty FIFO (not counting the Holding Register) occur coincident with each other, both are recorded as one entry with ‘one time-tag. if the second event occurs with- in 9 states after the first, the events will be / entered separately with time-tags at least one count apart. If the second event enters the FIFO coincident with the “skipped” time-tag situation (see B above) the time-tags will be at least two counts apart. PRELIMINARY 4-63 MMH 4826175 O144bal ITb

Product Information

N8397JFL specifications and overview.

Summary

COMMERCIAL/EXPRESS HMOS MICROCONTOLLER

Description

COMMERCIAL/EXPRESS HMOS MICROCONTOLLER

Source title N8397JFL Datasheet(PDF) - Intel Corporation

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