8XC51GB INTEL | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 22
Technical content
*Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. November 1994COPYRIGHT © INTEL CORPORATION, 1995 Order Number: 272337-002 8XC51GB CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER Commercial/Express 87C51GBÐ8 Kbytes OTP/8 Kbytes Internal Program Memory 83C51GBÐ8 Kbytes Factory Programmable ROM 80C51GBÐCPU with RAM and I/O 8XC51GBÐ3.5 MHz to 12 MHz g20% V CC 8XC51GB-1Ð3.5 MHz to 16 MHz g20% V CC Y 8 Kbytes On-Chip ROM/OTP ROM Y 256 Bytes of On-Chip Data RAM Y Two Programmable Counter Arrays with: Ð 2 x 5 High Speed Input/Output Channels Compare/Capture Ð Pulse Width Modulators Ð Watchdog Timer Capabilities Y Three 16-Bit Timer/Counters with Ð Four Programmable Modes: Ð Capture, Baud Rate Generation (Timer 2) Y Dedicated Watchdog Timer Y 8-Bit, 8-Channel A/D with: Ð Eight 8-Bit Result Registers Ð Four Programmable Modes Y Programmable Serial Channel with: Ð Framing Error Detection Ð Automatic Address Recognition Y Serial Expansion Port Y Programmable Clock Out Y Extended Temperature Range: b40§Ct o a85§C) Y 48 Programmable I/O Lines with
40 Schmitt Trigger Inputs
Y 15 Interrupt Sources with: Ð 7 External, 8 Internal Sources Ð 4 Programmable Priority Levels Y Pre-Determined Port States on Reset Y High Performance CHMOS Process Y TTL and CHMOS Compatible Logic Levels Y Power Saving Modes Y 64K External Data Memory Space Y 64K External Program Memory Space Y Three Level Program Lock System Y ONCE (ON-Circuit Emulation) Mode Y Quick Pulse Programming Algorithm Y MCSÉ 51 Microcontroller Fully Compatible Instruction Set Y Boolean Processor Y Oscillator Fail Detect Y Available in 68-Pin PLCC MEMORY ORGANIZATION PROGRAM MEMORY: Up to 8 Kbytes of the program memory can reside in the on-chip ROM. Also, the device can address up to 64K of program memory external to the chip. DATA MEMORY: This microcontroller has a 25 6 x 8 on-chip RAM. In addition it can address up to 64 Kbytes of external data memory. The Intel 8XC51GB is a single-chip control oriented microcontroller which is fabricated on Intel’s CHMOS III-E technology. The 8XC51GB is an enhanced version of the 8XC51FA and uses the same powerful instruction set and architecture as existing MCS 51 microcontroller products. Added features make it an even more powerful microcontroller for applications that require On-Chip A/D, Pulse Width Modulation, High Speed I/O, up/down counting capabilities and memory protection features. It also has a more versatile serial channel that facilitates multi-processor communications.
Figure 1. 8XC51GB Block Diagram and Reliability Handbook, Order No. 210997.
The 8XC51GB contains six 8-bit parallel I/O ports. port pins have multiplexed I/O and control functions. off. The pin is held high by a weak pullup. port registers are bit addressable. drain port, it provides a very high input impedance. have Schmitt trigger inputs. Ports 1, 2, 4, and 5 reset to a zero asynchronously. package. Its pin assignment is shown in Figure 2. Diagram is for Pin Reference Only. Package Size is Not to Scale. Figure 2. Pin Connections
Ports 0, 1, 2, 3, 4 and 5 have alternate functions as well as their I/O function as described below. Port Pin Alternate Function P0.0/ADO–P0.7/AD7 Multiplexed Address/Data for External Memory P1.0/T2 Timer 2 External Clock Input/Clock-Out P1.1/T2EX Timer 2 Reload/Capture/Direction Control P1.2/ECI PCA External Clock Input P1.3/CEXO–P1.7/CEX4 PCA Capture Input, Compare/PWM Output P2.0/A8–P2.7/A15 High Byte of Address for External Memory P3.0/RXD Serial Port Input P3.1/TXD Serial Port Output P3.2/INT0 External Interrupt 0 P3.3/INT1 External Interrupt 1 P3.4/T0 Timer 0 External Clock Input P3.5/T1 Timer 1 External Clock Input P3.6/WR Write Strobe for External Memory P3.7/RD Read Strobe for External Memory P4.0/SEPCLK Clock Source for Serial Expansion Port P4.1/SEPDAT Data I/O for the Serial Expansion Port P4.2/ECI1 PCA1 External Clock Input P4.3/C1EX0–P4.7/C1EX4 PCA1 Capture Input, Compare/PWM Output P5.2/INT2–P5.6/INT6 External Interrupt INT2–INT6 RST: Reset input. A low on this pin for two machine cycles while the oscillator is running resets the de- vice. The port pins will be driven to their reset condi- tion when a voltage below V IL max voltage is ap- plied, whether the oscillator is running or not. An internal pullup resistor permits a power-on reset with only a capacitor connected to V SS. ALE/PROG: Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin (ALE/PROG ) is also the program pulse input during programming of the 87C51GB. In normal operation ALE is emitted at a constant rate of (/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, how- ever, that one ALE pulse is skipped during each ac- cess to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With this bit set, the pin is weakly pulled high. However, the ALE disable fea- ture will be suspended during a MOVX or MOVC in- struction, idle mode, power down mode and ICE mode. The ALE disable feature will be terminated by reset. When the ALE disable feature is suspended or terminated, the ALE pin will no longer be pulled up weakly. Setting the ALE-disable bit has no affect if the microcontroller is in external execution mode. Throughout the remainder of this data sheet, ALE will refer to the signal coming out of the ALE/PROG pin, and the pin will be referred to as the ALE/PROG pin. PSEN: Program Store Enable is the read strobe to external Program Memory. When the 8XC51GB is executing code from external Program Memory, PSEN is activated twice each ma- chine cycle, except that two PSEN activations are skipped during each access to external Data Memo- ry. EA /VPP: External Access enable. EA must be strapped to V SS in order to enable the device to fetch code from external Program Memory locations 0000H to 1FFFH. Note, however, that if either of the Program Lock bits are programmed, EA will be inter- nally latched on reset. EA should be strapped to V CC for internal program executions.
The ONCE (‘‘On-Circuit Emulation’’) Mode facilitates testing and debugging of systems using the 8XC51GB without removing it from the circuit. The ONCE Mode is invoked by: 1) Pulling ALE low while the device is in reset and PSEN is high; 2) Holding ALE low as RESET is deactivated. While the device is in ONCE Mode, the Port 0 pins float, and the other port pins and ALE and PSEN are weakly pulled high. The oscillator circuit remains ac- tive. While the 8XC51GB is in this mode, an emula- tor or test CPU can be used to drive the circuit. Nor- mal operation is restored when a normal reset is ap- plied. Watchdog Timer (WDT) The 8XC51GB contains a dedicated Watchdog Tim- er (WDT) to allow recovery from a software or hard- ware upset. The WDT consists of a 14-bit counter which is cleared on Reset, and subsequently incre- mented every machine cycle. While the oscillator is running, the WDT will be incrementing and cannot be disabled. The counter may be reset by writing 1EH and E1H in sequence to the WDTRST Special Function Register. If the counter is not reset before it reaches 3FFFH (16383D), the chip will be forced into a reset sequence by the WDT. This works out to 12.28 ms @ 16 MHz. WDTRST is a write only regis- ter. The WDT does not force the external reset pin low. While in Idle mode the WDT continues to count. If the user does not wish to exit Idle with a reset, then the processor must be periodically ‘‘woken up’’ to service the WDT. In Power Down mode, the WDT stops counting and holds its current value. Serial Expansion Port (SEP) The Serial Expansion Port is a half-duplex synchro- nous serial interface with the following features: Four Clock FrequenciesÐ XTAL/12, 24, 48, 96. Four Interface ModesÐ High/Low/Falling/Rising Edges. Interrupt Driven. Oscillator Fail Detect (OFD) The Oscillator Fail Detect circuitry triggers a reset if the oscillator frequency is lower than the OFD trig- ger frequency. It can be disabled by software by writ- ing E1H followed by 1EH to the OFDCON register. Before going into Power Down Mode, the OFD must be disabled or it will force the GB out of Power Down. The OFD has the following features. OFD Trigger Frequency: Below 20 KHz, the 8XC51GB will be held in reset. Above 400 KHz, the 8XC51GB will not be held is reset. Functions in Normal and Idle Modes. Reactivated by Reset (or External Interrupt Ze- ro/One Pins) after Software Disable. 8XC51GB EXPRESS The Intel EXPRESS products are designed to meet the needs of those applications whose operating re- quirements exceed commercial standards. With the commercial standard temperature range, operational characteristics are guaranteed over the temperature range of 0 §Ct o a70§C. With the ex- tended temperature range option, operational char- acteristics are guaranteed over the range of b40§C to a85§C. The 87C51GB EXPRESS is packaged in the 68-lead PLCC package. In order to designate a part as an EXPRESS part, a ‘‘T’’ is added as a prefix to the part number. TN87C51GB denotes an EX- PRESS part in a PLCC package. All AC and DC parameters in this data sheet apply to the EXPRESS devices.
ABSOLUTE MAXIMUM RATINGS * Ambient Temperature under Bias ÀÀÀÀ0 §Ct o a70§C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b65§Ct o a150§C Voltage on EA/V PP Pin to V SS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0V to a13.0V* IOL per I/O Pin ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ15 mA Voltage on Any Other Pin to V SS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀb0.5V to a6.5V Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W (Based on Package heat transfer limitations, not de- vice power consumption) *OTP only. NOTICE: This data sheet contains preliminary infor- mation on new products in production. The specifica- tions are subject to change without notice. Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. OPERATING CONDITIONS Symbol Description Min Max Units TA Ambient Temperature Under Bias Commercial 0 a70 §C Express b40 a85 §C VCC Supply Voltage 4.0 6.0 V fOSC Oscillator Frequency 8XC51GB 3.5 12 MHz 8XC51GB-1 3.5 16 MHz DC CHARACTERISTICS (Over Operating Conditions) Symbol Parameter Min Typ (1) Max Unit Test Conditions VIL Input Low Voltage b0.5 0.2 V CC b 0.1 V (except Port 2 and EA ) VIL1 Input Low Voltage b0.5 0.2 V CC b 0.3 V (Port 2) VIL2 Input Low Voltage 0 0.2 V CC b 0.3 V (EA) VIH Input High Voltage 0.2 V CC a 0.9 V CC a 0.5 V (except XTAL1 and RST ) VIH1 Input High Voltage 0.7 V CC VCC a 0.5 V (XTAL1, RST ) VOL Output Low Voltage 0.3 V I OL e 100 mA (2,3) (Ports 1, 2, 3, 4 and 5) 0.45 V I OL e 1.6 mA (2,3) 1.0 V I OL e 3.5 mA (2,3) VOL1 Output Low Voltage 0.3 V I OL e 200 mA (2,3) (Port 0, PSEN , ALE) 0.45 V I OL e 3.2 mA (2,3) 1.0 V I OL e 7.0 mA (2,3)
DC CHARACTERISTICS (Over Operating Conditions) (Continued) Symbol Parameter Min Typ (1) Max Unit Test Conditions VOH Output High Voltage V CC b 0.3 V I OH eb 10 mA (4) (Ports 1, 2, 3, 4 and 5, VCC b 0.7 V I OH eb 30 mA (4) ALE, PSEN ) VCC b 1.5 V I OH eb 60 mA (4) VOH1 Output High Voltage V CC b 0.3 V I OH eb 200 mA (Port 0 in External VCC b 0.7 V I OH eb 3.2 mABus Mode) VCC b 1.5 V I OH eb 7.0 mA IIL Logical 0 Input Current b50 mAV IN e 0.45V ITL Logical 1-to-0 Transition b650 mAV IN e 2.0V Current (Ports 1, 2, 3, 4, 5) ILI Input Leakage Current g10 mA 0.45 k VIN k VCC (Port 0) RRST RST Pullup Resistor 50 300 k X CIO Pin Capacitance 10 pF Freq e 1 MHz TA e 25§C IPD Power Down Current 50 mA (5) IDL Idle Mode Current 18 mA (5) ICC Operating Current @16 MHz 50 mA (5) IREF A/D Converter Reference 5 mA Current NOTES: 1. Typical values are obtained using V CC e 5.0V, T A e 25§C, and are not guaranteed. 2. Under steady state (non-transient) conditions, I OL must be externally limited as follows: Maximum I OL per Port Pin: 10 mA Maximum I OL per 8-Bit PortÐ Port 0: 26 mA Ports 1–5: 15 mA Maximum Total I OL for All Outputs Pins: 101 mA If I OL exceeds the test conditions, V OL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 3. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4V on the low level outputs of ALE and Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change from 1 to 0. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8V. It may be desirable to qualify ALE or other signals with a Schmitt Trigger, or CMOS-level input logic. 4. Capacitive loading on Ports 0 and 2 cause the V OH on ALE and PSEN to drop below the 0.9 V CC specification when the address lines are stabilizing. 5. See Figures 6–10 for test conditions. Minimum V CC for Power Down is 2V.
EXPLANATION OF THE AC SYMBOLS Each timing symbol has 5 characters. The first char- acter is always a ‘‘T’’ (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for: A: Address C: Clock D: Input Data H: Logic Level HIGH I: Instruction (Program Memory Contents) L: Logic Level LOW, or ALE P: PSEN Q: Output Data R: RD Signal T: Time V: Valid W: WR Signal X: No Longer a Valid Logic Level Z: Float For Example: TAVLL e Time from Address Valid to ALE Low TLLPL e Time from ALE Low to PSEN LowAC SPECIFICATIONS Over Operating Conditions, Load Capacitance on Port 0, ALE, and PSEN e 100 pF, Load Capacitance on all other outputs e 80 pF EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS Symbol Parameter 12 MHz Osc. Variable Osc. Units Min Max Min Max 1/TCLCL Osc. Freq. 3.5 16 MHz TLHLL ALE Pulse Width 127 2TCLCL b 40 ns TAVLL ADDR Valid to ALE Low 43 TCLCL b 40 ns TLLAX ADDR Hold after ALE Low 53 TCLCL b 30 ns TLLIV ALE Low to Valid Inst. IN 234 4TCLCL b 100 ns TLLPL ALE LOW to PSEN LOW 53 TCLCL b 30 ns TPLPH PSEN Pulse Width 205 3TCLCL b 45 ns TPLIV PSEN Low to Valid Instr In 145 3TCLCL b 105 ns TPXIX Input Instr. Hold after PSEN 00 n s TPXIZ Input Instr. Float after PSEN 59 TCLCL b 25 ns TAVIV ADDR to Valid Instr. In 312 5TCLCL b 105 ns TPLAZ PSEN Low to ADDR Float 10 10 ns TRLRH RD Pulse Width 400 6TCLCL b 100 ns TWLWH WR Pulse Width 400 6TCLCL b 100 ns TRLDV RD Low to Valid Data In 252 5TCLCL b 165 ns TRHDX Data Hold after RD 00 n s TRHDZ Data Float after RD 107 2TCLCL b 60 ns TLLDV ALE Low to Valid Data In 517 8TCLCL b 150 ns TAVDV ADDR to Valid Data In 585 9TCLCL b 165 ns TLLWL ALE Low to RD or WR Low 200 300 3TCLCL b 50 3TCLCL a 50 ns TAVWL ADDR Valid to RD or WR Low 203 4TCLCL b 130 ns TQVWX Data Valid to WR Transition 33 TCLCL b 50 ns TWHQX Data Hold after WR 33 TCLCL b 50 ns TQVWH Data Valid to WR High 433 7 TCLCL b 150 ns TRLAZ RD Low to Addr Float 0 0 ns TWHLH RD or WR High to ALE High 43 123 TCLCL b 40 TCLCL a 40 ns
EXTERNAL PROGRAM MEMORY READ CYCLE 272337–11 EXTERNAL DATA MEMORY READ CYCLE 272337–12 EXTERNAL DATA MEMORY WRITE CYCLE 272337–13
SERIAL PORT TIMINGÐSHIFT REGISTER MODE Test Conditions: Over Operating Conditions, Load Capacitance e 80 pF Symbol Parameter
12 MHz Variable
UnitsOscillator Oscillator Min Max Min Max TXLXL Serial Port Clock 1 12TCLCL ms Cycle Time TQVXH Output Data Setup to 700 10TCLCL b 133 ns Clock Rising Edge TXHQX Output Data Hold after 50 2TCLCL b 117 ns Clock Rising Edge TXHDX Input Data Hold after 0 0 ns Clock Rising Edge TXHDV Clock Rising Edge to 700 10TCLCL b 133 ns Input Data Valid SHIFT REGISTER MODE TIMING WAVEFORMS 272337–14 EXTERNAL CLOCK DRIVE Symbol Parameter Min Max Units 1/TCLCL Oscillator Frequency 3.5 16 MHz TCHCX High Time 20 ns TCLCX Low Time 20 ns TCLCH Rise Time 20 ns TCHCL Fall Time 20 ns EXTERNAL CLOCK DRIVE WAVEFORM 272337–15
SEP AC TIMING SPECIFICATIONS Test Conditions: Over Operating Conditions, Load Capacitance e 80 pF Symbol Parameter UnitsOscillator Oscillator Min Max Min Max TXSXL SEPCLK Cycle Time 1 12 TCLCL ms TXSST Output Data Setup to SEPCLK 435 6 TCLCL b 65 ns TXSOH Output Data Hold after SEPCLK 445 6 TCLCL b 55 ns TXSIH Input Data Hold after SEPCLK 210 2 TCLCL a 43 ns Sampling Edge TXSDV Input Data Valid to SEPCLK 947 12 TCLCL b 53 ns Sampling Edge SEP Waveform (SEPS1 e 0; SEPS0 e 0; CLKPOL e 0; CLKPH e 0) 272337–16 272337–17
AC TESTING INPUT, OUTPUT WAVEFORMS 272337–18 AC inputs during testing are driven at V CCb0.5V for a Logic ‘‘1’’ and 0.5V for a Logic ‘‘0’’. Timing measurements are made at V IH for a Logic ‘‘1’’ and V OL max for a Logic ‘‘0’’. FLOAT WAVEFORMS 272337–19 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, and begins to float when a 100 mV change from the loaded V OH/VOL level occurs. I OL/IOH t g20 mA. A TO D CHARACTERISTICS The absolute conversion accuracy is dependent on the accuracy of AV REF. The specifications given be- low assume adherence to the Operating Conditions section of this data sheet. Testing is done at AV REF e 5.12V, and V CC e 5.0V. OPERATING CONDITIONS VCC ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ4.0V to 6.0V AVREF ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ4.5V to 5.5V VSS,A V SS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0V ACH0–7 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀAV SS to V REF TA ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0§Ct o a70§C Ambient FOSC (STD Version)ÀÀÀÀÀÀÀÀÀÀÀ3.5 MHz to 12 MHz FOSC (-1 Version) ÀÀÀÀÀÀÀÀÀÀÀÀÀ3.5 MHz to 16 MHz A/D CONVERTER SPECIFICATIONS TA e 0§Ct o a70§C Parameter Min Typ * Max Units ** Notes Resolution 256 256 Levels 8 8 Bits Absolute Error (Ch 2–7) 0 g1 LSB Absolute Error (Ch 0 and 1) 0 g2 LSB Full Scale Error g1 LSB Zero Offset Error g1 LSB Non-Linearity 0 g1 LSB Differential Non-Linearity 0 g1 LSB Channel-to-Channel Matching 0 g1 LSB Repeatability g0.25 LSB
A/D CONVERTER SPECIFICATIONS TA e 0§Ct o a70§C (Continued) Parameter Min Typ * Max Units ** Notes Temperature Coefficients: Offset 0.003 LSB/ §C Full Scale 0.003 LSB/ §C Differential Non-Linearity 0.003 LSB/ §C Input Capacitance 3 pF Off Isolation b60 dB (8, 9) Feedthrough b60 dB (8) VCC Power Supply Rejection b60 dB (8) Input Resistance to 750 1.2K X Sample-and-Hold Capacitor DC Input Leakage 0 3.0 mA NOTES: *These values are expected for most parts at 25 §C **AN ‘‘LSB’’ as used here, has a value of approximately 20 mV. 8. DC to 100 KHz 9. Multiplexer Break-Before-Make Guaranteed. 10. There is no indication when a single A/D conversion is complete. Please refer to the 8XC51GB Hardware Description on how to read a single A/D conversion. 11. T CY e 12 TCLCL A/D Conversion Time Notes Per Channel 26 T CY (10, 11)
8 Conversions 208 T CY (11)
(also refer to timing diagrams). DATA LINES: P0.0–P0.7 for D0–D7. *See Table 2 for proper input on these pins. Figure 11. Programming the OTP Table 2. OTP Programming Modes
- Input the valid address on the address lines.
- Input the appropriate data byte on the data lines.
- Activate the correct combination of control sig-
/VPP from V CC to 12.75V g0.25V.
- Pulse ALE/PROG 5 times for the OTP array, and
Figure 12. Programming Signal’s Waveforms
gram against software piracy.
- If program protection is desired, the user submits
user must submit an encryption table. ming the Encryption Array, refer to Table 2. possible program protection. and data . The 83C51GB has 1 program lock bit. provided in Table 2 for Read Signature Byte. Table 3. Program Lock Bits and the Features
2 P U U MOVC instructions executed from external program
3 P P U Same as 2, also verify is disabled. 4 P P P Same as 3, also external execution is disabled. *Any other combination of lock bits is not defined.
OTP PROGRAMMING AND VERIFICATION CHARACTERISTICS (TA e 21§Ct o2 7 §C; V CC e 5V g 20%; V SS e 0V) Symbol Parameter Min Max Units VPP Programming Supply Voltage 12.5 13.0 V IPP Programming Supply Current 75 mA 1/TCLCL Oscillator Frequency 4 6 MHz TAVGL Address Setup to PROG Low 48TCLCL TGHAX Address Hold after PROG 48TCLCL TDVGL Data Setup to PROG Low 48TCLCL TGHDX Data Hold after PROG 48TCLCL TEHSH (Enable) High to V PP 48TCLCL TSHGL V PP Setup to PROG Low 10 ms TGHSL V PP Hold after PROG 10 ms TGLGH PROG Width 90 110 ms TAVQV Address to Data Valid 48TCLCL TELQV ENABLE Low to Data Valid 48TCLCL TEHQZ Data Float after ENABLE 0 48TCLCL TGHGL PROG High to PROG Low 10 ms PROGRAMMING AND VERIFICATION WAVEFORMS 272337–22 *25 Pulses for Encryption Table and Lock Bits.
Absolute ErrorÐ The maximum difference between corresponding actual and ideal code transitions. Ab- solute Error accounts for all deviations of an actual converter from an ideal converter. Actual CharacteristicÐ The characteristic of an ac- tual converter. The characteristic of a given convert- er may vary over temperature, supply voltage, and frequency conditions. An actual characteristic rarely has ideal first and last transition locations or ideal code widths. It may even vary over multiple conver- sions under the same conditions. Break-Before-MakeÐThe property of a multiplexer which guarantees that a previously selected channel will be deselected before a new channel is selected (e.g., the converter will not short inputs together). Channel-to-Channel MatchingÐ The difference be- tween corresponding code transitions of actual char- acteristics taken from different channels under the same temperature, voltage and frequency condi- tions. CharacteristicÐA graph of input voltage versus the resultant output code for an A/D converter. It de- scribes the transfer function of the A/D converter. CodeÐThe digital value output by the converter. Code CenterÐ The voltage corresponding to the midpoint between two adjacent code transitions. Code TransitionÐ The point at which the converter changes from an output code of Q, to a code of Q a 1. The input voltage corresponding to a code tran- sition is defined to be that voltage which is equally likely to produce either of two adjacent codes. Code WidthÐ The voltage corresponding to the dif- ference between two adjacent code transitions. CrosstalkÐSee ‘‘Off-Isolation’’. DC Input LeakageÐ Leakage current to ground from an analog input pin. Differential Non-LinearityÐ The difference be- tween the ideal and actual code widths of the termi- nal based characteristic. FeedthroughÐAttenuation of a voltage applied on the selected channel of the A/D Converter after the sample window closes. Full Scale ErrorÐ The difference between the ex- pected and actual input voltage corresponding to the full scale code transition. Ideal CharacteristicÐ A characteristic with its first code transition at V IN e 0.5 LSB, its last code tran- sition at V IN e (VREF b 1.5 LSB) and all code widths equal to one LSB. Input ResistanceÐ The effective series resistance from the analog input pin to the sample capacitor. LSBÐLeast Significant BitÐ The voltage corre- sponding to the full scale voltage divided by 2 n, where n is the number of bits of resolution of the converter. For an 8-bit converter with a reference voltage of 5.12V, one LSB is 20 mV. Note that this is different than digital LSBs since an uncertainty of two LSBs, when referring to an A/D converter, equals 40 mV. (This has been confused with an un- certainty of two digital bits, which would mean four counts, or 80 mV). MonotonicÐThe property of successive approxi- mation converters which guarantees that increasing input voltages produce adjacent codes of increasing value, and that decreasing input voltages produce adjacent codes of decreasing value. No Missed CodesÐ For each and every output code, there exists a unique input voltage range which produces that code only. Non-LinearityÐThe maximum deviation of code transitions of the terminal based characteristic from the corresponding code transitions of the ideal char- acteristic. Off-IsolationÐAttenuation of a voltage applied on a deselected channel of the A/D converter. (Also re- ferred to as Crosstalk.) RepeatabilityÐThe difference between corre- sponding code transitions from different actual char- acteristics taken from the same converter on the same channel at the same temperature, voltage and frequency conditions. ResolutionÐThe number of input voltage levels that the converter can unambiguously distinguish between. Also defines the number of useful bits of information which the converter can return. Sample DelayÐ The delay from receiving the start conversion signal to when the sample window opens. Sample Delay UncertaintyÐ The variation in the sample delay. Sample TimeÐ The time that the sample window is open. Sample Time UncertaintyÐ The variation in the sample time.
Sample WindowÐ Begins when the sample capaci- tor is attached to a selected channel and ends when the sample capacitor is disconnected from the se- lected channel. Successive ApproximationÐ An A/D conversion method which uses a binary search to arrive at the best digital representation of an analog input. Temperature CoefficientsÐ Change in the stated variable per degree centrigrade temperature change. Temperature coefficients are added to the typical values of a specification to see the effect of temperature drift. Terminal Based CharacteristicÐ An actual charac- teristic which has been rotated and translated to re- move zero offset and full scale error. V CC RejectionÐAttenuation of noise on the V CC line to the A/D converter. Zero OffsetÐ The difference between the expected and actual input voltage corresponding to the first code transition. DATA SHEET REVISION SUMMARY The following differences exist between this data- sheet and the previous version (270869-003): 1. Merged 87C51GB Express (270889-001). 2. New order number 272337-001. The following differences exist between the 270869- 003 data sheet and the previous version (270869- 002): 1. Changed data sheet status from ‘‘Advance Infor- mation’’ to ‘‘Preliminary’’ and updated associated notices. 2. Added 83C51GB throughout. 3. Added Package and Process Information. 4. Clarified g2 LSB accuracy for channels 0 and 1 in A/D Converter Section. 5. Added ‘‘ROM and EPROM Lock System’’ section and added 83C51GB to ‘‘Program Lock Bits’’ section. 6. Modified Signature Bytes Table. The following differences exist between the 270869-002 data sheet and the previous version (270869-001): 1. Changed data sheet status from ‘‘Product Pre- view’’ to ‘‘Advance Information’’ and updated as- sociated notices. 2. Asynchronous port reset was added to RESET pin description. 3. ALE disable paragraph was added to ALE pin de- scription. 4. C 1,C 2 guidelines clarified in Figure 4. 5. Operating Conditions heading was added. 6. Maximum I OL per I/O pin was added to Absolute Maximum Ratings. 7. VT a,V T b,V HYS,V OL2, and V TL removed. 8. V OL value for ALE included with V OL1. 9. V IL1 and V IL2 added. 10. RRST minimum changed from 40K to 50K. RRST maximum changed from 225K to 300K. 11. I PD maximum changed from 200 mAt o5 0 mA. 12. I DL maximum changed from 15 mA to 18 mA. 13. Typical values for I PD,I DL,I CC, and I REF re- moved. 14. Note 3 (page 9) was reworded. 15. SEP AC Timings added. 16. A/D Absolute Error for Channels 0 and 1 changed to g2 LSB. 17. T CY clarified. 18. Encryption array paragraph was added. 19. Corrected pin numbers on Figure 11 to reflect PLCC package.