80C186XL INTEL | Alldatasheet
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Technical content
*Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. October 1995 COPYRIGHT © INTEL CORPORATION, 1995 Order Number: 272431-004 80C186XL/80C188XL 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS Y Low Power, Fully Static Versions of 80C186/80C188 Y Operation Modes: Ð Enhanced Mode Ð DRAM Refresh Control Unit Ð Power-Save Mode Ð Direct Interface to 80C187 (80C186XL Only) Ð Compatible Mode Ð NMOS 80186/80188 Pin-for-Pin Replacement for Non-Numerics
Applications
Ð Static, Modular CPU Ð Clock Generator Ð 2 Independent DMA Channels Ð Programmable Interrupt Controller Ð 3 Programmable 16-Bit Timers Ð Dynamic RAM Refresh Control Unit Ð Programmable Memory and Peripheral Chip Select Logic Ð Programmable Wait State Generator Ð Local Bus Controller Ð Power-Save Mode Ð System-Level Testing Support (High Impedance Test Mode) Y Completely Object Code Compatible with Existing 8086/8088 Software and Has 10 Additional Instructions over Y Speed Versions Available Ð 25 MHz (80C186XL25/80C188XL25) Ð 20 MHz (80C186XL20/80C188XL20) Ð 12 MHz (80C186XL12/80C188XL12) Y Direct Addressing Capability to
1 MByte Memory and 64 Kbyte I/O
Y Available in 68-Pin: Ð Plastic Leaded Chip Carrier (PLCC) Ð Ceramic Pin Grid Array (PGA) Ð Ceramic Leadless Chip Carrier (JEDEC A Package) Y Available in 80-Pin: Ð Quad Flat Pack (EIAJ) Ð Shrink Quad Flat Pack (SGFP) Y Available in Extended Temperature Range ( b40§Ct o a85§C) The Intel 80C186XL is a Modular Core re-implementation of the 80C186 microprocessor. It offers higher speed and lower power consumption than the standard 80C186 but maintains 100% clock-for-clock functional com- patibility. Packaging and pinout are also identical. 272431-1
16-Bit High-Integration Embedded Processors CONTENTS PAGE INTRODUCTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4 80C186XL CORE ARCHITECTURE ÀÀÀÀÀÀÀÀ 4 80C186XL Clock Generator ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4 Bus Interface Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5 80C186XL PERIPHERAL ARCHITECTURE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5 Chip-Select/Ready Generation Logic ÀÀÀÀÀÀÀ 5 DMA Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6 Timer/Counter Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6 Interrupt Control Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6 Enhanced Mode Operation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6 Queue-Status Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6 DRAM Refresh Control Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7 Power-Save Control ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7 Interface for 80C187 Math Coprocessor (80C186XL Only) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7 ONCE Test Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7 PACKAGE INFORMATION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8 Pin Descriptions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8 80C186XL/80C188XL Pinout Diagrams ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 16 ELECTRICAL SPECIFICATIONS ÀÀÀÀÀÀÀÀÀ 22 Absolute Maximum Ratings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22 DC SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22 Power Supply Current ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23 CONTENTS PAGE AC SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24 Major Cycle Timings (Read Cycle) ÀÀÀÀÀÀÀÀÀ 24 Major Cycle Timings (Write Cycle) ÀÀÀÀÀÀÀÀÀ 26 Major Cycle Timings (Interrupt Acknowledge Cycle) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 27 Software Halt Cycle Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 28 Clock Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 29 Ready, Peripheral and Queue Status Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 30 Reset and Hold/HLDA Timings ÀÀÀÀÀÀÀÀÀÀÀÀ 31 AC TIMING WAVEFORMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 36 AC CHARACTERISTICS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 37 EXPLANATION OF THE AC SYMBOLS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 39 DERATING CURVES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 40 80C186XL/80C188XL EXPRESS ÀÀÀÀÀÀÀÀÀ 41 80C186XL/80C188XL EXECUTION TIMINGS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 41 INSTRUCTION SET SUMMARY ÀÀÀÀÀÀÀÀÀÀ 42 REVISION HISTORY ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 48 ERRATA ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 48 PRODUCT IDENTIFICATION ÀÀÀÀÀÀÀÀÀÀÀÀÀ 48
Pin names in parentheses applies to 80C188XL. Figure 1. 80C186XL/80C188XL Block Diagram
multiplexed address/data bus. # Drive LOCK HIGH and then float. # RD/QSMD low results in Queue Status Mode. # UCS and LCS low results in ONCE Mode. control register block is shown in Figure 3. are provided for midrange memory. Figure 3. Internal Register Map
The 80C186XL provides a chip select for low memo- ry called LCS . The bottom of memory contains the interrupt vector table, starting at location 00000H. The 80C186XL provides four MCS lines which are active within a user-locatable memory block. This block can be located within the 80C186XL 1 Mbyte memory address space exclusive of the areas de- fined by UCS and LCS . Both the base address and size of this memory block are programmable. The 80C186XL can generate chip selects for up to seven peripheral devices. These chip selects are ac- tive for seven contiguous blocks of 128 bytes above a programmable base address. The base address may be located in either memory or I/O space. The 80C186XL can generate a READY signal inter- nally for each of the memory or peripheral CS lines. The number of WAIT states to be inserted for each peripheral or memory is programmable to provide 0–3 wait states for all accesses to the area for which the chip select is active. In addition, the 80C186XL may be programmed to either ignore ex- ternal READY for each chip-select range individually or to factor external READY with the integrated ready generator. Upon RESET, the Chip-Select/Ready Logic will per- form the following actions: # All chip-select outputs will be driven HIGH. # Upon leaving RESET, the UCS line will be pro- grammed to provide chip selects to a 1K block with the accompanying READY control bits set at 011 to insert 3 wait states in conjunction with ex- ternal READY (i.e., UMCS resets to FFFBH). # No other chip select or READY control registers have any predefined values after RESET. They will not become active until the CPU accesses their control registers. DMA Unit The 80C186XL DMA controller provides two inde- pendent high-speed DMA channels. Data transfers can occur between memory and I/O spaces (e.g., Memory to I/O) or within the same space (e.g., Memory to Memory or I/O to I/O). Data can be transferred either in bytes (8 bits) or in words (16 bits) to or from even or odd addresses. NOTE: Only byte transfers are possible on the 80C188XL. Each DMA channel maintains both a 20-bit source and destination pointer which can be optionally in- cremented or decremented after each data transfer (by one or two depending on byte or word transfers). Each data transfer consumes 2 bus cycles (a mini- mum of 8 clocks), one cycle to fetch data and the other to store data. Timer/Counter Unit The 80C186XL provides three internal 16-bit pro- grammable timers. Two of these are highly flexible and are connected to four external pins (2 per timer). They can be used to count external events, time ex- ternal events, generate nonrepetitive waveforms, etc. The third timer is not connected to any external pins, and is useful for real-time coding and time de- lay applications. In addition, the third timer can be used as a prescaler to the other two, or as a DMA request source. Interrupt Control Unit The 80C186XL can receive interrupts from a number of sources, both internal and external. The 80C186XL has 5 external and 2 internal interrupt sources (Timer/Couners and DMA). The internal in- terrupt controller serves to merge these requests on a priority basis, for individual service by the CPU. Enhanced Mode Operation In Compatible Mode the 80C186XL operates with all the features of the NMOS 80186, with the exception of 8087 support (i.e. no math coprocessing is possi- ble in Compatible Mode). Queue-Status information is still available for design purposes other than 8087 support. All the Enhanced Mode features are completely masked when in Compatible Mode. A write to any of the Enhanced Mode registers will have no effect, while a read will not return any valid data. In Enhanced Mode, the 80C186XL will operate with Power-Save, DRAM refresh, and numerics coproc- essor support (80C186XL only) in addition to all the Compatible Mode features. If connected to a math coprocessor (80C186XL only), this mode will be invoked automatically. With- out an NPX, this mode can be entered by tying the RESET output signal from the 80C186XL to the TEST /BUSY input. Queue-Status Mode The queue-status mode is entered by strapping the RD pin low. RD is sampled at RESET and if LOW, the 80C186XL will reconfigure the ALE and WR pins to be QS0 and QS1 respectively. This mode is avail- able on the 80C186XL in both Compatible and En- hanced Modes.
vated when the BIU executes the refresh bus cycle. essor clock frequency by a programmable factor. tion for one-fourth a programmed block size. Table 1. MCS Assignments pled on the low-to-high transition of the RES pin. to guarantee entrance into ONCE Mode.
PACKAGE INFORMATION
This section describes the pin functions, pinout and thermal characteristics for the 80C186XL in the Quad Flat Pack (QFP), Plastic Leaded Chip Carrier (PLCC), Leadless Chip Carrier (LCC) and the Shrink Quad Flat Pack (SQFP). For complete package specifications and information, see the Intel Packag- ing Outlines and Dimensions Guide (Order Number: 231369). Pin Descriptions Each pin or logical set of pins is described in Table 3. There are four columns for each entry in the Pin Description Table. The following sections describe each column. Column 1: Pin Name In this column is a mnemonic that de- scribes the pin function. Negation of the signal name (i.e., RESIN ) implies that the signal is active low. Column 2: Pin Type A pin may be either power (P), ground (G), input only (I), output only (O) or in- put/output (I/O). Please note that some pins have more than one function. Column 3: Input Type (for I and I/O types only) These are two different types of input pins on the 80C186XL: asynchronous and synchronous. Asynchronous pins require that setup and hold times be met only to guarantee recognition. Synchro- nous input pins require that the setup and hold times be met to guarantee proper operation. Stated simply, missing a setup or hold on an asynchronous pin will result in something minor (i.e., a tim- er count will be missed) whereas miss- ing a setup or hold on a synchronous pin result in system failure (the system will ‘‘lock up’’). An input pin may also be edge or level sensitive. Column 4: Output States (for O and I/O types only) The state of an output or I/O pin is de- pendent on the operating mode of the device. There are four modes of opera- tion that are different from normal active mode: Bus Hold, Reset, Idle Mode, Pow- erdown Mode. This column describes the output pin state in each of these modes. The legend for interpreting the information in the Pin Descriptions is shown in Table 2. As an example, please refer to the table entry for AD7:0. The ‘‘I/O’’ signifies that the pins are bidirec- tional (i.e., have both an input and output function). The ‘‘S’’ indicates that, as an input the signal must be synchronized to CLKOUT for proper operation. The ‘‘H(Z)’’ indicates that these pins will float while the processor is in the Hold Acknowledge state. R(Z) indicates that these pins will float while RESIN is low. All pins float while the processor is in the ONCE Mode (with the exception of X2).
Table 2. Pin Description Nomenclature
Table 3. Pin Descriptions VCC P System Power: a5 volt power supply. clock periods corresponding to the length of the RES signal. CLKOUT. CLKOUT is active during reset and bus hold. generation via an RC network. HIGH state when the input is not externally driven. , interrupts will be serviced. to accept a new command. BUSY is active HIGH. Pin names in parentheses apply to the 80C188XL.
Table 3. Pin Descriptions (Continued) Maskable Interrupt cannot be avoided by programming. (see Interrupt Controller section of this data sheet). of the bus in memory or I/O operations. Pin names in parentheses apply to the 80C188XL.
indicate a refresh bus cycle. Status Mode, RD must be connected to GND. LOW to yield control to the SRDY pin. Pin names in parentheses apply to the 80C188XL.
SRDY pin accepts an active-HIGH input synchronized to CLKOUT. unused, it should be tied LOW to yield control to the ARDY pin. HOLD I A(L) Ð HOLD indicates that another bus master is requesting the local bus. will again drive the local bus and control lines. Pin names in parentheses apply to the 80C188XL.
enter ONCE Mode inadvertently. LCS is software programmable. not enter ONCE mode inadvertently. range portion of memory (8K–512K). The addressMCS2 O H(1) ranges activating MCS0–3 are software programmable. signal numerics coprocessor errors. range activating PCS5 is software-programmable. the previously latched value during HOLD. Pin names in parentheses apply to the 80C188XL.
this pin will retain the previously latched value during HOLD. places write data on the data bus. products, do not connect to these pins. Pin names in parentheses apply to the 80C188XL.
XXXXXXXXC indicates the Intel FPO number. Figure 4. 80C186XL/80C188XL Pinout Diagrams
XXXXXXXXC indicates the Intel FPO number. Figure 4. 80C186XL/80C188XL Pinout Diagrams (Continued)
XXXXXXXXA indicates the Intel FPO number. Figure 4. 80C186XL/80C288XL Pinout Diagrams (Continued)
Table 4. LCC/PLCC Pin Functions with Location Pin names in parentheses apply to the 80C188XL. Table 5. LCC/PGA/PLCC Pin Locations with Pin Names
1 AD15 (A15)
2 AD7
3 AD14 (A14)
4 AD6
5 AD13 (A13)
6 AD5
7 AD12 (A12)
8 AD4
10 AD11 (A11)
11 AD3
12 AD10 (A10)
13 AD2
14 AD9 (A9)
15 AD1
16 AD8 (A8)
17 AD0
18 DRQ0
19 DRQ1
20 TMR IN 0
21 TMR IN 1
22 TMR OUT 0
23 TMR OUT 1
24 RES
25 PCS0
26 V SS
27 PCS1
28 PCS2
29 PCS3
30 PCS4
31 PCS5 /A1
32 PCS6 /A2
33 LCS
34 UCS
35 MCS3 /NPS
36 MCS2
37 MCS1 /ERROR
38 MCS0 /PEREQ
39 DEN
40 DT/R
41 INT3/INTA1
42 INT2/INTA0
43 V CC
44 INT1/SELECT
45 INT0
46 NMI
47 TEST
48 LOCK
49 SRDY
50 HOLD
51 HLDA
55 ARDY
56 CLKOUT
57 RESET
61 ALE/QS0
63 WR /QS1
64 BHE (RFSH)
65 A19/S2
66 A18/S3
67 A17/S4
68 A16/S3
Pin names in parentheses apply to the 80C188XL.
Table 6. QFP Pin Functions with Location Pin names in parentheses apply to the 80C188XL. Table 7. QFP Pin Locations with Pin Names
3 A16/S3
4 A17/S4
5 A18/S5
6 A19/S6
7 BHE
10 ALE/QS0
13 V SS
18 RESET
19 CLKOUT
20 ARDY
25 HLDA
26 HOLD
27 SRDY
28 LOCK
29 TEST /BUSY
30 NMI
31 INT0
32 INT1/SELECT
33 V CC
34 V CC
35 INT2/INTA0
36 INT3/INTA1
37 DT/R
38 DEN
39 MCS0 /PEREQ
40 MCS1 /ERROR
41 MCS2
42 MCS3 /NPS
45 UCS
46 LCS
47 PCS6 /A2
48 PCS5 /A1
49 PCS4
50 PCS3
51 PCS2
52 PCS1
53 V SS
54 PCS0
55 RES
56 TMR OUT 1
57 TMR OUT 0
58 TMR IN 1
59 TMR IN 0
60 DRQ1
61 DRQ0
64 AD0
65 AD8 (A8)
66 AD1
67 AD9 (A9)
68 AD2
69 AD10 (A10)
70 AD3
71 AD11 (A11)
73 V CC
74 AD4
75 AD12 (A12)
76 AD5
77 AD13 (A13)
78 AD6
79 AD14 (A14)
80 AD7
Pin names in parentheses apply to the 80C188XL.
Table 8. SQFP Pin Functions with Location Pin names in parentheses apply to the 80C188XL. Table 9. SQFP Pin Locations with Pin Names
1 AD0
2 AD8 (A8)
3 AD1
5 AD9 (A9)
6 AD2
7 AD10 (A10)
8 AD3
9 AD11 (A11)
11 V CC
12 AD4
13 AD12 (A12)
14 AD5
15 AD13 (A13)
16 AD6
17 AD14 (A14)
18 AD7
19 AD15 (A15)
21 A16/S3
22 A17/S4
23 A18/S5
24 A19/S6
26 BHE
27 WR /QS1
28 RD /QSMD
29 ALE/QS0
31 V SS
34 RESET
36 CLKOUT
37 ARDY
41 V SS
42 HLDA
43 HOLD
44 SRDY
45 LOCK
46 TEST /BUSY
47 NMI
48 INT0
49 INT1/SELECT
50 V CC
51 V CC
52 INT2/INTA0
53 INT3/INTA1
54 DT/R
56 DEN
57 MCS0 /PEREQ
58 MCS1 /ERROR
59 MCS2
60 MCS3 /NPS
61 V CC
62 UCS
63 LCS
64 PCS6 /A2
65 PCS5 /A1
66 PCS4
67 PCS3
68 PCS2
69 PCS1
70 V SS
71 PCS0
73 RES
74 TMR OUT 1
75 TMR OUT 0
76 TMR IN 1
77 TMR IN 0
78 DRQ1
79 DRQ0
Pin names in parentheses apply to the 80C188XL.
Absolute Maximum Ratings * Ambient Temperature under Bias ÀÀÀÀ0 §Ct o a70§C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b65§Ct o a150§C Voltage on Any Pin with Respect to Ground ÀÀÀÀÀÀÀÀÀÀÀÀ b1.0V to a7.0V Package Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1W Not to exceed the maximum allowable die tempera- ture based on thermal resistance of the package. NOTICE: This data sheet contains preliminary infor- mation on new products in production. The specifica- tions are subject to change without notice. Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. NOTICE: The specifications are subject to change without notice. DC SPECIFICATIONS TA e 0§Ct o a70§C, V CC e 5V g10% Symbol Parameter Min Max Units Test Conditions VIL Input Low Voltage b0.5 0.2 V CC b 0.3 V (Except X1) VIL1 Clock Input Low b0.5 0.6 V Voltage (X1) VIH Input High Voltage 0.2 V CC a 0.9 V CC a 0.5 V (All except X1 and RES ) VIH1 Input High Voltage (RES ) 3.0 V CC a 0.5 V VIH2 Clock Input High 3.9 V CC a 0.5 V Voltage (X1) VOL Output Low Voltage 0.45 V I OL e 2.5 mA (S0, 1, 2) IOL e 2.0 mA (others) VOH Output High Voltage 2.4 V CC VI OH eb 2.4 mA @ 2.4V (4) VCC b 0.5 V CC VI OH eb 200 mA @ VCC b0.5(4) ICC Power Supply Current 100 mA @ 25 MHz, 0 §C VCC e 5.5V(3) 90 mA @ 20 MHz, 0 §C VCC e 5.5V(3) 62.5 mA @ 12 MHz, 0 §C VCC e 5.5V (3) 100 mA @ DC 0 §C VCC e 5.5V ILI Input Leakage Current g10 mA @ 0.5 MHz, 0.45V s VIN s VCC ILO Output Leakage Current g10 mA @ 0.5 MHz, 0.45V s VOUT s VCC(1) VCLO Clock Output Low 0.45 V I CLO e 4.0 mA
- Pins being floated during HOLD or by invoking the ONCE Mode.
- Characterization conditions are a) Frequency
- Current is measured with the device in RESET with X1 and X2 driven and all other non-power pins open.
Local Bus Controller and Reset for details. and X2 driven and all other non-power pins open. is static. I QL is typically less than 100 mA. Figure 5. I CC vs Frequency
MAJOR CYCLE TIMINGS (READ CYCLE) TA e 0§Ct o a70§C, V CC e 5V g10% All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C L e 50 pF. For AC tests, input V IL e 0.45V and V IH e 2.4V except at X1 where V IH e VCC b 0.5V. Values Conditions TestSymbol Parameter 80C186XL25 80C186XL20 80C186XL12 Unit Min Max Min Max Min Max 80C186XL GENERAL TIMING REQUIREMENTS (Listed More Than Once) TDVCL Data in Setup (A/D) 8 10 15 ns TCLDX Data in Hold (A/D) 3 3 3 ns 80C186XL GENERAL TIMING RESPONSES (Listed More Than Once) TCHSV Status Active Delay 3 20 3 25 3 35 ns TCLSH Status Inactive Delay 3 20 3 25 3 35 ns TCLAV Address Valid Delay 3 20 3 27 3 36 ns TCLAX Address Hold 0 0 0 ns TCLDV Data Valid Delay 3 20 3 27 3 36 ns TCHDX Status Hold Time 10 10 10 ns TCHLH ALE Active Delay 20 20 25 ns TLHLL ALE Width T CLCL b 15 T CLCL b 15 T CLCL b 15 ns TCHLL ALE Inactive Delay 20 20 25 ns TAVLL Address Valid to ALE Low T CLCH b 10 T CLCH b 10 T CLCH b 15 ns Equal Loading TLLAX Address Hold from ALE T CHCL b 8T CHCL b 10 T CHCL b 15 ns Equal Inactive Loading TAVCH Address Valid to Clock High 0 0 0 ns TCLAZ Address Float Delay T CLAX 20 T CLAX 20 T CLAX 25 ns TCLCSV Chip-Select Active Delay 3 20 3 25 3 33 ns TCXCSX Chip-Select Hold from T CLCH b 10 T CLCH b 10 T CLCH b 10 ns Equal Command Inactive Loading TCHCSX Chip-Select Inactive Delay 3 17 3 20 3 30 ns TDXDL DEN Inactive to DT/R Low 0 0 0 ns Equal Loading TCVCTV Control Active Delay 1 3 17 3 22 3 37 ns TCVDEX DEN Inactive Delay 3 17 3 22 3 37 ns TCHCTV Control Active Delay 2 3 20 3 22 3 37 ns TCLLV LOCK Valid/Invalid Delay 3 17 3 22 3 37 ns
AC SPECIFICATIONS (Continued) MAJOR CYCLE TIMINGS (READ CYCLE) (Continued) TA e 0§Ct o a70§C, V CC e 5V g10% All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C L e 50 pF. For AC tests, input V IL e 0.45V and V IH e 2.4V except at X1 where V IH e VCC b 0.5V. Values Conditions TestSymbol Parameter 80C186XL25 80C186XL20 80C186XL12 Unit Min Max Min Max Min Max 80C186XL TIMING RESPONSES (Read Cycle) TAZRL Address Float 0 0 0 ns to RD Active TCLRL RD Active Delay 3 20 3 27 3 37 ns TRLRH RD Pulse Width 2T CLCL b 15 2T CLCL b 20 2T CLCL b 25 ns TCLRH RD Inactive Delay 3 20 3 27 3 37 ns TRHLH RD Inactive T CLCH b 14 T CLCH b 14 T CLCH b 14 ns Equal to ALE High Loading TRHAV RD Inactive to T CLCL b 15 T CLCL b 15 T CLCL b 15 ns Equal Address Active Loading
AC SPECIFICATIONS (Continued) MAJOR CYCLE TIMINGS (WRITE CYCLE) TA e 0§Ct o a70§C, V CC e 5V g10% All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C L e 50 pF. For AC tests, input V IL e 0.45V and V IH e 2.4V except at X1 where V IH e VCC b 0.5V. Values Conditions TestSymbol Parameter 80C186XL25 80C186XL20 80C186XL12 Unit Min Max Min Max Min Max 80C186XL GENERAL TIMING RESPONSES (Listed More Than Once) TCHSV Status Active Delay 3 20 3 25 3 35 ns TCLSH Status Inactive Delay 3 20 3 25 3 35 ns TCLAV Address Valid Delay 3 20 3 27 3 36 ns TCLAX Address Hold 0 0 0 ns TCLDV Data Valid Delay 3 20 3 27 3 36 ns TCHDX Status Hold Time 10 10 10 ns TCHLH ALE Active Delay 20 20 25 ns TLHLL ALE Width T CLCL b 15 T CLCL b 15 T CLCL b 15 ns TCHLL ALE Inactive Delay 20 20 25 ns TAVLL Address Valid to ALE Low T CLCH b 10 T CLCH b 10 T CLCH b 15 ns Equal Loading TLLAX Address Hold from ALE T CHCL b 10 T CHCL b 10 T CHCL b 15 ns Equal Inactive Loading TAVCH Address Valid to Clock High 0 0 0 ns TCLDOX Data Hold Time 3 3 3 ns TCVCTV Control Active Delay 1 3 20 3 25 3 37 ns TCVCTX Control Inactive Delay 3 17 3 25 3 37 ns TCLCSV Chip-Select Active Delay 3 20 3 25 3 33 ns TCXCSX Chip-Select Hold from T CLCH b 10 T CLCH b 10 T CLCH b 10 ns Equal Command Inactive Loading TCHCSX Chip-Select Inactive Delay 3 17 3 20 3 30 ns TDXDL DEN Inactive to DT/R Low 0 0 0 ns Equal Loading TCLLV LOCK Valid/Invalid Delay 3 17 3 22 3 37 ns 80C186XL TIMING RESPONSES (Write Cycle) TWLWH WR Pulse Width 2T CLCL b 15 2T CLCL b 20 2T CLCL b 25 ns TWHLH WR Inactive to ALE High T CLCH b 14 T CLCH b 14 T CLCH b 14 ns Equal Loading TWHDX Data Hold after WR TCLCL b 10 T CLCL b 15 T CLCL b 20 ns Equal Loading TWHDEX WR Inactive to DEN Inactive T CLCH b 10 T CLCH b 10 T CLCH b 10 ns Equal Loading
AC SPECIFICATIONS (Continued) MAJOR CYCLE TIMINGS (INTERRUPT ACKNOWLEDGE CYCLE) TA e 0§Ct o a70§C, V CC e 5V g10% All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C L e 50 pF. For AC tests, input V IL e 0.45V and V IH e 2.4V except at X1 where V IH e VCC b 0.5V. Values Conditions TestSymbol Parameter 80C186XL25 80C186XL20 80C186XL12 Unit Min Max Min Max Min Max 80C186XL GENERAL TIMING REQUIREMENTS (Listed More Than Once) TDVCL Data in Setup (A/D) 8 10 15 ns TCLDX Data in Hold (A/D) 3 3 3 ns 80C186XL GENERAL TIMING RESPONSES (Listed More Than Once) TCHSV Status Active Delay 3 20 3 25 3 35 ns TCLSH Status Inactive Delay 3 20 3 25 3 35 ns TCLAV Address Valid Delay 3 20 3 27 3 36 ns TAVCH Address Valid to Clock High 0 0 0 ns TCLAX Address Hold 0 0 0 ns TCLDV Data Valid Delay 3 20 3 27 3 36 ns TCHDX Status Hold Time 10 10 10 ns TCHLH ALE Active Delay 20 20 25 ns TLHLL ALE Width T CLCL b 15 T CLCL b 15 T CLCL b 15 ns TCHLL ALE Inactive Delay 20 20 25 ns TAVLL Address Valid to ALE Low T CLCH b 10 T CLCH b 10 T CLCH b 15 ns Equal Loading TLLAX Address Hold to ALE T CHCL b 10 T CHCL b 10 T CHCL b 15 ns Equal Inactive Loading TCLAZ Address Float Delay T CLAX 20 T CLAX 20 T CLAX 25 ns TCVCTV Control Active Delay 1 3 17 3 25 3 37 ns TCVCTX Control Inactive Delay 3 17 3 25 3 37 ns TDXDL DEN Inactive to DT/R Low 0 0 0 ns Equal Loading TCHCTV Control Active Delay 2 3 20 3 22 3 37 ns TCVDEX DEN Inactive Delay 3 17 3 22 3 37 ns (Non-Write Cycles) TCLLV LOCK Valid/Invalid Delay 3 17 3 22 3 37 ns
AC SPECIFICATIONS (Continued) SOFTWARE HALT CYCLE TIMINGS TA e 0§Ct o a70§C, V CC e 5V g10% All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C L e 50 pF. For AC tests, input V IL e 0.45V and V IH e 2.4V except at X1 where V IH e VCC b 0.5V. Values Conditions TestSymbol Parameter 80C186XL25 80C186XL20 80C186XL12 Unit Min Max Min Max Min Max 80C186XL GENERAL TIMING REQUIREMENTS (Listed More Than Once) TCHSV Status Active Delay 3 20 3 25 3 35 ns TCLSH Status Inactive Delay 3 20 3 25 3 35 ns TCLAV Address Valid Delay 3 20 3 27 3 36 ns TCHLH ALE Active Delay 20 20 25 ns TLHLL ALE Width T CLCL b 15 T CLCL b 15 T CLCL b 15 ns TCHLL ALE Inactive Delay 20 20 25 ns TDXDL DEN Inactive to DT/R Low 0 0 0 ns Equal Loading TCHCTV Control Active Delay 2 3 20 3 22 3 37 ns
AC SPECIFICATIONS (Continued) CLOCK TIMINGS TA e 0§Ct o a70§C, V CC e 5V g10% All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C L e 50 pF. For AC tests, input V IL e 0.45V and V IH e 2.4V except at X1 where V IH e VCC b 0.5V. Values Conditions TestSymbol Parameter 80C186XL25 80C186XL20 80C186XL12 Unit Min Max Min Max Min Max 80C186XL CLKIN REQUIREMENTS (1) TCKIN CLKIN Period 20 % 25 % 40 % ns TCLCK CLKIN Low Time 8 % 10 % 16 % ns 1.5V (2) TCHCK CLKIN High Time 8 % 10 % 16 % ns 1.5V (2) TCKHL CLKIN Fall Time 5 5 5 ns 3.5 to 1.0V TCKLH CLKIN Rise Time 5 5 5 ns 1.0 to 3.5V 80C186XL CLKOUT TIMING TCICO CLKIN to 17 17 21 ns CLKOUT Skew TCLCL CLKOUT Period 40 % 50 80 % ns TCLCH CLKOUT 0.5 T CLCL b 5 0.5 T CLCL b 5 0.5 T CLCL b 5n s C L e 100 pF (3) Low Time TCHCL CLKOUT 0.5 T CLCL b 5 0.5 T CLCL b 5 0.5 T CLCL b 5n s C L e 100 pF (4) High Time TCH1CH2 CLKOUT 6 8 10 ns 1.0 to 3.5V Rise Time TCL2CL1 CLKOUT 6 8 10 ns 3.5 to 1.0V Fall Time NOTES: 1. External clock applied to X1 and X2 not connected. 2. T CLCK and T CHCK (CLKIN Low and High times) should not have a duration less than 40% of T CKIN. 3. Tested under worst case conditions: V CC e 5.5V. T A e 70§C. 4. Tested under worst case conditions: V CC e 4.5V. T A e 0§C.
AC SPECIFICATIONS (Continued) READY, PERIPHERAL AND QUEUE STATUS TIMINGS TA e 0§Ct o a70§C, V CC e 5V g10% All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C L e 50 pF. For AC tests, input V IL e 0.45V and V IH e 2.4V except at X1 where V IH e VCC b 0.5V. Values Conditions TestSymbol Parameter 80C186XL25 80C186XL20 80C186XL12 Unit Min Max Min Max Min Max 80C186XL READY AND PERIPHERAL TIMING REQUIREMENTS (Listed More Than Once) TSRYCL Synchronous Ready (SRDY) 8 10 15 ns Transition Setup Time (1) TCLSRY SRDY Transition Hold Time (1) 81 0 1 5 n s TARYCH ARDY Resolution Transition 8 10 15 ns Setup Time (2) TCLARX ARDY Active Hold Time (1) 81 0 1 5 n s TARYCHL ARDY Inactive Holding Time 8 10 15 ns TARYLCL Asynchronous Ready 10 15 25 ns (ARDY) Setup Time (1) TINVCH INTx, NMI, TEST /BUSY, 8 10 15 ns TMR IN Setup Time (2) TINVCL DRQ0, DRQ1 Setup Time (2) 81 0 1 5 n s 80C186XL PERIPHERAL AND QUEUE STATUS TIMING RESPONSES TCLTMV Timer Output Delay 17 22 33 ns TCHQSV Queue Status Delay 22 27 32 ns NOTES: 1. To guarantee proper operation. 2. To guarantee recognition at clock edge.
AC SPECIFICATIONS (Continued) RESET AND HOLD/HLDA TIMINGS TA e 0§Ct o a70§C, V CC e 5V g10% All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C L e 50 pF. For AC tests, input V IL e 0.45V and V IH e 2.4V except at X1 where V IH e VCC b 0.5V. Values Conditions TestSymbol Parameter 80C186XL25 80C186XL20 80C186XL12 Unit Min Max Min Max Min Max 80C186XL RESET AND HOLD/HLDA TIMING REQUIREMENTS TRESIN RES Setup 15 15 15 ns THVCL HOLD Setup (1) 81 0 1 5 n s 80C186XL GENERAL TIMING RESPONSES (Listed More Than Once) TCLAZ Address Float Delay T CLAX 20 T CLAX 20 T CLAX 25 ns TCLAV Address Valid Delay 3 20 3 22 3 36 ns 80C186XL RESET AND HOLD/HLDA TIMING RESPONSES TCLRO Reset Delay 17 22 33 ns TCLHAV HLDA Valid Delay 3 17 3 22 3 33 ns TCHCZ Command Lines Float Delay 22 25 33 ns TCHCV Command Lines Valid Delay 20 26 36 ns (after Float) NOTE: 1. To guarantee recognition at next clock.
- Status inactive in state preceding T 4.
- If latched A 1 and A 2 are selected instead of PCS5 and PCS6 , only T CLCSV is applicable.
- For write cycle followed by read cycle.
- Changes in T-state preceding next bus cycle if followed by write.
Pin names in parentheses apply to the 80C188XL. Figure 6. Read Cycle Waveforms
- Status inactive in state preceding T 4.
- If latched A 1 and A 2 are selected instead of PCS5 and PCS6 , only T CLCSV is applicable.
- For write cycle followed by read cycle.
- Changes in T-state preceding next bus cycle if followed by read, INTA, or halt.
Pin names in parentheses apply to the 80C188XL. Figure 7. Write Cycle Waveforms
- Status inactive in state preceding T 4.
- The data hold time lasts only until INTA goes inactive, even if the INTA transition occurs prior to T CLDX (min).
- INTA occurs one clock later in Slave Mode.
- For write cycle followed by interrupt acknowledge cycle.
- Changes in T-state preceding next bus cycle if followed by write.
Pin names in parentheses apply to the 80C188XL. Figure 8. Interrupt Acknowledge Cycle Waveforms
- For write cycle followed by halt cycle.
Pin names in parentheses apply to the 80C188XL. Figure 9. Software Halt Cycle Waveforms
EXPLANATION OF THE AC SYMBOLS Each timing symbol has from 5 to 7 characters. The first character is always a ‘T’ (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. A: Address ARY: Asynchronous Ready Input C: Clock Output CK: Clock Input CS: Chip Select CT: Control (DT/R , DEN ,...) D: Data Input DE: DEN H: Logic Level High OUT: Input (DRQ0, TIM0, . . . ) L: Logic Level Low or ALE O: Output QS: Queue Status (QS1, QS2) R: RD Signal, RESET Signal S: Status (S0 ,S 1 ,S 2 ) SRY: Synchronous Ready Input V: Valid W: WR Signal X: No Longer a Valid Logic Level Z: Float Examples: T CLAV Ð Time from Clock low to Address valid TCHLH Ð Time from Clock high to ALE high TCLCSV Ð Time from Clock low to Chip Select valid
ing requirements exceed commercial standards. for both commercial and EXPRESS parts. Table 10. Prefix Identification # No wait states or bus HOLDs occur. derived from adding the instruction timings shown.
Function Format Clock Clock Comments Cycles Cycles DATA TRANSFER MOV e Move: Register to Register/Memory 1000100w m o dr e g r / m 2/12 2/12 * Register/memory to register 1000101w m o dr e g r / m 2 / 9 2 / 9 * Immediate to register/memory 1100011w m o d0 0 0 r / m data data if w e1 12/13 12/13 8/16-bit Immediate to register 1011w r e g data data if w e1 3/4 3/4 8/16-bit Memory to accumulator 1010000w addr-low addr-high 8 8 * Accumulator to memory 1010001w addr-low addr-high 9 9 * Register/memory to segment register 10001110 m o d0r e g r / m 2 / 9 2/13 Segment register to register/memory 10001100 m o d0r e g r / m 2/11 2/15 PUSH e Push: Memory 11111111 m o d110 r / m 1 6 2 0 Register 01010 r e g 1 0 1 4 Segment register 000r e g110 9 1 3 Immediate 011010s0 data data if s e01 0 1 4 PUSHA e Push All 01100000 3 6 6 8 POP e Pop: Memory 10001111 m o d000 r / m 2 0 2 4 Register 01011 r e g 1 0 1 4 Segment register 000r e g111 (regi01) 8 12 POPA e P o pA l l 01100001 5 1 8 3 XCHG e Exchange: Register/memory with register 1000011w m o dr e g r / m 4/17 4/17 * Register with accumulator 10010 r e g 3 3 IN e Input from: Fixed port 1110010w port 10 10 * Variable port 1110110w 8 8 * OUT e Output to: Fixed port 1110011w port 9 9 * Variable port 1110111w 7 7 * XLAT e Translate byte to AL 11010111 1 1 1 5 LEA e Load EA to register 10001101 m o dr e g r / m 6 6 LDS e Load pointer to DS 11000101 m o dr e g r / m (modi11) 18 26 LES e Load pointer to ES 11000100 m o dr e g r / m (modi11) 18 26 LAHF e Load AH with flags 10011111 2 2 SAHF e Store AH into flags 10011110 3 3 PUSHF e Push flags 10011100 9 1 3 POPF e Pop flags 10011101 8 1 2 Shaded areas indicate instructions not available in 8086/8088 microsystems. NOTE: *Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.
INSTRUCTION SET SUMMARY (Continued) 80C186XL 80C188XL Function Format Clock Clock Comments Cycles Cycles DATA TRANSFER (Continued) SEGMENT e Segment Override: CS 00101110 2 2 SS 00110110 2 2 DS 00111110 2 2 ES 00100110 2 2 ARITHMETIC ADD e Add: Reg/memory with register to either 000000dw m o dr e g r / m 3/10 3/10 * Immediate to register/memory 100000sw m o d000 r / m data data if s w e01 4/16 4/16 * Immediate to accumulator 0000010w data data if w e1 3/4 3/4 8/16-bit ADC e Add with carry: Reg/memory with register to either 000100dw m o dr e g r / m 3/10 3/10 * Immediate to register/memory 100000sw m o d010 r / m data data if s w e01 4/16 4/16 * Immediate to accumulator 0001010w data data if w e1 3/4 3/4 8/16-bit INC e Increment: Register/memory 1111111w m o d000 r / m 3/15 3/15 * Register 01000 r e g 3 3 SUB e Subtract: Reg/memory and register to either 001010dw m o dr e g r / m 3/10 3/10 * Immediate from register/memory 100000sw m o d101 r / m data data if s w e01 4/16 4/16 * Immediate from accumulator 0010110w data data if w e1 3/4 3/4 8/16-bit SBB e Subtract with borrow: Reg/memory and register to either 000110dw m o dr e g r / m 3/10 3/10 * Immediate from register/memory 100000sw m o d011 r / m data data if s w e01 4/16 4/16 * Immediate from accumulator 0001110w data data if w e1 3/4 3/4 * 8/16-bit DEC e Decrement Register/memory 1111111w m o d001 r / m 3/15 3/15 * Register 01001 r e g 3 3 CMP e Compare: Register/memory with register 0011101w m o dr e g r / m 3/10 3/10 * Register with register/memory 0011100w m o dr e g r / m 3/10 3/10 * Immediate with register/memory 100000sw m o d111 r / m data data if s w e01 3/10 3/10 * Immediate with accumulator 0011110w data data if w e1 3/4 3/4 8/16-bit NEG e Change sign register/memory 1111011w m o d011 r / m 3/10 3/10 * AAA e ASCII adjust for add 00110111 8 8 DAA e Decimal adjust for add 00100111 4 4 AAS e ASCII adjust for subtract 00111111 7 7 DAS e Decimal adjust for subtract 00101111 4 4 MUL e Multiply (unsigned): 1111011w m o d1 0 0 r / m Register-Byte 26–28 26–28 Register-Word 35–37 35–37 Memory-Byte 32–34 32–34 Memory-Word 41–43 41–43 * Shaded areas indicate instructions not available in 8086/8088 microsystems. NOTE: *Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.
INSTRUCTION SET SUMMARY (Continued) 80C186XL 80C188XL Function Format Clock Clock Comments Cycles Cycles ARITHMETIC (Continued) IMUL e Integer multiply (signed): 1111011w m o d101 r / m Register-Byte 25–28 25–28 Register-Word 34–37 34–37 Memory-Byte 31–34 32–34 Memory-Word 40–43 40–43 * IMUL e Integer Immediate multiply 011010s1 m o dr e g r / m data data if s e0 22–25/ 22–25/ (signed) 29–32 29–32 DIV e Divide (unsigned): 1111011w m o d110 r / m Register-Byte 29 29 Register-Word 38 38 Memory-Byte 35 35 Memory-Word 44 44 * IDIV e Integer divide (signed): 1111011w m o d111 r / m Register-Byte 44–52 44-52 Register-Word 53–61 53–61 Memory-Byte 50–58 50–58 Memory-Word 59–67 59–67 * AAM e ASCII adjust for multiply 11010100 00001010 1 9 1 9 AAD e ASCII adjust for divide 11010101 00001010 1 5 1 5 CBW e Convert byte to word 10011000 2 2 CWD e Convert word to double word 10011001 4 4 LOGIC Shift/Rotate Instructions: Register/Memory by 1 1101000w m o dT T Tr / m 2/15 2/15 Register/Memory by CL 1101001w m o dT T Tr / m 5an/17an5 an/17an Register/Memory by Count 1100000w m o dT T Tr / m count 5an/17an5 an/17an TTT Instruction
000 R O L
001 R O R
010 R C L
011 R C R
101 S H R
111 S A R
AND e And: Reg/memory and register to either 001000dw m o dr e g r / m 3/10 3/10 * Immediate to register/memory 1000000w m o d100 r / m data data if w e1 4/16 4/16 * Immediate to accumulator 0010010w data data if w e1 3/4 3/4 * 8/16-bit TESTeAnd function to flags, no result: Register/memory and register 1000010w m o dr e g r / m 3/10 3/10 * Immediate data and register/memory 1111011w m o d000 r / m data data if w e1 4/10 4/10 * Immediate data and accumulator 1010100w data data if w e1 3/4 3/4 8/16-bit OReOr: Reg/memory and register to either 000010dw m o dr e g r / m 3/10 3/10 * Immediate to register/memory 1000000w m o d001 r / m data data if w e1 4/16 4/16 * Immediate to accumulator 0000110w data data if w e1 3/4 3/4 * 8/16-bit Shaded areas indicate instructions not available in 8086/8088 microsystems. NOTE: *Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.
INSTRUCTION SET SUMMARY (Continued) 80C186XL 80C188XL Function Format Clock Clock Comments Cycles Cycles LOGIC (Continued) XOR e Exclusive or: Reg/memory and register to either 001100dw m o dr e g r / m 3/10 3/10 * Immediate to register/memory 1000000w m o d110 r / m data data if w e1 4/16 4/16 * Immediate to accumulator 0011010w data data if w e1 3/4 3/4 8/16-bit NOT e Invert register/memory 1111011w m o d010 r / m 3/10 3/10 * STRING MANIPULATION MOVS e Move byte/word 1010010w 1 4 1 4 * CMPS e Compare byte/word 1010011w 2 2 2 2 * SCAS e Scan byte/word 1010111w 1 5 1 5 * LODS e Load byte/wd to AL/AX 1010110w 1 2 1 2 * STOS e Store byte/wd from AL/AX 1010101w 1 0 1 0 * INS e Input byte/wd from DX port 0110110w 1 4 1 4 OUTS e Output byte/wd to DX port 0110111w 1 4 1 4 Repeated by count in CX (REP/REPE/REPZ/REPNE/REPNZ) MOVS e Move string 11110010 1010010w 8 a8n 8 a8n* CMPS e Compare string 1111001z 1010011w 5 a22n 5 a22n* SCAS e Scan string 1111001z 1010111w 5 a15n 5 a15n* LODS e Load string 11110010 1010110w 6 a11n 6 a11n* STOS e Store string 11110010 1010101w 6 a9n 6 a9n* INS e Input string 11110010 0110110w 8 a8n 8 a8n* OUTS e Output string 11110010 0110111w 8 a8n 8 a8n* CONTROL TRANSFER CALL e Call: Direct within segment 11101000 disp-low disp-high 15 19 Register/memory 11111111 m o d010 r / m 13/19 17/27 indirect within segment Direct intersegment 10011010 segment offset 23 31 segment selector Indirect intersegment 11111111 m o d011 r / m (mod i 11) 38 54 JMP e Unconditional jump: Short/long 11101011 disp-low 14 14 Direct within segment 11101001 disp-low disp-high 14 14 Register/memory 11111111 m o d100 r / m 11/17 11/21 indirect within segment Direct intersegment 11101010 segment offset 14 14 segment selector Indirect intersegment 11111111 m o d101 r / m (mod i 11) 26 34 Shaded areas indicate instructions not available in 8086/8088 microsystems. NOTE: *Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.
INSTRUCTION SET SUMMARY (Continued) 80C186XL 80C188XL Function Format Clock Clock Comments Cycles Cycles CONTROL TRANSFER (Continued) RET e Return from CALL: Within segment 11000011 1 6 2 0 Within seg adding immed to SP 11000010 data-low data-high 18 22 Intersegment 11001011 2 2 3 0 Intersegment adding immediate to SP 11001010 data-low data-high 25 33 JE/JZ e Jump on equal/zero 01110100 disp 4/13 4/13 JMP not JL/JNGE e Jump on less/not greater or equal 01111100 disp 4/13 4/13 taken/JMP JLE/JNG e Jump on less or equal/not greater 01111110 disp 4/13 4/13 taken JB/JNAE e Jump on below/not above or equal 01110010 disp 4/13 4/13 JBE/JNA e Jump on below or equal/not above 01110110 disp 4/13 4/13 JP/JPE e Jump on parity/parity even 01111010 disp 4/13 4/13 JO e Jump on overflow 01110 000 disp 4/13 4/13 JS e Jump on sign 01111000 disp 4/13 4/13 JNE/JNZ e Jump on not equal/not zero 01110101 disp 4/13 4/13 JNL/JGE e Jump on not less/greater or equal 01111101 disp 4/13 4/13 JNLE/JG e Jump on not less or equal/greater 01111111 disp 4/13 4/13 JNB/JAE e Jump on not below/above or equal 01110011 disp 4/13 4/13 JNBE/JA e Jump on not below or equal/above 01110111 disp 4/13 4/13 JNP/JPO e Jump on not par/par odd 01111011 disp 4/13 4/13 JNO e Jump on not overflow 01110001 disp 4/13 4/13 JNS e Jump on not sign 01111001 disp 4/13 4/13 JCXZ e Jump on CX zero 11100011 disp 5/15 5/15 LOOP e Loop CX times 11100010 disp 6/16 6/16 LOOP not LOOPZ/LOOPE e Loop while zero/equal 11100001 disp 6/16 6/16 taken/LOOP LOOPNZ/LOOPNE e Loop while not zero/equal 11100000 disp 6/16 6/16 taken ENTER e Enter Procedure 11001000 data-low data-high L L e 0 15 19 L e 1 25 29 L l 1 22a16(nb1) 26 a20(nb1) LEAVE e Leave Procedure 11001001 8 8 INT e Interrupt: Type specified 11001101 type 47 47 Type 3 11001100 4 5 4 5 i f INT. taken/ INTO e Interrupt on overflow 11001110 48/4 48/4 if INT. not taken IRET e Interrupt return 11001111 2 8 2 8 BOUND e Detect value out of range 01100010 m o dr e g r / m 3 3 – 3 5 3 3 – 3 5 Shaded areas indicate instructions not available in 8086/8088 microsystems. NOTE: *Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.
INSTRUCTION SET SUMMARY (Continued) 80C186XL 80C188XL Function Format Clock Clock Comments Cycles Cycles PROCESSOR CONTROL CLC e Clear carry 11111000 2 2 CMC e Complement carry 11110101 2 2 STC e Set carry 11111001 2 2 CLD e Clear direction 11111100 2 2 STD e Set direction 11111101 2 2 CLI e Clear interrupt 11111010 2 2 STI e Set interrupt 11111011 2 2 HLT e Halt 11110100 2 2 WAIT e Wait 10011011 6 6 i f TEST e 0 LOCK e Bus lock prefix 11110000 2 2 NOP e No Operation 10010000 3 3 (TTT LLL are opcode to processor extension) Shaded areas indicate instructions not available in 8086/8088 microsystems. NOTE: *Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers. The Effective Address (EA) of the memory operand is computed according to the mod and r/m fields: if mod e 11 then r/m is treated as a REG field if mod e 00 then DISP e 0*, disp-low and disp- high are absent if mod e 01 then DISP e disp-low sign-ex- tended to 16-bits, disp-high is absent if mod e 10 then DISP e disp-high: disp-low if r/m e 000 then EA e (BX) a (SI) a DISP if r/m e 001 then EA e (BX) a (DI) a DISP if r/m e 010 then EA e (BP) a (SI) a DISP if r/m e 011 then EA e (BP) a (DI) a DISP if r/m e 100 then EA e (SI) a DISP if r/m e 101 then EA e (DI) a DISP if r/m e 110 then EA e (BP) a DISP* if r/m e 111 then EA e (BX) a DISP DISP follows 2nd byte of instruction (before data if required) *except if mod e 00 and r/m e 110 then EA e disp-high: disp-low. EA calculation time is 4 clock cycles for all modes, and is included in the execution times given whenev- er appropriate. Segment Override Prefix 0 0 1 reg 1 1 0 reg is assigned according to the following: Segment reg Register 00 ES 01 CS 10 SS 11 DS REG is assigned according to the following table: 16-Bit (w e 1) 8-Bit (w e 0)
000 AX 000 AL
001 CX 001 CL
010 DX 010 DL
011 BX 011 BL
100 SP 100 AH
101 BP 101 CH
110 SI 110 DH
111 DI 111 BH
The physical addresses of all operands addressed by the BP register are computed using the SS seg- ment register. The physical addresses of the desti- nation operands of the string primitive operations (those addressed by the DI register) are computed using the ES segment, which may not be overridden.
REVISION HISTORY
This data sheet replaces the following data sheets: # 272031-002 80C186XL # 270975-002 80C188XL # 272309-001 SB80C186XL # 272310-001 SB80C188XL ERRATA An A or B step 80C186XL/80C188XL has the follow- ing errata. The A or B step 80C186XL/80C188XL can be identified by the presence of an ‘‘A’’ or ‘‘B’’ alpha character, respectively, next to the FPO num- ber. The FPO number location is shown in Figure 4. 1. An internal condition with the interrupt controller can cause no acknowledge cycle on the INTA1 line in response to INT1. This errata only occurs when Interrupt 1 is configured in cascade mode and a higher priority interrupt exists. This errata will not occur consistently, it is dependent on in- terrupt timing. The C step 80C186XL/80C188XL has no known er- rata. The C step can be identified by the presence of a ‘‘C’’ or ‘‘D’’ alpha character next to the FPO num- ber. The FPO number location is shown in Figure 4. PRODUCT IDENTIFICATION Intel 80C186XL devices are marked with a 9-charac- ter alphanumeric Intel FPO number underneath the product number. This data sheet (272431-001) is valid for devices with an ‘‘A’’, ‘‘B’’, ‘‘C’’, or ‘‘D’’ as the ninth character in the FPO number, as illustrated in Figure 4.