80C186EB INTEL | Alldatasheet
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*Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. October 1995 COPYRIGHT © INTEL CORPORATION, 1995 Order Number: 272433-004 80C186EB/80C188EB AND 80L186EB/80L188EB 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS X Full Static Operation X True CMOS Inputs and Outputs Y Integrated Feature Set Ð Low-Power Static CPU Core Ð Two Independent UARTs each with an Integral Baud Rate Generator Ð Two 8-Bit Multiplexed I/O Ports Ð Programmable Interrupt Controller Ð Three Programmable 16-Bit Timer/Counters Ð Clock Generator Ð Ten Programmable Chip Selects with Integral Wait-State Generator Ð Memory Refresh Control Unit Ð System Level Testing Support (ONCE Mode) Y Direct Addressing Capability to 1 Mbyte Memory and 64 Kbyte I/O Y Speed Versions Available (5V): Ð 25 MHz (80C186EB25/80C188EB25) Ð 20 MHz (80C186EB20/80C188EB20) Ð 13 MHz (80C186EB13/80C188EB13) Y Available in Extended Temperature Range ( b40§Ct o a85§C) Y Speed Versions Available (3V): Ð 16 MHz (80L186EB16/80L188EB16) Ð 13 MHz (80L186EB13/80L188EB13) Ð 8 MHz (80L186EB8/80L188EB8) Y Low-Power Operating Modes: Ð Idle Mode Freezes CPU Clocks but keeps Peripherals Active Ð Powerdown Mode Freezes All Internal Clocks Y Supports 80C187 Numeric Coprocessor Interface (80C186EB PLCC Only) Y Available In: Ð 80-Pin Quad Flat Pack (QFP) Ð 84-Pin Plastic Leaded Chip Carrier (PLCC) Ð 80-Pin Shrink Quad Flat Pack (SQFP) The 80C186EB is a second generation CHMOS High-Integration microprocessor. It has features that are new to the 80C186 family and include a STATIC CPU core, an enhanced Chip Select decode unit, two independent Serial Channels, I/O ports, and the capability of Idle or Powerdown low power modes. 272433–1
80C186EB/80C188EB and 80L186EB/80L188EB 16-Bit High-Integration Embedded Processors CONTENTS PAGE INTRODUCTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4 CORE ARCHITECTURE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4 Bus Interface Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4 Clock Generator ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4 80C186EC PERIPHERAL ARCHITECTURE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5 Interrupt Control Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5 Timer/Counter Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5 Serial Communications Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7 Chip-Select Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7 I/O Port Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7 Refresh Control Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7 Power Management Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7 80C187 Interface (80C186EB Only) ÀÀÀÀÀÀÀÀÀ 7 ONCE Test Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7 PACKAGE INFORMATION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8 Prefix Identification ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8 Pin Descriptions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8 80C186EB PINOUT ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14 PACKAGE THERMAL SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22 ELECTRICAL SPECIFICATIONS ÀÀÀÀÀÀÀÀÀ 23 Absolute Maximum Ratings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23 CONTENTS PAGE Recommended Connections ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23 DC SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24 ICC versus Frequency and Voltage ÀÀÀÀÀÀÀÀÀ 27 PDTMR Pin Delay Calculation ÀÀÀÀÀÀÀÀÀÀÀÀÀ 27 AC SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 28 AC CharacteristicsÐ80C186EB25 ÀÀÀÀÀÀÀÀÀ 28 AC CharacteristicsÐ80C186EB20/13 ÀÀÀÀÀ 30 AC CharacteristicsÐ80L186EB16 ÀÀÀÀÀÀÀÀÀ 32 Relative Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 36 Serial Port Mode 0 Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 37 AC TEST CONDITIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 38 AC TIMING WAVEFORMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 38 DERATING CURVES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 41 RESET ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 42 BUS CYCLE WAVEFORMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 45 EXECUTION TIMINGS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 52 INSTRUCTION SET SUMMARY ÀÀÀÀÀÀÀÀÀÀ 53 ERRATA ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 59 REVISION HISTORY ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 59
Figure 1. 80C186EB/80C188EB Block Diagram
80C186EB/80C188EB, 80L186EB/80L188EB INTRODUCTION Unless specifically noted, all references to the 80C186EB apply to the 80C188EB, 80L186EB, and 80L188EB. References to pins that differ between the 80C186EB/80L186EB and the 80C188EB/ 80L188EB are given in parentheses. The ‘‘L’’ in the part number denotes low voltage operation. Physi- cally and functionally, the ‘‘C’’ and ‘‘L’’ devices are identical. The 80C186EB is the first product in a new genera- tion of low-power, high-integration microprocessors. It enhances the existing 186 family by offering new features and new operating modes. The 80C186EB is object code compatible with the 80C186XL/ 80C188XL microprocessors. The 80L186EB is the 3V version of the 80C186EB. The 80L186EB is functionally identical to the 80C186EB embedded processor. Current 80C186EB users can easily upgrade their designs to use the 80L186EB and benefit from the reduced power consumption inherent in 3V operation. The feature set of the 80C186EB meets the needs of low power, space critical applications. Low-Power applications benefit from the static design of the CPU core and the integrated peripherals as well as low voltage operation. Minimum current consump- tion is achieved by providing a Powerdown mode that halts operation of the device, and freezes the clock circuits. Peripheral design enhancements en- sure that non-initialized peripherals consume little current. Space critical applications benefit from the inte- gration of commonly used system peripherals. Two serial channels are provided for services such as diagnostics, inter-processor communication, modem interface, terminal display interface, and many oth- ers. A flexible chip select unit simplifies memory and peripheral interfacing. The interrupt unit provides sources for up to 129 external interrupts and will pri- oritize these interrupts with those generated from the on-chip peripherals. Three general purpose tim- er/counters and sixteen multiplexed I/O port pins round out the feature set of the 80C186EB. Figure 1 shows a block diagram of the 80C186EB/ 80C188EB. The Execution Unit (EU) is an enhanced
8086 CPU core that includes: dedicated hardware to
speed up effective address calculations, enhance execution speed for multiple-bit shift and rotate in- structions and for multiply and divide instructions, string move instructions that operate at full bus bandwidth, ten new instruction, and fully static oper- ation. The Bus Interface Unit (BIU) is the same as that found on the original 186 family products, ex- cept the queue status mode has been deleted and buffer interface control has been changed to ease system design timings. An independent internal bus is used to allow communication between the BIU and internal peripherals. CORE ARCHITECTURE Bus Interface Unit The 80C186EB core incorporates a bus controller that generates local bus control signals. In addition, it employs a HOLD/HLDA protocol to share the local bus with other bus masters. The bus controller is responsible for generating 20 bits of address, read and write strobes, bus cycle status information, and data (for write operations) in- formation. It is also responsible for reading data off the local bus during a read operation. A READY in- put pin is provided to extend a bus cycle beyond the minimum four states (clocks). The local bus controller also generates two control signals (DEN and DT/R ) when interfacing to exter- nal transceiver chips. (Both DEN and DT/R are available on the PLCC devices, only DEN is avail- able on the QFP and SQFP devices.) This capability allows the addition of transceivers for simple buffer- ing of the multiplexed address/data bus. Clock Generator The processor provides an on-chip clock generator for both internal and external clock generation. The clock generator features a crystal oscillator, a divide- by-two counter, and two low-power operating modes. The oscillator circuit is designed to be used with ei- ther a parallel resonant fundamental or third-over- tone mode crystal network. Alternatively, the oscilla- tor circuit may be driven from an external clock source. Figure 2 shows the various operating modes of the oscillator circuit. The crystal or clock frequency chosen must be twice the required processor operating frequency due to the internal divide-by-two counter. This counter is used to drive all internal phase clocks and the exter- nal CLKOUT signal. CLKOUT is a 50% duty cycle processor clock and can be used to drive other sys- tem components. All AC timings are referenced to CLKOUT.
Figure 3. Peripheral Control Block Registers
80C186EB/80C188EB, 80L186EB/80L188EB Serial Communications Unit The Serial Control Unit (SCU) of the 80C186EB con- tains two independent channels. Each channel is identical in operation except that only channel 0 is supported by the integrated interrupt controller (channel 1 has an external interrupt pin). Each channel has its own baud rate generator that is in- dependent of the Timer/Counter Unit, and can be internally or externally clocked at up to one half the 80C186EB operating frequency. Independent baud rate generators are provided for each of the serial channels. For the asynchronous modes, the generator supplies an 8x baud clock to both the receive and transmit register logic. A 1x baud clock is provided in the synchronous mode. Chip-Select Unit The 80C186EB Chip-Select Unit (CSU) integrates logic which provides up to ten programmable chip- selects to access both memories and peripherals. In addition, each chip-select can be programmed to automatically insert additional clocks (wait-states) into the current bus cycle and automatically termi- nate a bus cycle independent of the condition of the READY input pin. I/O Port Unit The I/O Port Unit (IPU) on the 80C186EB supports two 8-bit channels of input, output, or input/output operation. Port 1 is multiplexed with the chip select pins and is output only. Most of Port 2 is multiplexed with the serial channel pins. Port 2 pins are limited to either an output or input function depending on the operation of the serial pin it is multiplexed with. Refresh Control Unit The Refresh Control Unit (RCU) automatically gen- erates a periodic memory read bus cycle to keep dynamic or pseudo-static memory refreshed. A 9-bit counter controls the number of clocks between re- fresh requests. A 12-bit address generator is maintained by the RCU and is presented on the A12:1 address lines during the refresh bus cycle. Address bits A19:13 are pro- grammable to allow the refresh address block to be located on any 8 Kbyte boundary. Power Management Unit The 80C186EB Power Management Unit (PMU) is provided to control the power consumption of the device. The PMU provides three power modes: Ac- tive, Idle, and Powerdown. Active Mode indicates that all units on the 80C186EB are functional and the device consumes maximum power (depending on the level of periph- eral operation). Idle Mode freezes the clocks of the Execution and Bus units at a logic zero state (all peripherals continue to operate normally). The Powerdown mode freezes all internal clocks at a logic zero level and disables the crystal oscillator. All internal registers hold their values provided V CC is maintained. Current consumption is reduced to just transistor junction leakage. 80C187 Interface (80C186EB Only) The 80C186EB (PLCC package only) supports the direct connection of the 80C187 Numerics Coproc- essor. ONCE Test Mode To facilitate testing and inspection of devices when fixed into a target system, the 80C186EB has a test mode available which forces all output and input/ output pins to be placed in the high-impedance state. ONCE stands for ‘‘ON Circuit Emulation’’. The ONCE mode is selected by forcing the A19/ONCE pin LOW (0) during a processor reset (this pin is weakly held to a HIGH (1) level) while RESIN is ac- tive.
80C186EB/80C188EB, 80L186EB/80L188EB
PACKAGE INFORMATION
This section describes the pins, pinouts, and thermal characteristics for the 80C186EB in the Plastic Leaded Chip Carrier (PLCC) package, Shrink Quad Flat Pack (SQFP), and Quad Flat Pack (QFP) pack- age. For complete package specifications and infor- mation, see the Intel Packaging Outlines and Dimen- sions Guide (Order Number: 231369). Prefix Identification With the extended temperature range, operational characteristics are guaranteed over the temperature range corresponding to b40§Ct o a85§C ambient. Package types are identified by a two-letter prefix to the part number. The prefixes are listed in Table 1. Table 1. Prefix Identification
- The 5V 25 MHz and 3V 16 MHz versions are only avail-
- There are three columns for each entry in the Pin
2 lists all the possible symbols for this column. (Asynchronous or Synchronous). istics for input pins are S(E), S(L), A(E) and A(L). state as a function of the device operating mode. ble characteristics in Table 2.
Table 2. Pin Description Nomenclature
Table 3. Pin Descriptions shorted externally to a V CC board plane. shorted externally to a V SS board plane. connections to an internal Pierce oscillator. OSCOUT does not float in ONCE mode. transistions every falling edge of CLKIN. begins fetching opcodes at memory location 0FFFF0H. startup characteristics of the crystal oscillator. be serviced by the CPU. NMI is latched internally. with an 80C187 numerics coprocessor (80C186EB only). AD15:0 I/O S(L) H(Z) These pins provide a multiplexed Address and Data bus. Pin names in parentheses apply to the 80C188EB/80L188EB.
Table 3. Pin Descriptions (Continued) low during reset or improper operation may result. correctly programming the Chip-Select Unit. Pin names in parentheses apply to the 80C188EB/80L188EB.
active and must not be driven low. boundaries not conditioned by a LOCK prefix. Pin names in parentheses apply to the 80C188EB/80L188EB.
handshake signal to allow interrupt expansion. P2.7 I/O A(L) H(X) BI-DIRECTIONAL, open-drain Port pins. communications, TXD will function as a clock output. RXD0 I/O A(L) R(Z) Receive Data input accepts serial data information. transmission or data (TXD becomes the clock). the operating frequency of the processor. Pin names in parentheses apply to the 80C188EB/80L188EB.
component (i.e., contacts facing down). (i.e., contacts facing down). Table 4. PLCC Pin Names with Package Location Pin names in parentheses apply to the 80C188EB/80L188EB.
Table 5. PLCC Package Locations with Pin Name
6 ALE
7 BHE
11 DEN
12 HLDA
13 HOLD
14 TEST
15 LOCK
16 DT/R
17 NMI
18 READY
22 V SS
23 V CC
29 LCS
30 UCS
31 INT0
32 INT1
33 INT2/INTA0
34 INT3/INTA1
35 INT4
36 PDTMR
37 RESIN
38 RESOUT
40 OSCOUT
41 CLKIN
42 V CC
43 V SS
44 CLKOUT
45 T0OUT
46 T0IN
47 T1OUT
48 T1IN
51 CTS0
52 TXD0
53 RXD0
60 NCS
61 AD0
62 AD8 (A8)
63 V SS
64 V CC
65 V SS
66 AD1
67 AD9 (A9)
68 AD2
69 AD10 (A10)
70 AD3
71 AD11 (A11)
72 AD4
73 AD12 (A12)
74 AD5
75 AD13 (A13)
76 AD6
77 AD14 (A14)
78 AD7
79 AD15 (A15)
80 A16
81 A17
82 A18
83 A19/ONCE
84 V SS
Pin names in parentheses apply to the 80C188EB/80L188EB.
This is the FPO number location (indicated by X’s). Pin names in parentheses apply to the 80C188EB/80L188EB. Figure 4. 84-Pin Plastic Leaded Chip Carrier Pinout Diagram
Table 6. QFP Pin Name with Package Location Pin names in parentheses apply to the 80C188EB/80L188EB.
Table 7. QFP Package Location with Pin Names
1 CTS0
2 TXD0
3 RXD0
10 AD0
11 AD8 (A8)
13 V CC
14 V SS
15 AD1
16 AD9 (A9)
17 AD2
18 AD10 (A10)
19 AD3
20 AD11 (A11)
21 AD4
22 AD12 (A12)
23 AD5
24 AD13 (A13)
25 AD6
26 AD14 (A14)
27 AD7
28 AD15 (A15)
29 A16
30 A17
31 A18
32 A19/ONCE
33 V SS
34 V CC
35 V SS
38 ALE
39 BHE
43 DEN
44 HLDA
45 HOLD
46 TEST
47 LOCK
48 NMI
49 READY
53 V SS
54 V CC
60 LCS
61 UCS
62 INT0
63 INT1
64 INT2/INTA0
65 INT3/INTA1
66 INT4
67 PDTMR
68 RESIN
69 RESOUT
70 OSCOUT
71 CLKIN
73 V SS
74 CLKOUT
75 T0OUT
76 T0IN
77 T1OUT
78 T1IN
Pin names in parentheses apply to the 80C188EB/80L188EB.
This is the FPO number location (indicated by X’s). Pin names in parentheses apply to the 80C188EB/80L188EB. Figure 5. Quad Flat Pack Pinout Diagram
Table 8. SQFP Pin Functions with Location Table 9. SQFP Pin Locations with Pin Names
1 HLDA
2 HOLD
3 TEST
4 LOCK Ý
5 NMI
6 READY
10 V SS
11 V CC
17 LCS Ý
18 UCS Ý
19 INT0
20 INT1
21 INT1/INTA0 Ý
22 INT3/INTA1 Ý
23 INT4
24 PDTMR
25 RESIN
26 RESOUT
27 OSCOUT
28 CLKIN
30 V SS
31 CLKOUT
32 T0OUT
33 T0IN
34 T1OUT
35 T1IN
38 CTS0
39 TXD0
40 RXD0
47 AD0
48 AD8 (A8)
50 V CC
51 V SS
52 AD1
53 AD9 (A9)
54 AD2
55 AD10 (A10)
56 AD3
57 AD11 (A11)
58 AD4
59 AD12 (A12)
60 AD5
61 AD13 (A13)
62 AD6
63 AD14 (A14)
64 AD7
65 AD15 (A15)
66 A16
67 A17
68 A18
69 A19/ONCE
71 V CC
72 V SS
73 RD Ý
74 WR Ý
75 ALE
76 BHE Ý (RFSHÝ)
77 S2 Ý
78 S1 Ý
79 S0 Ý
80 DEN Ý
Pin names in parentheses apply to the 80C188EB/80L188EB.
XXXXXXXXC indicates Intel FPO number. Pin names in parentheses apply to the 80C188EB/80L188EB. Figure 6. SQFP Package
Table 10. Thermal Resistance ( iCA) at Various Airflows (in §C/Watt)
80C186EB/80C188EB, 80L186EB/80L188EB ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b65§Ct o a150§C Case Temp under Bias ÀÀÀÀÀÀÀÀÀ b65§Ct o a120§C Supply Voltage with Respect to V SSÀÀÀÀÀÀÀÀÀÀÀb0.5V to a 6.5V Voltage on other Pins with Respect to V SS ÀÀÀÀÀÀb0.5V to V CC a 0.5V NOTICE: This data sheet contains preliminary infor- mation on new products in production. It is valid for the devices indicated in the revision history. The specifications are subject to change without notice. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. Recommended Connections Power and ground connections must be made to multiple V CC and V SS pins. Every 80C186EB-based circuit board should include separate power (V CC) and ground (V SS) planes. Every V CC pin must be connected to the power plane, and every V SS pin must be connected to the ground plane. Pins identi- fied as ‘‘NC’’ must not be connected in the system. Liberal decoupling capacitance should be placed near the processor. The processor can cause tran- sient power surges when its output buffers tran- sition, particularly when connected to large capaci- tive loads. Low inductance capacitors and interconnects are recommended for best high frequency electrical per- formance. Inductance is reduced by placing the de- coupling capacitors as close as possible to the proc- essor V CC and V SS package pins. Always connect any unused input to an appropriate signal level. In particular, unused interrupt inputs (INT0:4) should be connected to V CC through a pull- up resistor (in the range of 50 K X). Leave any un- used output pin or any NC pin unconnected.
80C186EB/80C188EB, 80L186EB/80L188EB DC SPECIFICATIONS (80C186EB/80C188EB) Symbol Parameter Min Max Units Notes VCC Supply Voltage 4.5 5.5 V VIL Input Low Voltage b0.5 0.3 V CC V VIH Input High Voltage 0.7 V CC VCC a 0.5 V VOL Output Low Voltage 0.45 V I OL e 3 mA (Min) VOH Output High Voltage V CC b 0.5 V I OH eb 2 mA (MIn) VHYR Input Hysterisis on RESIN 0.50 V ILI1 Input Leakage Current for Pins: g15 mA0 V s VIN s VCC AD15:0 (AD7:0), READY, HOLD, RESIN, CLKIN, TEST , NMI, INT4:0, T0IN, T1IN, RXD0, BCLK0 , CTS0 , RXD1, BCLK1 , CTS1 , P2.6, P2.7 ILI2 Input Leakage Current for Pins: g0.275 g7m A 0 V s VIN k VCC ERROR, PEREQ ILI3 Input Leakage Current for Pins: b0.275 b5.0 mA V IN e 0.7 V CC (Note 1) A19/ONCE, A18:16, LOCK ILO Output Leakage Current g15 mA 0.45 s VOUT s VCC (Note 2) ICC Supply Current Cold (RESET) 80C186EB25 115 mA (Notes 3, 7) 80C186EB20 108 mA (Note 3) 80C186EB13 73 mA (Note 3) IID Supply Current Idle 80C186EB25 91 mA (Notes 4, 7) 80C186EB20 76 mA (Note 4) 80C186EB13 48 mA (Note 4) IPD Supply Current Powerdown 80C186EB25 100 mA (Notes 5, 7) 80C186EB20 100 mA (Note 5) 80C186EB13 100 mA (Note 5) CIN Input Pin Capacitance 0 15 pF T F e 1 MHz COUT Output Pin Capacitance 0 15 pF T F e 1 MHz (Note 6) NOTES: 1. These pins have an internal pull-up device that is active while RESIN is low and ONCE Mode is not active. Sourcing more current than specified (on any of these pins) may invoke a factory test mode. 2. Tested by outputs being floated by invoking ONCE Mode or by asserting HOLD. 3. Measured with the device in RESET and at worst case frequency, V CC, and temperature with ALL outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V CC or GND. 4. Measured with the device in HALT (IDLE Mode active) and at worst case frequency, V CC, and temperature with ALL outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V CC or GND. 5. Measured with the device in HALT (Powerdown Mode active) and at worst case frequency, V CC, and temperature with ALL outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V CC or GND. 6. Output Capacitance is the capacitive load of a floating output pin. 7. Operating temperature for 25 MHz is 0 §Ct o7 0 §C, V CC e 5.0 g10%.
80C186EB/80C188EB, 80L186EB/80L188EB DC SPECIFICATIONS (80L186EB16) (operating temperature, 0 §Ct o7 0 §C) Symbol Parameter Min Max Units Notes VCC Supply Voltage 3.0 5.5 V VIL Input Low Voltage b0.5 0.3 V CC V VIH Input High Voltage 0.7 V CC VCC a 0.5 V VOL Output Low Voltage 0.45 V I OL e 1.6 mA (Min) (Note 1) VOH Output High Voltage V CC b 0.5 V I OH eb 1 mA (Min) (Note 1) VHYR Input Hysterisis on RESIN 0.50 V ILI1 Input Leakage Current for pins: g15 mA0 V s VIN s VCC AD15:0 (AD7:0), READY, HOLD, RESIN, CLKIN, TEST , NMI, INT4:0, T0IN, T1IN, RXD0, BCLK0, CTS0 , RXD1, BCLK1 , CTS1, SINT1, P2.6, P2.7 ILI2 Input Leakage Current for Pins: b0.275 b2m A V IN e 0.7 V CC (Note 2) A19/ONCE, A18:16, LOCK ILO Output Leakage Current g15 mA 0.45 s VOUT s VCC (Note 3) ICC3 Supply Current (RESET, 3.3V) 80L186EB16 54 mA (Note 4) IID3 Supply Current Idle (3.3V) 80L186EB16 38 mA (Note 5) IPD3 Supply Current Powerdown (3.3V) 80L186EB16 40 mA (Note 6) CIN Input Pin Capacitance 0 15 pF T F e 1 MHz COUT Output Pin Capacitance 0 15 pF T F e 1 MHz (Note 7) NOTES: 1. I OL and I OH measured at V CC e 3.0V. 2. These pins have an internal pull-up device that is active while RESIN is low and ONCE Mode is not active. Sourcing more current than specified (on any of these pins) may invoke a factory test mode. 3. Tested by outputs being floated by invoking ONCE Mode or by asserting HOLD. 4. Measured with the device in RESET and at worst case frequency, V CC, and temperature with ALL outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V CC or GND. 5. Measured with the device in HALT (IDLE Mode active) and at worst case frequency, V CC, and temperature with ALL outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V CC or GND. 6. Measured with the device in HALT (Powerdown Mode active) and at worst case frequency, V CC, and temperature with ALL outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V CC or GND. 7. Output Capacitance is the capacitive load of a floating output pin.
80C186EB/80C188EB, 80L186EB/80L188EB DC SPECIFICATIONS (80L186EB13/80L188EB13, 80L186EB8/80L188EB8) Symbol Parameter Min Max Units Notes VCC Supply Voltage 2.7 5.5 V VIL Input Low Voltage b0.5 0.3 V CC V VIH Input High Voltage 0.7 V CC VCC a 0.5 V VOL Output Low Voltage 0.45 V I OL e 1.6 mA (Min) (Note 1) VOH Output High Voltage V CC b 0.5 V I OH eb 1 mA (Min) (Note 1) VHYR Input Hysterisis on RESIN 0.50 V ILI1 Input Leakage Current for pins: g15 mA0 V s VIN s VCC AD15:0 (AD7:0), READY, HOLD, RESIN, CLKIN, TEST , NMI, INT4:0, T0IN, T1IN, RXD0, BCLK0, CTS0 , RXD1, BCLK1 , CTS1, SINT1, P2.6, P2.7 ILI2 Input Leakage Current for Pins: b0.275 b2m A V IN e 0.7 V CC (Note 2) A19/ONCE, A18:16, LOCK ILO Output Leakage Current g15 mA 0.45 s VOUT s VCC (Note 3) ICC5 Supply Current (RESET, 5.5V) 80L186EB13 73 mA (Note 4) 80L186EB8 45 mA (Note 4) ICC3 Supply Current (RESET, 2.7V) 80L186EB13 36 mA (Note 4) 80L186EB8 22 mA (Note 4) IID5 Supply Current Idle (5.5V) 80L186EB13 48 mA (Note 5) 80L186EB8 31 mA (Note 5) IID3 Supply Current Idle (2.7V) 80L186EB13 24 mA (Note 5) 80L186EB8 15 mA (Note 5) IPD5 Supply Current Powerdown (5.5V) 80L186EB13 100 mA (Note 6) 80L186EB8 100 mA (Note 6) IPD3 Supply Current Powerdown (2.7V) 80L186EB13 30 mA (Note 6) 80L186EB8 30 mA (Note 6) CIN Input Pin Capacitance 0 15 pF T F e 1 MHz COUT Output Pin Capacitance 0 15 pF T F e 1 MHz (Note 7) NOTES: 1. I OL and I OH measured at V CC e 2.7V. 2. These pins have an internal pull-up device that is active while RESIN is low and ONCE Mode is not active. Sourcing more current than specified (on any of these pins) may invoke a factory test mode. 3. Tested by outputs being floated by invoking ONCE Mode or by asserting HOLD. 4. Measured with the device in RESET and at worst case frequency, V CC, and temperature with ALL outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V CC or GND. 5. Measured with the device in HALT (IDLE Mode active) and at worst case frequency, V CC, and temperature with ALL outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V CC or GND. 6. Measured with the device in HALT (Powerdown Mode active) and at worst case frequency, V CC, and temperature with ALL outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V CC or GND. 7. Output Capacitance is the capacitive load of a floating output pin.
and is typically less than 50 mA. quency within the specified operating range. crystal or resonator circuit time to stabilize. and/or higher temperature will increase delay time. Table 11. Device Capacitance (C DEV) Values
- Max C DEV is calculated at b40§C, all floating outputs driven to V CC or GND, and all
outputs loaded to 50 pF (including CLKOUT and OSCOUT). OSCOUT, which are not loaded.
80C186EB/80C188EB, 80L186EB/80L188EB AC SPECIFICATIONS AC CharacteristicsÐ80C186EB25 Symbol Parameter
25 MHz
TF CLKIN Frequency 0 50 MHz 1 TC CLKIN Period 20 % ns 1 TCH CLKIN High Time 8 % ns 1, 2 TCL CLKIN Low Time 8 % ns 1, 2 TCR CLKIN Rise Time 1 7 ns 1, 3 TCF CLKIN Fall Time 1 7 ns 1, 3 OUTPUT CLOCK TCD CLKIN to CLKOUT Delay 0 16 ns 1, 4 T CLKOUT Period 2 *TC ns 1 TPH CLKOUT High Time (T/2) b 5 (T/2) a 5n s 1 TPL CLKOUT Low Time (T/2) b 5 (T/2) a 5n s 1 TPR CLKOUT Rise Time 1 6 ns 1, 5 TPF CLKOUT Fall Time 1 6 ns 1, 5 OUTPUT DELAYS TCHOV1 ALE, S2:0 , DEN , DT/R , BHE (RFSH), LOCK , A19:16 3 17 ns 1, 4, 6, 7 TCHOV2 GCS0:7, LCS , UCS , NCS ,R D ,W R 3 2 0 n s 1 ,4 ,6 ,8 TCLOV1 BHE (RFSH), DEN , LOCK , RESOUT, HLDA, T0OUT, 3 17 ns 1, 4, 6 T1OUT, A19:16 TCLOV2 RD,W R , GCS7:0 , LCS , UCS , AD15:0 (AD7:0, A15:8), 3 20 ns 1, 4, 6 NCS, INTA1:0 , S2:0 TCHOF RD,W R , BHE (RFSH), DT/R , LOCK , S2:0 , A19:16 0 20 ns 1 TCLOF DEN, AD15:0 (AD7:0, A15:8) 0 20 ns 1
80C186EB/80C188EB, 80L186EB/80L188EB AC SPECIFICATIONS AC CharacteristicsÐ80C186EB25 (Continued) Symbol Parameter TCHIS TEST, NMI, INT4:0, BCLK1:0, T1:0IN, READY, CTS1:0 , P2.6, P2.7 10 ns 1, 9 TCHIH TEST, NMI, INT4:0, BCLK1:0, T1:0IN, READY, CTS1:0 3n s 1 , 9 TCLIS AD15:0 (AD7:0), READY 10 ns 1, 10 TCLIH READY, AD15:0 (AD7:0) 3 ns 1, 10 TCLIS HOLD, PEREQ, ERROR 10 ns 1, 9 TCLIH HOLD, PEREQ, ERROR 3n s 1 , 9 NOTES: 1. See AC Timing Waveforms , for waveforms and definition. 2. Measure at V IH for high time, V IL for low time. 3. Only required to guarantee I CC. Maximum limits are bounded by T C,T CH and T CL. 4. Specified for a 50 pF load, see Figure 13 for capacitive derating information. 5. Specified for a 50 pF load, see Figure 14 for rise and fall times outside 50 pF. 6. See Figure 14 for rise and fall times. 7. T CHOV1 applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release. 8. T CHOV2 applies to RD and WR only after a HOLD release. 9. Setup and Hold are required to guarantee recognition. 10. Setup and Hold are required for proper operation.
80C186EB/80C188EB, 80L186EB/80L188EB AC SPECIFICATIONS AC CharacteristicsÐ80C186EB20/80C186EB13 Symbol Parameter
20 MHz 13 MHz
TF CLKIN Frequency 0 40 0 26 MHz 1 TC CLKIN Period 25 % 38.5 % ns 1 TCH CLKIN High Time 10 % 12 % ns 1, 2 TCL CLKIN Low Time 10 % 12 % ns 1, 2 TCR CLKIN Rise Time 1818 n s 1 , 3 TCF CLKIN Fall Time 1818 n s 1 , 3 OUTPUT CLOCK TCD CLKIN to CLKOUT Delay 0 17 0 23 ns 1, 4 T CLKOUT Period 2 *TC 2*TC ns 1 TPH CLKOUT High Time (T/2) b 5 (T/2) a 5 (T/2) b 5 (T/2) a 5n s 1 TPL CLKOUT Low Time (T/2) b 5 (T/2) a 5 (T/2) b 5 (T/2) a 5n s 1 TPR CLKOUT Rise Time 1616 n s 1 , 5 TPF CLKOUT Fall Time 1616 n s 1 , 5 OUTPUT DELAYS TCHOV1 ALE, S2:0 , DEN , DT/R , 3 2 2 3 2 5 n s 1 ,4 ,6 ,7 BHE (RFSH), LOCK , A19:16 TCHOV2 GCS0:7, LCS , UCS , NCS , 3 2 7 3 3 0 n s 1 ,4 ,6 ,8 RD,W R TCLOV1 BHE (RFSH), DEN , LOCK , 3 2 2 3 2 5 n s 1 ,4 ,6 RESOUT, HLDA, T0OUT, T1OUT, A19:16 TCLOV2 RD,W R , GCS7:0 , LCS , 3 2 7 3 3 0 n s 1 ,4 ,6 UCS, AD15:0 (AD7:0, A15:8), NCS , INTA1:0 , S2:0 TCHOF RD,W R , BHE (RFSH) , 02 502 5 n s 1 DT/R, LOCK , S2:0 , A19:16 TCLOF DEN, AD15:0 (AD7:0, 0 25 0 25 ns 1 A15:8)
80C186EB/80C188EB, 80L186EB/80L188EB AC SPECIFICATIONS AC CharacteristicsÐ80C186EB20/80C186EB13 (Continued) Symbol Parameter TCHIS TEST, NMI, INT4:0, BCLK1:0, T1:0IN, 10 10 ns 1, 9 READY, CTS1:0 , P2.6, P2.7 TCHIH TEST, NMI, INT4:0, BCLK1:0, T1:0IN, 3 3 ns 1, 9 READY, CTS1:0 TCLIS AD15:0 (AD7:0), READY 10 10 ns 1, 10 TCLIH READY, AD15:0 (AD7:0) 3 3 ns 1, 10 TCLIS HOLD, PEREQ, ERROR 10 10 ns 1, 9 TCLIH HOLD, PEREQ, ERROR 3 3 ns 1, 9 NOTES: 1. See AC Timing Waveforms , for waveforms and definition. 2. Measure at V IH for high time, V IL for low time. 3. Only required to guarantee I CC. Maximum limits are bounded by T C,T CH and T CL. 4. Specified for a 50 pF load, see Figure 13 for capacitive derating information. 5. Specified for a 50 pF load, see Figure 14 for rise and fall times outside 50 pF. 6. See Figure 14 for rise and fall times. 7. T CHOV1 applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release. 8. T CHOV2 applies to RD and WR only after a HOLD release. 9. Setup and Hold are required to guarantee recognition. 10. Setup and Hold are required for proper operation.
80C186EB/80C188EB, 80L186EB/80L188EB AC SPECIFICATIONS AC CharacteristicsÐ80L186EB16 Symbol Parameter
16 MHz
TF CLKIN Frequency 0 32 MHz 1 TC CLKIN Period 31.25 % ns 1 TCH CLKIN High Time 13 % ns 1, 2 TCL CLKIN Low Time 13 % ns 1, 2 TCR CLKIN Rise Time 1 8 ns 1, 3 TCF CLKIN Fall Time 1 8 ns 1, 3 OUTPUT CLOCK TCD CLKIN to CLKOUT Delay 0 30 ns 1, 4 T CLKOUT Period 2 *TC ns 1 TPH CLKOUT High Time (T/2) b 5 (T/2) a 5n s 1 TPL CLKOUT Low Time (T/2) b 5 (T/2) a 5n s 1 TPR CLKOUT Rise Time 1 9 ns 1, 5 TPF CLKOUT Fall Time 1 9 ns 1, 5 OUTPUT DELAYS TCHOV1 DT/R, LOCK , A19:16, R FSH 3 2 2 n s 1 ,4 ,6 ,7 TCHOV2 GCS0:7, LCS , UCS , NCS ,R D ,W R 3 2 7 n s 1 ,4 ,6 ,8 TCHOV3 BHE, DEN 32 5 n s 1 , 4 TCHOV4 ALE 3 30 ns 1, 4 TCHOV5 S2:0 33 3 n s 1 , 4 TCLOV1 LOCK, RESOUT, HLDA, T0OUT, T1OUT, A19:16 3 22 ns 1, 4, 6 TCLOV2 RD,W R , GCS7:0 , LCS , UCS , NCS , INTA1:0 , AD15:0 3 27 ns 1, 4, 6 (AD7:0, A15:8) TCHOF RD,W R , BHE (RFSH), DT/R , LOCK , S2:0 , A19:16 0 25 ns 1 TCLOF DEN, AD15:0 (AD7:0, A15:8) 0 25 ns 1 TCLOV3 BHE, DEN 3 2 5 n s 1 ,4 ,6 TCLOV5 S2:0 3 3 3 n s 1 ,4 ,6
80C186EB/80C188EB, 80L186EB/80L188EB AC SPECIFICATIONS AC CharacteristicsÐ80L186EB16 (Continued) Symbol Parameter TCHIS TEST, NMI, INT4:0, BCLK1:0, T1:0IN, READY, CTS1:0 , P2.6, P2.7 15 ns 1, 9 TCHIH TEST, NMI, INT4:0, T1:0IN, BCLK1:0, READY, CTS1:0 3n s 1 , 9 TCLIS AD15:0 (AD7:0), READY 15 ns 1, 10 TCLIH READY, AD15:0 (AD7:0) 3 ns 1, 10 TCLIS HOLD 15 ns 1, 9 TCLIH HOLD 3 ns 1, 9 NOTES: 1. See AC Timing Waveforms , for waveforms and definition. 2. Measure at V IH for high time, V IL for low time. 3. Only required to guarantee I CC. Maximum limits are bounded by T C,T CH and T CL. 4. Specified for a 50 pF load, see Figure 13 for capacitive derating information. 5. Specified for a 50 pF load, see Figure 14 for rise and fall times outside 50 pF. 6. See Figure 14 for rise and fall times. 7. T CHOV1 applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release. 8. T CHOV2 applies to RD and WR only after a HOLD release. 9. Setup and Hold are required to guarantee recognition. 10. Setup and Hold are required for proper operation.
80C186EB/80C188EB, 80L186EB/80L188EB AC SPECIFICATIONS AC CharacteristicsÐ80L186EB13/80L186EB8 Symbol Parameter 13 MHz 8 MHz Units Notes Min Max Min Max INPUT CLOCK Tr CLKIN Frequency 0 26 0 16 MHz 1 TC CLKIN Period 38.5 % 62.5 % ns 1 TCH CLKIN High Time 15 % 15 % ns 1, 2 TCL CLKIN Low Time 15 % 15 % ns 1, 2 TCR CLKIN Rise Time 1 8 1 8 ns 1, 3 TCF CLKIN Fall Time 1 8 1 8 ns 1, 3 OUTPUT CLOCK TCD CLKIN to CLKOUT Delay 0 10 0 50 ns 1, 4 T CLKOUT Period 2 *TC 2*TC ns 1 TPH CLKOUT High Time (T/2) b 5 (T/2) a5 (T/2) b 5 (T/2) a5n s 1 TPL CLKOUT Low Time (T/2) b 5 (T/2) a 5 (T/2) b 5 (T/2) a 5n s 1 TPR CLKOUT Rise Time 1 10 1 15 ns 1, 5 TPF CLKOUT Fall Time 1 10 1 15 ns 1, 5 OUTPUT DELAYS TCHOV1 ALE, S2-0 , DEN , DT/R , 3 2 5 3 3 0 n s 1 ,4 ,6 ,7 BHE (RFSH), LOCK , A19:16 TCHOV2 GCS0:7, LCS , UCS , 3 30 3 35 ns 1, 4,6, 8 NCS,R D ,W R TCLOV1 BHE (RFSH), DEN , 3 2 5 3 3 0 n s 1 ,4 ,6 LOCK, RESOUT, HLDA, T0OUT, T1OUT, A19:16 TCLOV2 S2:0,R D ,W R , GCS7:0 , 3 3 0 3 3 5 n s 1 ,4 ,6 LCS, UCS , NCS , INTA1:0, AD15:0 (AD7:0, A15:8) TCHOF RD,W R , BHE (RFSH), 0 30 0 30 ns 1 DT/R, LOCK , S2:0 , A19:16 TCLOF DEN, AD15:0 0 30 0 35 ns 1 (AD7:0, A15:8)
80C186EB/80C188EB, 80L186EB/80L188EB AC SPECIFICATIONS AC CharacteristicsÐ80L186EB13/80L186EB8 (Continued) Symbol Parameter 13 MHz 8 MHz Units Notes Min Max Min Max SYNCHRONOUS INPUTS TCHIS TEST, NMI, INT4:0, 20 25 ns 1, 9 BCLK1:0, T1:0IN, READY CTS1:0 , P2.6, P2.7 TCHIH TEST, NMI, INT4:0, T1:0IN, 3 3 ns 1, 9 BCLK1:0, READY, CTS1:0 TCLIS AD15:0 (AD7:0), READY 20 25 ns 1, 10 TCLIH READY, AD15:0 (AD7:0) 3 3 ns 1, 10 TCLIS HOLD 20 25 ns 1, 9 TCLIH HOLD 3 3 ns 1, 9 NOTES: 1. See AC Timing Waveforms , for waveforms and definition. 2. Measured at V IH for high time, V IL for low time. 3. Only required to guarantee I CC. Maximum limits are bounded by T C,T CH and T CL. 4. Specified for a 50 pF load, see Figure 13 for capacitive derating information. 5. Specified for a 50 pF load, see Figure 14 for rise and fall times outside 50 pF. 6. See Figure 14 for rise and fall times. 7. T CHOV1 applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release. 8. T CHOV2 applies to RD and WR only after a HOLD release. 9. Setup and Hold are required to guarantee recognition. 10. Setup and Hold are required for proper operation.
80C186EB/80C188EB, 80L186EB/80L188EB AC SPECIFICATIONS (Continued) Relative Timings (80C186EB25, 20, 13/80L186EB16, 13, 8) Symbol Parameter Min Max Units Notes RELATIVE TIMINGS TLHLL ALE Rising to ALE Falling T b 15 ns TAVLL Address Valid to ALE Falling (/2T b 10 ns TPLLL Chip Selects Valid to ALE Falling (/2T b 10 ns 1 TLLAX Address Hold from ALE Falling (/2T b 10 ns TLLWL ALE Falling to WR Falling (/2T b 15 ns 1 TLLRL ALE Falling to RD Falling (/2T b 15 ns 1 TWHLH WR Rising to ALE Rising (/2T b 10 ns 1 TAFRL Address Float to RD Falling 0 ns TRLRH RD Falling to RD Rising (2 *T) b 5n s 2 TWLWH WR Falling to WR Rising (2 *T) b 5n s 2 TRHAV RD Rising to Address Active T b 15 ns TWHDX Output Data Hold after WR Rising T b 15 ns TWHPH WR Rising to Chip Select Rising (/2T b 10 ns 1 TRHPH RD Rising to Chip Select Rising (/2T b 10 ns 1 TPHPL CS Inactive to CS Active (/2T b 10 ns 1 TOVRH ONCE Active to RESIN Rising T ns 3 TRHOX ONCE Hold from RESIN Rising T ns 3 NOTES: 1. Assumes equal loading on both pins. 2. Can be extended using wait states. 3. Not tested
80C186EB/80C188EB, 80L186EB/80L188EB AC SPECIFICATIONS (Continued) Serial Port Mode 0 Timings (80C186EB25, 20, 13/80L186EB16, 13, 8) Symbol Parameter Min Max Unit Notes TXLXL TXD Clock Period T (n a 1) ns 1, 2 TXLXH TXD Clock Low to Clock High (n l 1) 2T b 35 2T a 35 ns 1 TXLXH TXD Clock Low to Clock High (n e 1) T b 35 T a 35 ns 1 TXHXL TXD Clock High to Clock Low (n l 1) (n b 1) T b 35 (n b 1) T a 35 ns 1, 2 TXHXL TXD Clock High to Clock Low (n e 1) T b 35 T a 35 ns 1 TQVXH RXD Output Data Setup to TXD Clock High (n l 1) (n b 1) T b 35 ns 1, 2 TQVXH RXD Output Data Setup to TXD Clock High (n e 1) T b 35 ns 1 TXHQX RXD Output Data Hold after TXD Clock High (n l 1) 2T b 35 ns 1 TXHQX RXD Output Data Hold after TXD Clock High (n e 1) T b 35 ns 1 TXHQZ RXD Output Data Float after Last TXD Clock High T a 20 ns 1 TDVXH RXD Input Data Setup to TXD Clock High T a 20 ns 1 TXHDX RXD Input Data Hold after TXD Clock High 0 ns 1 NOTES: 1. See Figure 12 for waveforms. 2. n is the value of the BxCMP register ignoring the ICLK Bit (i.e., ICLK e 0).
Figure 15. Cold Reset Waveforms low for two CLKIN periods. If RESIN is sampled high while CLKOUT is low (dashed line), then CLKOUT will not be affected.
Figure 16. Warm Reset Waveforms low for two CLKIN periods. If RESIN is sampled high while CLKOUT is low (dashed line), then CLKOUT will not be affected.
needed for a given application. Figure 17. Read, Fetch, and Refresh Cycle Waveforms
Figure 18. Write Cycle Waveforms
Figure 19. Halt Cycle Waveforms
Figure 20. Interrupt Acknowledge Cycle Waveform
Figure 21. HOLD/HLDA Waveforms
- READY must be low by either edge to cause a wait state.
- Lighter lines indicate READ cycles, darker lines indicate WRITE cycles.
Figure 22. Refresh during Hold Acknowledge
- READY must be low by either edge to cause a wait state.
- Lighter lines indicate READ cycles, darker lines indicate WRITE cycles.
Figure 23. Ready Waveforms
80C186EB/80C188EB, 80L186EB/80L188EB EXECUTION TIMINGS A determination of program execution timing must consider the bus cycles necessary to prefetch in- structions as well as the number of execution unit cycles necessary to execute instructions. The fol- lowing instruction timings represent the minimum execution time in clock cycles for each instruction. The timings given are based on the following as- sumptions: # The opcode, along with any data or displacement required for execution of a particular instruction, has been prefetched and resides in the queue at the time it is needed. # No wait states or bus HOLDs occur. # All word-data is located on even-address bound- aries (80C186EB only). All jumps and calls include the time required to fetch the opcode of the next instruction at the destination address. All instructions which involve memory accesses can require one or two additional clocks above the mini- mum timings shown due to the asynchronous hand- shake between the bus interface unit (BIU) and exe- cution unit. With a 16-bit BIU, the 80C186EB has sufficient bus performance to ensure that an adequate number of prefetched bytes will reside in the queue (6 bytes) most of the time. Therefore, actual program execu- tion time will not be substantially greater than that derived from adding the instruction timings shown. The 80C188EB 8-bit BIU is limited in its performance relative to the execution unit. A sufficient number of prefetched bytes may not reside in the prefetch queue (4 bytes) much of the time. Therefore, actual program execution time will be substantially greater than that derived from adding the instruction timings shown.
80C186EB/80C188EB, 80L186EB/80L188EB INSTRUCTION SET SUMMARY 80C186EB 80C188EB Function Format Clock Clock Comments Cycles Cycles DATA TRANSFER MOV e Move: Register to Register/Memory 1000100w m o dr e g r / m 2/12 2/12 * Register/memory to register 1000101w m o dr e g r / m 2 / 9 2 / 9 * Immediate to register/memory 1100011w m o d0 0 0 r / m data data if w e1 12/13 12/13 8/16-bit Immediate to register 1011w r e g data data if w e1 3/4 3/4 8/16-bit Memory to accumulator 1010000w addr-low addr-high 8 8 * Accumulator to memory 1010001w addr-low addr-high 9 9 * Register/memory to segment register 10001110 m o d0r e g r / m 2 / 9 2/13 Segment register to register/memory 10001100 m o d0r e g r / m 2/11 2/15 PUSH e Push: Memory 11111111 m o d110 r / m 1 6 2 0 Register 01010 r e g 1 0 1 4 Segment register 000r e g110 9 1 3 Immediate 011010s0 data data if s e01 0 1 4 PUSHA e Push All 01100000 3 6 6 8 POP e Pop: Memory 10001111 m o d000 r / m 2 0 2 4 Register 01011 r e g 1 0 1 4 Segment register 000r e g111 (regi01) 8 12 POPA e P o pA l l 01100001 5 1 8 3 XCHG e Exchange: Register/memory with register 1000011w m o dr e g r / m 4/17 4/17 * Register with accumulator 10010 r e g 3 3 IN e Input from: Fixed port 1110010w port 10 10 * Variable port 1110110w 8 8 * OUT e Output to: Fixed port 1110011w port 9 9 * Variable port 1110111w 7 7 * XLAT e Translate byte to AL 11010111 1 1 1 5 LEA e Load EA to register 10001101 m o dr e g r / m 6 6 LDS e Load pointer to DS 11000101 m o dr e g r / m (modi11) 18 26 LES e Load pointer to ES 11000100 m o dr e g r / m (modi11) 18 26 LAHF e Load AH with flags 10011111 2 2 SAHF e Store AH into flags 10011110 3 3 PUSHF e Push flags 10011100 9 1 3 POPF e Pop flags 10011101 8 1 2 Shaded areas indicate instructions not available in 8086/8088 microsystems. NOTE: *Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.
80C186EB/80C188EB, 80L186EB/80L188EB INSTRUCTION SET SUMMARY (Continued) 80C186EB 80C188EB Function Format Clock Clock Comments Cycles Cycles DATA TRANSFER (Continued) SEGMENT e Segment Override: CS 00101110 2 2 SS 00110110 2 2 DS 00111110 2 2 ES 00100110 2 2 ARITHMETIC ADD e Add: Reg/memory with register to either 000000dw m o dr e g r / m 3/10 3/10 * Immediate to register/memory 100000sw m o d000 r / m data data if s w e01 4/16 4/16 * Immediate to accumulator 0000010w data data if w e1 3/4 3/4 8/16-bit ADC e Add with carry: Reg/memory with register to either 000100dw m o dr e g r / m 3/10 3/10 * Immediate to register/memory 100000sw m o d010 r / m data data if s w e01 4/16 4/16 * Immediate to accumulator 0001010w data data if w e1 3/4 3/4 8/16-bit INC e Increment: Register/memory 1111111w m o d000 r / m 3/15 3/15 * Register 01000 r e g 3 3 SUB e Subtract: Reg/memory and register to either 001010dw m o dr e g r / m 3/10 3/10 * Immediate from register/memory 100000sw m o d101 r / m data data if s w e01 4/16 4/16 * Immediate from accumulator 0010110w data data if w e1 3/4 3/4 8/16-bit SBB e Subtract with borrow: Reg/memory and register to either 000110dw m o dr e g r / m 3/10 3/10 * Immediate from register/memory 100000sw m o d011 r / m data data if s w e01 4/16 4/16 * Immediate from accumulator 0001110w data data if w e1 3/4 3/4 * 8/16-bit DEC e Decrement Register/memory 1111111w m o d001 r / m 3/15 3/15 * Register 01001 r e g 3 3 CMP e Compare: Register/memory with register 0011101w m o dr e g r / m 3/10 3/10 * Register with register/memory 0011100w m o dr e g r / m 3/10 3/10 * Immediate with register/memory 100000sw m o d111 r / m data data if s w e01 3/10 3/10 * Immediate with accumulator 0011110w data data if w e1 3/4 3/4 8/16-bit NEG e Change sign register/memory 1111011w m o d011 r / m 3/10 3/10 * AAA e ASCII adjust for add 00110111 8 8 DAA e Decimal adjust for add 00100111 4 4 AAS e ASCII adjust for subtract 00111111 7 7 DAS e Decimal adjust for subtract 00101111 4 4 MUL e Multiply (unsigned): 1111011w m o d1 0 0 r / m Register-Byte 26–28 26–28 Register-Word 35–37 35–37 Memory-Byte 32–34 32–34 Memory-Word 41–43 41–43 * Shaded areas indicate instructions not available in 8086/8088 microsystems. NOTE: *Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.
80C186EB/80C188EB, 80L186EB/80L188EB INSTRUCTION SET SUMMARY (Continued) 80C186EB 80C188EB Function Format Clock Clock Comments Cycles Cycles ARITHMETIC (Continued) IMUL e Integer multiply (signed): 1111011w m o d101 r / m Register-Byte 25–28 25–28 Register-Word 34–37 34–37 Memory-Byte 31–34 31–34 Memory-Word 40–43 40–43 * IMUL e Integer Immediate multiply 011010s1 m o dr e g r / m data data if s e0 22–25/ 22–25/ (signed) 29–32 29–32 DIV e Divide (unsigned): 1111011w m o d110 r / m Register-Byte 29 29 Register-Word 38 38 Memory-Byte 35 35 Memory-Word 44 44 * IDIV e Integer divide (signed): 1111011w m o d111 r / m Register-Byte 44–52 44–52 Register-Word 53–61 53–61 Memory-Byte 50–58 50–58 Memory-Word 59–67 59–67 * AAM e ASCII adjust for multiply 11010100 00001010 1 9 1 9 AAD e ASCII adjust for divide 11010101 00001010 1 5 1 5 CBW e Convert byte to word 10011000 2 2 CWD e Convert word to double word 10011001 4 4 LOGIC Shift/Rotate Instructions: Register/Memory by 1 1101000w m o dT T Tr / m 2/15 2/15 Register/Memory by CL 1101001w m o dT T Tr / m 5an/17an5 an/17an Register/Memory by Count 1100000w m o dT T Tr / m count 5an/17an5 an/17an TTT Instruction
000 R O L
001 R O R
010 R C L
011 R C R
101 S H R
111 S A R
AND e And: Reg/memory and register to either 001000dw m o dr e g r / m 3/10 3/10 * Immediate to register/memory 1000000w m o d100 r / m data data if w e1 4/16 4/16 * Immediate to accumulator 0010010w data data if w e1 3/4 3/4 * 8/16-bit TESTeAnd function to flags, no result: Register/memory and register 1000010w m o dr e g r / m 3/10 3/10 * Immediate data and register/memory 1111011w m o d000 r / m data data if w e1 4/10 4/10 * Immediate data and accumulator 1010100w data data if w e1 3/4 3/4 8/16-bit OReOr: Reg/memory and register to either 000010dw m o dr e g r / m 3/10 3/10 * Immediate to register/memory 1000000w m o d001 r / m data data if w e1 4/16 4/16 * Immediate to accumulator 0000110w data data if w e1 3/4 3/4 * 8/16-bit Shaded areas indicate instructions not available in 8086/8088 microsystems. NOTE: *Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.
80C186EB/80C188EB, 80L186EB/80L188EB INSTRUCTION SET SUMMARY (Continued) 80C186EB 80C188EB Function Format Clock Clock Comments Cycles Cycles LOGIC (Continued) XOR e Exclusive or: Reg/memory and register to either 001100dw m o dr e g r / m 3/10 3/10 * Immediate to register/memory 1000000w m o d110 r / m data data if w e1 4/16 4/16 * Immediate to accumulator 0011010w data data if w e1 3/4 3/4 8/16-bit NOT e Invert register/memory 1111011w m o d010 r / m 3/10 3/10 * STRING MANIPULATION MOVS e Move byte/word 1010010w 1 4 1 4 * CMPS e Compare byte/word 1010011w 2 2 2 2 * SCAS e Scan byte/word 1010111w 1 5 1 5 * LODS e Load byte/wd to AL/AX 1010110w 1 2 1 2 * STOS e Store byte/wd from AL/AX 1010101w 1 0 1 0 * INS e Input byte/wd from DX port 0110110w 1 4 1 4 OUTS e Output byte/wd to DX port 0110111w 1 4 1 4 Repeated by count in CX (REP/REPE/REPZ/REPNE/REPNZ) MOVS e Move string 11110010 1010010w 8 a8n 8 a8n* CMPS e Compare string 1111001z 1010011w 5 a22n 5 a22n* SCAS e Scan string 1111001z 1010111w 5 a15n 5 a15n* LODS e Load string 11110010 1010110w 6 a11n 6 a11n* STOS e Store string 11110010 1010101w 6 a9n 6 a9n* INS e Input string 11110010 0110110w 8 a8n 8 a8n* OUTS e Output string 11110010 0110111w 8 a8n 8 a8n* CONTROL TRANSFER CALL e Call: Direct within segment 11101000 disp-low disp-high 15 19 Register/memory 11111111 m o d010 r / m 13/19 17/27 indirect within segment Direct intersegment 10011010 segment offset 23 31 segment selector Indirect intersegment 11111111 m o d011 r / m (mod i 11) 38 54 JMP e Unconditional jump: Short/long 11101011 disp-low 14 14 Direct within segment 11101001 disp-low disp-high 14 14 Register/memory 11111111 m o d100 r / m 11/17 11/21 indirect within segment Direct intersegment 11101010 segment offset 14 14 segment selector Indirect intersegment 11111111 m o d101 r / m (mod i 11) 26 34 Shaded areas indicate instructions not available in 8086/8088 microsystems. NOTE: *Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.
80C186EB/80C188EB, 80L186EB/80L188EB INSTRUCTION SET SUMMARY (Continued) 80C186EB 80C188EB Function Format Clock Clock Comments Cycles Cycles CONTROL TRANSFER (Continued) RET e Return from CALL: Within segment 11000011 1 6 2 0 Within seg adding immed to SP 11000010 data-low data-high 18 22 Intersegment 11001011 2 2 3 0 Intersegment adding immediate to SP 11001010 data-low data-high 25 33 JE/JZ e Jump on equal/zero 01110100 disp 4/13 4/13 JMP not JL/JNGE e Jump on less/not greater or equal 01111100 disp 4/13 4/13 taken/JMP JLE/JNG e Jump on less or equal/not greater 01111110 disp 4/13 4/13 taken JB/JNAE e Jump on below/not above or equal 01110010 disp 4/13 4/13 JBE/JNA e Jump on below or equal/not above 01110110 disp 4/13 4/13 JP/JPE e Jump on parity/parity even 01111010 disp 4/13 4/13 JO e Jump on overflow 01110 000 disp 4/13 4/13 JS e Jump on sign 01111000 disp 4/13 4/13 JNE/JNZ e Jump on not equal/not zero 01110101 disp 4/13 4/13 JNL/JGE e Jump on not less/greater or equal 01111101 disp 4/13 4/13 JNLE/JG e Jump on not less or equal/greater 01111111 disp 4/13 4/13 JNB/JAE e Jump on not below/above or equal 01110011 disp 4/13 4/13 JNBE/JA e Jump on not below or equal/above 01110111 disp 4/13 4/13 JNP/JPO e Jump on not par/par odd 01111011 disp 4/13 4/13 JNO e Jump on not overflow 01110001 disp 4/13 4/13 JNS e Jump on not sign 01111001 disp 4/13 4/13 JCXZ e Jump on CX zero 11100011 disp 5/15 5/15 LOOP e Loop CX times 11100010 disp 6/16 6/16 LOOP not LOOPZ/LOOPE e Loop while zero/equal 11100001 disp 6/16 6/16 taken/LOOP LOOPNZ/LOOPNE e Loop while not zero/equal 11100000 disp 6/16 6/16 taken ENTER e Enter Procedure 11001000 data-low data-high L L e 0 15 19 L e 1 25 29 L l 1 22a16(nb1) 26 a20(nb1) LEAVE e Leave Procedure 11001001 8 8 INT e Interrupt: Type specified 11001101 type 47 47 Type 3 11001100 4 5 4 5 i f INT. taken/ INTO e Interrupt on overflow 11001110 48/4 48/4 if INT. not taken IRET e Interrupt return 11001111 2 8 2 8 BOUND e Detect value out of range 01100010 m o dr e g r / m 3 3 – 3 5 3 3 – 3 5 Shaded areas indicate instructions not available in 8086/8088 microsystems. NOTE: *Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.
80C186EB/80C188EB, 80L186EB/80L188EB INSTRUCTION SET SUMMARY (Continued) 80C186EB 80C188EB Function Format Clock Clock Comments Cycles Cycles PROCESSOR CONTROL CLC e Clear carry 11111000 2 2 CMC e Complement carry 11110101 2 2 STC e Set carry 11111001 2 2 CLD e Clear direction 11111100 2 2 STD e Set direction 11111101 2 2 CLI e Clear interrupt 11111010 2 2 STI e Set interrupt 11111011 2 2 HLT e Halt 11110100 2 2 WAIT e Wait 10011011 6 6 i f TEST e 0 LOCK e Bus lock prefix 11110000 2 2 NOP e No Operation 10010000 3 3 (TTT LLL are opcode to processor extension) Shaded areas indicate instructions not available in 8086/8088 microsystems. NOTE: *Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers. FOOTNOTES The Effective Address (EA) of the memory operand is computed according to the mod and r/m fields: if mod e 11 then r/m is treated as a REG field if mod e 00 then DISP e 0*, disp-low and disp- high are absent if mod e 01 then DISP e disp-low sign-ex- tended to 16-bits, disp-high is absent if mod e 10 then DISP e disp-high: disp-low if r/m e 000 then EA e (BX) a (SI) a DISP if r/m e 001 then EA e (BX) a (DI) a DISP if r/m e 010 then EA e (BP) a (SI) a DISP if r/m e 011 then EA e (BP) a (DI) a DISP if r/m e 100 then EA e (SI) a DISP if r/m e 101 then EA e (DI) a DISP if r/m e 110 then EA e (BP) a DISP* if r/m e 111 then EA e (BX) a DISP DISP follows 2nd byte of instruction (before data if required) *except if mod e 00 and r/m e 110 then EA e disp-high: disp-low. EA calculation time is 4 clock cycles for all modes, and is included in the execution times given whenev- er appropriate. Segment Override Prefix 0 0 1 reg 1 1 0 reg is assigned according to the following: Segment reg Register 00 ES 01 CS 10 SS 11 DS REG is assigned according to the following table: 16-Bit (w e 1) 8-Bit (w e 0)
000 AX 000 AL
001 CX 001 CL
010 DX 010 DL
011 BX 011 BL
100 SP 100 AH
101 BP 101 CH
110 SI 110 DH
111 DI 111 BH
The physical addresses of all operands addressed by the BP register are computed using the SS seg- ment register. The physical addresses of the desti- nation operands of the string primitive operations (those addressed by the DI register) are computed using the ES segment, which may not be overridden.
80C186EB/80C188EB, 80L186EB/80L188EB ERRATA An 80C186EB/80L186EB with a STEPID value of 0001H has the following known errata. A device with a STEPID of 0001H can be visually identified by the presence of an ‘‘A’’ alpha character next to the FPO number. The FPO number location is shown in Figures 4, 5 and 6. 1. A19/ONCE is not latched by the rising edge of RESIN. A19/ONCE must remain active (LOW) at all times to remain in the ONCE Mode. Removing A19/ONCE after RESIN is high will return all out- put pins to a driving state, however, the 80C186EB will remain in a reset state. 2. During interrupt acknowledge (INTA) bus cycles, the bus controller will ignore the state of the READY pin if the previous bus cycle ignored the state of the READY pin. This errata can only oc- cur if the Chip-Select Unit is being used. All active chip-selects must be programmed to use READY (RDY bit must be programmed to a 1) if wait- states are required for INTA bus cycles. 3. CLKOUT will transition off the rising edge of CLKIN rather than the falling edge of CLKIN. This does not affect any bus timings other than T CD. 4. RESIN has a hysterisis of only 130 mV. It is rec- ommended that RESIN be driven by a Schmitt triggered device to avoid processor lockup during reset using an RC circuit. 5. SINT1 will only go active for one clock period when a receive or transmit interrupt is pending (i.e., it does not remain active until the S1STS register is read). If SINT1 is to be connected to any of the processor interrupt lines (INT0–INT4), then it must be latched by user logic. An 80C186EB/80L186EB with a STEPID value of 0001H or 0002H has the following known errata. A device with a STEPID of 0002H can be visually iden- tified by noting the presence of a ‘‘B’’, ‘‘C’’, ‘‘D’’, or ‘‘E’’ alpha character next to the FPO number. The FPO number location is shown in Figures 4, 5 and 6. 1. An internal condition with the interrupt controller can cause no acknowledge cycle on the INTA1 line in response to INT1. This errata only occurs when Interrupt 1 is configured in cascade mode and a higher priority interrupt exists. This errata will not occur consistantly, it is dependent on in- terrupt timing.
REVISION HISTORY
This data sheet replaces the following data sheets: 270803-004 80C186EB 270885-003 80C188EB 270921-003 80L186EB 270920-003 80L188EB 272311-001 SB80C188EB/SB80L188EB 272312-001 SB80C186EB/SB80L186EB