80960SA INTEL | Alldatasheet
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licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel. non-impact printers, network adapters and I/O controllers. Figure 1. The 80960S A Processor’s Highly Parallel Architecture
EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BU S
1.0 THE i960® PROCESSO R
interrupt response times and high performance. Figure 2. 80960SA Programming Environment
1.1 Key Performance Features
The 80960SA architecture is based on the most recent advances in microprocessor technology and is grounded in Intel’s long experience in the design and manufacture of embedded microprocessors. Many features contribute to the 80960SA’s excep- tional performance: 1. Large Register Set. Having a large number of registers reduces the number of times that a processor needs to access memory. Modern compilers can take advantage of this feature to optimize execution speed. For maximum flexi- bility, the 80960S A provides thirty-two 32-bit registers. (SeeFigure 2.) 2. Fast Instruction Execution.Simple functions make up the bulk of instructions in most programs so that execution speed can be improved by ensuring that these core instruc- tions are executed as quickly as possible. The most frequently executed instructions — such as register-register moves, add/subtract, logical operations and shifts — execute in one to two cycles. (Table 1 contains a list of instruc- tions.) 3. Load/Store Architecture. One way to improve execution speed is to reduce the number of times that the processor must access memory to perform an operation. As with other processors based on RISC technology, the 80960SA has a Load/Store architecture. As such, only the LOAD and STORE instructions reference memory; all other instructions operate on registers. This type of architecture simplifies instruction decoding and is used in combination with other techniques to increase parallelism. 4. Simple Instruction Formats. All instructions in the 80960S A are 32 bits long and must be aligned on word boundaries. This alignment makes it possible to eliminate the instruction alignment stage in the pipeline. To simplify the instruction decoder, there are only five instruction formats; each instruction uses only one format. (SeeFigure 3.) 5. Overlapped Instruction Execution. Load operations allow execution of subsequent instructions to continue before the data has been returned from memory, so that these instructions can overlap the load. The 80960SA manages this process transparently to software through the use of a register score- board. Conditional instructions also make use of a scoreboard so that subsequent unrelated instructions may be executed while the condi- tional instruction is pending. 6. Integer Execution Optimization. When the result of an arithmetic execution is used as an operand in a subsequent calculation, the value is sent immediately to its destination register. At the same time, the value is put on a bypass path to the ALU, thereby saving the time that otherwise would be required to retrieve the value for the next operation. 7. Bandwidth Optimizations. The 80960SA gets optimal use of its memory bus bandwidth because the bus is tuned for use with the on- chip instruction cache: instruction cache line size matches the maximum burst size for instruction fetches. The 80960S A automatically fetches four words in a burst and stores them directly in the cache. Due to the size of the cache and the fact that it is continually filled in anticipation of needed instructions in the program flow, the 80960SA is relatively insen- sitive to memory wait states. The benefit is that the 80960SA delivers outstanding performance even with a low cost memory system. 8. Cache Bypass . If a cache miss occurs, the processor fetches the needed instruction then sends it on to the instruction decoder at the same time it updates the cache. Thus, no extra time is spent to load and read the cache.
Table 1. 80960SA Instruction Set
Figure 3. Instruction Formats
1.1.1 Memory Space And Addressing Mode s
processor are contained in a single address space. Table 2. Memory Addressing Mode s
- 12-Bit Offset
- 32-Bit Offset
- Register-Indirect
- Register + 12-Bit Offset
- Register + 32-Bit Offset
- Register + (Index-Register x Scale-Factor)
- Register x Scale Factor + 32-Bit Displacement
- Register + (Index-Register x Scale-Factor) + 32- Bit Displacement Scale-Factor is 1, 2, 4, 8 or 16
1.1.2 Data Types
- 8-, 16-, 32- and 64-bit ordinals
- 8-, 16-, 32- and 64-bit integers Non-Numeric:
- Bit
- Bit Field
- Triple Word (96 bits)
- Quad-Word (128 bits)
1.1.3 Large Register Set
leads to greater instruction processing speed.
local register is 32 bits wide.
1.1.4 Multiple Register Sets
access the procedure stack resident in memory. pointer (FP) to the procedure stack. to all procedures for fast parameter passing. Figure 4. Multiple Register Sets Are Stored On-Chip
1.1.5 Instruction Cache
To further reduce memory accesses, the 80960S A includes a 512-byte on-chip instruction cache. The instruction cache is based on the concept of locality of reference; most programs are not usually executed in a steady stream but consist of many branches, loops and procedure calls that lead to jumping back and forth in the same small section of code. Thus, by maintaining a block of instructions in cache, the number of memory references required to read instructions into the processor is greatly reduced. To load the instruction cache, instructions are fetched in 16-byte blocks; up to four instructions can be fetched at one time. An efficient prefetch algorithm increases the probability that an instruction will already be in the cache when it is needed. Code for small loops often fits entirely within the cache, leading to a great increase in processing speed since further memory references might not be necessary until the program exits the loop. Similarly, when calling short procedures, the code for the calling procedure is likely to remain in the cache so it will be there on the procedure’s return.
1.1.6 Register Scoreboarding
The instruction decoder is optimized in several ways. One optimization method is the ability to overlap instructions by using register scoreboarding. Register scoreboarding occurs when a LOAD moves a variable from memory into a register. When the instruction initiates, a scoreboard bit on the target register is set. Once the register is loaded, the bit is reset. In between, any reference to the register contents is accompanied by a test of the scoreboard bit to ensure that the load has completed before processing continues. Since the processor does not need to wait for the LOAD to complete, it can execute additional instructions placed between the LOAD and the instruction that uses the register contents, as shown in the following example: ld data_2, r4 ld data_2, r5 Unrelated instruction Unrelated instruction add r4, r5, r6 In essence, the two unrelated instructions between LOAD and ADD are executed “for free” (i.e., take no apparent time to execute) because they are executed while the register is being loaded. Up to three load instructions can be pending at one time with three corresponding scoreboard bits set. By exploiting this feature, system programmers and compiler writers have a useful tool for optimizing execution speed.
1.1.7 High Bandwidth Bus
The 8096 0SA CPU resides on a high-bandwidth address/data bus. The bus provides a direct commu- nication path between the processor and the memory and I/O subsystem interfaces. The processor uses the bus to fetch instructions, manipulate memory and respond to interrupts. Bus features include:
- 16-bit data path multiplexed onto the lower bits of the 32-bit address path
- Eight 16-bit half-word burst capability which allows transfers from 1 to 16 bytes at a time
- High bandwidth reads and writes with32 Mbytes/s burst (at 20 MHz) Table 3 defines bus signal names and functions; Table 4 defines other component-support signals such as interrupt lines.
1.1.8 Interrupt Handling
The 80960S A can be interrupted in one of two ways: by the activation of one of four interrupt pins or by sending a message on the processor’s data bus. The 8096 0SA is unusual in that it automatically handles interrupts on a priority basis and can keep track of pending interrupts through its on-chip interrupt controller. Two of the interrupt pins can be configured to provide 8259A-style handshaking for expansion beyond four interrupt lines.
1.1.9 Debug Features
The 80960SA has built-in debug capabilities. There are two types of breakpoints and six trace modes. Debug features are controlled by two internal 32-bit registers, the Process-Controls Word and the Trace- Controls Word. By setting bits in these control words, a software debug monitor can closely control how the processor responds during program execution.
The 8096 0S A provides two hardware breakpoint registers on-chip which, by using a special command, can be set to any value. When the instruction pointer matches either breakpoint register value, the breakpoint handling routine is automati- cally called. The 80960SA also provides software breakpoints through the use of two instructions: MARK and FMARK. These can be placed at any point in a program and cause the processor to halt execution at that point and call the breakpoint handling routine. The breakpoint mechanism is easy to use and provides a powerful debugging tool. Tracing is available for instructions (single step execution), calls and returns and branching. Each trace type may be enabled separately by a special debug instruction. In each case, the 80960S A executes the instruction first and then calls a trace handling routine (usually part of a software debug monitor). Further program execution is halted until the routine completes, at which time execution resumes at the next instruction. The 80960SA ’s tracing mechanisms, implemented completely in hardware, greatly simplify the task of software test and debug.
1.1.10 Fault Detection
The 8096 0SA has an automatic mechanism to handle faults. Fault types include trace and arithmetic faults. When the processor detects a fault, it automatically calls the appropriate fault handling routine and saves the current instruction pointer and necessary state information to make efficient recovery possible. Like interrupt handling routines, fault handling routines are usually written to meet the needs of specific applications and are often included as part of the operating system or kernel. For each of the fault types, there are numerous subtypes that provide specific information about a fault. The fault handler can use this specific infor- mation to respond correctly to the fault.
1.1.11 Built-in Testability
Upon reset, the 80960SA automatically conducts an exhaustive internal test of its major blocks of logic. Then, before executing its first instruction, it does a zero check sum on the first eight words in memory to ensure that the memory image was programmed correctly. If a problem is discovered at any point during the self-test, the 80960S A asserts itsFAIL pin and will not begin program execution. Self test takes approximately24,000 cycles to complete. System manufacturers can use the 80960SA’s self- test feature during incoming parts inspection. No special diagnostic programs need to be written. The test is both thorough and fast. The self-test capability helps ensure that defective parts are discovered before systems are shipped and, once in the field, the self-test makes it easier to distinguish between problems caused by processor failure and problems resulting from other causes.
1.1.12 CHMO S
The 80960SA is fabricated using Intel’s CHMOS IV (Complementary High Speed Metal Oxide Semicon- ductor) process. The 80960SA is available at 10 and
16 MHz in the QFP package and at 10,16 and 20
MHz in the PLCC package.
Table 3. 80960SA Pin Description: Bus Signals (Sheet 1 of 2) divided by two inside the 80960SA to generate the internal processor clock. ADDRESS BU S carries the upper 16 bits of the 32-bit physical address to memory. It is valid throughout the burst cycle; no latch is required. cycle carries data on the bus. ADDRESS BU S carries the word addresses of the 32-bit address to memory. active HIGH and floats to a high impedance state during a hold cycle (Th). deasserted during the following Td state.AS is driven HIGH during reset. WRITE/REA D specifies, during a Ta cycle, whether the operation is a write or read. It is latched on-chip and remains valid during Td cycles. asserted. DT/R is driven HIGH during reset. inserting a wait state (Tw ).
asserted, the processor assertsLOC K during the Ta cycle of the read transaction. mode is used in conjunction with an in-circuit emulator. the current bus cycle.BE 1 corresponds to AD15:8;BE 0 corresponds to AD7:1, D0. The byte enable lines are asserted appropriately during each data cycle. continues andFAIL remains deasserted. deasserted, the processor deasserts HLDA and enters the Ti or Ta state. during the last Td and associated with Tw cycles in a burst access. continues andFAIL remains deasserted. Table 3. 80960SA Pin Description: Bus Signals (Sheet 2 of 2)
Table 4. 80960S A Pin Description: Support Signals RESE T I RESE T clears the processor’s internal logic and causes it to reinitialize. RESE T must be asserted for at least 41 CLK2 cycles for a predictable reset. before the next rising edge of CLK2. an interrupt vector before using this pin. during reset to determine if the self-test sequence is to be executed. pin marked NC; these pins may be reserved for factory use.
2.0 ELECTRICAL SPECIFICATION S
2.1 Power and Grounding
2.2 Power Decoupling
ularly when connected to a large capacitive load. capacitors as much as possible.
2.3 Connection Recommendation s
pulled up. No inputs should ever be left floating. shows the recommended resistor value. Do not connect external logic to pins marked NC. Figure 5. Connection Recommendation
2.4 C haracteristic Curves
when measured at three input voltage (VC C ) levels. shows the worst case output low voltage (VO L). the rising edge of the bus address/data (AD) signals.
Figure 6. Typical Supply Current vs. Case Temperature Figure 7. Typical Current vs. Frequency (Room Temp)
20 MHz
16 MHz
10 MHz
Figure 8. Typical Current vs. Frequency Figure 9. Capacitive Derating Curve
2.5 Test Load Circuit
Figure 10 illustrates the load circuit used to test the 80960SA’s output pins. Figure 10. Test Load Circuit for Three-State Output Pins
2.6 ABSOLUTE MAXIMUM RATINGS *
specifications are subject to change without notice. permanent damage. These are stress ratings only. “Operating Conditions” may affect device reliability.
2.7 DC Characteristics
Table 5. D C Characteristics
10 MHz-QFP
10 MHz-PLCC
16 MHz-PLC C
20 MHz-PLC C
- Not measured for open-drain output.
- INT0 andLOC K have internal pullup devices.
- Input, output and clock capacitance are not tested.
2.8 AC Specifications
relationships for the 80960S A signals. Figure 11. Drive Levels and Timing Relationships for 80960S A Signals
Table 6. 80960S A AC Characteristics (10 MHz)
- Processor clock (CLK2) rise time and fall time are not tested.
- A float condition occurs when the maximum output current becomes less than ILO . Float delay is not tested, but should be
no longer than the valid delay.
- MeetingRESE T setup and hold times is an optional method of synchronizing your clocks. If you decide to use an asyn-
chronous reset, synchronizing the clock can be accomplished by usingAS.
Table 7. 80960SA AC Characteristics (16 MHz)
- Processor clock (CLK2) rise time and fall time are not tested.
- A float condition occurs when the maximum output current becomes less than ILO . Float delay is not tested, but should be
no longer than the valid delay.
- MeetingRESE T setup and hold times is an optional method of synchronizing your clocks. If you decide to use an asyn-
chronous reset, synchronizing the clock can be accomplished by usingAS.
Table 8. 80960SA AC Characteristics (20 MHz)
- Processor clock (CLK2) rise time and fall time are not tested.
- A float condition occurs when the maximum output current becomes less than ILO . Float delay is not tested, but should be
no longer than the valid delay.
- MeetingRESE T setup and hold times is an optional method of synchronizing your clocks. If you decide to use an asyn-
chronous reset, synchronizing the clock can be accomplished by usingAS.
Figure 14. HOLD Timin g
3.0 MECHANICAL DAT A
3.1 Packaging
- 80-lead quad flat pack (EIAJ QFP). Shown in Figure 15.
- 84-lead plastic leaded chip carrier (PLCC). Shown inFigure 16. Dimensions for both package types are given in the IntelPackaging handbook (Order #240800).
3.2 Pin Assignment
The QFP and PLCC have different pin assignments. planes in your circuit board for power distribution. Figure 15. 80-Lead EIAJ Quad Flat Pack (QFP) Package
Figure 16. 84-Lead Plastic Leaded Chip Carrier (PLCC) Package AS
3.3 Pinout
Table 9. 80960SA QFP Pinout — In Pin Order
1 A22 21 V C C 41 BE 0 61 VC C
2 A21 22 V SS 42 VC C 62 VSS
3 A20 23 V C C 43 VSS 63 N C
4 A19 24 V SS 44 CLK 2 64 AS
5 A18 25 AD 6 45 RESE T 65 VSS
6 A17 26 AD 5 46 INT0 66 ALE
7 A16 27 AD 4 47 INT1 67 READ Y
8 V C C 28 AD 3 48 INT2/INTR 68 A31
9 V SS 29 AD 2 49 INT3/INTA 69 A30
10 AD1 5 30 AD 1 50 HLD A 70 A29
11 AD1 4 31 D 0 51 VC C 71 A28
12 V C C 32 V SS 52 VSS 72 VSS
13 V SS 33 V C C 53 HOL D 73 VC C
14 AD1 3 34 A 3 54 W /R 74 A27
15 AD1 2 35 A 2 55 DE N 75 A26
16 AD1 1 36 V C C 56 DT /R 76 A25
17 AD1 0 37 V SS 57 BLAS T 77 VC C
18 AD 9 38 A 1 58 LOC K 78 VSS
19 AD 8 39 N C 59 VC C 79 A24
20 AD 7 40 BE 1 60 VSS 80 A23
Do not connect any external logic to any pins marked NC.
Table 10. 80960SA QFP Pinout — In Signal Order Do not connect any external logic to any pins marked N.C.
Table 11. 80960S A PLCC Pinout — In Pin Order
1 VC C 22 VSS 43 VSS 64 HOL D
2 N C 23 N C 44 VC C 65 N C
3 A27 24 AD1 3 45 A3 66 W /R
4 A26 25 AD1 2 46 A2 67 DE N
5 A25 26 AD1 1 47 VC C 68 DT /R
6 VC C 27 AD1 0 48 VSS 69 BLAS T
7 VSS 28 AD 9 49 A1 70 LOC K
8 A24 29 AD 8 50 N C 71 V C C
9 A23 30 AD 7 51 BE 1 72 V SS
10 A22 31 VC C 52 BE 0 73 V C C
11 A21 32 VSS 53 VC C 74 V SS
12 A20 33 VC C 54 VSS 75 N C
13 A19 34 VSS 55 CLK 2 76 A S
14 A18 35 AD 6 56 RESE T 77 V SS
15 A17 36 AD 5 57 INT0 78 ALE
16 A16 37 AD 4 58 INT1 79 READ Y
17 VC C 38 AD 3 59 INT2/INTR 80 A31
18 VSS 39 D 2 60 INT3/INTA 81 A30
19 AD1 5 40 D 1 61 HLD A 82 A29
20 AD1 4 41 D 0 62 VC C 83 A28
21 VC C 42 N C 63 VSS 84 V SS
Do not connect any external logic to any pins marked NC.
Table 12. 80960SA PLCC Pinout — In Signal Order Do not connect any external logic to any pins marked NC.
3.4 Package Thermal Specifications
typically 80 percent of specified IC C maximum (cold). Table 13. 80960S A QFP Package Thermal Characteristics This table applies to 80960SA QFP soldered directly to board. Table 14. 80960SA PLCC Package Thermal Characteristics This table applies to 80960SA PLCC soldered directly to board.
3.5 Stepping Register Information
Table 15. Die Stepping Cross Reference
4.0 WAVEFORM S
a cold reset functional waveform. Figure 17. Non-Burst Read and Write Transactions Without Wait States
Figure 18. Quad Word Burst Read Transaction With 1, 0, 0, 0, 0, 0, 0, 0 Wait States
Figure 19. Burst Write Transaction With 2, 1, 1, 1 Wait States (6-8 Bytes Transferred)
Figure 20. Accesses Generated by Quad Word Read Bus Request,
Figure 21. Interrupt Acknowledge Cycle
Figure 22. Cold Reset Waveform
5.0 REVISION HISTOR Y
Output Pins) removed to reflect current test conditions. 2.7 DC Characteristics (pg. 14) -001 IO L value at 0.45V improved. LOC K pin IO L value at 0.45V relaxed. LOC K pin IO L value at 0.60V deleted. 80960SA 16 MHz QFP added to product list. 3.5 Stepping Register Information (pg. 27) -001 New section added.
2.3 Connection Recommendations
Figure 6. Typical Supply Current vs. Figure 7. Typical Current vs. Fre- Figure 8. Typical Current vs. Fre- -004 Regraphed new data in three graphs instead of two. Table 5. DC Characteristics (pg. 15) -004 Input Leakage Current (ILI2) Specification added to accu- rately describe leakage ofINT0 andLOC K as inputs.
10 MHz 280 240
16 MHz 350 300
Page numbers refer to 80960SA data sheet number 272206-001.
Table 6. 80960SA AC Characteristics Table 7. 80960SA AC Characteristics
10 MHz 24 ns T1 - 11 ns
16 MHZ 15 ns T1 - 11 ns
Table 8. 80960SA AC Characteristics -004 New 20 MHz specification table added for 80960SA C-step. Table 11. 80960SA PLCC Pinout — In -004 θJA increased to reflect smaller die size and lower IC C. The test program has not changed. Table 9. 80960SA and 80960SB QFP Page numbers refer to 80960SA data sheet number 272206-001.