VS28F016SV INTEL | Alldatasheet
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*Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. December 1995COPYRIGHT © INTEL CORPORATION, 1995 Order Number: 271312-002 VS28F016SV, MS28F016SV 16-Mbit (1-Mbit x 16, 2-Mbit x 8) FlashFile TM MEMORY Y VS28F016SV Ð b40§Ct o a125§C Ð SE2 Grade Y MS28F016SV Ð b55§Ct o a125§C Ð QML Certified Ð SE1 Grade Y SmartVoltage Technology Ð User-Selectable 3.3V or 5V V CC Ð User-Selectable 5V or 12V V PP Y Three Voltage/Speed Options Ð 80 ns Access Time, 5.0V g5% Ð 85 ns Access Time, 5.0V g10% Ð 120 ns Access Time, 3.3V g10% Y 1 Million Erase Cycles per Block Typical Y 14.3 MB/sec Burst Write Transfer Rate Y Configurable x8 or x16 Operation Y 56-Lead SSOP Plastic Package Y Backwards-Compatible with VE28F008, M28F008 and 28F016SA Command Set Y Revolutionary Architecture Ð Multiple Command Execution Ð Write During Erase Ð Command Super-Set of the Intel VE28F008, M28F008 Ð Page Buffer Write Y Multiple Power Savings Modes Y Two 256-Byte Page Buffers Y State-of-the-Art 0.6 mm ETOX TM IV Flash Technology Intel’s VS/MS28F016SV, 16-Mbit FlashFiIe TM Memory is the latest member of Intel’s high density, high per- formance memory family for the Industrial, Special Environment, and Military markets. Its user selectable V CC and V PP (SmartVoltage Technology), innovative capabilities, 100% compatibility with the VE28F008 and M28F008, multiple power savings modes, selective block locking, and very fast read/write performance make it the ideal choice for any applications that need a high density and a wide temperature range memory device. The VS/MS28F016SV is the ideal choice for designers who need to break free from the dependence on slow rotating media or battery backed up memory arrays. With two product grades (SE1: b55§Ct o a125§C, and SE2: b40§Ct o a125§C) available, the VS/MS28F016SV is perfect for the non-PC industries like Telecommunications, Embedded/Industrial, Auto- motive, Navigation, Wireless Communication, Commercial Aircraft, and all Military programs. The VS/MS28F016SV’s x8/x16 architecture allows for the optimization of the memory to processor interface. The flexible block locking options enable bundling of executable application software in a Resident Flash Array (RFA), PCMCIA Memory or ATA Cards or Memory modules. The VS/MS28F016SV is offered in a 56-lead SS0P (Shrink Small Outline Package) and is manufactured on Intel’s 0.6 mm ETOX TM IV process technology.
VS28F016SV, MS28F016SV FlashFile TM MEMORY CONTENTS PAGE
1.0 INTRODUCTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 3
1.1 Enhanced Features ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 3
1.2 Product Overview ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 3
2.0 DEVICE PINOUT ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5
2.1 Lead Descriptions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
3.0 MEMORY MAPS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 10
3.1 Extended Status Registers Memory
Map ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 11
4.0 BUS OPERATIONS, COMMANDS
ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12
4.1 Bus Operations for Word-Wide
Mode (BYTE Ý e VIH) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12
4.2 Bus Operations for Byte-Wide
Mode (BYTE Ý e VIL) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12
4.3 VE28F008 or M28F008 Compatible
Mode Command Bus Definitions ÀÀÀÀÀ 13
4.4 VS/MS28F016SV-Performance
ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14
4.5 Compatible Status Register ÀÀÀÀÀÀÀÀÀ 16
4.6 Global Status Register ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 17
4.7 Block Status Register ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 18
4.8 Device Configuration Code ÀÀÀÀÀÀÀÀÀ 19
5.0 ELECTRICAL SPECIFICATIONS ÀÀÀÀÀ 20
5.1 Absolute Maximum Ratings ÀÀÀÀÀÀÀÀÀ 20
5.2 Capacitance ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21
5.3 Timing Nomenclature ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22
5.4 DC Characteristics (V CC e 3.3V g0.5V) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 25 5.5 DC Characteristics (V CC e 5.0V g0.5V) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 28
5.6 AC CharacteristicsÐRead Only
Operations ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 31
5.7 Power-Up and Reset Timings ÀÀÀÀÀÀÀ 35
5.8 AC Characteristics for
WEÝÐControlled Command Write Operations ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 36
5.9 AC Characteristics for
CEÝÐControlled Command Write Operations ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 39
5.10 AC Characteristics for
WEÝÐControlled Page Buffer Write Operations ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 42
5.11 AC Characteristics for
CEÝÐControlled Page Buffer Write Operations ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 44
5.12 Erase and Word/Byte Write
Performance ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 45
6.0 MECHANICAL SPECIFICATIONS ÀÀÀÀ 47
DEVICE NOMENCLATURE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 48 ADDITIONAL INFORMATION ÀÀÀÀÀÀÀÀÀÀÀÀ 48 DATA SHEET REVISION HISTORY ÀÀÀÀÀÀ 48
VS28F016SV, MS28F016SV FlashFile TM Memory
1.0 INTRODUCTION
The documentation of the Intel VS/MS28F016SV memory device includes this data sheet, a detailed user’s manual, and a number of application notes, all of which are referenced at the end of this data sheet. The data sheet is intended to give an overview of the chip feature-set and of the operating AC/DC specifications. The 28F016SA (compatible with VS/MS28F016SV) User’s Manual provides com- plete descriptions of the user modes, system inter- face examples and detailed descriptions of all princi- ples of operation. It also contains the full list of software algorithm flowcharts, and a brief section on compatibility with the Intel VE28F008 and M28F008.
1.1 Enhanced Features
The VS/MS28F016SV is backwards compatible with the VE28F008 and M28F008 and offers the follow- ing enhancements: # SmartVoltage Technology Ð Selectable 5.0V or 12.0V V PP # VPP Level Bit in Block Status Register # Additional RY/BY Ý Configuration Ð Pulse-On-Write/Erase # Additional Upload Device Information Command Feedback Ð Device Revision Number Ð Device Proliferation Code Ð Device Configuration Code # x8/x16 Architecture # Block Locking # 2 Page Buffers # Instruction Queuing
1.2 Product Overview
The VS/MS28F016SV is a high-performance, 16-Mbit (16,777,216-bit) block erasable, non-volatile random access memory, organized as either 1 Mword x 16 or 2 Mbyte x 8. The VS/MS28F016SV includes thirty-two 64-KB (65,536 byte) blocks or thirty-two 32-KW (32,768 word) blocks. A chip mem- ory map is shown in Figure 3. The implementation of a new architecture, with many enhanced features, will improve the device op- erating characteristics and result in greater product reliability and ease of use. The VS/MS28F016SV incorporates SmartVoltage technology, providing V CC operation at both 3.3V and 5.0V and program and erase capability at V PP e 12.0V or 5.0V. Operating at V CC e 3.3V, the VS/MS28F016SV consumes approximately one-half the power consumption at 5.0V V CC, while 5.0V V CC provides highest read performance capability. V PP e 5.0V operation eliminates the need for a separate 12.0V converter, while V PP e 12.0V maximizes write/erase performance. In addition to the flexible program and erase voltages, the dedicated V PP gives complete code protection with V PP s VPPLK. Depending on system design specifications, the VS/MS28F016SV is capable of supporting Ð 80 ns access times with a V CC of 5.0V g5% and loading of 30 pF Ð 85 ns access times with a V CC of 5.0V g10% and loading of 100 pF Ð 120 ns access times with a V CC of 3.3V g5% and loading of 50 pF A 3/5 Ý input pin configures the device’s internal cir- cuitry for optimal 3.3V or 5.0V Read/Write operation. A Command User Interface (CUI) serves as the sys- tem interface between the microprocessor or micro- controller and the internal memory operation. Internal Algorithm Automation allows Byte/Word Writes and Block Erase operations to be executed using a Two-Write command sequence to the CUI in the same way as the VE28F008 or M28F008 8-Mbit FlashFile memory. A super-set of commands has been added to the basic VE28F008 or M28F008 command-set to achieve higher write performance and provide addi- tional capabilities. These new commands and fea- tures include: # Page Buffer Writes to Flash # Command Queuing Capability # Automatic Data Writes during Erase # Software Locking of Memory Blocks # Two-Byte Successive Writes in 8-bit Systems # Erase All Unlocked Blocks
VS28F016SV, MS28F016SV FlashFile TM Memory Writing of memory data is performed in either byte or word increments typically within 6 msec (12.0V V PP) b a 33% improvement over the VE28F008 or M28F008. A Block Erase operation erases one of the 32 blocks in about 1.0 sec (12.0V V PP), indepen- dent of the other blocks, which is about a 65% im- provement over the VE28F008 or M28F008. Each block can be written and erased a minimum of 100,000 cycles. Systems can achieve one million Block Erase Cycles by providing wear-leveling algo- rithms and graceful block retirement. These tech- niques have already been employed in many flash file systems and hard disk drive designs. The VS/MS28F016SV incorporates two Page Buff- ers of 256 bytes (128 words) each to allow page data writes. This feature can improve a system write performance by up to 4.8 times over previous flash memory devices, which have no Page Buffers. All operations are started by a sequence of Write commands to the device. Three Status Registers (described in detail later in this data sheet) and a RY/BY Ý output pin provide information on the prog- ress of the requested operation. While the VE28F008 or M28F008 requires an opera- tion to complete before the next operation can be requested, the VS/MS28F016SV allows queuing of the next operation while the memory executes the current operation. This eliminates system overhead when writing several bytes in a row to the array or erasing several blocks at the same time. The VS/MS28F016SV can also perform Write operations to one block of memory while performing Erase of another block. The VS/MS28F016SV provides selectable block locking to protect code or data such as Device Driv- ers, PCMCIA card information, ROM-Executable O/S or Application Code. Each block has an associ- ated non-volatile lock-bit which determines the lock status of the block. In addition, the VS/MS28F016SV has a master Write Protect pin (WP Ý) which prevents any modifications to memory blocks whose lock-bits are set. The VS/MS28F016SV contains three types of Status Registers to accomplish various functions: # A Compatible Status Register (CSR) which is 100% compatible with the VE28F008 or M28F008 FlashFile memory Status Register. The CSR, when used alone, provides a straightfor- ward upgrade capability to the VS/MS28F016SV from a VE28F008- or M28F008-based design. # A Global Status Register (GSR) which informs the system of command Queue status, Page Buffer status, and overall Write State Machine (WSM) status. # 32 Block Status Registers (BSRs) which provide block-specific status information such as the block lock-bit status. The GSR and BSR memory maps for Byte-Wide and Word-Wide modes are shown in Figures 4 and 5. The VS/MS28F016SV incorporates an open drain RY/BY Ý output pin. This feature allows the user to OR-tie many RY/BY Ý pins together in a multiple memory configuration such as a Resident Flash Ar- ray. Other configurations of the RY/BY Ý pin are en- abled via special CUI commands and are described in detail in the 16-Mbit Flash Product Family User’s Manual. The VS/MS28F016SV’s Upload Device Information command is enhanced compared to the VE28F008 or M28F008, providing access to additional device information. This command uploads the Device Re- vision Number, Device Proliferation Code and De- vice Configuration Code. The Device Proliferation Code for the VS/MS28F016SV is 01H, and the De- vice Configuration Code identifies the current RY/BY Ý configuration. Section 4.4 documents the exact page buffer address locations for all uploaded information. A subsequent Page Buffer Swap and Page Buffer Read command sequence is necessary to read the correct device information. The VS/MS28F016SV also incorporates a dual chip- enable function with two input pins, CE 0Ý and CE1Ý. These pins have exactly the same functional- ity as the regular chip-enable pin, CE Ý,o nt h e VE28F008 or M28F008. For minimum chip designs, CE 1Ý may be tied to ground and system logic may use CE 0Ý as the chip enable input. The VS/MS28F016SV uses the logical combination of these two signals to enable or disable the entire chip. Both CE 0Ý and CE 1Ý must be active low to enable the device. If either one becomes inactive, the chip will be disabled. This feature, along with the open drain RY/BY Ý pin, allows the system designer to reduce the number of control pins used in a large array of 16-Mbit devices. The BYTE Ý pin allows either x8 or x16 read/writes to the VS/MS28F016SV. BYTE Ý at logic low se- lects 8-bit mode with address A 0 selecting between low byte and high byte. On the other hand, BYTE Ý
VS28F016SV, MS28F016SV FlashFile TM Memory at logic high enables 16-bit operation with address A1 becoming the lowest order address and address A0 is not used (don’t care). A device block diagram is shown in Figure 1. The VS/MS28F016SV is specified for a maximum access time of 80 ns (t ACC) at 5.0V operation (4.75V to 5.25V) in either the SE1 or SE2 grades. A corre- sponding maximum access time of 120 ns at 3.3V (3.15V to 3.45V) is achieved for reduced power con- sumption applications. The VS/MS28F016SV incorporates an Automatic Power Saving (APS) feature which substantially re- duces the active current when the device is in static mode of operation (addresses not switching). In APS mode, the typical I CC current is 1 mA at 5.0V (0.8 mA at 3.3V). A deep power-down mode of operation is invoked when the RP Ý (called PWD Ý on the VE28F008 or M28F008) pin transitions low. This mode brings the device power consumption to less than 30.0 mA, typ- ically, and provides additional write protection by acting as a device reset pin during power transitions. A reset time of 500 ns (5.0V V CC operation) is re- quired from RP Ý switching high until outputs are again valid. In the Deep Power-Down state, the WSM is reset (any current operation will abort) and the CSR, GSR and BSR registers are cleared. A CMOS standby mode of operation is enabled when either CE 0Ý or CE 1Ý transitions high and RPÝ stays high with all input control pins at CMOS levels. In this mode, the device typically draws an I CC standby current of 70 mAa t5 VV CC.
2.0 DEVICE PINOUT
The VS/MS28F016SV 56L-SSOP pinout configura- tion is shown in Figure 2.
Figure 1. Block Diagram
VS28F016SV, MS28F016SV FlashFile TM Memory
2.1 Lead Descriptions
Symbol Type Name and Function A0 INPUT BYTE-SELECT ADDRESS: Selects between high and low byte when device is in x8 mode. This address is latched in x8 Data Writes. Not used in x16 mode (i.e., the A 0 input buffer is turned off when BYTE Ý is high). A1 -A 15 INPUT WORD-SELECT ADDRESSES: Select a word within one 64-Kbyte block. A 6-15 selects 1 of 1024 rows, and A 1-5 selects 16 of 512 columns. These addresses are latched during Data Writes. A16 -A 20 INPUT BLOCK-SELECT ADDRESSES: Select 1 of 32 Erase blocks. These addresses are latched during Data Writes, Erase and Lock-Block operations. DQ0 -D Q 7 INPUT/OUTPUT LOW-BYTE DATA BUS: Inputs data and commands during CUI write cycles. Outputs array, buffer, identifier or status data in the appropriate read mode. Floated when the chip is de-selected or the outputs are disabled. DQ8 -D Q 15 INPUT/OUTPUT HIGH-BYTE DATA BUS: Inputs data during x16 Data-Write operations. Outputs array, buffer or identifier data in the appropriate read mode; not used for Status Register reads. Floated when the chip is de-selected or the outputs are disabled. CE0Ý,C E 1Ý INPUT CHIP ENABLE INPUTS: Activate the device’s control logic, input buffers, decoders and sense amplifiers. With either CE 0Ý or CE 1Ý high, the device is de-selected and power consumption reduces to standby levels upon completion of any current Data-Write or Erase operations. Both CE 0Ý,C E 1Ý must be low to select the device. All timing specifications are the same for both signals. Device Selection occurs with the latter falling edge of CE 0Ý or CE 1Ý. The first rising edge of CE 0Ý or CE 1Ý disables the device. RPÝ INPUT RESET/POWER-DOWN: RPÝ low places the device in a Deep Power-Down state. All circuits that consume static power, even those circuits enabled in standby mode, are turned off. When returning from Deep Power-Down, a recovery time of t PHQV at 5.0V V CC is required to allow these circuits to power-up. When RP Ý goes low, any current or pending WSM operation(s) are terminated, and the device is reset. All Status Registers return to ready (with all status flags cleared). Exit from Deep Power-Down places the device in read array mode. OEÝ INPUT OUTPUT ENABLE: Gates device data through the output buffers when low. The outputs float to tri-state off when OE Ý is high. NOTE: CExÝ overrides OE Ý, and OE Ý overrides WE Ý. WEÝ INPUT WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue Registers and Address Queue Latches. WE Ý is active low, and latches both address and data (command or array) on its rising edge. Page Buffer addresses are latched on the falling edge of WE
VS28F016SV, MS28F016SV FlashFile TM Memory
2.1 Lead Descriptions (Continued)
Symbol Type Name and Function RY/BYÝ OPEN DRAIN READY/BUSY: Indicates status of the internal WSM. When low, it indicates that the WSM is busy performing an operation. RY/BY Ý floating indicatesOUTPUT that the WSM is ready for new operations (or WSM has completed all pending operations), or erase is suspended, or the device is in deep power- down mode. This output is always active (i.e., not floated to tri-state off when OE Ý or CE 0Ý,C E 1Ý are high), except if a RY/BY Ý Pin Disable command is issued. WPÝ INPUT WRITE PROTECT: Erase blocks can be locked by writing a nonvolatile lock- bit for each block. When WP Ý is low, those locked blocks as reflected by the Block-Lock Status bits (BSR.6), are protected from inadvertent data writes or erases. When WP Ý is high, all blocks can be written or erased regardless of the state ot the lock-bits. The WP Ý input buffer is disabled when RP Ý transitions low (deep power-down mode). BYTEÝ INPUT BYTE ENABLE: BYTEÝ low places device in x8 mode. All data is then input or output on DQ 0–7 , and DQ 8–15 float. Address A 0 selects between the high and low byte. BYTE Ý high places the device in x16 mode, and turns off the A0 input buffer. Address A 1, then becomes the lowest order address. 3/5Ý INPUT 3.3/5.0 VOLT SELECT: 3/5Ý high configures internal circuits for 3.3V operation. 3/5 Ý low configures internal circuits for 5.0V operation. NOTE: Reading the array with 3/5 Ý high in a 5.0V system could damage the device. Reference the power-up and reset timings (Section 5.7) for 3/5 Ý switching delay to valid data. VPP SUPPLY WRITE/ERASE POWER SUPPLY (12.0V g0.6V, 5.0V g0.5V): For erasing memory array blocks or writing words/bytes/pages into the flash array. V PP e 5.0V g0.5V eliminates the need for a 12V converter, while connection to 1 2.0V g0.6V maximizes Write/Erase Performance. NOTE: Successful completion of write and erase attempts is inhibited with V PP at or below 1.5V. Write and erase attempts with V PP between 1.5V and 4.5V, between 5.5V and 11.4V, and above 12.6V produce spurious results and should not be attempted. switch 3.3V to 5.0V (or vice versa), first ramp V CC down to GND, and then power to the new V CC voltage. Do not leave any power pins floating. GND SUPPLY GROUND FOR ALL INTERNAL CIRCUITRY: Do not leave any ground pins floating. NC NO CONNECT: Lead may be driven or left floating.
56-Lead SSOP Mechanical Diagrams and dimensions are shown at the end of this data sheet. Figure 2. SSOP Pinout Configuration
3.0 MEMORY MAPS
Figure 3. VS/MS28F016SV Memory Maps (Byte-Wide and Word-Wide Modes)
3.1 Extended Status Registers Memory Map
Figure 4. Extended Status Register Memory Map Figure 5. Extended Status Register Memory Map
VS28F016SV, MS28F016SV FlashFile TM Memory
4.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS
4.1 Bus Operations for Word-Wide Mode (BYTE Ý e VIH)
Mode Notes RP Ý CE1Ý CE0Ý OEÝ WEÝ A1 DQ0-15 RY/BYÝ Read 1,2,7 V IH VIL VIL VIL VIH XD OUT X Output Disable 1,6,7 V IH VIL VIL VIH VIH X High Z X Standby 1,6,7 V IH VIL VIH X X X High Z X VIH VIL VIH VIH Deep Power-Down 1,3 V IL X X X X X High Z V OH Manufacturer ID 4 V IH VIL VIL VIL VIH VIL 0089H V OH Device ID 4 V IH VIL VIL VIL VIH VIH 66A0H V OH Write 1,5,6 V IH VIL VIL VIH VIL XD IN X
4.2 Bus Operations for Byte-Wide Mode (BYTE Ý e VIL)
Mode Notes RP Ý CE1Ý CE0Ý OEÝ WEÝ A0 DQ0-7 RY/BYÝ Read 1,2,7 V IH VIL VIL VIL VIH XD OUT X Output Disable 1,6,7 V IH VIL VIL VIH VIH X High Z X Standby 1,6,7 V IH VIL VIH X X X High Z X VIH VIL VIH VIH Deep Power-Down 1,3 V IL X X X X X High Z V OH Manufacturer ID 4 V IH VIL VIL VIL VIH VIL 89H V OH Device ID 4 V IH VIL VIL VIL VIH VIH A0H V OH Write 1,5,6 V IH VIL VIL VIH VIL XD IN X NOTES: 1. X can be V IH or V IL for address or control pins except for RY/BY Ý, which is either V OL or V OH. 2. RY/BY Ý output is open drain. When the WSM is ready, Erase is suspended or the device is in deep power-down mode. RY/BYÝ will be at V OH if it is tied to V CC through a resistor. RY/BY Ý at V OH is independent of OE Ý while a WSM operation is in progress. 3. RP Ý at GND g0.2V ensures the lowest deep power-down current. 4. A 0 and A 1 at V IL provide device manufacturer codes in x8 and x16 modes respectively. A 0 and A 1 at V IH provide device ID codes in x8 and x16 modes respectively. All other addresses are set to zero. 5. Commands for Erase, Data Write, or Lock-Block operations can only be completed successfully when V PP e VPPH1or VPP e VPPH2. 6. While the WSM is running, RY/BY Ý in level-mode (default) stays at V OL until all operations are complete. RY/BY Ý goes to V OH when the WSM is not busy or in erase suspend mode. 7. RY/BY Ý may be at V OL while the WSM is busy performing various operations. For example, a Status Register read during a Write operation.
VS28F016SV, MS28F016SV FlashFile TM Memory
4.3 VE28F008 and M28F008 Compatible Mode Command Bus Definitions
First Bus Cycle Second Bus Cycle Oper Addr Data (4) Oper Addr Data (4) Read Array Write X xxFFH Read AA AD Intelligent Identiier 1 Write X xx90H Read IA ID Read Compatible Status Register 2 Write X xx70H Read X CSRD Clear Status Register 3 Write X xx50H Word/Byte Write Write X xx40H Write WA WD Alternate Word/Byte Write Write X xx10H Write WA WD Block Erase/Confirm Write X xx20H Write BA xxD0H Erase Suspend/Resume Write X xxB0H Write X xxD0H ADDRESS DATA AA e Array Address AD e Array Data BA e Block Address CSRD e CSR Data IA e ldentitier Address ID e Identifier Data WA e Write Address WD e Write Data X e Don’t Care NOTES: 1. Following the Intelligent Identifier command, two Read operations access the manutacturer and device signature codes. 2. The CSR is automatically available after device enters data write, erase, or suspend operations. tions. 4. The upper byte of the data bus (DQ 8–15 ) during command writes is a ‘‘Don’t Care’’ in x16 operation of the device.
VS28F016SV, MS28F016SV FlashFile TM Memory
4.4 VS/MS28F016SVÐPerformance Enhancement Command Bus Definitions
First Bus Cycle Second Bus Cycle Third Bus Cycle Oper Addr Data (13) Oper Addr Data (13) Oper Addr Data Read Extended 1 Write X xx71H Read RA GSRD Status Register BSRD Page Buffer Swap 7 Write X xx72H Read Page Buffer Write X xx75H Read PA PD Single Load to Write X xx74H Write PA PD Page Buffer Sequential Load to x8 4,6,10 Write X xxE0H Write X BCL Write X BCH Page Buffer x16 4,5,6,10 Write X xxE0H Write X WCL Write X WCH Page Buffer Write x8 3,4,9,10 Write X xx0CH Write A 0 BC(L,H) Write WA BC(H,L) to Flash x16 4,5,10 Write X xx0CH Write X WCL Write WA WCH Two-Byte Write x8 3 Write X xxFBH Write A 0 WD(L,H) Write WA WD(H,L) Lock Block/ Write X xx77H Write BA xxD0H Confirm Upload Status 2 Write X xx97H Write X xxD0H Bits/Confirm Upload Device 11 Write X xx99H Write X xxD0H Information/ Confirm Erase All Unlocked Write X xxA7H Write X xxD0H Blocks/Confirm RY/BYÝ Enable to 8 Write X xx96H Write X xx01H Level-Mode RY/BYÝ Pulse- 8 Write X xx96H Write X xx02H On-Write RY/BYÝ Pulse- 8 Write X xx96H Write X xx03H On-Erase RY/BYÝ Disable 8 Write X xx96H Write X xx04H RY/BYÝ Pulse- 8 Write X xx96H Write X xx05H On-Write/Erase Sleep 12 Write X xxF0H Abort Write X xx80H ADDRESS BA e Block Address PA e Page Butter Address RA e Extended Register Address WA e Write Address X e Don’t Care DATA AD e Array Data PD e Page Buffer Data BSRD e BSR Data GSRD e GSR Data WC (L,H) e Word Count (Low, High) BC (L,H) e Byte Count (Low, High) WD (L,H) e Write Data (Low, High)
VS28F016SV, MS28F016SV FlashFile TM Memory NOTES: 1. RA can be the GSR address or any BSR address. See Figures 4 and 5 for Extended Status Register memory maps. 2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the actual lock-bit status. 3. A 0 is automatically complemented to load second byte of data. BYTE Ý must be at V IL.A 0 value determines which WD/BC is supplied first: A 0 e 0 looks at the WDL/BCL, A 0 e 1 looks at the WDH/BCH. 4. BCH/WCH must be at 00H for this product because of the 256-byte (128-word) Page Buffer size, and to avoid writing the Page Buffer contents to more than one 256-byte segment within an array block. They are simply shown for future Page Buffer expandability. 5. In x16 mode, only the lower byte DQ 0-7 is used for WCL and WCH. The upper byte DQ 8-15 is a don’t care. 6. PA and PD (whose count is given in cycles 2 and 3) are supplied starting in the fourth cycle, which is not shown. 7. This command allows the user to swap between available Page Buffers (0 or 1). 8. These commands reconfigure RY/BY Ý output to one of two pulse-modes or enable and disable the RY/BY Ý function. 9. Write address, WA, is the Destination address in the flash array which must match the Source address in the Page Buffer. Refer to the 16-Mbit Flash Product Family User’s Manual. 10. BCL e 00H corresponds to a byte count of 1. Similarly, WCL e 00H corresponds to a word count of 1. 11. After writing the Upload Device Information command and the Confirm command, the following information is output at Page Buffer addresses specified below: Address Information 06H, 07H (Byte Mode) Device Revision Number 03H (Word Mode) Device Revision Number 1EH (Byte Mode) Device Configuration Code 0FH (DQ 0–7 ) (Word Mode) Device Configuration Code 1FH (Byte Mode) Device Proliferation Code (01H) 0FH (DQ 8–15 ) (Word Mode) Device Proliferation Code (01H) A page buffer swap followed by a page buffer read sequence is necessary to access this information. The contents of all other Page Buffer locations, after the Upload Device Information command is written, are reserved for future imple- mentation by Intel Corporation. See Section 4.8 for a description of the Device Configuration Code. This code also corresponds to data written to the 28F016SV after writing the RY/BY Ý Reconfiguration command. 12. To ensure that the 28F0165V’s power consumption during Sleep Mode reaches the deep power-down current level, the system also needs to de-select the chip by taking either or both CE 0Ý or CE 1Ý high. 13. The upper byte of the data bus (DQ 8–15 ) during command wntes is a Don’t Care in x16 operation of the device.
VS28F016SV, MS28F016SV FlashFile TM Memory
4.5 Compatible Status Register
WSMS ESS ES DWS VPPS R R R 76 5 43 2 1 0 NOTES: CSR.7 e WRITE STATE MACHINE STATUS RY/BY Ý output or WSMS bit must be checked to determine completion of an operation (Erase, Erase1 e Ready Suspend, or Data Write) before the appropriate Status bit0 e Busy (ESS, ES or DWS) is checked for success. CSR.6 e ERASE-SUSPEND STATUS 1 e Erase Suspended 0 e Erase In Progress/Completed CSR.5 e ERASE STATUS If DWS and ES are set to ‘‘1’’ during an erase attempt, an improper command sequence was entered. Clear the1 e Error In Block Erasure CSR and attempt the operation again.0 e Successful Block Erase CSR.4 e DATA-WRITE STATUS 1 e Error in Data Write 0 e Data Write Successful CSR.3 e VPP STATUS The VPPS bit, unlike an A/D converter, does not provide continuous indication of V PP level. The WSM interrogates1 e VPP Error Detect, Operation Abort VPP’s level only after the Data-Write or Erase command0 e VPP OK sequences have been entered, and informs the system if VPP has not been switched on. VPPS is not guaranteed to report accurate feedback between V PPLK(max) and VPPH1(min) and between V PPH1(max) and V PPH2(min) and above V PPH2(max). CSR.2-0 e RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use; mask them out when polling the CSR.
VS28F016SV, MS28F016SV FlashFile TM Memory
4.6 Global Status Register
WSMS OSS DOS DSS QS PBAS PBS PBSS 76 5 4 3 2 1 0 NOTES: GSR.7 e WRITE STATE MACHINE STATUS [1] RY/BYÝ output or WSMS bit must be checked to determine completion of an operation (Block Lock,1 e Ready Suspend, any RY/BY Ý reconfiguration, Upload Status0 e Busy Bits, Erase or Data Write) before the appropriate Status bit (OSS or DOS) is checked for success. GSR.6 e OPERATION SUSPEND STATUS 1 e Operation Suspended 0 e Operation in Progress/Completed GSR.5 e DEVICE OPERATION STATUS 1 e Operation Unsuccessful 0 e Operation Successful or Currently Running GSR.4 e DEVICE SLEEP STATUS 1 e Device in Sleep 0 e Device Not in Sleep MATRIX 5/4 00 e Operation Successful or Currently If operation currently running, then GSR.7 e 0. Running 01 e Device in Sleep mode or Pending If device pending sleep, then GSR.7 e 0. Sleep 10 e Operation Unsuccessful 11 e Operation Unsuccessful or Aborted Operation aborted: Unsuccessful due to Abort command. GSR.3 e QUEUE STATUS 1 e Queue Full 0 e Queue Available GSR.2 e PAGE BUFFER AVAILABLE STATUS 1 e One or Two Page Buffers Available The device contains two Page Buffers. 0 e No Page Buffer Available GSR.1 e PAGE BUFFER STATUS 1 e Selected Page Buffer Ready 0 e Selected Page Buffer Busy Selected Page Buffer is currently busy with WSM operation GSR.0 e PAGE BUFFER SELECT STATUS 1 e Page Buffer 1 Selected 0 e Page Buffer 0 Selected NOTE: 1. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block. GSR.7 provides indication when all queued operations are completed.
VS28F016SV, MS28F016SV FlashFile TM Memory
4.7 Block Status Register
BS BLS BOS BOAS QS VPPS VPPL R 76 5 4 3 2 10 NOTES: BSR.7 e BLOCK STATUS [1] RY/BYÝ output or BS bit must be checked to determine completion of an operation (Block Lock,1 e Ready Suspend, Erase or Data Write) before the appropriate0 e Busy Status bits (BOS, BLS) is checked for success. BSR.6 e BLOCK LOCK STATUS 1 e Block Unlocked for Write/Erase 0 e Block Locked for Write/Erase BSR.5 e BLOCK OPERATION STATUS 1 e Operation Unsuccessful 0 e Operation Successful or Currently Running BSR.4 e BLOCK OPERATION ABORT STATUS 1 e Operation Aborted The BOAS bit will not be set until BSR.7 e 1. 0 e Operation Not Aborted MATRIX 5/4 00 e Operation Successful or Currently Running e Not a Valid Combination 10 e Operation Unsuccessful 11 e Operation Aborted Operation halted via Abort command. BSR.3 e QUEUE STATUS 1 e Queue Full 0 e Queue Available BSR.2 e VPP STATUS 1 e VPP Error Detect, Operation Abort 0 e VPP OK BSR.1 e VPP LEVEL BSR.1 is not guaranteed to report accurate feedback between the V PPH1 and V PPH2 voltage ranges. Writes1 e VPP Detected at 5.0V g10% and erases with V PP between V PPLK(max) and V PPH10 e VPP Detected at 12.0V g5% (min), between V PPH1(max) and V PPH2(min), and above V PPH2(max) produce spurious results and should not be attempted. BSR.1 was a RESERVED bit on the 28F016SA. BSR.0 e RESERVED FOR FUTURE ENHANCEMENTS This bit is reserved for future use; mask it out when polling the BSRs. NOTE: 1. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block. GSR.7 provides indication when all queued operations are completed.
VS28F016SV, MS28F016SV FlashFile TM Memory
4.8 Device Configuration Code
NOTES: DCC.2-DCC.0 e RY/BYÝ CONFIGURATION (RB2-RB0) Undocumented combinations of RB2-RB0 are reserved by Intel Corporation for future001 e Level Mode (Default) implementations and should not be used.010 e Pulse-On-Write 011 e Pulse-On-Erase 100 e RY/BYÝ Disabled 101 e Pulse-On-Write/Erase DCC.7-DCC.3 e RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use; mask them out when reading the Device Configuration Code. Set these bits to ‘‘0’’ when writing the desired RY/BY Ý configuration to the device.
VS28F016SV, MS28F016SV FlashFile TM Memory
5.0 ELECTRICAL SPECIFICATIONS
5.1 Absolute Maximum Ratings *
ÐSE1 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b55§Ct o a125§C ÐSE2 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b40§Ct o a125§C Storage Temperature ÀÀÀÀÀÀÀÀÀÀÀÀ b65§ to a125§C NOTICE: This data sheet contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest data sheet be- fore finalizing a design. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. VCC e 3.3V g0.15V Systems (4) Sym Parameter Notes Min Max Units Test Conditions TCSE2 Operating Temperature, SE2 b40 a125 §C TCSE1 Operating Temperature, SE1 b55 a125 §C VCC VCC with Respect to GND 1 b0.2 7.0 V VPP VPP Supply Voltage with Respect to GND 1,2 b0.2 14.0 V V Voltage on any Pin (except V CC,VPP) with 1,5 b0.5 VCC VRespect to GND a0.5 I Current into any Non-Supply Pin 5 g30 mA IOUT Output Short Circuit Current 3 100 mA VCC e 5.0V g0.5V, V CC e 5.0V g0.25V Systems (4, 5) Sym Parameter Notes Min Max Units Test Conditions TCSE2 Operating Temperature, SE2 b40 a125 §C TCSE1 Operating Temperature, SE1 b55 a125 §C VCC VCC with Respect to GND 1 b0.2 7.0 V VPP VPP Supply Voltage with Respect to GND 1,2 b0.2 14.0 V V Voltage on any Pin (except V CC,VPP) with 1,5 b2.0 7.0 VRespect to GND I Current into any Non-Supply Pin 5 g30 mA IOUT Output Short Circuit Current 3 100 mA NOTES: 1. Minimum DC voltage is b0.5V on input/output pins. During transitions, this level may undershoot to b2.0V for periods k20 ns. Maximum DC voltage on input/output pins is V CC a 0.5V which, during transitions, may overshoot to V CC a 2.0V for periods k20 ns. 2. Maximum DC voltage on V PP may overshoot to a14.0V for periods k20 ns. 3. Output shorted for no more than one second. No more than one output shorted at a time. 4. AC specifications are valid at both voltage ranges. See DC Characteristics tables for voltage range-specific specifications. 5. This specification also applies to pin marked ‘‘NC’’. 6. 5% V CC specifications refer to the VS/MS28F016SV-80 in its high speed test configuration.
VS28F016SV, MS28F016SV FlashFile TM Memory
5.2 Capacitance
For a 3.3V g0.15V System: Sym Parameter Notes Typ Max Units Test Conditions CIN Capacitance Looking into an 1 6 8 pF T A e 25§C, f e 1.0 MHz Address/Control Pin COUT Capacitance Looking into an 1 8 12 pF T A e 25§C, f e 1.0 MHz Output Pin CLOAD Load Capacitance Driven by 1,2 50 pF For V CC e 3.3V g0.15V Outputs for Timing Specifications Equivalent Load Timing Circuit 2.5 ns 50 X transmission line delay For a 5.0V System: Sym Parameter Notes Typ Max Units Test Conditions CIN Capacitance Looking into an 1 6 8 pF T Ae25§C, f e 1.0 MHz Address/Control Pin COUT Capacitance Looking into an 1 8 12 pF T A e 25§C, f e 1.0 MHz Output Pin CLOAD Load Capacitance Driven by 1,2 100 pF For V CC e 5.0V g0.5V Outputs for Timing Specifications 30 pF For V CC e 5.0V g0.25V Equivalent Testing Load Circuit for 2.5 ns 25 X transmission line VCC g10% delay Equivalent Testing Load Circuit for 2.5 ns 85 X transmission line VCC g5% delay NOTES: 1. Sampled, not 100% tested. Guaranteed by design. 2. To obtain iBIS models for the VS/MS28F016SV, please contact your local Intel/Distribution Sales Office.
VS28F016SV, MS28F016SV FlashFile TM Memory
5.3 Timing Nomenclature
All 3.3V system timings are measured from where signals cross 1.5V. For 5.0V systems use the standard JEDEC cross point definitions. Each timing parameter consists of 5 characters. Some common examples are defined as follows: tCE tELQV time(t) from CE Ý (E) going low (L) to the outputs (Q) becoming valid (V) tOE tGLQV time(t) from OE Ý (G) going low (L) to the outputs (Q) becoming valid (V) tACC tAVQV time(t) from address (A) valid (V) to the outputs (Q) becoming valid (V) tAS tAVWH time(t) from address (A) valid (V) to WEÝ (W) going high (H) tDH tWHDX time(t) from WE Ý (W) going high (H) to when the data (D) can become un- defined (X) Pin Characters Pin States A Address Inputs H High D Data Inputs L Low Q Data Outputs V Valid EC E Ý (Chip Enable) X Driven, but not Necessarily Valid F BYTE Ý (Byte Enable) Z High Impedance GO E Ý (Output Enable) WW E Ý (Write Enable) PR P Ý (Deep Power-Down Pin) R RY/BY Ý (Ready Busy) V Any Voltage Level Y 3/5 Ý Pin 5V V CC at 4.5V Minimum 3V V CC at 3.15V Minimum
VS28F016SV, MS28F016SV FlashFile TM Memory
5.4 DC Characteristics
VCC e 3.3V g0.15V, T CSE2 eb 40§Ct o a125§C, T CSE1 eb 55§Ct o a125§C Sym Parameter Notes Min Max Units Test Conditions ILI Input Load Current 1 g1 mAV CC e VCC Max, VIN e VCC or GND ILO Output Leakage Current 1 g10 mAV CC e VCC Max, VOUT e VCC or GND ICCS VCC Standby 1,5 130 mAV CC e VCC Max, Current CE 0Ý,C E 1Ý,R P Ý e VCC g0.2V BYTEÝ,W P Ý, 3/5 Ý e VCC g0.2V or GND g0.2V 4m A V CC e VCC Max, CE0Ý,C E 1Ý,R P Ý e VIH BYTEÝ,W P Ý, 3/5 Ý e VIH or V IL ICCD VCC Deep Power- 1 50 mAR P Ý e GND g0.2V Down Current BYTE Ý e VCC g0.2V or GND g0.2V ICCR1V CC Read Current 1,4,5 60 mA V CC e VCC Max CMOS: CE 0Ý,C E 1Ý e GND g0.2V BYTEÝ e GND g0.2V or VCC g0.2V Inputs e GND g0.2V or VCC g0.2V TTL: CE 0Ý,C E 1Ý e VIL, BYTEÝ e VIL or V IH INPUTS e VIL or V IH, f e 8 MHz, I OUT e 0m A ICCR2V CC Read Current 1,4,5,6 40 mA V CC e VCC Max CMOS: CE 0Ý,C E 1Ý e GND g0.2V BYTEÝ e GND g0.2V or VCC g0.2V Inputs e GND g0.2V or VCC g0.2V TTL: CE 0Ý,C E 1Ý e VIL, BYTEÝ e VIL or V IH INPUTS e VIL or V IH, f e 4 MHz, I OUT e 0m A
VS28F016SV, MS28F016SV FlashFile TM Memory
5.4 DC Characteristics (Continued)
VCC e 3.3V g0.3V, T CSE2 eb 40§Ct o a125§C, T CSE1 eb 55§Ct o a125§C Sym Parameter Notes Min Max Units Test Conditions ICCW VCC Write Current 1,6 12 mA Word/Byte Write in Progress VPP e 12.0V g5% 17 mA Word/Byte Write in Progress VPP e 5.0V g10% ICCE VCC Block Erase 1,6 12 mA Block Erase in Progress Current V PP e 12.0V g5% 17 mA Block Erase in Progress VPP e 5.0V g10% ICCES VCC Erase 1,2 6 mA CE 0Ý,C E 1Ý e VIH Suspend Current Block Erase Suspended IPPS VPP Standby/Read 1 g100 mAV PP s VCC IPPR Current 200 mAV PP l VCC IPPD VPP Deep Power- 1 50 mAR P Ý e GND g0.2V Down Current IPPW VPP Write Current 1 15 mA V PP e 12.0V g5% Word/Byte Write in Progress 25 mA V PP e 5.0V g10% Word/Byte Write in Progress IPPE VPP Erase Current 1 10 mA V PP e 12.0V g5% Block Erase in Progress 20 mA V PP e 5.0V g10% Block Erase in Progress IPPES VPP Erase 1 200 mAV PP e VPPH1 or VPPH2, Suspend Current Block Erase Suspended VIL Input Low Voltage b0.3 0.8 V VIH Input High Voltage V CC 2.0 a V 0.3 VOL Output Low 0.4 V V CC e VCC Min and Voltage I OLe 4m A
VS28F016SV, MS28F016SV FlashFile TM Memory VCC e 3.3V g0.15V, T CSE2 eb 40§Ct o a125§C, T CSE1 eb 55§Ct o a125§C Sym Parameter Notes Min Max Units Test Conditions VOH1 Output High 2.4 V I OHeb 2.0 mA Voltage V CC e VCC Min VOH2V CCb0.2 V I OH eb 100 mA VCC e VCC Min VPPLK VPP Erase/Write 3 0.0 1.8 V Lock Voltage VPPH1 VPP during 3 4.5 5.5 V Write/Erase Operations VPPH2 VPP during 3 11.4 12.6 V Write/Erase Operations VLKO VCC Erase/Write 1.8 V Lock Voltage NOTES: 1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (package and speeds). 2. I CCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of I CCES and I CCR. 3. Block Erases, Word/Byte Writes and Lock Block operations are inhibited when V PP s VPPLK and not guaranteed in the ranges between V PPLK(max) and V PPH1(min), between V PPH1(max) and V PPH2(min) and above V PPH2(max). 4. Automatic Power Savings (APS) reduces I CCR to less than 3 mA in static operation. 6. Sampled, but not 100% tested. Guaranteed by design.
VS28F016SV, MS28F016SV FlashFile TM Memory
5.5 DC Characteristics
VCC e 5.0V g 0.5V, 5.0V g 0.25V, T CSE2 eb 40§Ct o a125§C, T CSE1 eb 55§Ct o a125§C Sym Parameter Notes Min Max Units Test Conditions ILI Input Load Current 1 g1 mAV CC e VCC Max VINe VCC or GND ILO Output Leakage 1 g10 mAV CCe VCC Max Current V IN e VCCor GND ICCS VCC Standby 1,5 130 mAV CCe VCC Max Current CE 0Ý,C E 1Ý,R P Ý e VCCg 0.2V BYTEÝ,W P Ý e VCCg 0.2V or GND g0.2V 4m A V CCe VCC Max CE0Ý,C E 1Ý,R P Ý e VIH BYTEÝ,W P Ý, 3/5 Ý e VIH or V IL ICCD VCC Deep Power- 1 50 mAR P Ý e GND g0.2V Down Current BYTE Ý e VCC g0.2V or GND g0.2V ICCR1V CC Read Current 1,4,5 135 mA V CC e VCC Max, CMOS:CE0Ý,C E 1Ý e GND g 0.2V BYTEÝ e GND g0.2V or VCC g0.2V Inputs e GND g0.2V or VCC g0.2V TTL: CE 0Ý,C E 1Ý e VIL, BYTEÝ e VIL or V IH, Inputs e VIL or V IH, f e 10 MHz, I OUT e 0m A ICCR2V CC Read Current 1,4,5,6 90 mA V CC e VCC Max, CMOS:CE0Ý,C E 1Ý e GND g 0.2V BYTEÝ e GND g0.2V or VCC g0.2V Inputs e GND g0.2V or VCC g0.2V TTL: CE 0Ý,C E 1Ý e VIL, BYTEÝ e VIL or V IH, Inputs e VIL or V IH, f e 5 MHz, I OUT e 0m A
VS28F016SV, MS28F016SV FlashFile TM Memory
5.5 DC Characteristics (Continued)
VCC e 5.0V g 0.5V, 5.0V g 0.25V, T CSE2 eb 40§Ct o a125§C, T CSE1 eb 55§Ct o a125§C Sym Parameter Notes Min Max Units Test Conditions ICCW VCC Write Current 1,6 35 mA Word/Byte in Progress VPP e 12.0V g5% 40 mA Word/Byte in Progress VPP e 5.0V g10% ICCE VCC Block Erase 1,6 25 mA Block Erase in Progress Current V PP e 12.0V g5% 30 mA Block Erase in Progress VPP e 5.0V g10% ICCES VCC Erase 1,2 10 mA CE 0Ý,C E 1Ý e VIH Suspend Current Block Erase Suspended IPPS VPP Standby/Read 1 g100 mAV PP s VCC IPPR Current 200 mAV PPl VCC IPPD VPP Deep Power- 1 50 mAR P Ý e GND g0.2V Down Current IPPW VPP Write Current 1,6 12 mA V PP e 12.0V g5% Word/Byte Write in Progress 22 mA V PP e 5.0V g10% Word/Byte Write in Progress IPPE VPP Block Erase 1,6 10 mA V PP e 12.0V g5% Current Block Erase in Progress 20 mA V PP e 5.0V g10% Block Erase in Progress IPPES VPP Erase 1 200 mAV PP e VPPH1 or V PPH2, Suspend Current Block Erase Suspended VIL Input Low Voltage 6 b0.5 0.8 V VIH Input High Voltage 6 2.0 V CC V a0.5
VS28F016SV, MS28F016SV FlashFile TM Memory VCC e 5.0V g 0.5V, 5.0V g 0.25V, T CSE2 eb 40§Ct o a125§C, T CSE1 eb 55§Ct o a125§C Sym Parameter Notes Min Max Units Test Conditions VOL Output Low 6 0.45 V V CCe VCC Min Voltage I OLe 5.8 mA VOH1 Output High 6 0.85 V I OHeb 2.5 mA Voltage V CC VCC e VCC Min VOH26 V CC IOHeb 100 mA b0.4 V CCe VCC Min VPPLK VPP Write/Erase 3,6 0.0 1.8 V Lock Voltage VPPH1 VPP during 4.5 5.5 V Write/Erase Operations VPPH2 VPP during 11.4 12.6 V Write/Erase Operations VLKO VCC Write/Erase 1.8 V Lock Voltage NOTES: 1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (package and speeds). 2. I CCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of I CCESand I CCR. 3. Block Erases, Word/Byte Writes and Lock Block operations are inhibited when V PP s VPPLK and not guaranteed in the ranges between V PPLK(max) and V PPH1(min), between V PPH1(max) and V PPH2(min) and above V PPH2(max). 4. Automatic Power Saving (APS) reduces I CCR to less than 1 mA in Static operation. 6. Sampled, not 100% tested. Guaranteed by design.
VS28F016SV, MS28F016SV FlashFile TM Memory
5.6 AC CharacteristicsÐRead Only Operations (1)
VCC e 3.3V g0.15V, T CSE2 eb 40§Ct o a125§C, T CSE1 eb 55§Ct o a125§C, Load e 50 pF Versions Units Sym Parameter Notes Min Max tAVAV Read Cycle Time 120 ns tAVQV Address to Output Delay (T ACC) 120 ns tELQV CEÝ to Output Delay (T CE) 2,7 120 ns tPHQV RPÝ High to Output Delay 620 ns tGLQV OEÝ to Output Delay (T OE) 2 45 ns tELQX CEÝ to Output in Low Z 3,7 0 ns tEHQZ CEÝ to Output in High Z 3,7 50 ns tGLQX OEÝ to Output in Low Z 3 0 ns tGHQZ OEÝ to Output in High Z 3 30 ns tOH Output Hold from Address, CE Ý or OE Ý 3,7 0 ns Change, Whichever Occurs First tFLQV BYTEÝ to Output Delay 3 120 ns tFHQV tFLQZ BYTEÝ Low to Output in High Z 3 30 ns tELFL CEÝ Low to BYTE Ý High or Low 3,7 5 ns tELFH Extended Status Register Reads Sym Parameter Notes Min Max Units tAVEL Address Setup to CE Ý Going Low 3,7,8,9 0 ns tAVGL Address Setup to OE Ý Going Low 3,7,9 0 ns
VS28F016SV, MS28F016SV FlashFile TM Memory
5.6 AC CharacteristicsÐRead Only Operations (1) (Continued)
VCC e 5.0V g0.25V, T CSE2 eb 40§Ct o a125§C, T CSE1 eb 55§Ct o a125§C, Load e 30 pF VCC e 5.0V g0.5V, T CSE2 eb 40§Ct o a125§C, T CSE1 eb 55§Ct o a125§C, Load e 100 pF Versions(4) VS/MS28F016SV-85 VS/MS28F016SV-85 VS/MS28F016SV-100 UnitVCC g5%(5) VCC g10%(6) VCC g 10% Sym Parameter Notes Min Max Min Max Min Max tAVAV Read Cycle Time 80 85 100 ns tAVQV Address to Output 80 85 100 ns Delay (T ACC) tELQV CEÝ to Output 2 80 85 100 ns Delay (T CE) tPHQV RPÝ to Output 400 480 480 ns Delay tGLQV OEÝ to Output 2 30 35 40 ns Delay (T OE) tELQX CEÝ to Output in 3 0 0 0 ns Low Z tEHQZ CEÝ to Output in 3 25 30 35 ns High Z tGLQX OEÝ to Output in 3 0 0 0 ns Low Z tGHQZ OEÝ to Output in 3 25 30 35 ns High Z tOH Output Hold from 3 0 0 0 ns Address, CE Ý or OEÝ Change, Whichever Occurs First tFLQV BYTEÝ to Output 3 80 85 100 ns DelaytFHQV tFLQZ BYTEÝ Low to 3 25 30 35 ns Output in High Z tELFL CEÝ Low to 3 5 5 5 ns BYTEÝ High ortELFH Low Extended Status Register Reads Sym Parameter Notes Min Max Min Max Min Max Unit tAVEL Address Setup to CE Ý Going 3,7,8,9 0 0 0 ns Low tAVGL Address Setup to OE Ý Going 3,7,9 0 0 0 ns Low
- See AC Input/Output Reference Waveforms for timing measurements, Figures 6 and 7.
Ý may be delayed up to t ELQV –tGLQV after the falling edge of CE Ý, without impacting t ELQV.
- Sampled, not 100% tested. Guaranteed by design.
- Device speeds are defined as:
- See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit.
- See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.
xÝ is defined as the latter of CE 0Ý or CE 1Ý going low, or the f.
- This timing parameter is used to latch the correct BSR data onto the outputs.
- The address setup requirement for Extended Status Register reads must only be met referenced to the falling edge of the
are activated after OE Ý, specification t AVEL must be referenced. Ý is defined as the latter of CE 0Ý or CE 1Ý going low, or the first of CE 0Ý or CE 1Ý going high. Figure 11. Read Timing Waveforms
CExÝ is defined as the latter of CE 0Ý or CE 1Ý going low, or the first of CE 0Ý or CE 1Ý going high. Figure 12. BYTE Ý Timing Waveforms
5.7 Power-Up and Reset Timings
Figure 13. V CC Power-Up and RP Ý Reset Waveforms CE0Ý,C E 1Ý and OE Ý are switched low after Power-Up.
- The t YLPH and/or t YHPH times must be strictly followed to guarantee all other read and write specifications for the
- The power supply may start to switch concurrently with RP
- The address access time and RP Ý high to data valid time are shown for 5.0V V CC operation of the 28F016SV-085
Speed Test Configuration) values.
VS28F016SV, MS28F016SV FlashFile TM Memory
5.8 AC Characteristics for WE ÝÐControlled Command Write Operations (1)
VCC e 3.3V g0.15V, T CSE2 eb 40§Ct o a125§C, T CSE1 eb 55§Ct o a125§C, Load e 50 pF Versions Unit Sym Parameter Notes Min Max tAVAV Write Cycle Time 120 ns tVPWH(1,2) VPP Setup to WE Ý Going High 3 100 ns tPHEL RPÝ Setup to CE Ý Going Low 3,7 480 ns tELWL CEÝ Setup to WE Ý Going Low 3,7 10 ns tAVWH Address Setup to WE Ý Going High 2,6 75 ns tDVWH Data Setup to WE Ý Going High 2,6 75 ns tWLWH WEÝ Pulse Width 75 ns tWHDX Data Hold from WE Ý High 2 10 ns tWHAX Address Hold from WE Ý High 2 10 ns tWHEH CEÝ Hold from WE Ý High 3,7 10 ns tWHWL WEÝ Pulse Width High 45 ns tGHWL Read Recovery before Write 3 0 ns tWHRL WEÝ High to RY/BY Ý Going Low 3 100 ns tRHPL RPÝ Hold from Valid Status Register (CSR, 3 0 ns GSR, BSR) Data and RY/BY Ý High tPHWL RPÝ High Recovery to WE Ý Going Low 3 480 ns tWHGL Write Recovery before Read 95 ns tQVVL(1,2) VPP Hold from Valid Status Register (CSR, 3 0 ms GSR, BSR) Data and RY/BY Ý High tWHQV(1) Duration of Word/Byte Write Operation 3,4,5,11 5 ms tWHQV(2) Duration of Block Erase Operation 3,4 0.3 10 sec
VS28F016SV, MS28F016SV FlashFile TM Memory (Continued) VCC e 5.0V g0.25V, T CSE2 eb 40§Ct o a125§C, T CSE1 eb 55§Ct o a125§C, Load e 30 pF VCC e 5.0V g0.5V, T CSE2 eb 40§Ct o a125§C, T CSE1 eb 55§Ct o a125§C, Load e 100 pF Versions VS/MS28F016SV-85 VS/MS28F016SV-85 VS/MS28F016SV-100 UnitVCC g5% V CC g10% V CC g10% Sym Parameter Notes Min Max Min Max Min Max tAVAV Write Cycle 80 85 100 ns Time tVPWH(1) VPP Setup to 3 100 100 100 ns WEÝ GoingtVPWH(2) High tPHEL RPÝ Setup to 3,7 480 480 480 ns CEÝ Going Low tELWL CEÝ Setup to 3,7 0 0 0 ns WEÝ Going Low tAVWH Address 2,6 50 50 50 ns Setup to WE Ý Going High tDVWH Data Setup to 2,6 50 50 50 ns WE Ý Going High tWLWH WEÝ Pulse 50 60 70 ns Width tWHDX Data Hold 2 10 10 10 ns from WE Ý High tWHAX Address Hold 2 10 10 10 ns from WE Ý High tWHEH CEÝ Hold 3,7 10 10 10 ns from WE Ý High tWHWL WEÝ Pulse 30 30 30 ns Width High tGHWL Read 3 0 0 0 ns Recovery before Write tWHRL WEÝ High to 3 100 100 100 ns RY/BYÝ Going Low tRHPL RPÝ Hold 3 0 0 0 ns from Valid Status Register (CSR, GSR, BSR) Data and RY/BY Ý High
VS28F016SV, MS28F016SV FlashFile TM Memory VCC e 5.0V g0.25V, T CSE2 eb 40§Ct o a125§C, T CSE1 eb 55§Ct o a125§C, Load e 30 pF VCC e 5.0V g0.5V, T CSE2 eb 40§Ct o a125§C, T CSE1 eb 55§Ct o a125§C, Load e 100 pF (Continued) Versions VS/MS28F016SV-85 VS/MS28F016SV-85 VS/MS28F016SV-100 UnitVCC g5% V CC g10% V CC g10% Sym Parameter Notes Min Max Min Max Min Max tPHWL RPÝ High 3 1 1 1 ms Recovery to WE Ý Going Low tWHGL Write 60 65 70 ns Recovery before Read tQVVL(1) VPP Hold 3 0 0 0 ms from ValidtQVVL(2) Status Register (CSR, GSR, BSR) Data and RY/ BY Ý High tWHQV(1) Duration of 3,4,5,11 4.5 4.5 4.5 ms Word/Byte Write Operation tWHQV(2) Duration of 3,4 0.3 10 0.3 10 0.3 10 sec Block Erase Operation NOTES: 1. Read timings during write and erase are the same as for normal read. 2. Refer to command definition tables for valid address and data values. 3. Sampled, not 100% tested. Guaranteed by design. 4. Write/Erase durations are measured to valid Status Register (CSR) Data. V PP e 12.0V g0.6V 5. Word/Byte Write operations are typically performed with 1 Programming Pulse. 6. Address and Data are latched on the rising edge of WE Ý for all Command Write operations. 7. CE xÝ is defined as the latter of CE 0Ý or CE 1Ý going low, or the first of CE 0Ý or CE 1Ý going high. 8. Device speeds are defined as: 80/85, 100 ns at V CC e 5.0V equivalent to 120 ns at V CC e 3.3V 9. See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit. 10. See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit. 11. The TBD information will be available in a technical paper. Please contact Intel’s Application Hotline or your local sales office for more information.
- This address string depicts data write/erase cycles with corresponding verification via ESRD.
- This address string depicts data write/erase cycles with corresponding verification via CSRD.
- This cycle is invalid when using CSRD for verification during data write/erase operations.
Ý is defined as the latter of CE 0Ý or CE 1Ý going low or the first of CE 0Ý or CE 1Ý going high.
- RP Ý low transition is only to show t RHPL; not valid for above Read and Write cycles.
- V PP voltage during write/erase operations valid at both 12.0V and 5.0V.
- V PP voltage equal to or below V PPLK provides complete flash memory array protection.
Figure 14. AC Waveforms for Command Write Operations
VS28F016SV, MS28F016SV FlashFile TM Memory
5.9 AC Characteristics for CE ÝÐControlled Command Write Operations (1)
VCC e 3.3V g0.15V, T CSE2 eb 40§Ct o a125§C, T CSE1 eb 55§Ct o a125§C, Load e 50 pF Versions Unit Sym Parameter Notes Min Max tAVAV Write Cycle Time 120 ns tPHWL RPÝ Setup to WE Ý Going Low 3 480 ns tVPEH(1,2) VPP Setup to CE Ý Going High 3,7 100 ns tWLEL WEÝ Setup to CE Ý Going Low 3,7 0 ns tAVEH Address Setup to CE Ý Going High 2,6,7 75 ns tDVEH Data Setup to CE Ý Going High 2,6,7 75 ns tELEH CEÝ Pulse Width 7 75 ns tEHDX Data Hold from CE Ý High 2,7 10 ns tEHAX Address Hold from CE Ý High 2,7 10 ns tEHWH WEÝ hold from CE Ý High 3 10 ns tEHEL CEÝ Pulse Width High 7 45 ns tGHEL Read Recovery before Write 3 0 ns tEHRL CEÝ High to RY/BY Ý Going Low 3,7 100 ns tRHPL RPÝ Hold from Valid Status Register (CSR, 3 0 ns GSR, BSR) Data and RY/BY Ý High tPHEL RPÝ High Recovery to CE Ý Going Low 3,7 480 ns tEHGL Write Recovery before Read 95 ns tQVVL(1,2) VPP Hold from Valid Status Register (CSR, 3 0 ms GSR, BSR) Data and RY/BY Ý High tEHQV(1) Duration of Word/Byte Write Operation 3,4,5,11 5 ms tEHQV(2) Duration of Block Erase Operation 4 0.3 10 sec
VS28F016SV, MS28F016SV FlashFile TM Memory (Continued) VCC e 5.0V g0.25V, T CSE2 eb 40§Ct o a125§C, T CSE1 eb 55§Ct o a125§C, Load e 30 pF VCC e 5.0V g0.5V, T CSE2 eb 40§Ct o a125§C, T CSE1 eb 55§Ct o a125§C, Load e 100 pF Versions(4) VS/MS28F016SV-85 VS/MS28F016SV-85 VS/MS28F016SV-100 VCC g5% V CC g10% V CC g10% Unit Sym Parameter Notes Min Max Min Max Min Max tAVAV Write Cycle 80 85 100 ns Time tPHWL RPÝ Setup to 3 480 480 480 ns WEÝ Going Low tVPEH(1,2) VPP Setup to 3,7 100 100 100 ns CEÝ Going High tWLEL WEÝ Setup to 3,7 0 0 0 ns CEÝ Going Low tAVEH Address Setup 2,6,7 50 50 50 ns to CE Ý Going High tDVEH Data Setup to 2,6,7 50 50 50 ns CE Ý Going High tELEH CEÝ Pulse 7 50 60 70 ns Width tEHDX Data Hold from 2,7 10 10 10 ns CE Ý High tEHAX Address Hold 2,7 10 10 10 ns from CE Ý High tEHWH WE Hold from 3,7 10 10 10 ns CE Ý High tEHEL CEÝ Pulse 7 30 30 30 ns Width High tGHEL Read Recovery 3 0 0 0 ns before Write tEHRL CEÝ High to 3,7 100 100 100 ns RY/BYÝ Going Low tRHPL RPÝ Hold from 3 0 0 0 ns Valid Status Register (CSR, GSR, BSR) Data and RY/BYÝ High
VS28F016SV, MS28F016SV FlashFile TM Memory VCC e 5.0V g0.25V, T CSE2 eb 40§Ct o a125§C, T CSE1 eb 55§Ct o a125§C, Load e 30 pF VCC e 5.0V g0.5V, T CSE2 eb 40§Ct o a125§C, T CSE1 eb 55§Ct o a125§C, Load e 100 pF (Continued) Versions(4) VS/MS28F016SV-85 VS/MS28F016SV-85 VS/MS28F016SV-100 VCC g5% V CC g10% V CC g10% Unit Sym Parameter Notes Min Max Min Max Min Max tPHEL RPÝ High 3,7 1 1 1 ms Recovery to CE Ý Going Low tEHGL Write 60 65 70 ns Recovery before Read tQVVL(1,2) VPP Hold 3 0 0 0 ms from Valid Status Register (CSR, GSR, BSR) Data at RY/BYÝ High tEHQV(1) Duration of 3,4,5,11 4.5 4.5 4.5 ms Word/Byte Write Operation tEHQV(2) Duration of 3,4 0.3 10 0.3 10 0.3 10 sec Block Erase Operation NOTES: 1. Read timings during write and erase are the same as for normal read. 2. Refer to command definition tables for valid address and data values. 3. Sampled, not 100% tested. Guaranteed by design. 4. Write/erase durations are measured to valid Status Data. V PP e 12.0V g 0.6V. 5. Word/Byte Write operations are typically performed with 1 Programming Pulse. 6. Address and Data are latched on the rising edge of CE Ý for all command write operations. 7. CE xÝ is defined as the latter of CE 0Ý or CE 1Ý going low, or the first of CE 0Ý or CE 1Ý going high. 8. Device speeds are defined as: 80/85, 100 ns at V CC e 5.0V equivalent to 120 ns at V CC e 3.3V 9. See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit. 10. See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit. 11. The TBD information will be available in a technical paper. Please contact Intel’s Application Hotline or your local sales office for more information.
- This address string depicts data-write/erase cycles with corresponding verification via ESRD.
- This address string depicts data-write/erase cycles with corresponding verification via CSRD.
- This cycle is invalid when using CSRD for verification during data write/erase operations.
Ý is defined as the latter of CE 0Ý or CE 1Ý going low or the first of CE 0Ý or CE 1Ý going high.
- RP Ý low transition is only to show t RHPL; not valid for above Read and Write cycles.
- V PP voltage during Write/Erase operations valid at both 12.0V and 5.0V.
- V PP voltage equal to or below V PPLK provides complete flash memory array protection.
Figure 15. Alternate AC Waveforms for Command Write Operations
VS28F016SV, MS28F016SV FlashFile TM Memory
5.10 AC Characteristics for WE ÝÐControlled Page Buffer Write Operations (1)
VCC e 3.3V g0.3V, T CSE2 eb 40§Ct o a125§C, T CSE1 eb 55§Ct o a125§C, Load e 50 pF Versions 28F016SV-120 Unit Sym Parameter Notes Min Typ Max tAVWL Address Setup to WE Ý Going Low 2 25 ns VCC e 5.0V g0.5V, T CSE2 eb 40§Ct o a125§C, T CSE1 eb 55§Ct o a125§C, Load e 50 pF Versions(3) VCC g5% 28F016SV-080 (4) UnitVCC g10% 28F016SV-080 (5) 28F016SV-085(5) Sym Parameter Notes Min Typ Max Min Typ Max tAVWL Address Setup 2 15 15 ns to WE Ý Going Low NOTES: 1. All other specifications for WE ÝÐControlled Write Operations can be found in section 5.8. 2. Address must be valid during the entire WE Ý low pulse. 3. Device speeds are defined as: 80/85, 100 ns at V CC e 5.0V equivalent to 120 ns at V CC e 3.3V 4. See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit. 5. See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.
- CE XÝ is defined as the latter of CE 0Ý or CE 1Ý going low, or the first of CE 0Ý or CE 1Ý going high.
Figure 16. WE ÝÐControlled Page Buffer Write Timing Waveforms (Loading Data to the Tape Buffer)
5.11 AC Characteristics for CE ÝÐControlled Page Buffer Write Operations (1)
- All other specifications for CE ÝÐControlled Write Operations can be found in section 5.9.
- Address must be valid during the entire CE Ý low pulse.
- CEx Ý is defined as the latter of CE 0Ý or CE 1Ý going low, or the first of CE 0Ý or CE 1Ý going high.
- Device speeds are defined as:
- See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit.
- See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.
Ý is defined as the latter of CE 0Ý or CE 1Ý going low, or the first of CE 0Ý or CE 1Ý going high. Figure 17. Controller Page Buffer Write Timing Waveforms
VS28F016SV, MS28F016SV FlashFile TM Memory
5.12 Erase and Word/Byte Write Performance (3,5)
VCC e 3.3V g0.15V, V PP e 5.0V g0.5V, T CSE2 eb 40§Ct o a125§C, T CSE1 eb 55§Ct o a125§C Sym Parameter Notes Typ (1) Units Test Conditions Page Buffer Byte Write Time 2,6,7 8 ms Page Buffer Word Write Time 2,6,7 16 ms tWHRH1A Byte Write Time 2,7 29 ms tWHRH1B Word Write Time 2,7 35 ms tWHRH(2) Block Write Time 2,7 1.9 sec Byte Write Mode tWHRH(3) Block Write Time 2,7 1.2 sec Word Write Mode Block Erase Time 2,7 1.4 sec Full Chip Erase Time 2,7 44.8 sec Erase Suspend Latency Time 4 12 ms to Read Auto Erase Suspend Latency 15 ms Time to Write VCC e 3.3V g0.15V, V PP e 12.0V g0.6V, T CSE2 eb 40§Ct o a125§C, T CSE1 eb 55§Ct o a125§C Sym Parameter Notes Typ (1) Units Test Conditions Page Buffer Byte Write Time 2,6,7 2.2 ms Page Buffer Word Write Time 2,6,7 4.4 ms tWHRH(1) Word/Byte Write Time 2,7 9 ms tWHRH(2) Block Write Time 2,7 0.6 sec Byte Write Mode tWHRH(3) Block Write Time 2,7 0.3 sec Word Write Mode Block Erase Time 2 0.8 sec Full Chip Erase Time 2,7 25.6 sec Erase Suspend Latency Time 4 9 ms to Read Auto Erase Suspend Latency 12 ms Time to Write
VS28F016SV, MS28F016SV FlashFile TM Memory
5.12 Erase and Word/Byte Write Performance (3,5) (Continued)
VCC e 5.0V, V PP e 5.0V g0.5V, T CSE2 eb 40§Ct o a125§C, T CSE1 eb 55§Ct o a125§C Sym Parameter Notes Typ (1) Units Test Conditions Page Buffer Byte Write Time 2,6,7 8 ms Page Buffer Word Write Time 2,6,7 16 ms tWHRH1A Byte Write Time 2,7 20 ms tWHRH1B Word Write Time 2,7 25 ms tWHRH(2) Block Write Time 2,7 1.4 sec Byte Write Mode tWHRH(3) Block Write Time 2,7 0.85 sec Word Write Mode Block Erase Time 2,7 1.0 sec Full Chip Erase Time 2,7 32.0 sec Erase Suspend Latency Time 4 9 ms to Read Auto Erase Suspend Latency 12 ms Time to Write VCC e 5.0V g 0.5V, V PP e 12.0V g0.6V, T CSE2 eb 40§Ct o a125§C, T CSE1 eb 55§Ct o a125§C Sym Parameter Notes Typ (1) Units Test Conditions Page Buffer Byte Write Time 2,6,7 2.1 ms Page Buffer Word Write Time 2,6,7 4.1 ms tWHRH(1) Word/Byte Write Time 2,7 6 ms tWHRH(2) Block Write Time 2,7 0.4 sec Byte Write Mode tWHRH(3) Block Write Time 2,7 0.2 sec Word Write Mode Block Erase Time 2 0.6 sec Full Chip Erase Time 2,7 19.2 sec Erase Suspend Latency Time 4 7 ms to Read Auto Erase Suspend Latency 10 ms Time to Write NOTES: 1. 25 §C, and normal voltages. 2. Excludes system-level overhead. 3. These performance numbers are valid for all speed versions. 4. Specification applies to interrupt latency for single block erase. Suspend latency for erase all unlocked blocks operation extends the maximum latency time to 270 ms. 5. Sampled, but not 100% tested. Guaranteed by design. 6. Assumes using the full Page Buffer to Write to Flash (256 bytes or 128 words).
6.0 MECHANICAL SPECIFICATIONS
Figure 18. Mechanical Specifications of the VS/MS28F0165V 56-Lead SSOP Package
VS28F016SV, MS28F016SV FlashFile TM Memory DEVICE NOMENCLATURE V S28F016SVÐ85 M S28F016SVÐ85 ll l l V e SE2 S e SSOP l Access Speed M e SE1 SV e SmartVoltage Technology Depending on system design specifcations, the VS/MS28F016SV-85 is capable of supporting Ð 85 ns access time with a V CC of 5.0V g10% and loading of 100 pF Ð 100 ns access time with a V CC of 5.0V g10% and loading of 100 pF ADDITIONAL INFORMATION Order Number Document/Tool 297372 16-Mbit Flash Product Family User’s Manual
292163 AP-610 ‘‘Flash Memory In-System Code and Data Update Techinques’’
292144 AP-393 ‘‘28F016SV Compatibility with 28F016SA’’
292127 AP-378 ‘‘System Optimization Using the Enhanced Features of the
28F016SA’’
292126 AP-377 ‘‘16-Mbit Flash Product Family Software Drivers, 28F016SA/
28F016SV/28F016XS/28F016XD’’
292124 AP-387 ‘‘Upgrade Considerations from the 28F008SA to the 28F016SA’’
292123 AP-374 ‘‘Flash Memory Write Protection Techniques’’
292092 AP-357 ‘‘Power Supply Solutions for Flash Memory’’
292165 AB-62 ‘‘Compiling Optimized Code for Embedded Flash RAM Memories’’
294016 ER-33 ‘‘ETOX TM Flash Memory TechnologyÐInsight to Intel’s Fourth
Generation Process Innovation’’
297508 FLASHBuilder Utility
Contact Intel/Distribution Flash Cycling Utility Sales Office Contact Intel/Distribution 28F016SV iBIS Models Sales Office Contact Intel/Distribution 28F016SV VHDL/Verilog Models Sales Office Contact Intel/Distribution 28F016SV Timing Designer Library Files Sales Office Contact Intel/Distribution 28F016SV Orcad and ViewLogic Schematic Symbols Sales Office DATA SHEET REVISION HISTORY Number Description
001 Original Version
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