MR82510

M82510 INTEL | Alldatasheet

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*Other brands and names are the property of their respective owners. changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. modems, serial portsÐincluding expanding performance areas: MCS É-51 9-bit format and high speed async. M82510 is fabricated in CHMOS III technology and includes a software powerdown option. *IBM and PC AT are registered trademarks of IBM Corporation. Figure 1. Block Diagram

Figure 2. Package Pinouts Symbol Pin Type Name and DescriptionNo. 22 Bus to select one of the internal registers for read or write. 25 transfer of bytes between the CPU and the M82510. INT 5 O INTERRUPT: A high on this output pin signals an interrupt request to the CPU. reading the M82510 Status registers. refer to the System Clock Generation.

Symbol Pin Type Name and DescriptionNo. BRGB output signal when configured as either a clock generator or as a timer. function to pin TB except it outputs the signals from BRGA instead of BRGB. OUT0 - Output pin. This is a general purpose output pin controlled by the CPU. details.) This pin can be used as a General Purpose Input. output of the internal system clock. OUT1 - General purpose output pin. Table 1. Multifunction Pins

11 OUT0 TA *DSR

12 OUT1 ICLK *DCD

overhead normally required for serial operations. and modes to support serial communication. through its registers to support a variety of functions. ured to support 8250A/16450 emulation. Figure 3. M82510 Register Architecture Table 2. M82510 Register/Block Functions

8250 LSR, MSR, GIR GER LCR, MCR MCR TXD, RXD

8250 Compatibility

Table 3. 8250A/16450 Compatible Registers

02 GIR/BANK BANK IIR Ð

03 LCR LCR LCR LCR

04 MCR MCR MCR MCR

05 LSR LSR LSR LSR

06 MSR MSR MSR MSR

07 ACR0 ACR0 SCR SCR

Table 4. Default Wake-Up Mode

Figure 4. Interrupt Structure and at the individual source level within the module. ter, will reset the status bits. interrupt is coded into the General Interrupt register. The INT pin is forced low upon acknowledgment. pin is forced low for two clocks and then updated. is considered as an automatic acknowledgment. This forces the INT pin low for two clock cycles.

Figure 8. Tx FIFO the Threshold. The threshold is user programmable. tem’s interrupt service latency. FIFO. This error will not be reported to the CPU. The transmitter has three modes of handshaking. is activated whenever the transmitter is enabled. the FIFO, the handshake is done by the Tx Machine. than Control Characters are recognized.

Figure 9. Rx FIFO it will LOCK the FIFO if an address mismatch occurs. dow to receive the data bits. registers and resume normal operation.

Table 7. Standard Baud Rates Table 8. Duty Cycles

1 Same as Source

0 FORBIDDEN

Each of the M82510 BRGs can be used as Timers. forbidden in the Timer Mode only. Figure 12. Local Loopback shorted internally, TXD pin output is held at Mark. nally shorted to RI , DCD , DSR and CTS respectively. OUT0 is held at a mark state.

Table 9. Register Map

2 GIR/BANK BANK

3 LCR LCR

4 MCR MCR

5 LSR LSR

6 MSR MSR

7 ACR0 ACR0

1 RXF TXF

3 TMST TMCR

4 FLR MCR

5 RST RCM

6 MSR TCM

7 GSR ICM

1 FMD FMD

3 TMD TMD

4 IMD IMD

5 ACR1 ACR1

6 RIE RIE

7 RMD RMD

3 BBCF BBCF

4 PMD PMD

5 MIE MIE

6 TMIE TMIE

grouped into the following categories.

BANK ZERO 8250A/16450ÐCOMPATIBLE BANK Register 7 6 5 4 3 2 1 0 Address Default TxD (33) Tx Data Tx Data Tx Data Tx Data Tx Data Tx Data Tx Data Tx Data 0 Ð bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 RxD (35) Rx Data Rx Data Rx Data Rx Data Rx Data Rx Data Rx Data Rx Data 0 Ð bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 BAL (11) BRGA LSB Divide Count (DLAB e 1) 0 02H BAH (12) BRGA MSB Divide Count (DLAB e 1) 1 00H GER (16) 0 0 Timer Tx Machine Modem Rx Machine Tx FIFO Rx FIFO 1 00H Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Enable Enable Enable Enable Enable Enable GIR/BANK 0 BANK BANK 0 Active Active Active Interrupt 2 01H (21) Pointer Pointer Block Int Block Int Block Int Pending bit 1 bit 0 bit 2 bit 1 bit 0 LCR (2) DLAB Set Parity Parity Parity Stop bit Character Character 3 00H Divisor Break Mode Mode Mode Length Length Length Latch bit 2 bit 1 bit 0 bit 0 bit 1 bit 0 Access bit MCR (32) 0 0 OUT 0 Loopback OUT 2 OUT 1 RTS DTR 4 00H Complement Control bit Complement Complement Complement Complement LSR (22) 0 TxM Tx FIFO Break Framing Parity Overrun Rx FIFO 5 60H Idle Interrupt Detected Error Error Error Int Req MSR (27) DCD Input RI Input DSR Input CTS Input State State (H xL) State State 6 00H Inverted Inverted Inverted Inverted Change Change Change Change in DCD in RI in DSR in CTS ACR0 (5) Address or Control Character Zero 7 00H BANK ONEÐGENERAL WORK BANK Register 7 6 5 4 3210 Address Default TxD (33) Tx Data Tx Data Tx Data Tx Data Tx Data Tx Data Tx Data Tx Data 0 Ð bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 RxD (35) Rx Data Rx Data Rx Data Rx Data Rx Data Rx Data Rx Data Rx Data 0 Ð bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 RxF (24) Ð Rx Char Rx Char Rx Char Address or Break Rx Char Ninth 1 Ð OK Noisy Parity Control Flag Framing Data bit Error Character Error of Rx Char TxF (34) Address Software Ninth bit 0 0000 1 Ð Marker bit Parity bit of Data Char GIR/BANK 0 BANK BANK 0 Active Active Active Interrupt 2 01H (21) Pointer Pointer Block Int Block Int Block Int Pending bit 1 bit 0 bit 2 bit 1 bit 0 TMST (26) Ð Ð Gate B Gate A Ð Ð Timer B Timer A 3 30H State State Expired Expired TMCR (31) 0 0 Trigger Trigger 0 0 Start Start 3 Ð Gate B Gate A Timer B Timer A MCR (32) 0 0 OUT 0 Loopback OUT 2 OUT 1 RTS DTR 4 00H Complement Control bit Complement Complement Complement Complement NOTE: The register number is provided as a reference number for the register description.

BANK ONEÐGENERAL WORK BANK (Continued) Register 7 6 5 4 3 2 1 0 Address Default FLR (25) Ð Rx FIFO Level Ð Tx FIFO Level 4 00H RST (23) Address/ Address/ Break Break Framing Parity Overrun Rx FIFO 5 00H Control Control Terminated Detected Error Error Error Interrupt Character Character Requested Received Match RCM (30) Rx Rx Flush Flush Lock Rx Open Rx 0 0 5 Ð Enable Disable RxM Rx FIFO FIFO FIFO MSR (27) DCD RI Input DSR Input CTS Input State State State State 6 00H Complement Inverted Inverted Inverted Change Change Change Change in DCD in RI in DSR in CTS TCM (29) 0 0 0 0 Flush Tx Flush Tx Tx Tx 6 Ð Machine FIFO Enable Disable GSR (20) Ð Ð Timer TxM Modem RxM Tx FIFO Rx FIFO 7 12H Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt ICM (28) 0 0 0 Software Manual Int Status Power 0 7 Ð Reset Acknowledge Clear Down Command Mode BANK TWOÐGENERAL CONFIGURATION Register 7 6 5 4 3 2 1 0 Address Default FMD (4) 0 0 Rx FIFO Threshold 0 0 Tx FIFO Threshold 1 00H GIR/BANK 0 BANK BANK 0 Active Active Active Interrupt 2 01H (21) Pointer Pointer Block Int Block Int Block Int Pending bit 1 bit 0 bit 2 bit 1 bit 0 TMD (3) Error Control 9-bit Transmit Mode Software Stop Bit Length 3 00H Echo Character Character Parity Disable Echo Disable Length Mode IMD (1) 0 0 0 0 Interrupt Rx FIFO ulan Loopback or 4 0CH Acknowledge Depth Mode Echo Mode Mode Select of Operation ACR1 (6) Address or Control Character 1 5 00H RIE (17) Address/ Address/ Break Break Framing Parity Overrun 0 6 1EH Control Control Terminate Detect Error Error Error Character Character Interrupt Interrupt Interrupt Interrupt Interrupt Recognition Match Enable Enable Enable Enable Enable Interrupt Interrupt Enable Enable RMD (7) Address/Control Disable Sampling Start bit 0 0 0 7 00H Character Mode DPLL Window Sampling Mode Mode BANK THREEÐMODEM CONFIGURATION Register 7 6 5 4 3 2 1 0 Address Default CLCF (8) Rx Clock Rx Clock Tx Clock Tx Clock 0 0 0 0 0 00H Mode Source Mode Source BACF (9) 0 BRGA 0 0 0 BRGA 0 0 1 04H Clock Mode Source BBL (13) BRGB LSB Divide Count (DLAB e 1) 0 05H BBH (14) BRGB MSB Divide Count (DLAB e 1) 1 00H

mode by programming the configuration registers as necessary. The configuration options available to the user are listed below. Table 11. Configuration Options

1. IMDÐINTERNAL MODE REGISTER IMDÐInternal Mode Register 271072–14 This register defines the general device mode of op- eration. The bit functions are as follows: 7–4: Reserved IAM: Interrupt Acknowledge Mode Bit 0 Ð Manual acknowledgement of pend- ing interrupts 1 Ð Automatic acknowledgement of pending interrupts (upon CPU serv- ice) This bit, when set, configures the M82510 for the automatic acknowledge mode. This causes the M82510 INT line to go low for two clock cycles upon service of the interrupt. After two clock cycles it is then updated. It is useful in the edge triggered mode. In manual acknowledgement mode the CPU must explicitly issue a command to clear the INT pin. (The INT pin then goes low for a minimum of two clock cycles until another enabled status register bit is set.) RFD: Receive FIFO Depth 0 Ð Four Bytes 1 Ð One Byte This bit configures the depth of the Rx FIFO. With a FIFO depth of one, the FIFO will act as a 1-byte buffer to emulate the 8250A. ULM: uLAN Mode 0 Ð Normal Mode 1 Ð uLAN Mode This bit, enables the M82510 to recognize and/or match address using the 9-bit MCS-51 asynchro- nous protocol. LEM: Loopback/Echo Mode Select This bit selects the mode of loopback operation, or the mode of echo operation; depending upon which operation mode is selected by the Modem Control register bit LC. In loopback mode (Modem Control register bit LC e 1) it selects between local and remote loop- back. 0 Ð Local Loopback 1 Ð Remote Loopback In echo mode (Modem Control register bit LC e 0) it selects between echo or non-echo operation. 0 Ð No Echo 1 Ð Echo Operation

1. LCRÐLINE CONFIGURE REGISTER

activities) until this bit is reset. Table 12. Parity Modes

0 X X X No Parity

Table 13. Stop Bit Length define the character length. See Table 14. Table 14. Character Length

1. TMDÐTransmit Machine Mode Register TMDÐTransmit Machine Mode Register 271072–16 This register together with the Line Configure Regis- ter defines the Tx machine mode of operation. EEDÐError Echo DisableÐ Disables Echo of char- acters received with errors (valid in echo mode only). CEDÐControl Character Echo DisableÐ Disables Echo of characters recognized as control characters (or address characters in uLAN mode). Valid in echo mode only. NBCLÐNine-Bit LengthÐ This bit, coupled with LCR (CL0, CL1), selects Transmit/Receive charac- ter length of nine bits. See Table 14. TM1ÐTM0ÐTransmit ModeÐ These bits select one of three modes of control over the CTS and RTS lines. 00ÐManual ModeÐ In this mode the CPU has full control of the Transmit operation. The CPU has to explicitly enable/disable transmission, and activate/ check the RTS /CTS pins. 01ÐReserved 10ÐSemi-Automatic ModeÐ In this mode the M82510 transmits only when CTS input is active. The M82510 activates the RTS output as long as transmission is enabled. 11ÐAutomatic ModeÐ In this mode the M82510 transmits only when CTS input is active. The RTS output is activated only when transmission is en- abled and there is more data to transmit. SPFÐSoftware Parity ForceÐ This bit defines the parity modes along with the PM0, PM1, and PM2 bits of the LCR register. When software parity is enabled the software must determine the parity bit through the TxF register on transmission, or check the parity bit in RxF upon reception. See Table 12. SBL2ÐSBL1ÐStop Bit LengthÐ These bits, to- gether with the SBL0 bit of the LCR register define the stop bit length. See Table 13.

1. FMDÐFIFO MODE REGISTER FMDÐFIFO Mode Register 271072–17 This register configures the Tx and Rx FIFO’s threshold levelsÐthe occupancy levels that can cause an interrupt. 7Ð6ÐReserved RFT1ÐRFT0ÐReceive FIFO ThresholdÐ When the Rx FIFO occupancy is greater than the level indi- cated by these bits the Rx FIFO Interrupt is activat- ed. 3Ð2ÐReserved TFT1ÐTFT0ÐTransmit FIFO ThresholdÐ When the TX FIFO occupancy is less than or equal to the level indicated by these bits the Tx FIFO Interrupt is activated. 5. ACR0ÐADDRESS/CONTROL CHARACTER REGISTER 0 ARC0ÐAddress/Control Character Register 0 271072–18 This register contains a byte which is compared to each received character. The exact function de- pends on the configuration of the IMD register. In normal mode this register may be used to pro- gram a special control character; a matched charac- ter will be reported in the RECEIVE STATUS regis- ter. The maximum length of the control characters is eight bits. If the length is less than eight bits then the character must be right justified and the leading bits be filled with zeros. In uLAN mode this register contains the eight-bit sta- tion address for recognition. In this mode only in- coming address characters (i.e., characters with ad- dress bit set) will be compared to these register. The PCRF bit in the RECEIVE STATUS register will be set when an Address or Control Character match occurs. 6. ACR1ÐADDRESS/CONTROL CHARACTER REGISTER 1 ARC1ÐAddress/Control Character Register 1 271072–19 NOTE: This register is identical in function to ACR0.

1. RMDÐRECEIVE MACHINE MODE REGISTER RMDÐReceive Machine Mode Register 271072–20 This register defines the Rx Machine mode of opera- tion. uCM0, uCM1ÐuLAN/Control Character Recogni- tion ModeÐ In normal mode it defines the Control Character recognition mode. In ulan mode they de- fine modes of address recognition. In uLAN mode: selects the mode of address recog- nition. 00ÐManual ModeÐ Rx Machine reports reception of any address character, via CRF bit of RECEIVE STATUS register, and writes it to the Rx FIFO. 01ÐSemi-Automatic ModeÐ Operates the same as Manual Mode but, in addition, the Rx Machine OPENS (unlocks) the Rx FIFO upon reception of any address characters. Subsequent received charac- ters will be written into the FIFO. (Note: it is the us- er’s responsibility to LOCK the FIFO if the address character does not match the station’s address.) 10ÐAutomatic ModeÐ The Rx Machine will OPEN (unlock) the Rx FIFO upon Address Match. In addi- tion the Rx Machine LOCKs the Rx FIFO upon rec- ognition of address mismatch; i.e., it controls the flow of characters into the Rx FIFO depending upon the results of the address comparison. If a match occurs it will allow characters to be sent to the FIFO; if a mismatch occurs it will keep the characters out of the FIFO by LOCKING it. 11ÐReserved In normal Mode: selects the mode of Standard Set Control Character Recognition (programmed control characters are always recognized). 00Ð No Standard Set Control Characters Recog- nized. 01Ð ASCII Control Characters (00HÐ1 FH a 7FH). 10Ð Reserved. 11Ð EBCDIC Control Character Recognized (00H b 3FH). DPDÐDisable Digital Phase Locked LoopÐ When set, disables the DPLL machine. (Note: using the DPLL in a very noisy media, may increase the error rate.) SWMÐSampling Window ModeÐ This bit controls the mode of data sampling: 0ÐSmall Window, 3/16 sampling. 1ÐLarge Window, 7/16 sampling. SSMÐStart Bit Sampling ModeÐ This bit controls the mode of Start Bit sampling. 0Ð Majority Voting for start bit. In this mode a ma- jority of the samples determines the bit. 1Ð In this mode if one of the bit samples is not ‘0’, the start bit will not be detected.

1. CLCFÐCLOCKS CONFIGURE REGISTER CLCFÐClocks Configure Register 271072–21 This register defines the Transmit and Receive Code modes and sources. RxCMÐRx Clock ModeÐ This bit selects the mode of the receive clock which is used to sample the received data. 0Ð 16X Mode. 1Ð 1X Mode. In this mode the receive data must be synchronous to the Rx Clock; supplied via the SCLK pin. RxCSÐRx Clock SourceÐ This bit selects the source of the internal receive clock in the case of 16X mode (as programmed by the RxCM bit above). 0ÐBRGB Output 1ÐBRGA Output TxCMÐTransmit Clock ModeÐ This bit selects the mode of the Transmit Data Clock, which is used to clock out the Transmit Data. 0Ð 16X Mode 1Ð 1X Mode. In this mode the Transmit data is synchronous to the Serial Clock; supplied via the SCLK pin. TxCSÐTransmit Clock SourceÐ Selects the source of internal Transmit Clock in case of 16X mode. 0ÐBRGB Output. 1ÐBRGA Output. 9. BACFÐBRGA CONFIGURATION REGISTER BACFÐBRGA Configuration Register 271072–22 This register defines the BRGA clock sources and the mode of operation. BACSÐBRGA Clock SourceÐ Selects the input clock source for Baud Rate Generator A. 0ÐSystem Clock 1ÐSCLK Pin This bit has no effect if BRGA is configured as a timer. BAMÐBRGA Mode of OperationÐ Selects be- tween the Timer mode or the Baud Rate Generator Mode. 0Ð Timer Mode (in this mode the input clock source is always the system clock). 1Ð Baud Rate Generator Mode

1. BBCFÐBRGB CONFIGURATION REGISTER BBCFÐBRGB Configuration Register 271072–23 This register defines the BRGB clock sources and mode of operation. (Note: BRGB can also take its Input Clock from the output of BRGA.) BBCS1, BBCS0ÐThese two bits together define the input Clock Sources for BRGB. These bits have no effect when in the timer mode. 00Ð System Clock 01Ð SCLK Pin 10Ð BRGA Output 11Ð Reserved BBMÐBRGB Mode of Operation. 0Ð Timer Mode (In this mode the input clock source is always the system clock.) 1Ð BRG Mode 11. BALÐBRGA DIVIDE COUNT LEAST SIGNIFICANT BYTE BALÐBRGA Divide Count Low Byte 271072–24 This register contains the least significant byte of the BRGA divisor/count. 12. BAHÐBRGA DIVIDE COUNT MOST SIGNIFICANT BYTE BAHÐBRGA Divide Count High Byte 271072–25 This register contains the most significant byte of the BRGA divisor/count. 13. BBLÐBRGB DIVIDE COUNT LEAST SIGNIFICANT BYTE BBLÐBRGB Divide Count Low Byte 271072–26 This register contains the least significant byte of the BRGB divisor/count.

1. BBHÐBRGB DIVIDE COUNT MOST SIGNIFICANT BYTE BBHÐBRGB Divide Count High Byte 271072–27 This register contains the most significant byte of the BRGB divisor/count. 15. PMDÐI/O PIN MODE REGISTER PMDÐI/O Pin Mode Register 271072–28 This register is used to configure the direction and function of the multifunction pins. The following op- tions are available on each pin. 1. Direction: Input or Output Pin. 0Ð Defines the Pin as an output pin (general pur- pose or special function). 1Ð Defines the pin as an input pin. 2. Function: General purpose or special purpose pin (no effect if the pin is programmed as an Input). 0Ð special function output pin. 1Ð general purpose output pin. DIODÐDCD /ICLK/OUT1 Direction. 0Ð Output: ICLK or OUT1 (depending on bit DIOF) 1Ð Input: DCD . DIOFÐDCD/ICLK/OUT1 Function (output mode only). 0Ð ICLK (Output of the Internal System Clock). 1Ð OUT1 general purpose output, Controlled by MODEM CONTROL Register DTADÐDSR /TA/OUT0 Direction. 0Ð Output: TA or OUT0 (Dependent upon DTAF). 1Ð Input: DSR . DTAFÐDSR/TA/OUT0 Direction (output mode only). 0Ð TA (BRGA Output or Timer A Termination Pulse). 1Ð OUT0 (general purpose output, controlled by MODEM CONTROL). RRFÐRI /SCLK Function 0Ð SCLK (Receive and/or Transmit Clock) 1Ð RI DTFÐDTR/TB Function 0Ð TB (BRGB Output Clock on Timer B termina- tion pulse depending upon the mode of BRGB). 1Ð DTR

INTERRUPT/STATUS REGISTERS The M82510 uses a two layer approach to handle interrupt and status generation. Device level regis- ters show the status of the major M82510 functional block (MODEM, FIFO, Tx MACHINE, Rx MACHINE, TIMERS, etc.). Each block may be examined by reading its individual block level registers. Also each block has interrupt enable/generation logic which may generate a request to the built-in interrupt con- troller, the interrupt requests are then resolved on a priority basis. Interrupt Masking The M82510 has a device enable register, GER, which can be used to enable or mask-out any block interrupt request. Some of the blocks (Rx Machine, Modem, Timer) have an enable register associated with their status register which can be used to mask out the individual sources within the block. Interrupts are enabled when programmed high. 16. GERÐGENERAL ENABLE REGISTER GERÐGeneral Enable Register 271072–29 This register enables or disables the bits of the GSR register from being reflected in the GIR register. It serves as the device enable register and is used to mask the interrupt requests from any of the M82510 block (See Figure 1). TIEÐTimers Interrupt Enable TxIEÐTransmit Machine Interrupt Enable. MIEÐModem Interrupt Enable. RxIEÐRx Machine Interrupt Enable. TFIEÐTransmit FIFO Interrupt Enable. RFIEÐReceive FIFO Interrupt Enable. 17. RIEÐRECEIVE INTERRUPT ENABLE REGISTER RIEÐReceive Interrupt Enable Register 271072–30 This register enables interrupts from the Rx Ma- chine. It is used to mask out interrupt requests gen- erated by the status bits of the RST register. CREÐControl/uLAN Address Character Recog- nition Interrupt Enable.Ð Enables Interrupt when CRF bit of RST register is set. PCREÐProgrammable Control/Address Charac- ter Match Interrupt Enable.Ð Enables Interrupt on PCRF bit of RST. BkTeÐBreak Termination Interrupt Enable. BkDEÐBreak Detection Interrupt EnableÐ En- able Interrupt on BkD bit of RST. FEEÐFraming Error EnableÐ Enable Interrupt on FE bit of RST. PEEÐParity Error EnableÐ Enable Interrupt on PE bit of RST. OEEÐOverrun Error EnableÐ Enable Interrupt on OE bit of RST.

1. TMIEÐTIMER INTERRUPT ENABLE REGISTER TMIEÐTimers/Interrupt Enable Register 271072–31 This is the enable register for the Timer Block. It is used to mask out interrupt requests generated by the status bits of the TMST register. TBIEÐTimer B Expired Interrupt EnableÐ En- ables Interrupt on TBEx bit of TMST. TAIEÐTimer A Expired Interrupt EnableÐ En- ables Interrupt on TAEx bit of TMST. 19. MIEÐMODEM INTERRUPT ENABLE REGISTER MIEÐModem Interrupt Enable Register 271072–32 This register enables interrupts from the Modem Block. It is used to mask out interrupt requests gen- erated by the status bits of the MODEM STATUS register. DCDEÐDelta DCD Interrupt EnableÐ Enables In- terrupt on DDCD bit of MODEM STATUS. RIEÐDelta RI Interrupt EnableÐ Enables Interrupt on DRI bit of MODEM STATUS. DSREÐDelta DSR Interrupt EnableÐ Enables In- terrupt on DSR bit of MODEM STATUS. CTSEÐDelta CTS Interrupt EnableÐ Enables In- terrupt on DCTS bits of MODEM STATUS. STATUS/INTERRUPT The M82510 has two device status registers, which reflect the overall status of the device, and five block status registers. The two device status registers, GSR and GIR, and supplementary in function. GSR reflects the interrupt status of all blocks, whereas GIR depicts the highest priority interrupt only. GIR is updated after the GSR register; the delay is of ap- proximately two clock cycles.

1. GSRÐGENERAL STATUS REGISTER GSRÐGeneral Status Register 271072–33 This register reflects all the pending block-level In- terrupt requests. Each bit in GSR reflects the status of a block and may be individually enabled by GER. GER masks-out interrupts from GIR; it does not have any effect on the bits in GSR. The only way that the bits can be masked out in GSR (i.e., not appear in GSR) is if they are masked out at the lower level. TIRÐTimers Interrupt RequestÐ This bit indicates that one of the timers has expired. (See TMST) TxIRÐTransmit Machine Interrupt RequestÐ In- dicates that the Transmit Machine is either empty or disabled (Idle). MIRÐModem Interrupt RequestÐ This bit, if set, indicates an interrupt from the Modem Module. (As reflected in MODEM STATUS.) RxIRÐReceive Machine Interrupt RequestÐ (As reflected in RST.) TFIRÐTransmit FIFO Interrupt RequestÐ Tx FIFO occupancy is below or equal to threshold. RFIRÐReceive FIFO Interrupt RequestÐ Rx FIFO Occupancy is above threshold. 21. GIR/BANKÐGENERAL INTERRUPT REGISTER/BANK REGISTER General Interrupt Register/Bank Register 271072–34 This register holds the highest priority enabled pend- ing interrupt from GSR. In addition it holds a pointer to the current register segment. Writing into this reg- ister will update only the BANK bits. BANK1, BANK0ÐBank Pointer BitsÐ These two bits point to the currently accessible register bank. The user can read and write to these bits. The ad- dress of this register is always two within all four register banks. BI2, BI1, BI0,ÐInterrupt Bits 0–2Ð These three bits reflect the highest priority enabled pending inter- rupt from GSR. 101: Timer Interrupt (highest priority) 100: Tx Machine Interrupt 011: Rx Machine Interrupt 010: Rx FIFO Interrupt 001: Tx FIFO Interrupt 000: Modem Interrupt (lowest priority) IPNÐInterrupt PendingÐ This bit is active low. It indicates that there is an interrupt pending. The in- terrupt logic asserts the INT pin as soon as this bit goes active. (Note: the GIR register is continuously updated; so that, while the user is serving one inter- rupt source, a new interrupt with higher priority may enter GIR and replace the older interrupt.)

1. LSRÐLINE STATUS REGISTER LSRÐLine Status Register 271072–35 This register holds the status of the serial link. It shares five of its bits with the RST register (BkD, FE, PE, OE, and RFIR). When this register is read, the RST register (BITS 1–7) and LSR register (BITS 1– 4) are cleared. This register is provided for compati- bility with the INS8250A. TxStÐTransmit Machine Status BitÐ Same as TxIR bit of GSR register. If high it indicates that the Transmit Machine is in Idle State. (Note: Idle may indicate that the TxM is either empty or disabled. TFStÐTransmit FIFO StatusÐ Same as TFIR bit of GSR. It indicates that the Transmit FIFO level is equal to or below the Transmit FIFO Threshold. There are two ways to disable the transmit FIFO status from being reflected in GIR: 1. Writing a ‘‘0’’ to the TFIE bit of the GER register 2. Dynamically by using the Tx FIFO HOLD IN- TERRUPT logic. When the Tx FIFO is in the Hold State, no interrupts are generated regard- less of the TFIR and TFIE bits. The Transmit FIFO enters the Hold State when the CPU reads the GIR register and the source of the interrupt is Tx FIFO. To Exit, the CPU must drop the TFIR bit of GSR by writing a character to Tx FIFO, or drop TFIE bit of GER (Disable Tx FIFO). BkdÐBreak DetectedÐ See Bkd bit in RST register for full explanation. The BkD bit in RST register is the same as this bit. FEÐFraming Error DetectedÐ See FE bit in RST register for a full explanation. The FE bit in RST reg- ister is the same as this bit. PEÐParity Error DetectedÐ See PE bit in RST register for full explanation. The PE bit in RST regis- ter is the same as this bit. OEÐOverrun ErrorÐ See OE bit in RST register for full explanation. The OE bit in RST register is the same as this bit. RFIRÐReceive FIFO Interrupt RequestÐ This bit is identical to RFIR bit of GSR. It indicates that the RX FIFO level is above the Rx FIFO Threshold. This bit is forced LOW during any READ from the Rx FIFO. A zero written to this bit will acknowledge an Rx FIFO interrupt.

1. RSTÐRECEIVE MACHINE STATUS REGISTER RSTÐReceive Machine Status Register 271072–36 This register displays the status of the Receive Ma- chine. It reports events that have occurred since the RST was cleared. This register is cleared when it is read except for BIT0, Rx FIFO interrupt. Each bit in this register, when set, can cause an interrupt. Five bits of this register are shared with the LSR register. CRFÐControl/Address Character ReceivedÐ When enabled, this bit can cause an interrupt if a control character or address character is received. In uLAN Mode: indicates that an address charac- ter has been received. In normal Mode: indicates that a standard control character (either ASCII or EBCDIC) has been re- ceived. PCRFÐProgrammed Control/Address Character ReceivedÐThis bit, when enabled, will cause an in- terrupt when an address or control character match occurs. In uLAN Mode: indicates that an address charac- ter equal to one of the registers ACR0 or ACR1 has been received. In normal Mode: indicates that a character which matches the registers ACR0 or ACR1 has been received. BkTÐBreak TerminatedÐ This bit indicates that a break condition has been terminated. BkDÐBreak DetectedÐ This bit indicates that a Break Condition has been detected, i.e., RxD input was held low for one character frame plus a stop BIT. FEÐFraming ErrorÐ This bit indicates that a re- ceived character did not have a valid stop bit. PEÐParity ErrorÐ Indicates that a received charac- ter had a parity error. OEÐOverrun ErrorÐ Indicates that a received character was lost because the Rx FIFO was full. RFIRÐReceive FIFO Interrupt RequestÐ Same as the RFIR bit of LSR register.

1. RXFÐRECEIVED CHARACTER FLAGS RxFÐReceive Flags Register 271072–37 This register contains additional information about the character in the RXD register. It is loaded by the Rx Machine simultaneously with the RXD register. ROKÐReceived Character OKÐ This bit indicates that the character in RXD no parity or framing error. The parity error is not included in the s/w parity mode. RxNÐReceived Character NoisyÐ The character in RXD was noisy. This bit, valid only in 16X sam- pling mode, indicates that the received character had non-identical samples for at least one of its bits. RPEÐReceive Character Parity ErrorÐ This bit in- dicates that the RxD character had a Parity Error. However, in S/W Parity mode it holds the received parity bit as is. ACRÐAddress/Control Character MarkerÐ This bit indicates that the character in RXD is either: A control CharacterÐin normal Mode. An Address Character in uLAN Mode. RFEÐReceive Character Framing ErrorÐ Indi- cates that no Stop bit was found for the character in RXD. NOTE: A Framing Error will be generated for the first char- acter of the Break sequence. RNDÐNinth Bit of Received CharacterÐ The most significant bit of the character in RXD is written into this bit. This bit is zero for characters with less than nine bits. BKFÐBreak FlagÐ Indicates that the character is part of a ‘‘break’’ sequence. 25. FLRÐFIFO LEVEL REGISTER FLRÐFIFO Level Register 271072–38 This register holds the current Receive and Transmit FIFO occupancy levels. RFL2, RFL1, RFL0ÐReceive FIFO Level of Occu- pancyÐThese three bits indicate the level of Occu- pancy of the Rx FIFO. The valid range is zero (000) to four (100). TFL2, TFL1, TFL0ÐTransmit FIFO Level of Occu- pancyÐThese three bits indicate the level of occu- pancy in the transmit FIFO. The valid range is zero (000) to four (100).30

1. TMSTÐTIMER STATUS REGISTER TMSTÐTimer Status Register 271072–39 This register holds the status of the timers. Bits TBEx and TAEx generate interrupts which are re- flected in bit TIR of GSR. Bits GBS and GAS just display the counting status, they do not generate in- terrupts. GBSÐGate B StateÐ This bit does not generate an interrupt. It indicates the counting state of the soft- ware gate of Timer B, as written through the TMCR register. 0Ðcounting disabled 1Ðcounting enabled GASÐGateÐA StateÐ This bit does not generate an interrupt. It reflects the state of the software gate of Timer A, as written through the TMCR register. 0Ðcounting disabled 1Ðcounting enabled TBExÐTimer B ExpiredÐ When Set generates an interrupt through TIR bit of GSR. Indicates that Tim- er B count has expired. This bit is set via the terminal count pulse generated by the timer when it termi- nates counting. TAExÐTimer A ExpiredÐ Same as TBEx except it refers to Timer A. 27. MSRÐMODEM/I/O PINS REGISTER MSRÐModem/I/O Pins Status Register 271072–40 This register holds the status of the Modem input pins (CTS, DCD, DSR, RI). It is the source of inter- rupts (MSR 0–3) for the MIR bit of GSR. If any of the above inputs change levels the appropriate bit in MODEM STATUS is set. Reading MODEM STATUS will clear the status bits. DCDCÐDCD ComplementÐHolds the comple- ment of the DCD input pin if programmed as an input in PMD. DRICÐHolds the complement of the RI input pin if programmed as an input in PMD. DSRCÐDSR ComplementÐHolds the complement of the DSR input pin if configured as an input in PMD. CTSCÐCTS ComplementÐHolds the complement of the CTS pin. DDCDÐDelta DCD ÐIndicates that the DCD input pin has changed state since this register was last read. DRIÐDelta RI ÐIndicates that there was a high-to- low transition on the RI input pin since the register was last read. DDSRÐDelta DSR ÐIndicates that the DSR input pin has changed state since this register was last read. DCTSÐDelta CTS ÐIndicates that the CTS input pin has changed state since this register was last read. COMMAND REGISTERS The command registers are write only; they are used to trigger an operation by the device. Once the oper- ation is started the register is automatically reset. There is a device level register as well as four block command registers. It is recommended that only one command be issued during a write cycle.

1. ICMÐINTERNAL COMMAND REGISTER ICMÐInternal Command Register 271072–41 This register activates the device’s general func- tions. SRSTÐDevice Software RESETÐ Causes a total device reset; the effect is identical to the hardware reset (except for strapping options). The reset lasts four clocks and puts the device into the Default Wake-up Mode. INTAÐInterrupt AcknowledgeÐ This command is an explicit acknowledgement of the M82510’s inter- rupt request. It forces the INT pin inactive for two clocks; afterwards, the INT pin may again go active if other enabled interrupts are pending. This command is provided for the Manual Acknowledge mode of the M82510. StCÐStatus ClearÐ Clears the following status reg- isters: RST, MSR, and TMST. PDMÐPower DownÐ This command forces the de- vice into the power-down mode. Refer to the func- tional description for details. 29. TCMÐTRANSMIT COMMAND REGISTER TCMÐTransmit Command Register 271072–42 This register controls the operation of the Transmit Machine. FTMÐFlush Transmit MachineÐ Resets the Transmit Machine logic (but not the registers or FIFO) and enables transmission. FTFÐFlush Transmit FIFOÐ Clears the Tx FIFO. TxENÐTransmit EnableÐ Enables Transmission by the Transmit Machine. TxDiÐTransmit DisableÐ Disables transmission. If transmission is occurring when this command is is- sued the Tx Machine will complete transmission of the current character before disabling transmission.

1. RCMÐRECEIVE COMMAND REGISTER RCMÐReceive Command Register 271072–43 This register controls the operation of the Rx ma- chine. RxEÐReceive EnableÐ Enables the reception of characters. RxDiÐReceive DisableÐ Disables reception of data on RXD pin. FRMÐFlush Receive MachineÐ Resets the Rx Machine logic (but not registers and FIFOs), enables reception, and unlocks the receive FIFO. FRFÐFlush Receive FIFOÐ Clears the Rx FIFO. LRFÐLocks Rx FIFOÐ Disables the write mecha- nism of the Rx FIFO so that characters subsequently received are not written to the Rx FIFO but are lost. However, reception is not disabled and complete status/event reporting continues. (This command may be used in the uLAN mode to disable loading of characters into the Rx FIFO until an address match is detected.) ORFÐOpen (Unlock) Rx FIFOÐ This command en- ables or unlocks the write mechanism of the Rx FIFO. 31. TMCRÐTIMER CONTROL REGISTER TMCRÐTimer Control Register 271072–44 This register controls the operation of the two M82510 timers. It has no effect when the timers are configured as baudÐrate generators. TGA and TGB are not reset after command execution. TGBÐTimer-B GateÐ This bit serves as a gate for Timer B operation: 1Ðenables counting 0Ðdisables counting TGAÐTimer-A GateÐ This bit serves as a gate for Timer-A operation: 1Ðenables counting 0Ðdisables counting STBÐStart Timer BÐ This command triggers timer B. At terminal count a status bit is set in TMST (TBEx). STAÐStart Timer AÐ This command triggers timer A. At terminal count a status bit is set in TMST (TAEx).

1. MCRÐMODEM CONTROL REGISTER MCRÐModem Control Register 271072–45 This register controls the modem output pins. With multi-function pins it affects only the pins configured as general purpose output pins. All the output pins invert the data, i.e. their output will be the comple- ment of the data written into this register. OUT0ÐOUT0 Output BitÐ This bit controls the OUT0 pin. The output signal is the complement of this bit. LCB Loopback Control BitÐ This bit puts the M82510 into loopback mode. The particular type of loopback is selected via the IMD register. OUT2ÐOUT2 Output BitÐ This bit controls the OUT2 pin. The output signal is the complement of this bit. OUT1ÐOUT1 Output BitÐ This bit controls the OUT1 pin. The output signal is the complement of this bit. RTSÐRTS Output BitÐ This bit controls the RTS pin. The output signal is the complement of this bit. DTRÐDTR Output BitÐ This bit controls the DTR pin. The output signal is the complement of this bit. DATA REGISTERS The data registers hold data or other information and may be accessed at any time. 33. TXDÐTRANSMIT DATA REGISTER TXDÐTransmit Data Register 271072–46 This register holds the next data byte to be pushed into the Transmit FIFO. For character formats with more than eight bits of data, or with additional com- ponents (S/W Parity, Address Marker Bit) the addi- tional data bits should be written into the TxF regis- ter. When a byte is written to this register its con- tents, along with the contents of the TxF register, are pushed to the top of the Transmit FIFO. This register is write only.

1. TXFÐTRANSMIT FLAGS REGISTER TxFÐTransmit Flags Register 271072–47 This register holds some additional components of the next character to be pushed into the Tx FIFO. The contents of this register are pushed into the Tx FIFO with the Transmit Data register whenever the TxD register is written to by the CPU. uLANÐuLAN Address Marker BitÐ This bit is transmitted in uLAN mode as the address marker bit. SPÐSoftware Parity BitÐ This bit is transmitted in S/W parity mode as the character’s parity bit. D8ÐNinth Bit of DataÐ In nine-bit character length mode this bit is transmitted as the MSB (D8) bit. 35. RXDÐRECEIVE DATA REGISTER RXDÐReceive Data Register 271072–48 This register holds the earliest received character in the Rx FIFO. The character is right justified and leading bits are zeroed. This register is loaded by the Rx Machine with the first received character. Read- ing the register causes the next register from the Rx FIFO to be loaded into RxD and RxF registers.

NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. ABSOLUTE MAXIMUM RATINGS Case Temperature under Bias ÀÀÀ b55§Ct o a125§C Storage Temperature ÀÀÀÀÀÀÀÀÀÀÀÀ b65§ to a150§C Voltage on V CC Pin (w.r.t. V SS)ÀÀÀÀÀÀb0.5V to a7V Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ250 mW Operating Conditions Symbol Description Min Max Units TC Case Temperature (Instant On) b55 a125 §C VCC Digital Supply Voltage 4.50 5.50 V DC SPECIFICATIONS DC CHARACTERISTICS (Over Specified Operating Conditions) Symbol Parameter Notes Min Max Units VIL Input Low Voltage (1) b0.5 0.8 V VIH1 Input High Voltage-Cerdip (1) 2.4 V CCa0.5 V VIH2 Input High Voltage-LCC (2) 2.6 V CCa0.5 V VOL Output Low Voltage (2), (8) 0.45 V VOH Output High Voltage (3), (8) 2.4 V ILI Input Leakage Current (4) g10 mA ILO 3-State Leakage Current (5) g10 mA ICC Power Supply Current (6) 3.8 mA/MHz ISTBY Standby Supply Current (9) 500 mA IOHR RTS, DTR Strapping Current (10) 0.4 mA IOLR RTS, DTR Strapping Current (11) 11 mA CIN Input Capacitance (7) 10 pF CIO I/O Capacitance (7) 10 pF CXTAL X1, X2 Load 10 pF NOTES: 1. Does not apply to CLK/X1 pin, when configured as crystal oscillator input (X1). @ IOL e 2 mA. 3. @ IOH eb 0.4 mA. 4. 0 k VIN k VCC. 5. 0.45V k VOUT k (VCC b 0.45). IOL e IOH e 0. 7. Freq e 1 MHz. 8. Does not apply to OUT2/X2 pin, when configured as crystal oscillator output (X2). 9. Same as 7, but input clock not running. 10. Applies only during hardware reset for clock configuration options. Strapping current for logic HIGH. 11. Applies only during hardware reset for clock configuration. Strapping current for logic LOW.

(Over Specified Operating Conditions) Testing Conditions: # All AC output parameters are under output load of 20 to 100 pF, unless otherwise specified. # AC testing inputs are driven at 2.4V for logic ‘1’ on CERDIP, 2.7V on LCC, and 0.45V for logic ‘0’. Output timing measurements are made at 1.5V for both a logical ‘0’ and ‘1’. # In the following tables, the units are ns, unless otherwise specified. System Interface SpecificationÐSystem Clock Specification: The M82510 system clock is supplied via the CLK pin or generated by an on-chip crystal oscillator. The clock is optionally divided by two. The CLK parame- ters are given separately for internal divide-by-two option ACTIVE and INACTIVE. The system clock (after division by two, if active) must be at least 16X the Tx or Rx baud rate (the faster of the two). SYSTEM CLOCK SPECIFICATIONS Symbol Parameter Min Max Notes DIVIDE BY TWO OPTIONÐACTIVE TCY/2 CLK Period 54 250 (2) TCLCH CLK Low Time 25 TCHCL CLK High Time 25 TCH1CH2 CLK Rise Time 10 (1) TCL2CL1 CLK Fall Time 10 (1) FXTAL External Crystal 4.0 18.432 Frequency Rating MHz DIVIDE BY TWO OPTIONÐINACTIVE TCY CLK Period 108 TCLCH CLK Low Tme 54 TCHCL CLK High Time 44 250 TCH1CH2 CLK Rise Time 15 (1) TCL2CL1 CLK Fall Time 15 (1) NOTES: 1. Rise/fall times are measured between 0.8 and 2.0V. 2. Tcy in ACTIVE divide by two option is TWICE the input clock period. RESET SPECIFICATION Symbol Parameter Min Max Notes TRSHL Reset WidthÐCLK/X1 Configured to CLK 8 T CY (1) TTLRSL RTS/DTR LOW Setup to Reset Inactive 6 T CY (2) TRSLTX RTS/DTR Low Hold after Reset Inactive 0 T CY b 20 (2) 271072–49 NOTES: 1. In case of CLK/X1 configured as X1, 1 Ms is required to guarantee crystal oscillator wake-up. 2. RTS/DTR are internally driven HIGH during RESET active time. The pin should be either left OPEN or externally driven LOW during RESET according to the required configuration of the system clock. These parameters specify the timing re- quirements on these pins, in case they are externally driven LOW during RESET. The maximum spec on TRSLTX requires that the RTS/DTR pins not be forced later than TRSLTX maximum.

Symbol Parameter Min Max Notes TRLRH RD Active Width 2 Tcy a 65 TAVRL Address/CS Setup Time to RD Active 7 TRHAX Address/CS Hold Time after RD Inactive 0 TRLDV Data Out Valid Delay after RD Active 2 Tcy a 65 TCIAD Command Inactive to Active Delay Tcy a 15 (1) TRHDZ Data Out Float Delay after RD Inactive 40 NOTE: 1. Command refers to either Read or Write signals. 271072–50 WRITE CYCLE SPECIFICATION Symbol Parameter Min Max Notes TWLWH WR Active Width 2 Tcy a 15 TAVWL Address CS Setup Time to WR Active 7 TWHAX Address and CS Hold Time after WR 0 TDVWH Data in Setup Time to WR Inactive 90 TWHDX Data in Hold Time after WR Inactive 12 271072–51 NOTE: Many of the serial interface pins have more than one function; sometimes the different functions have different timings. In such a case, the timing of each function of a pin is given separately.

SCLK PIN SPECIFICATIONÐ16x CLOCKING MODE Symbol Parameter Min Max Notes TXCY SCLK Period 216 TXLXH SCLK Low Time 93 TXHXL SCLK High Time 93 TXH1XH2 SCLK Rise Time 15 (1) TXL2XL1 SCLK Fall Time 15 (1) NOTE: 1. Rise/fall times are measured between 0.8V and 2.0V. SCLK PIN SPECIFICATIONÐ1x CLOCK MODE Symbol Parameter Min Max Notes TXCY SCLK Period 3500 TXLXH SCLK Low Time 1650 TXHXL SCLK High Time 1650 TXH1XH2 SCLK Rise Time 15 (1) TXL2XL1 SCLK Fall Time 15 (1) NOTE: 1. Rise/fall times are measured between 0.8V and 2.0V. RXD SPECIFICATION (1x MODE) Symbol Parameter Min Max Notes TRPW RXD Setup Time to SCLK High 250 TRPD RXD Hold Time After SCLK High 250 271072–52 TXD SPECIFICATION (1x MODE) Symbol Parameter Min Max Notes TSCLKTXD TXD Valid Delay after SCLK Low Ð 170 REMOTE LOOPBACK SPECIFICATION Symbol Parameter Min Max Notes TRXDTXD TXD Delay after RXD Ð 170

271072–53 Transmit Logic Diagram 271072–54 INTEL CORPORATION, 2200 Mission College Blvd., Santa Clara, CA 95052; Tel. (408) 765-8080 INTEL CORPORATION (U.K.) Ltd., Swindon, United Kingdom; Tel. (0793) 696 000 INTEL JAPAN k.k., Ibaraki-ken; Tel. 029747-8511 Printed in U.S.A./xxxx/0896/B10M/xx xx