MC8744H10

Intel Corporation

DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO

Manufacturer: Intel Corporation

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fev | | TT TTT TTT TTT PTT Tey yy swe | [| | TT TT | TT tT TT PPP suet [ws] w]v[wlwfafalelalalslele| | | | tt I | REV STATUS Pew | | | | | tte ty | tt ty oF Sets sweet | ttetstelsfelfel>[ofafelajuy PREPARED BY PMIC N/A Pa DEFENSE ELECTRONICS SUPPLY CENTER Lloro. Moan DAYTON, OHIO 45444 STANDARDIZED ' MILITARY VY DRAWING Ad?) aT MICROCIRCUIT, DIGITAL, HMOS, REMOTE UNIVERSAL PERIPHERAL INTERFACE, THIS DRAWING I: y, THIS DRauIne 1s avaiLasle YT) oy WY. 77961) mononitaic SILICON AND AGENCIES OF THE DRAWING APPROVAL DATE 1 DEPARTMENT OF DEFENSE “— 92-05-22 SIZE CAGE CODE 5962-89971 AMSC N/A REVISION LEVEL A 67268 SHEET 1 oF 27 DESC FOR 195 “ oe Jul 91 uek ry DISTRIBUTION STATEMENT A. Approved for public retease; distribution is unlimted.

SCOPE 1.1 Scope. This draving forms @ part of a one part - one part number documentation system (see 6.6 herein). Two Product assurance classes consisting of military high reliability (device classes B, @, and M) and space application (device classes S$ and V), and a choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). Device class M microcircuits represent non-JAN class 8 microcircuits in accordance with 1.2.1 of MIL-STD-883, “Provisions for the use of HIL-STU-883 in conjunction with compliant non-JAN devices". When available, a choice of radiation hardness assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN shall be as shown in the following example: 5962 - 89971 o1 s x x Federal RHA Device Device Case Lead stock class designator type class outline finish \\ / (see 1.2.3) Vi ! Drawing number 1.2.1 Radiation hardness assurance (RHA) designator. Device classes M, B, and S RHA marked devices shell icc c the HIL-N-38510 specified RHA levels and shall be Rarked with the appropriate RHA designator. Device classes @ ond V RHA marked devices shall meet the MIL-I-38535 specified RHA levels and shall be marked with the appropriate [Hh designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) shall identify the circuit function as follows: Device type Generic number Circuit function Frequency a1 8744H~10 Remote universal peripheral interface 10 MHz 1.2.3 Device class designator. The device class designator shall be a single Letter identifying the product assurance Level as follows: Device class Device requirements documentation LJ Vendor self~certification to the requirements for non-JAN class 8 microcircuits in accordance with 1.2.1 of MIL-STD-883 Bors Certification and qualification to MIL-~H-38510 Qorv Certification and qualification to M{L-I-38535 1.2.4 Case outline(s). For device classes M, B, and S, case outline(s) shall meet the requirements in appendix C of MIL-M-38510 and as Listed below. for device classes Q and V, case outline(s) shall meet the requirements of NIL-1-38535, appendix ¢ of NIL-H-38510, and as Listed below. Outline letter Case outline Q D-S (40-lead, 2.096" x 620" x 225") dual-in Line package 5962-89971 STANDARDIZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER LEVEL T DAYTON, OHIO 45444 REVISION SHEE’ - | DESC FORM .93A JUL 9!

1.2.5 Lead finish. ihe lead finish shall be as specified in MIL-M-38510 for classes M, 8, and S or MIL-1-38535 for classes Q and V. Finish letter "x" shall not be marked on the microcircuit or its packaging. The "x" designation is for use in specifications when lead finishes A, 8, and C are considered acceptable and interchangeable without preference. 1.3 Absolute maximum ratings. 1/ Vee supply voltage with respect to ground (V<.) (except EA) - - ~ -0.5 V to #7.0V Maximum power dissipation(Py) = ~~ =~ - === === 5555-7 2.00 1.4 Recommended operuting conditions. ~~ Supply voltage, Veg ttt 5.0 V 10% Minimum high Level input voltage yp: Frequency = - - = ---~---- 5-70 r reer 10 MHz i 1.5 Digital logic testing for device classes @ and V. Fault coverage measurement of manufacturing 2. APPLICABLE DOCUMENTS 2.1 Government specifications, standards, bulletin, and handbook. unless otherwise specified, the following specifications, standards, bulletin, and handbook of the issue Listed in that issue of the Department of Defense Index of Specifications and Standards specified in the solicitation, forma part of this drawing to the extent specified herein. — SPECIFICATIONS MILITARY MIL-M-38510 - MNicrocircuits, General Specification for. - MIL-1-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDAROS MILITARY HIL-STD-480 = Configuration Control-Engineering Changes, Deviations and Waivers. MIL-STD-883 - Test Methods and Procedures for Microelectronics. 41/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended _ operation at the maximum levels may degrade performance and affect reliability. 2/ Values will be added when they become available. SIZE 5962-89971 STANDARDIZED A MILITARY DRAWING _ DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHTO 45444 REVISTON LEVEL | SHEET DESC FORM 193A JUL 91 —

MIL-BUL~103 - List of Standardized Military Drawings (smD's). anoBooK MILITARY MIL-HDBK-780 - Standardized Military Drawings. (Copies of the specifications, standards, bulletin, and handbook required by manufacturers in connection with specific acquisition functions should be obtained from the contracting activity or as directed by the contracting activity.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing shall take precedence. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device class M shall be in accordance with 1.2.1 of } HIL-STD-883, “Provisions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices" end es specivind | herein. The individual item requirements for device classes 8 and $ shall be in accordance with Ml -f- 2640 (ch oe specified herein. For device classes B and S$, a full electrical characterization table for each device typo chell be included in this SMD. The individual item requirements for device classes Q and V shall be in accordance witli t MIL-1-38535, the device manufacturer's Quality Management (QM) plan, and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as | ‘specified in MIL-N-38510 for device classes M, B, and S and MIL-I-38535 for device classes Q and V and herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Block diagram. The block diagram shall be as specified on figure 2. 3.2.4 Radiation exposure circuit. The radiation exposure circuit shall be specified when available. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified tn table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein, Marking for device class M shall be in accordance with MIL-STO-883 (see 3.1 herein). In addition, the manufacturer's PIN may also be marked as Listed in MIL-AUL-103. Marking for device classes 8 and S shall be in accordance with MIL-M+38510. Marking for device classes Q and V shall be in accordance with MIL-1-38535. SIZE 5962-89971 | STANDARDIZED A MILITARY DRAWING a DEFENSE ELECTRONICS SUPPLY CENTER ; DAYTON, OHIO 45444 REVISION LEVEL | SHEET DESC FORM 193A JUL 91

3.5.1 Certification/compliance mark. The compliance mark for device class M shall be a "C" as required in MIL-STD-883 (see 3.1 herein) The certification mark for device classes B and $ shall be a "J" or “JAN" as required _ in MIL-M-38510. The certification mark for device classes Q and V shall be a "QML" as required in MIL-I-38535.

3.6 Certificate of compliance For device class M, a certificate of compliance shall be required from a

manufacturer in order to be listed as an approved source of supply in MIL-BUL-103 (see 6.7.3 herein). For device classes Q@ and V, a certificate of compliance shall be required from a QML-38535 Listed manufacturer in order to supply to the requirements of this drawing (sce 6.7.2 hercin). The certificate of compliance submitted to DESC-ECC — prior to listing as an approved source of supply for this drawing shall affirm that the manufacturer's product meets, for device class M the requirements of MIL-STD-883 (see 3.1 herein), or for device classes Q and V, the requirements of MIL-1-38535 and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required for device class M in MIL-STD-883 (see 3.1 herein) or device classes 8 and S in MIL-M-38510 or for device classes Q and V in MIL-I-38535 shall be provided — with each lot of microcircuits delivered to this drawing. 3.8 Notification of chanye for device class M. For device class M, notification to DESC-ECC of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change as defined in MIL-STD-480. 3.9 Verification and review for device class M. for device class M, DESC, DESC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. — 3.10 Microcircuit group assignment for device classes M, 8, and S$. Device classes M, B, and $ devices covered hy this drawing shall be in microcircuit group number 105 (see MIL-M-38510, appendix E). 3.11 Serialization for device class $. All device class $ devices shall be serialized in accordance with | MIL-M-38510. i _ 3.12 Processing EPROM's. ALL testing requirements and quality assurance provisions herein shall be satisfied by the manufacturer prior to delivery. 3.12.1 Erasure of EPROM's. When specified, devices shall be erased in accordance with the procedures and _ characteristics specified in 4.5. 3.12.2 Programmabi lity of EPROM's. when specified, devices shall be programmed to the specified pattern using . the procedures and characteristics specified in 4.6 and table III. 3.12.3 Verification of erasure of programmability of EPROM's. When specified, devices shall be verified as either programmed to the specified pattern or erased. As a minimum, verification shall consist of performing a functional test (subgroup 7) to verify that all bits are in the proper state. Any bit that does not verify to be ‘in the proper state shall constitute a device failure, and shall be removed from the lot. 5962-89971 | — STANDARDIZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER EET DAYTON, OHIO 45444 REVISION LEVEL | SHI 5 DESC FORM 195A JUL 91

TABLE T. Electrical performance characteristics. ee | i ] i] f Test | Symbol | Conditions 4/ |Group a Limits unit | | ~55°C ST, S$ 4125°C |subgroups | | { | | Vee = 5.0 V 210% | | Min | Max ! unless otherwise specified | | ] ] ! 1 Output low voltage [Vo Mee = 45 Vy, 11,2,3 4 | 0.45 | Vv ports 1, 2, 3 | IViy = Yay in, Vay max, | | | 1 { Hoy = 118 aa by | 1 | | ! ! ! ] ] | Output low voltage [Vor 4 IWog 4.5 V, 1,2,3 | | 0.45 | v ports 0, ALE, | [Vig = Yay min, Vay max, | | i | PSEN | [oy = 2.4 ma by | | | ! } ! t ] ] ] Output high voltage [Voy Vee = 4.5 V, 11,2,3 | 2.4 | {ov ports 1, 2, 3 | Win = Ypq min, Vyp max, | | 1 | i [oq = 88 na ! i I | | } ! ] ] | Output high voltage [Vous Veg = 4.5, 23 | 2.4 | Iv | port 0, ALE, I IVin = Ypy Min, Vay max, | I | | | PSEN | How = -HBo ux | I 1 1 en a Logical O input My 1Vyy 2 0.45 V y 11,2,3 | | 500 | yA current ports | | I | | | PE 7 SSN RRO SES ] | ] ] ] | Input high current |Tyyq IMiy 7 Veg “165 V 11,2,3 | | 500 | MA —forreser Input leakage Wey 10.45 V < Viy < Veg \\1,2,3 | | 2125 | pA bors I] ] l ] ! l Logical O input Wau IVyy = 0.45 V 11,2,3 | | -15 | oma a CS SS Power supply [lee [Veg 2 5.5 V, 1,2,3 | | 300 | ma current | Wyy = 5.3.¥ | | | l es ee ee ee ee eT Say Logical 0 input | [XTALT = Veg, \\1, 2,3 -3.5 mA current XTAL2 jt WWyp = 0.48 | | | \\ a a NUNES OSCR SS Logical input (yy | 1,23 | | 500 {HA Sc RS SO See footnotes at end of table. SIZE 5962-89971 | STANDARDIZED A | MILITARY DRAWING J | DEFENSE ELECTRONICS SUPPLY CENTER | DAYTON, OHIO 45444 REVISION LEVEL SHEET 4 } DESC FORM 193A - JUL 91

TABLE I. Electrical performance characteristics - Continued. — | | i] | ! Test | symbol | Conditions 1/ |Group A Limits unit | | 55°C s T, $ #125°C [subgroups | i] | | | Veg = 5-0 V #10% | | Min | Max | | __ | unless “sthervise specified | of = ] ] i} | | | Capacitance of [yg [Test frequency = 1 MHz 4/ | 4 | | 10 | pF 1/0 buffer | I | fl t | ae es en Sn Se Ss Seeeees Functional test | |See 4.4.1b [78 | | ALE pulse width Ionut |See figure 3 v 19, 10, 11 fate ¢,-40 | | ns ~ a SE Se Address setup to Itaver |See figure 3 sy 19, 10, 11 | teyey-40 | [as ALE [ I | I | i] = Address hold after [tii gy |see figure 3 y 19, 10, 19 | teye,-35 | ns | Ee i ee ee Sein en eee i 1 1 1 1 t ALE to valid Instr |tiiyy |See figure 3 sv |9, 10, 11 | [4teuep-150 | ns | a NN ALE to PSEN Itupe |See figure 3 v 9 10, 11 | te e_-25 | [ns | — | | i [ PSEN pulse width Itoepn |See figure 3 sv 19, 10, 11 [3te, ¢,-60 | 9s PSEN to valid Instr [tp ry |See figure 3 ay |9, 10, 11 | [3tqq-150 | ns In } | | i} Input Instr hold toxix See figure 3 s/ 9, 10,11 | 0 | [ns after PSEN ] | | ] Input Instr_float |eoxte |see figure 3 5s |9, 10, 11 | topep-20 | ons after PSEN —_ — ! ! Address valid Itpyay [See figure 3 vs 9,10, 11 | tag-8 | | ns after PSEN Address to valid Itayay |See figure 3 s/ |9, 10, 11 | [Ste qp-150 | ns Address float to \\tazeb |See figure 3 s/ \\9, 10, 11 | 25 | | ns PSEN —— — ] 1 ! | } RD pulse width tetrH |see figure 3 By 19, 10, 11 J6t¢, ¢,-700] [ns _ SS Dn Ce RS See footnote at end of table. SIZE 5962-89971 STANDARDIZED A MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 4544G REVISION LEVEL | SHEET - DESC FORM 193A JUL 91

TABLE I. Electrical performance characteristics - Continued. a Test | Symbot | Conditions 1/ |Group A Limits Unit | | -55°C S Te 5 #125°C |subgroups | | | | Veg = 5-0 v £10% | | Sin | Max | t unless “Gtherwise specified — I ] i] I i] WR pulse width Hyeyn |See figure 3 3/ 19, 10, 11 [6tey ¢,-100] [ons a es ee ec Sen Sees ee Address hold after Its ay |See figure 3 23s 19, 10, 11 | tepe,-35 | | ns ALE RD to valid ls |s f 3 sy \\9 10, 11 | |s 165 | 0 vali ee figure , 10, terer 716 ns ata in. Rov 9 2 ‘eLel! | | | Data hold after TenDx See figure 3 / {9, 10,11 | 0 | | ns RD. | | | t i] ! data float after lupe See figure 3 2s 5/ |9, 10, 11 l2tepey-70|ons RO ALE to valid tuipv [See figure 3 sv [9, 10, 11 | [Btqycp-150 | ons Data In a Addréss to tavov See figure 3 Ea {9, 10, 11 [9tergp-165. | ns valid Data In ~ oe oe } 1 | | ALE to WR or RD fescue |see figure 3 bya ls, 10, 14 |3t¢q ep -50 [5t eyo, 750 ns Address to UR Itave See figure 3 vy |9, 10, 11 |4te, 64-130] | ns or RD WR oF RO high to tunth [See figure 3 y 19, 10, 19 | tepey-50 | teycy #50 ns ALE high — + — i] | | Data valid to UR tovux [See figure 3 sv 9, 10, 11 | tercr-70 | | ons transition = oka setup before |e \\see figure 3 y lo. 10, 11 lreex 1501 | ns | | | Data hold after Itynax |See figure 3 sy [9, 10, 11 | te 6-50 | | ns ur address float after |tai a7 |See figure 3 2 ss 19, 10, 11 | ! 2 | ns Ro. - ! | ! i] | T Data clock Itocy |See figure 3 s/ |, 10,11 | 500 | | ns See footnotes at end of table. | 5962-89971 STANDARDIZED 7 MILITARY DRAWING ~ DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET 8 DESC FORM 193A JUL FL

TABLE I. Electrical performance characteristics - Continued. I ] | | | Test | symbol | Conditions 1/ |Group A Limits unit | | 95°C = Te = #125°C [subgroups ] | } i | | Veg = 5-0 Vv #10% | [Min | Max | unless otherwise specified | | | bata clock low Iyee |See figure 3 s/ ]9, 10,11 [ 180 | | ns Data clock high Itoey [See figure 3 s/ lo, 10,11 | 100 | | ns Transmit data Iti |see figure 3 sy 9, 10, 1 | 180 | ons delay | | } Data setup time —|tysp—s‘| See figure 3 s/ 9,10, 11] 40 | ns | | } | Data hold tine Ityys _-—*([See figure 3 5/ 910,11] 40 | | ns

1 Ineo 4 | | | |

Oscillator period §— tere, See figure 3 s/ |9, 10,11} 100 | 167 | ons. | if i — ] | | ] } | High tine Itcucx [See figure 3 av \\9, 10,117] 20 | | ns | wl. co ee Low time ltacx |eue figure 3 s/ |9, 10, 11 | 20 | | ns _ oo, | . i] ! Rise time toc [See figure 3 s/ 9, 10, 11 20 ns Fall time leone |see figure 3 2s 5/ ls, 10, 11 | 20 | ns . 4/ ALL testing to be performed using worst case conditions, unless otherwise specified. _ 2/. Vo, is degraded when the device rapidly discharges external capacitance. This ac noise is most pronounced doting emission of address data. When using external memory, locate the latch or buffer as close to the device as possible. 4s See 4.4.16. 5/ Output Load capacitance, ¢,, for port 0, ALE, PSEN outputs is 100 pF. Load capacitance for all other outputs 18 80 PF. 1/tgy g, = 6 MHZ tO 10 MHz. — SIZE 5962-89971 STANDARDIZED A MILITARY DRAWING —— _ DEFENSE ELECTRONICS SUPPLY CENTER | DAYTON, OHTO 45444 REVISION LEVEL | SHEET Tl) FORM 193A

4 DATA/TOX P34 34 ver EA

FIGURE 1. Terminal_connections.

FIGURE 2. Block diagram.

STATE 4} STATE S| state 6 | STATE 1| STATE 2] starr INTERNAL 3) STATE 4] stare 5 cuocK ms [ee es |e2 jes | e2 es [re are ri [ee v1 | ee a] pe we Ee THESE SIGNALS ARE NOT ACTIVATED (TEANAL_PROGRAM MEMORY FETCH QURING THE EXECUTION OF A HOVX EXTERNAL PROGRAM MEMORY FETCH INSTRUCTION PORN eT Po our JOATAl DATA PCL OUT] DATA Poe ‘SAMPLED AMPA SAMPLED FLOAT Float P2 (ExT) INDICATES ADOAESS TRANSITIONS { ae | 5 ; ; PCL OUT (IF proty.t: 1 OOH IS EMITTED MEMORY 1S EXTERKAL) PO OPL OR AL NG THIS PERLOO| DATA {___ ouT SAMPLED FLOAT SS re INOICATES DPH OR P2 SFA TRANST WALTE CYCLE To PCH TIONS Ca es A rere PCL OUT (EVEN IF PROGRAM MEMORY IS INTERNAL fo PLR Ra pe Data OUT POL OUT IIE PmoaruM INDICATES OPH DA P2 SFR TO PCH TRANSITIONS PORT OPERATION HOV PORT, SRC OLD DATA [New DATA PO PINS SAMPLED Wov DEST.PO ra FA WOW DEST. PORT (4. BP, P5) PO PINS SAMPLED {INCLUDES INTO, INT4, 70, Ta) P4, P2, P3 PINS SAMPLED 4, P2,P3 SEAT ney SHIET clock PIRS SaHPLED (MODE 0) ‘AXD Sal AXD SAKPLED This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however, ranges from 50 ns to 150 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propagation also varies from output to output and component to component. Typically though, (T, = 25°C, fully loaded) RD and WR propagation delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the ac specifications. | FIGURE 3. Switching test circuit and waveforms. | | 5962-89971 | STANDARDIZED 4

4 MILITARY DRAWING

y DEFENSE ELECIRONICS SUPPLY CENTER | DAYTON, OHIO 45444 REVISION LEVEL | SHEET wo! DESC FORM 193A JUL 9.1

FIGURE 3. Switching test circuit and waveforms - Continued.

AC Testing Input, Output, Float Waveforms. FIGURE 3. Switching test circuit and waveforms - Continued.

FIGURE 3. Switching test circuit and waveforms - Continued.

QUALITY ASSURANCE PROVISIONS 4.1 Sampling and inspection. for device class M, sampling and inspection procedures shall be in accordance with section 4 of MIL-M-38510 to the extent specified in MIL-STD-883 (see 3.1 herein). For device classes B and Ss, sampling and inspection procedures shall be in accordance with MIL-M-38510 and method 5005 of MIL-STD-883, except as modified herein. For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-I-38535 and the device manufacturer's QM plan. — 4.2 Screening. for device class M, screening shalt be in accordance with method 5004 of MIL-STD-833, and shall be conducted on all devices prior to quality conformance inspection. For device classes @ and S, screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to qualification and quality conformance inspection. For device classes Q and V, screening shall be in accordance with MIL-I-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. — 4.2.1 Additional criteria for device classes M, B, and S. a. Burn-in test, method 1015 of MIL-STD-883. a) Test condition A, 8, C, or D. For device class M, the test circuit shall be submitted to DESC-ECC for review with the certificate of compliance. For device classes 8 and S$, the test circuit shall be submitted to the qualifying activity. = (2) Th = +125°C, minimum. i b. Interim and final electrical test parameters shall be as specified in table IIA herein. ¢. A data retention stress test shall be included as part of the screening procedure and shall consis¢ ot _ following steps: Margin test_method A. (1) Program greater than 95 percent of the bit locations, including the slowest programming cell (see 3.12.2), The remaining cells shall provide a worst case speed pattern. _ (2) Bake, unbiased, for 72 hours at +140°C to screen for data retention Lifetime. . (3) Perform a margin test using Vy = *5.9 V at +25°C using loose timing (i.e., tace > 7 us). (4) Pertorm dynamic burn-in (see 4.2.14). 7 (5) Margin at Vy = 5.9 V. : (6) Perform electrical tests (see 4.2). (7) Erase (see 3.12.1), except devices submitted for groups A, B, C, and D testing. (8) Verify erasure (see 3.12.3). ~ SIZE 5962-89971 - STANDARDIZED A MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER ET DAYTON, OHIO 45444 REVISION LEVEL | SHEET =, _ DESC FORM 193A JUL 31

Margin test_method B. (1) Program at 25°C, 100 percent of the bits. (2) Bake, unbiased, for 24 hours at 250°C. (3) Perform margin test at Vy = 5.9 V. (4) Erase (see 3.12.1). (5S) Perform interim electrical tests in accordance with table IIA. (6) Program 100 percent of the bits and verify (see 3.12.2) (7) Perform burn-in (see 4.2.14), (8) One-hundred percent test at 25°C (group A, subgroups 1 and 7). Vy = 5.9 V with loose timing, apply PDA. (9) Perform remaining final electrical subgroups and group A testing. (10) Erase. Devices may be submitted for groups B, C, and 0 at this time. (11) Verify erasure (see 3.12.3). Steps 1 through 4 are performed at wafer Level. | 4.2.2 Additional criteria for device classes @ and V. | a. The burn-in test duration, test condition and test temperature or approved alternatives shell be es | specified in the device manufacturer's QM plan in accordance with MIL-1-38535. The burn-in (cst cituit { shall be submitted to DESC-ECC with the certificate of compliance and shall be under the control of the device manufacturer's Technology Review Board (TRB) in accordance with MIL-I-38535. b. Interim and final electrical test parameters shall be as specified in table IIA herein. ¢. Additional screening for device class V beyond the requirements of device class @ shall be as specified in appendix B of MIL-I-38555 and as detailed in table 1iB herein. . 4.3. Qualification inspection. 4.3.1 Qualification inspection for device classes B and §. Qualification inspection for device classes B and S shall be in accordance with MIL-M-38510. Inspections to be performed shalt be those specified in method 5005 of 4.3.2 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in accordance with MIL-1-38535. Inspections to be performed shall be those specified in MIL-1-38535 and 4.4 Conformance inspection. Quality conformance inspection for device class M shall be in accordance with MIL-STD-883 (see 3.1 herein) and as specified herein. Quality conformance inspection for device classes B and S shall be in accordance with MIL-M-38510 and as specified herein. Inspections to be performed for device classes M, B, and § shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections MIL-1-38535 including groups A, B, C, D, and E inspections and as specified herein except where option 2 of MIL-I-38535 permits alternate in-line control testing. 5962-89971 STANDARDIZED MILITARY DRAWING : DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL ) SHEET | DESC FORM 193A JUL 91

TABLE IIA. Electrical tect requirements. ee ee | Test | Subgroups | Subgroups | | requirements | (per method 5005, table 1) | (per mIL-1-38535, | | be cab — | [device [Device [Device [Device [device | | Iclass ictass [class Iclass Iclass | " {8 Ls Q v [Interim etectrical | | 11, 7,9 | 11, 7,9 | ~ (see 4.2) 1 Gsee 4.4) lou loa loa Imo mow | (see 4.4) In u u 10,11 10,14 I | | 1 | | [Group B end-point I { |2, 8a, 10 | | { (see 4.4) ! | ] ] ] | ] [Group ¢ end-point l2, 8a, 10 |2, 8a, 10] 12, 8a, 10 | 2, ga, 10 | = (see 4.4) ft [Group D end-point |2, 8a, 10 {2, 8a, 10 |2, 8a, 10 l2, 8a, 10 |2, 8a, 10 | _ (see 4.4) I i ! ] | | [Group & end-point |2, 8a, 10 2, 8a, 10 2, Ba, 10 |2, Ba, 10 (|2, 8a, 10 | _ | parameters | | | | ii if 1/ POA applies to subgroup 1. 2/ POA applies to subgroups 1 and 7. ~ 4.4.1 Group A inspection. a. Tests shall be as specified in table IIA herein. b. For device class M, subgroups 7 and 8 tests shall consist of verifying the EPROM pattern specified and _ instruction set. The instruction set forms a part of the vendor's test tape and shall be maintained and available from the approved source of supply. For device classes B and S, subgroups 7 and 8 tests shall include verification of the device functionality (including verification of EPROM pattern specified and instruction set). For device classes @ and V, subgroups 7 and 8 shall include verifying the functionality of the device; these tests shall have been graded in accordance with HIL-STD-883, test method 5012 (see 1.5 — herein). ©. Subgroup 4(Cjq measurements) shall be measured only for the initial test and after process or design changes which may affect input capacitance. A minimum sample size of five devices with zero rejects shall be required. _ SIZE 5962-89971 STANDARDIZED A MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET be DESC FORM 193A “~ JUL 91

TABLE IIB. Additional screening for device class V. eee T T I 1 Test MIL-STD-883, test method Lot requirement i [Particle impact | 2020 | 100% | noise detection | | - | { [Internal visual |2010, condition A or | 100% | {eared atternae ft | | [Nondestructive | 2023 or | 100% | bond pull approved alternate Reverse bias burn-in 1015, 100% Burn-in 1015, total of 240 hours 100% | at +125°C } | Radioyraphic 2012 100%. | 4.4.2 Group B inspection. The group B inspection end-point electrical parameters shall be as specified in teble IIA herein, 4.4.3 Group ¢ inspection. The group C inspection end-point electrical parameters shall be as specificd in tuble LIA herein. 4.4.3.1 Additional criteria for device classes M, B, and $. Steady-state life test conditions, method 1005 of MIL-STD-883: a. Test condition C or D. For device class M, the test circuit shall be submitted to DESC-ECC for review with the certificate of compliance. For device classes B and S, the test circuit shall be submitted to the qualifying activity. . bo Ty +125°C, minimum, ¢. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. d. ALL devices selected for testing shall be programmed with a checkerboard pattern ar equivalent. After completion of all testing, the devices shall be erased and verified. 4.4.3.2 Additional criteria for device classes Q and V. The steady-state Life test duration, test condition and test temperature or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-I-38535. The steady-state life test circuit shall be submitted to DESC-ECC with the certificate of compliance and shall be under the control of the device manufacturer's TRB in accordance with MIL-I-38535. 4.4.4 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein. 5962-89971 STANDARDIZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL | SHEET DESC FORM 193A JUL 9h

4.4.5 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured (see 3.5 herein). RHA levels for device classes 8B, S, Q@, and V shall be M, D, R, and ti and for device class M shall be M and D. RHA quality conformance inspection sample tests shall be performed at the RHA level specified in the acquisition document. a. RHA tests for device classes 8 and $ for levels M, D, R, and H or for device class M for levels M and D shall be performed through each Level to determine at what levels the devices meet the RHA requirements. These RHA tests shall be performed for initial qualification and after design or process changes which may affect the RHA performance of the device. : b. End-point electrical parameters shall be as specified in table IIA herein. ~ c. Prior to total dose irradiation, each selected sample shall be assembled in its qualified package. It shall pass the specified group A electrical parameters in table I for subgroups specified in table IIA herein. d. For device classes M, B, and S, the devices shall be subjected to radiation hardness assured tests as — specified in MIL-M-38510 for RHA level being tested, and meet the postirradiation end-point electrical parameter Limits as defined in table I at T, = +25°C 25 percent, after exposure. e. Prior to and during total dose irradiation testing, the devices shall be biased to establish a worst case condition as specified in the radiation exposure circuit. — f. For device classes M, B, and $, subgroups 1 and 2 in table V, method 5005 of MIL-STD-883 shall be tested as appropriate for devtce construction. g- When specified in the purchase order or contract, a copy of the RHA delta Limits shall be supplied. 4.5. Erasing procedure. the reconmendgd erasure procedure is exposure to ultraviolet Light (at 2537 Angstrons) to an integrated dose of at least 15 W-s/cm* rating for 20 to 30 minutes, at a distance of about 1 inch, should be _ sufficient. 4.6 Programming procedures. The programming characteristics in table III and the following procedures shall be used for programming the device: a. Connect the device in the electrical configuration (see figure 4) for programming. The waveforms of figure a & and progranming characteristics of table III shall apply. b. Initially and after each erasure, alt bits are in the high "H" state. To be programmed, the device must be running with a 4 to 6 HHz oscillator. The address of an EPROM Location to be programmed is applied to port be held low, and P2.7 and RST high. (These are all TTL Levels except RST, which requires 2.5 v tor high). _ EA/Vp, is held normally high, and is pulsed to #21 V. While EA/Vpp is at 21 V, The ALE/PROG pin, which is normally being held high, is pulsed low for 50 ms. The EA/Vpp is'returned to high. SIZE 5962-89971 : STANDARDIZED A MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER SHEET DAYTON, OHIO 45444 REVISION LEVEL 21 DESC FORM 153A

TABLE II1. Programming and verification characteristics. | ] | symbot | Parameter 1/ | fin | Max Units | ! | | \\Vpp [Programming supply voltage 25 | as | ov | | 1 : | / | | [pp [Programming current | | 30 | om | | | Wee, {Oscillator frequency | 4 6 wiz | | — Tenax Address hold after PROG Bt | ns __ | lewven loate setup to PROG Bt | [ons | --s- tt — | tou Data hold after PROG 48tcvop | ns i —_— | tensH ENABLE high to Vpp Broun | as | Isuee. [Vp setup to PROG 10 | | us touch [PROG width 45 58 as | Tavev Address to data valid Bt | as | terov ENABLE to data valid 48t ccc ns 1/ The following conditions apply during programming and verification: a. Veg 2 OV eo. 21°C 4 Taree d. See figure 4 5962-89971 STANDARDIZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, ORIO 45444 REVISION LEVEL | SHEET i 1 on DESC FORM 193A JUL 91

FIGURE 4. EPROM programming configuration and waveforms.

Programming Verification Configuration +5V AQOA I= pi v 000H- eof--—— PGM DATA OFFFH - Ag=AGi peg (USE 10K PULLUPS) P2.4 LT ea's ALE TTL HIGH = Ch pag ENABLE 2.7 — XTAL2 EA 4-6 MHz(_] AST VIH4 XTAL1 = -BSEN Programming Configuration +5V 7 poor. =A7_) P v : 0000H- py Pt ce 4 OFFFH P2.0 AB-ASS pa 3 PO PGM DATA P2.4 — LT p's ALE ALE PROG — UC) peg ; TTL HIGH P2.7 = _ XTAL2 EA EA/vpe ; 4-6 MHz(-] RST VIHt ' XTAL1 BEN 1 | I Veg 1 ; FIGURE 4. EPROM programming configuration and waveforms - Continued. A ; ‘SIRE 5962-89971 | | STANDARDIZED a ; ; MILITARY DRAWING | «DEFENSE ELECTRONICS SUPPLY CENTER a REVISION CEvEL | SHRET i , :

PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-M-38510 for device tO classes M, B, and § and MIL-I-38535 for device classes @ and V. # 6. NOTES ? 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit _ applications (original equipment), design applications, and logistics purposes 6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-prepared specification or drawing. 6.1.2 Substitutability. Device classes B and Q devices will replace device class M devices. 5 6.2 Configuration control of SMD's. ALL proposed changes to existing SHD's will be coordinated e_ with the users of record for the individual documents. This coordination will be accomplished in i accordance with MIL-STD-481 using 0D Form 1693, Engineering Change Proposal (Short Form). i 6.3 Record of users. Military and industrial users shall inform Defense Electronics Supply Center : when a system application requires configuration control and which SMO's are applicable to that system. DESC will : maintain a record of users and this List will be used for coordination and distribution of changes to the drawings. - Users of drawings covering microelectronic devices (FSC 5962) should contact DESC-ECC, telephone (513) 296-6022. i é 6.4 Comments. Comments on this drawing should be directed to DESC-ECC, Dayton, Ohio 45444, or telephone (513) P 296-8526. i 6.5 Symbols, definitions, and functional descriptions. , Symbol Type Name_and Description ADO-AD7 1/0 Port 0 (P0.0-P0.7): Port 0 is an 8-bit open drain ! bidirectional 1/0 port. It is also the multiplex low-order { address and data bus when using external memory. It is used for data output during program verification. Port 0 can } sink/source six LS TTL loads. H i vo Port 1 (P1.0-P1.7): Port 1 is an 8-bit quasi-bidirectional } 1/0. It is used for the low-order address byte during : program verification. Port 1 can sink/source four LS TTL i loads. RTS (P1.6) 0 Request-to-Send output: A low indicates that the device is ready to transmit. + CTS (P1.7) I Clear-to-Send input: A low indicates that a receiving station is ready to receive. _ i i f SIZE 5962-89971 - STANDARDIZED A MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER VEL SHEET DAYTON, OHIO 45444 REVISION LE 25 ' | _ DESC FORM 135A :

Symbol Type Name_and Description A8-A1S 1/0 Port 2 (P2.0-P2.7): Port 2 is an B-bit quasi-bidirectional 1/0 port. It also emits the high-order address byte when accessing external memory, It is used for the high-order address and the control signals during program verification. Port 2 sink/source four LS TIL loads. 1/0 Port 3 (P3.0-P3.7): Port 3 is an 8-bit quasibidirectional 1/0 port. It also contains the interrupt, timer, serial port, and RD and WR pins that are used by various options. The output Latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. Port 3 can sink/source four LS TTL loads. 1/0 RxD (P3.0) 1 In point-to-point or multipoint configurations, this pin controls the direction of pin P3.1. Serves as Receive Data input in loop and diagnostic modes. DATA TxD (P3.1) 0 In point-to-point or multipoint configurations, this pin functions as data input/output. In loop mode, it serves as transmit pin. A “O" written to this pin enables diagnostic mode. INTO (P3.2) I Interrupt 0 input or gate control input for counter 0. | INT? (P3.3) I Interrupt 1 input or gate control input for counter 0. H TO (P3.4) 1 Input to counter 0. | SCLK T1 (P3.5) I In addition to 1/0, this pin provides input to counter 1 or serves as SCLK (serial clock) input. GR ¢P3.6) ° WRITE: The write control signal Latches the data byte from port 0 into the external data memory. . RO (P3.7) ° READ: The read control signal enables external data memory to port 0. ast 1 A high on this pin for two machine cycles while the oscillator is running resets the device. A small external pull-down resistor (= 8.2 ka) from RST to Vee permits pover- on reset when capacitor (= 10 yf) is also connected from this pin to Veg. ec ALE/PROG ° Provides Address Latch Enable output used for latching the address into external memory during normal operation. It is activated every six oscillator periods except during an external data memory access. It also receives the program pulse input for programming the device. 5962-89971 STANDARDIZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHTO 45444 REVISION LEVEL | SHEET DESC COR LA

Synbol Type Name_and Description PSEN ° The program Store Enable output is a control signal that enables the external Program Memory to the bus during external fetch operations. It is activated every six ~ oscillator periods, except during external data memory accesses. Remains high during internal program execution. EAVpp 1 When held at a TTL high level, the device executes instructions from the internal ROM when the PC is less than 4096. When held at a TTL low Level, the device fetches all ~ instructions from external Program Memory. The pin also receives the 21 V EPROM programming supply voltage on the _ device. XTALT I Input to the oscillator’s high gain amplifier. Required — when a crystal is used. Connected to V.. when external source is used on XTAL2. XTAL2 i) Output from the oscillator's amplifier. Input to the internat timing circuitry. A crystal or external source can be used. — . { 6.6 One part = one part number system. The one part - one part number system described below has been developed | to allow for transitions between identical generic devices covered by the four major microcircuit requiremcnis | — documents (MIL-M-38510, MIL-H-38534, MIL-I-38535, and 1.2.1 of MIL-STD-883) without the necessity for the generation | of unique PIN's. The four military requirements documents represent different class levels, and previously when _ device manufacturer upgraded military product from one class level to another, the benefits of the upgraded product were unavailable to the Original Equipment Manufacturer (OEH), that was contractually locked into the orig itil unique PIN. By establishing a one part number system covering all four documents, the OEM can acquire to the _ highest class level available for a given generic device to meet system needs without modifying the original contract parts selection criteria. Example PIN Manufacturing Document Military documentation format under_new system source Listing Listing . New MIL-H-38510 Military Detail 5962-8997122(B or S)YY —GPL-38510 MIL-BUL-103 Specifications (in the SMD format) (Part 1 or 2) New MIL-H-38534 Standardized Military 5962-899712Z(H or K)YY ——QML-38534 MIL-BUL-103 Drawings _ New MIL-I-38535 Standardized Military 5962-8997122(Q or V)YY ——QNL-38535 MIL-BUL-103 Drawings _ New 1.2.1 of MIL-STD-883 Standardized — 5962-8997122(H)YY MIL-BUL~103 MIL-BUL-103 Military Drawings — 6.7 Sources of supply. 4.7.1 Sources of supply for device classes B and $. Sources of supply for device classes B and S are listed in aPL-38510. 6.7.2 Sources of supply for device classes @ and V. Sources of supply for device classes @ and V are Listed in QHL=38535- The vendors Listed in OML-38535 have submitted a certificate of compliance (see 3.6 herein) to DESC-ECC _ and have agreed to this drawing. 6.7.3 Approved sources of supply for device class H. Approved sources of supply for class M are Listed in _ HIL-BUL-103. The vendors Listed in MIL-BUL-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by DESC-ECC. SIZE 5962-89971 _ STANDARDIZED A MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER — DAYTON, OHIO 45444 REVISION LEVEL SHEET - DESC FORM 193A . 7 JUL, 91

STANDARDIZED MILITARY DRAWING SOURCE APPROVAL BULLETIN . DATE: 92-05-14 — Approved sources of supply for SMD 5962-89971 are Listed below for immediate acquisition only and shall be added to MIL-BUL-103 during the next revision. MIL-BUL-103 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been — submitted to and accepted by DESC-ECC. This bulletin is superseded by the next dated revision of MIL-BUL-103. | ] } | |Standardized | Vendor | Vendor | |mititary drawing | cae | similar | — |PIN | number =| PIN 4/ ij 5 ee Se Seca | — | | I I | 5962-8997101Hax | 34649 | Mc8744H-10 | 5 cs Seen 5 — 4/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the — performance requirements of this drawing. Vendor CAGE Vendor name number and address —

34649 Intel Corporation —

3065 Bowers Avenue

Santa Clara, CA 95051 Point of contact: 5000 W. Chandler Blvd - Chandler, AZ 85226 TO T _ | The information contained herein is disseminated for convenience only and | | the Government assumes no liability whatsoever for any inaccuracies in this | | information bulletin. il — SS

Product Information

MC8744H10 specifications and overview.

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DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO

Description

DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO

Source title MC8744H10 Datasheet(PDF) - Intel Corporation

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