M87C196KC INTEL | Alldatasheet
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*Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. February 1996COPYRIGHT © INTEL CORPORATION, 1996 Order Number: 271116-005 M87C196KC/M87C196KD 16-BIT HIGH-PERFORMANCE CHMOS MICROCONTROLLERS WITH ON-CHIP EPROM Special Environment M87C196KCÐ16 KBytes EPROM, 512 Bytes RAM M87C196KDÐ32 KBytes EPROM, 1024 Bytes RAM Y M87C196KC: 16 MHz Operation Y M87C196KD: 16 and 20 MHz Operation Y Register-to-Register Architecture Y 28 Interrupt Sources/16 Vectors Y Peripheral Transaction Server Y 1.4 ms 16 x 16 Multiply (20 MHz) Y 1.75 ms 16 x 16 Multiply (16 MHz) Y 2.4 ms 32/16 Divide (20 MHz) Y 3.0 ms 32/16 Divide (16 MHz) Y Powerdown and Idle Modes Y Five 8-Bit I/O Ports Y 16-Bit Watchdog Timer Y Available in 68-Lead PGA and 68-Lead Ceramic Quad Flatpack Packages Y Dynamically Configurable 8-Bit or 16-Bit Buswidth Y Full Duplex Serial Port Y High Speed I/O Subsystem Y 16-Bit Timer Y 16-Bit Up/Down Counter with Capture Y 3 Pulse-Width-Modulated Outputs Y Four 16-Bit Software Timers Y 8- or 10-Bit A/D Converter with Sample/Hold Y HOLD/HLDA Bus Protocol Y Product Grades Ð SE1 (QML): b55§Ct o a125§C Ð SE2 (QML): b40§Ct o a125§C (M87C196KD only) The M87C196KC/KD 16-bit microcontroller is a high performance member of the MCS É-96 microcontroller family. The M87C196KC/KD is an enhanced M80C196KB device with on-chip RAM and EPROM. Intel’s CHMOS III-E process provides a high performance processor along with low power consumption. Four high-speed capture inputs are provided to record times when events occur. Six high-speed outputs are available for pulse or waveform generation. The high-speed output can also generate four software timers or start an A/D conversion. Events can be based on the timer or up/down counter. For bus design information, configuration, and programming, please see the 8XC196KC/8XC196KD User’s Manual (order Ý272238). MCSÉ-96 is a registered trademark of Intel Corporation.
Figure 1. M87C196KC/KD Block Diagram
82 E A
91 V CC
Figure 2. Pin Definitions
Figure 3. 68-Pin Grid Array Pinout
Figure 4. 68-Pin Ceramic Quad Flatpack
VCC Main supply voltage (5V). VSS Digital circuit ground (0V). There are three V SS pins, all of which must be connected. VREF Reference voltage for the A/D converter (5V). V REF is also the supply voltage to the analog portion of the A/D converter and the logic used to read Port 0. Must be connected for A/D and Port 0 to function. ANGND Reference ground for the A/D converter. Must be held at nominally the same potential as VSS. VPP Timing pin for the return from powerdown circuit. Connect this pin with a 1 mF capacitor to VSS a n da1M X resistor to V CC. If this function is not used V PP may be tied to V CC. This pin is the programming voltage on the EPROM device. XTAL1 Input of the oscillator inverter and of the internal clock generator. XTAL2 Output of the oscillator inverter. CLKOUT Output of the internal clock generator. The frequency of CLKOUT is (/2 the oscillator frequency. RESET Reset input to the chip. BUSWIDTH Input for buswidth selection. If CCR bit 1 is a one, this pin selects the bus width for the bus cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH i sa0a n 8-bit cycle occurs. If CCR bit 1 is a 0, the bus is always an 8-bit bus. NMI A positive transition causes a vector through 203EH. INST Output high during an external memory read indicates the read is an instruction fetch. INST is valid throughout the bus cycle. INST is activated only during external memory accesses and output low for a data fetch. EA Input for memory select (External Access). EA equal to a TTL-high causes memory accesses to locations 2000H through 5FFFH to be directed to on-chip EPROM. EA equal to a TTL-low causes accesses to those locations to be directed to off-chip memory. ALE/ADV Address Latch Enable or Address Valid output, as selected by CCR. Both pin options provide a signal to demultiplex the address from the address/data bus. When the pin is ADV , it goes inactive high at the end of the bus cycle. ALE/ADV is activated only during external memory accesses. RD Read signal output to external memory. RD is activated only during external memory reads. WR/WRL Write and Write Low output to external memory, as selected by the CCR. WR will go low for every external write, while WRL will go low only for external writes where an even byte is being written. WR /WRL is activated only during external memory writes. BHE/WRH Bus High Enable or Write High output to external memory, as selected by the CCR. BHE e 0 selects the bank of memory that is connected to the high byte of the data bus. A0 e 0 selects the bank of memory that is connected to the low byte of the data bus. Thus accesses to a 16-bit wide memory can be to the low byte only (A0 e 0, BHE e 1), to the high byte only (A0 e 1, BHE e 0), or both bytes (A0 e 0, BHE e 0). If the WRH function is selected, the pin will go low if the bus cycle is writing to an odd memory location. BHE /WRH is valid only during 16-bit external memory write cycles.
PIN DESCRIPTIONS (Continued) Symbol Name and Function READY Ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory, or for bus sharing. When the external memory is not being used, READY has no effect. Two of them (HSI.2 and HSI.3) are shared with the HSO Unit. HSO Outputs from High Speed Output Unit. Six HSO pins are available: HSO.0, HSO.1, HSO.2, Port 0 8-bit high impedance input-only port. These pins can be used as digital inputs and/or as analog inputs to the on-chip A/D converter. Port 1 8-bit quasi-bidirectional I/O port. Port 2 8-bit multi-functional port. All of its pins are shared with other functions in the M87C196KC. Ports 3 and 4 8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the multiplexed address/data bus which has strong internal pullups. HOLD Bus Hold input requesting control of the bus. HLDA Bus Hold acknowledge output indicating release of the bus. BREQ Bus Request output activated when the bus controller has a pending external memory cycle.
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings * Case Temperature Under Bias ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b55§Ct o a125§C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b65§Ct o a150§C Voltage On Any Pin to V SSÀÀÀÀÀÀÀÀb0.5V to a7.0V Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W NOTICE: This data sheet contains preliminary infor- mation on new products in production. The specifica- tions are subject to change without notice. Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. OPERATING CONDITIONS Symbol Description Min Max Units TC (SE1) Case Temperature (Instant On) b55 a125 §C TC (SE2) Case Temperature (Instant On) b40 a125 §C VCC Digital Supply Voltage 4.50 5.50 V VREF Analog Supply Voltage 4.50 5.50 V FOSC Oscillator Frequency 3.5 16 MHz FOSC Oscillator Frequency (M87C196KD-20 only) 3.5 20 MHz NOTE: ANGND and V SS should be nominally at the same potential. DC Characteristics (Over Specified Operating Conditions) Symbol Description Min Max Units Test Conditions VIL Input Low Voltage b0.5 0.8 V VIH Input High Voltage (Note 1) 0.2 V CC a 1.0 V CC V VIH1 Input High Voltage on XTAL 1, EA 0.7 V CC VCC V VIH2 Input High Voltage on RESET 2.32 V CC V VOL Output Low Voltage 0.3 V I OL e 200 mA 0.45 V I OL e 2.8 mA
1.5 V I OL e 7m A
VOL1 Output Low Voltage 0.8 V IOL ea 0.4 mA in RESET on P2.5 (Note 2) NOTES: 1. All pins except RESET, XTAL1 and EA. 2. Violating these specifications in Reset may cause the part to enter test modes.
DC Characteristics (Over Specified Operating Conditions) (Continued) Symbol Description Min Max Units Test Conditions VOH Output High Voltage V CC b 0.3 V I OH eb 200 mA (Standard Outputs) V CC b 0.7 V I OH eb 3.2 mA VCC b 1.5 V I OH eb 7m A VOH1 Output High Voltage V CC b 0.3 V I OH eb 10 mA (Quasi-bidirectional Outputs) V CC b 0.7 V I OH eb 30 mA VCC b 1.5 V I OH eb 60 mA VOH2 Output High Voltage 2.0 V IOH eb 0.8 mA in RESET on P2.0 (Note 7) ILI Input Leakage Current (Std. Inputs) g10 mA0 k VIN k VCC b 0.3V ILI1 Input Leakage Current (Port 0) g3 mA0 k VIN k VREF ITL 1 to 0 Transition Current (QBD Pins) b650 mAV IN e 2.0V IIL Logical 0 Input Current (QBD Pins) b70 mAV IN e 0.45V IIH Logical 1 Input Current (NMI Pin) 250 mAV IN e VCC b 0.3V ICC Active Mode Current in Reset 75 mA XTAL1 e 16 MHz 93 mA XTAL1 e 20 MHz IREF A/D Converter Reference Current 5 mA V CC e VPP e VREF e 5.5V IIDLE Idle Mode Current 30 mA IPD Powerdown Mode Current 70 mAV CC e VPP e VREF e 5.5V RRST Reset Pullup Resistor 6K 65K X VCC e 5.5V, V IN e 4.0V CS Pin Capacitance (Any Pin to V SS)1 0 p F NOTES: (Notes apply to all specifications) 1. QBD (Quasi-bidirectional) pins include Port 1, P2.6 and P2.7. 2. Standard Outputs include AD0–15, RD ,W R , ALE, BHE , INST, HSO pins, PWM/P2.5, CLKOUT, RESET, Ports 3 and 4, TXD/P2.0, and RXD (in serial mode 0). The V OH specification is not valid for RESET. Ports 3 and 4 are open-drain outputs. 4. Maximum current per pin must be externally limited to the following values if V OL is held above 0.45V or V OH is held below V CC b 0.7V: IOL on Output pins: 10 mA IOH on quasi-bidirectional pins: self limiting IOH on Standard Output pins: 10 mA 5. Maximum current per bus pin (data and control) during normal operation is g3.2 mA. 6. During normal (non-transient) conditions the following total current limits apply: Port 1, P2.6 I OL:2 9m A I OH is self limiting HSO, P2.0, RXD, RESET IOL:2 9m A I OH:2 6m A P2.5, P2.7, WR , BHE IOL:1 3m A I OH:1 1m A AD0–AD15 I OL:5 2m A I OH:5 2m A RD, ALE, INST–CLKOUT I OL:1 3m A I OH:1 3m A 7. Violating these specifications in Reset may cause the part to enter test modes.
Figure 5. I CC and I IDLE vs Frequency For use over specified operating conditions.
- If max is exceeded, additional wait states will occur.
- If wait states are used, add 2 T
OSC * N, where N e number of wait states.
- Test Conditions: Capacitive load on all pins e 100 pF, Rise and fall times e 10 ns, F OSC e 16 MHz.
AC Characteristics (Continued) For user over specified operating conditions. The M87C196KC/KD will meet these specifications: Symbol Description Min Max Units Notes FXTAL Frequency on XTAL1 3.5 16 MHz KC/KD-16 3.5 20 MHz KD-20 TOSC 1/FXTAL 62.5 286 ns KC/KD-16 50 286 ns KD-20 TXHCH XTAL1 High to CLKOUT High or Low 10 110 ns TCLCL CLKOUT Cycle Time 2 T OSC ns TCHCL CLKOUT High Period T OSC b 10 T OSCa20 ns TCLLH CLKOUT Falling Edge to ALE Rising b51 5 n s TLLCH ALE Falling Edge to CLKOUT Rising b29 a15 ns TLHLH ALE Cycle Time 4 T OSC ns (Note 3) TLHLL ALE High Period T OSC b 10 T OSCa15 ns TAVLL Address Setup to ALE Falling Edge T OSC b 15 TLLAX Address Hold after ALE Falling Edge T OSC b 49 ns TLLRL ALE Falling Edge to RD Falling Edge T OSC b 36 ns TRLCL RD Low to CLKOUT Falling Edge 0 30 ns TRLRH RD Low Period T OSC b 5 ns (Note 3) TRHLH RD Rising Edge to ALE Rising Edge T OSC TOSC a 25 ns (Note 1) TRLAZ RD Low to Address Float 15 ns KC-16 30 ns KD-16/20 TLLWL ALE Falling Edge to WR Falling Edge T OSC b 10 ns TCLWL CLKOUT Low to WR Falling Edge 0 25 ns TQVWH Data Stable to WR Rising Edge T OSC b 23 TCHWH CLKOUT High to WR Rising Edge b10 15 ns TWLWH WR Low Period T OSC b 30 ns (Note 3) TWHQX Data Hold after WR Rising Edge T OSC b 30 ns TWHLH WR Rising Edge to ALE Rising Edge T OSC b 10 T OSC a 15 ns (Note 1) TWHBX BHE, INST after WR Rising Edge T OSC b 10 ns TWHAX AD8–15 HOLD after WR Rising T OSC b 50 ns (Note 2) TRHBX BHE, INST after RD Rising Edge T OSC b 10 ns TRHAX AD8–15 HOLD after RD Rising T OSC b 25 ns (Note 2) NOTES: 1. Assuming back-to-back bus cycles. 2. 8-Bit bus only. 3. If wait states are used, add 2 T OSC * N, where N e number of wait states. 4. Test Conditions: Capacitive load on all pins e 100 pF, Rise and fall times e 10 ns, F OSC e 16 MHz.
Figure 6. System Bus Timings
- To guarantee recognition at next clock.
Figure 9. HOLD /HLDA Timings
Figure 13. Serial Port WaveformÐShift Register Mode
AC EPROM Programming Characteristics Operating Conditions: Load Capacitance e 150 pF, T A ea 25§C g5§C, V CC,V REF e5V, VSS, ANGND e 0V, V PP e 12.50V g0.25V, EA e 12.50V g0.25V Symbol Description Min Max Units TSHLL Reset High to First PALE Low 1100 T OSC TLLLH PALE Pulse Width 50 T OSC TAVLL Address Setup Time 0 T OSC TLLAX Address Hold Time 100 T OSC TPLDV PROG Low to Word Dump Valid 50 T OSC TPHDX Word Dump Data Hold 50 T OSC TDVPL Data Setup Time 0 T OSC TPLDX Data Hold Time 400 T OSC TPLPH(2) PROG Pulse Width 50 T OSC TPHLL PROG High to Next PALE Low 220 T OSC TLHPL PALE High to PROG Low 220 T OSC TPHPL PROG High to Next PROG Low 220 T OSC TPHIL PROG High to AINC Low 0 T OSC TILIH AINC Pulse Width 240 T OSC TILVH PVER Hold after AINC Low 50 T OSC TILPL AINC Low to PROG Low 170 T OSC TPHVL PROG High to PVER Valid 220 T OSC NOTES: VPP e 12.50V. 2. This specification is for the Word Dump Mode. For programming pulses, use 300 T OSC a 100 ms. DC EPROM Programming Characteristics Symbol Description Min Max Units IPP VPP Supply Current (When Programming) 100 mA NOTE: VPP must be within 1V of V CC while V CC k 4.5V. V PP must not have a low impedance path to ground of V SS while VCC l 4.5V.
by ultraviolet light erasure. cause erasure when exposed to direct sunlight. for erasure should be a minimum of 15 Wsec/cm 2. Figure 14. Slave Programming Mode Data Program Mode with Single Program Pulse
10-BIT A/D CHARACTERISTICS The speed of the A/D converter in the 10-bit mode can be adjusted by setting a clock prescaler on or off. At high frequencies more time is needed for the comparator to settle. The maximum frequency with the clock prescaler disabled is 6 MHz. The conver- sion times with the prescaler turned on or off is shown in the table below. The AD ÐTIME register has not been characterized for the 10-bit mode. The converter is ratiometric, so the absolute accura- cy is dependent on the accuracy and stability of V REF.V REF must be close to V CC since it supplies both the resistor ladder and the digital section of the converter. A/D CONVERTER SPECIFICATIONS The specifications given below assume adherence to the Operating Conditions section of this data sheet. Testing is performed with V REF e 5.12V. Clock Prescaler On Clock Prescaler Off IOC2.4 e 0 IOC2.4 e 1 156.5 States 89.5 States 19.5 ms @ 16 MHz 29.8 ms @ 6 MHz Parameter Typical (3) Minimum Maximum Units * Notes Resolution 1024 1024 Levels 10 10 Bits Absolute Error 0 g8 LSBs Full Scale Error g3 LSBs Zero Offset Error g3 LSBs Non-Linearity 0 g8 LSBs Differential Non-Linearity Error lb1 a2 LSBs Channel-to-Channel Matching 0 g1 LSBs Repeatability g0.25 LSBs Temperature Coefficients: Offset 0.009 LSB/ §C Full Scale 0.009 LSB/ §C Differential Non-Linearity 0.009 LSB/ §C Off Isolation b60 dB 1, 2 Feedthrough b60 dB 1 VCC Power Supply Rejection b60 dB 1 Input Resistance 750 1.2K X DC Input Leakage 0 3.0 mA Sample Time: Prescaler On 16 States Prescaler Off 8 States Input Capacitance 3 pF NOTES: *An ‘‘LSB’’, as used here, has a value of approximately 5 mV. 1. DC to 100 KHz. 2. Multiplexer Break-Before-Make Guaranteed. 3. Typical values are expected for most devices at 25 §C.
8-BIT MODE A/D CHARACTERISTICS The 8-bit mode trades off resolution for a faster con- version time. The AD ÐTIME register must be used when performing an 8-bit conversion. The following specifications are tested @ 16 MHz with OA6H in AD ÐTIME. Sample Time Convert Time
20 States 56 States
A6H in AD ÐTIME 9.8 ms @ 16 MHz Parameter Typical Minimum Maximum Units * Notes Resolution 256 256 Levels 8 8 Bits Absolute Error 0 g2 LSBs Full Scale Error g1 LSBs Zero Offset Error g2 LSBs Non-Linearity 0 g2 LSBs Differential Non-Linearity Error lb1 a1 LSBs Channel-to-Channel Matching g1 LSBs Repeatability g0.25 LSBs Temperature Coefficients: Offset 0.003 LSB/ §C Full Scale 0.003 LSB/ §C Differential Non-Linearity 0.003 LSB/ §C NOTES: *An ‘‘LSB’’, as used here, has a value of approximately 20 mV. 1. Typical values are expected for most devices at 25 §C.
M87C196KC DESIGN INFORMATION M87C196KC Enhanced Feature Set over the M80C196KB 1. The M87C196KC has twice the RAM of the M80C196KB and 16 Kbytes of EPROM. Also, a Vertical Register Windowing Scheme allows the extra 256 bytes of RAM to be used as registers. This greatly reduces the context switching time. 2. Peripheral Transaction Server (PTS). The PTS is an alternative way to service an interrupt, reducing latency and overhead. Each interrupt can be mapped to its PTS channel, which acts like a DMA channel. Each interrupt can now do a single or block transfer, without executing an interupt service routine. Special PTS modes exist for the A/D converter, HSI, and HSO. 3. Two extra Pluse Width Modulated outputs. The M87C196KC has added 2 PWM outputs that are functional- ly compatible to the 80C196KB PWM. 4. Timer2 Internal Clocking. Timer2 can now be clocked with an internal source, every 1 or 8 state times. 5. The A/D can now perform an 8- as well as a 10-bit conversion. This trades off resolution for a faster conversion time. 6. Additional On-chip Memory Security. Two UPROM (Uneraseable Programmable Read Only Memory) bits can be programmed to disable the bus controller for external code and data fetches. Once programmed, a UPROM bit cannot be erased. By shutting off the bus controller for external fetches, no one can try and gain access to your code by executing from external memory. 7. New Instructions. The M87C196KC has 5 new instructions. An exchange (XCHB/XCHW) instruction swaps two memory locations, an Interruptable Block Move Instruction (BMOVI), a Table Indirect Jump (TIJMP) instruction, and two instructions for enabling and disabling the PTS (EPTS/DPTS). M80C196KB TO M87C196KC DESIGN CONSIDERATIONS 1. Memory Map. The M87C196KC has 512 bytes of RAM/SFRs and 16K of EPROM. The extra 256 bytes of RAM will reside in locations 100H–1FFH and the extra 8K of EPROM will reside in loca- tions 4000H–5FFFH. These locations are exter- nal memory on the M80C196KB. 2. EPROM programming. The M87C196KC has a different programming algorithm to support 16K of on-board memory. 3. ONCE Mode Entry. The ONCE mode is entered on the M87C196KC by driving the TXD pin low on the rising edge of RESET. The TXD pin is held high by a pullup that is specified at 1.4 mA and remain at 2.0V. This Pullup must not be overrid- den or the M87C196KC will enter the ONCE mode. 4. During the bus HOLD state, the M87C196KC weakly holds RD, WR, ALE, BHE and INST in their inactive states. The 80C196KB only holds ALE in its inactive state. 5. A RESET pulse from the M87C196KC is 16 states rather than 4 states as on the 80C196KB (i.e., a watchdog timer overflow). This provides a longer RESET pulse for other devices in the sys- tem. 6. The CDE pin on the KB has become a V SS pin on the KC to support 16 MHz operation. M87C196KC ERRATA 1. Missed EXTINT on P0.7. The 80C196KC20 could possibly miss an EXTINT on P0.7. See faxback Ý2049. 2. HIS ÐMODE divide-by-eight. See Faxback Ý2192. 3. IPD hump. See Faxback Ý2311.
M87C196KD DESIGN INFORMATION M87C196KD Enhancements over the M87C196KC The M87C196KD is an enhanced, pin-for-pin compatible upgrade to the M87C196KC. The M87C196KD offers the same functionality, packages, and pin-outs as the M87C196KC with twice the on-chip EPROM and register RAM. 1. Doubling the on-chip EPROM to 32 KBytes allows for larger on-chip programs. 2. Doubling the on-chip RAM to 1000 bytes allows for faster and more optimized code execution. M87C196KC TO M87C196KD DESIGN CONSIDERATIONS Due to the added memory, a few memory-specific functions have been modified on the M87C196KD. 1. The AC characteristic RD Low to Address Float (TRLAZ) maximum has been increased from 15 ns on the M87C196KC to 30 ns on the M87C196KD. 2. The memory map is expanded to accommodate the additional memory. Because the added mem- ory resides in memory locations that were always external to the M87C196KC, M87C196KC code may have to be modified to run on the M87C196KD. 3. The vertical windowing map is extended to allow all 1000 bytes of register RAM to be windowed into the lower register file. 4. The M87C196KD has a different autoprogram- ming algorithm to support 32 KBytes of on-chip EPROM.
indicates the placement of the new bit. Figure 17. M87C196KD New SFR Bit
- Added M87C196KD information.
- Deleted the memory map figure. *
- Deleted the horizontal windowing figure. *
- Deleted the SFR bit summaries. *
- Added the new CLKOUT disable feature.
IH2 and I CC DC specifications.
- Modified the T LLYV,T LLGV,T RLDV,T RHDZ,
- Modified the T HALBZ and T HAHAX HOLD/HLDA
- Added the package thermal characteristics.
Ý272238) for this information.