M8751H-8

M8751H-8 INTEL | Alldatasheet

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range of baud rates available to the serial port. used for I/O and memory expansion. which expose the M8751H-8 to ambient light may require an opaque label over the window. *HMOS is a patented pracess of Intel Corporation. Figure 1. Block Diagram

intel ; Ma751H-8 PRELIMINARY . Figure 2. Pin Configurations . Supply voltage during programming, verification, and tour LS TTL inputs. ing programming and program verification. Port 3 can sink/source four LS TTL inputs.

nal pulldown resistor (~8.2 KM) from RST to Vss . external Program Memory. is activated twice a= . low in order to enable the device to fetch code from —_he observed. voltage (Vpp) during EPROM programming. Figure 3. Either a quartz orystal or ceramic resonator Degraded | VoL

INTEL CORP (UP/PRPHLS) 20F p @™ 4826175 0081773 3 intel Meste PRELIMINARY 49-19-59 ABSOLUTE MAXIMUM RATINGS* “Notice: Stresses above those listed under “Abso- Jute Maximum Ratings” may cause permanent dam- Case Temperature age to the device. This is a stress rating only and Voltage on Any Pin to Veg tional sections of this specification is not implied. Ex. Voltage from Vpp tO VSS vsvsseseveveeseees2t.ey tended periods may affect device ralabilty. : following tables are subject to change. Operating Conditions * Case Temperature (instanton) | —s5_ [+126 [tc Digital Supply Voltage [450 | sso [| D.C. CHARACTERISTICS (Over Specified Operating Conditions) [symbol] Parameter min | Max [unit] Comments | Input Low Voltage [-os] o7 [v[ oo Input Low Voltage to EA pof ov [vj InputHigh Voltage Except xTAL2, AST) | 22 [Voctos| v[ Input High Voltage to XTAL2, RST [ 26 [Voc +0.5| V [XTALI = Ves Output Low Voltage Ports 1,2,a(Notet) | | 048 |v fin =12ma_ Voit | Output Low Voltage Port 0, ALE, PSEN 0.60 | V |lo. = 2.8mA (Note 1) 048 | V |lol=24mA Output High Voltage Ports 1,2, 3 fea [ |v [lon=-s0na Voxi | Output High Voltage Port 0 (in External V |lon = —300 pA Bus Mode), ALE; PSEN Logical 0 input Gurrent Pt, P2, Pa || =s00 [nalvw=o4sv | Logical 0 input Current to EA/Vpp | | _ -15 [ma [Vin = 0.48V Logical 0 Input Current to XTAL2 [ _[_ -46 [ma |XTALI = Ves, Vin = 0.45V Input Leakage Current to Port 0 [| +126 [pa] 0.45V < Vin < Veo lim [Logical input CurenttoEA/Vep || 500 | wA|Vw=2av | Input Current to RST/Vpp to Activate Reset| | 600 _| wA | Vin < (Veo - 1.8) Ico Power Supply Current 276 mA | Ail Outputs Disconnected, EA = Voc Capacitance of 1/0 Butters [ [10 [pF [tp = 1 MHz, Ta = 26°C NOTES: “ 1. Capacitive loading on Ports 0 and 2 may cause spurious nolse pulses to be superimposed on the Vos of ALE and Ports 1 and 3, The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1-0-0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE line may exceed 0.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a ‘Schmitt Trigger STROBE input. . 10-18

INTEL CORP (UP/PRPHLS) 2oe D Mi 4426175 0041774 5 mv intel MS751H-8 | PRELIMINARY ~ T49- 19-59 A.C. CHARACTERISTICS (Over Specified Operating Conditions), Load Capacitance for Port 0, ALE, ” and PSEN = 100 pF; Load Capacitance for all other outputs = 80 pF ; EXTERNAL PROGRAM MEMORY CHARACTERISTICS | min [max [min [Max | | wrcrct | OscitatorFrequeney | | | as Te Me [mH | aterusowidtn | 105 || arcucu-ss | |r | tavit | Address vaidtoate | 70 [|| routes [ns | TAX | Address HoldateraLe | 75 | | rouci-so | | ns _| | muv | auetovatdinstrin = [| a6 || arouct-1e5 [ns | Tul | auetoPseN | as || toucu-ao [ne | Hac | Stews [a reece [ rev | PSENtoVaidinstin | | ato || stoci-t6es [ne | - | Texx | InputinstrHoldaterPBEN | o [| | oo | Te | texz | InputinstrFloatatterPSEN | | 90 | | rouci-35 | ne _| * [texav | PSENto Address Vaid | 100 | | tou-es | ns | taviv | Addresstovaidinstrin [| 40 | | atouct-165 [ns _| [_tiaz | PSENLowtoAddress riot [ [20 | [aon _| EXTERNAL DATA MEMORY CHARACTERISTICS [ome | renee are ae | [min [| max | min [Mex | | TwuwH | WrPusowidtn | aso || ercuct-100 | ne | tuLax | Address Hoidatterace | 76 | | rouct-so | | ne | tauov | RDtovaiddatain | [| ao [| srouci-tes [ne | | tAHOX | DataHodatterRO | o | | oT ns | | TRHOZ | DataFloatatterRD || tes | | arcucu-es | ns | | tov | AletovaidDatain | | eso | | etouci-170 | ne | | Tavov | AddresstoVaiddatan [| e4o | | arcuct-1e5 | ns | [ tiwe | AstoWRorAD | aio | 440 | arouci-es | sroici+es [ne | | tavwi | AddsstoWRorAD | ass [| arcuct-1as [ne | | Tovwx | DataValidtoWRTransition | 40 | | rouct-es [| ns | | TovwH | DetaSetuptoWRHign | 00 | | rrouci-75 [ns | + [TWHOX | OataHeldatterWA | 60 | | rouo-es [ns | | tRLAZ | FDtowtoAddress Fiat | | 20 [ | ao | ns | [_TWHLH | ROorwAnightoaueHigh | 60 | 190 | touct-e5 [ roici+es | ne | 10-19

INTEL CORP (UP/PRPHLS) 20E py mm 4826175 0081775 7 Me igi Me75iH8 PRELIMINARY - T'499-179-S9 A.C. TIMING DIAGRAMS : EXTERNAL PROGRAM MEMORY READ CYCLE TLHLL- 12 TeLce . ALE ‘TLLIV- . TAVLL| TLLPL, 7 nana pont 0 RSTRN)-{_AO=a7_)—KnsiR WPS AO-A7_)—{ NST - . -TAVIV- - : pont 2 SaBRT X_Anoness As—ars ADDRESS AB AIS . 2100806 EXTERNAL DATA MEMORY READ CYCLE . . TLLOV: ‘TWH: ALE a Pa porte aoa eo} ovran $5) TRLAZ . poRT2 ORS? "ADDRESS AB-A15 OR SFR-P2 : 0888-7 EXTERNAL DATA MEMORY WRITE CYCLE . rwno| “ALE aaa “ ——— a poe Pe ay porto” (na nour pont2 gots ‘ADDRESS AS-A1S OR SFR-P2 . 210653-8 10-20 Y |

INTEL CORP (UP/PRPHLS) eoe D @™ 462b175 OO8177b 9 a intel M8751H-8 PRELIMINARY . T:49-17-59 EXTERNAL CLOCK DRIVE CHARACTERISTICS (XTAL2) [symbol [Parameter [| Min. |= Max— | Units | | stoic. | Oscilator Frequency | 35 | =| SMC | toncx | Hightime =| | dts | toucx | towtime | |i ts | to.ch | isotime =| |S] [town | raitime dT CECT Cd 25: as 2.5 ‘ on aa ascss-s SERIAL PORT TIMING—SHIFT REGISTER MODE Load Capacitance = 80 pF preemie | ao [min [Max | Min [Max | [TxLxt_[Serial Port Clock CycioTime | 10 || varouce | ne | [TAVXH | Oulput Data Setup to ClockRisingEdge [1117| | toro.ci-t9a ns | [TXHGX | Output Data Hold after Clock Rising Edge| 193 [| etcuoL-117| |_| [TxHOX [inputDataHoldafter ClockRisingEdge | 0 | | 0 | ——*; ns ‘| [TxHDV [Clock Rising EdgetoinputDatavaia | [ait7] «| tTLGL—133| ns | SHIFT REGISTER TIMING WAVEFORMS “TUL onnonnnnAnrAnnrny Sm A es ps es OO bewelieme | orm ata, i CD GD GD GD GD Cn Gay / . 4 mee wl ole : ™ sour casa 2 CG CG =) SC) GSC SC) a CD. . 4 ue ° ™ 10-21

INTEL CORP (UP/PRPHLS) 20c D M™ 4426175 0081777 O mm” intel we751H-9 PRELIMINARY A.C. TESTING INPUT/OUTPUT, FLOAT WAVEFORMS: Input/Output Float a rT) Pr FLOAT TEST POINTS. 2a 20 20 24 ous os os 210658-9 oas. os on on 210859-10 ‘AC inputs during testing are driven at 2.4V for a logic "1" and 0.45V for a logic “O". Timing measurements are made at 2.0V for a logio "1" and '0,8V for a logle “0”. For timing purposes, the float state is dofinad as the point at which a PO pin sinks 2.4 mA or sources 400 iA at the vottage test levels. : CLOCK WAVEFORMS INTERNAL | svaTes | stares | stares | stave | starea | staves | stave | arate s | crock pr [eal or fer tortor ter| eztes| ez |r |e ter |r| rs | pe xm SLE ] u nn ee ee a Da exTeRN, MEMORY ACTIVATEO OURING THE EXECUTION OF A MOVX INSTRUCTION aan 1 —T— rr LS Po — ba, Sreroor_feral_Trecour|_fovral_frevour|_ “el EE PaEXT) TNDIGATES ADDRESS TRANSIONS rr READ CYCLE a ee PCL OUT (\\F PROGRAM , EMO eioD MEMORY 1g EXTERNAL) ROAR yu age pa —__—_-J_ INDICATES OPH OR P2SFRTOPCH TRANSITIONS L—_§_§ waite cvcte, rn _ ‘PCL OUT(EVEN IF PROGRAM MEMORY 1S INTERNAL) [orcona | fa po our. pata or. CL OUT (IF PROGRAM p2 ——--_—S__ INDICATES OPH OA P2 SFR TO PCH TRANSITIONS MEMORY TS EXTERNAL) PORT OPERATION ‘MOV PORT, SAC. oLoDATA[REWOATA Ss pape Mov DEST, PO Fa FA__ MOV DEST, PORT (P1, P2,P3) POPINS SAMPLED (wcLuDEs NTOLINTL TOTY Fey Fa 1.72.63 SERIAL PORT SHIFT CLOCK PPL Pa PINS SAMPLED |__PINSSAMPLED {MODE 0} "AKO SAMPLED "AXD SAMPLED 210683-11 ‘This diagram indicates when signals are clockad Internally. The timo It takos the signals to propagate to the pins, howaver, ranges from 25 to 426 ns, This propagation delay is dependent on variables such as temperature and pin loading. Propagation also varies from output to output ‘and component to component. 10-22

Table 1. EPROM Programming Modes . 1" = logle high for that pin . “0" = logic low for that pin ~ . To be programmed, the part must be running with a are shown in later sections of this data sheet. Programmed Into that location is applied to Port_0. and free of glitches. Table 1. ALE Is pulsed low for 50 ms to program the = Program Verification ALE Is to be pulsed. ‘Then EA is raised to +21V, . Figure 5. Programming Configuration Figure 6. Program Verification

INTEL CORP (UP/PRPHLS) 20E @@ 44eb175 0081779 4 mir intel wersine PRELIMINARY programming operation. The address of the Program ory. While it is programmed, the internal Program Memory location to be read is applied to Port 1 and Memory cannot be read out, the device cannot be- pins P2.0-P2.3, The other pins should be:held at the -.. further programmed, and it cannot execute out of “Verify” levels indicated in Table 1. The contents of external program memory. Erasing the EPROM, the addressed location will come out on Port 0. Ex- __ thus clearing the ‘Security Bit, restores the device's ternal pullups are required on Port 0 for this opera- full functionality. It can then be reprogrammed. - tion. . The setup, which is shown in Figure 6, is the same — - + wpe as for programming the EPROM except that pin P2.7 Xe“DOWT CAREY is held at a logic low, or may be used as an active- ~ . low read strobe. " wer a *e EPROM Security x 723 west The security feature consists of a “locking” bit which ra as ALPROG . when programmed denies electrical access by any ms 0 me PULSE TO GMD external means to the on-chip Program Memory. ma The bit is programmed as shown in Figure 7. The veto) ar wi b—iavrr setup and procedure are the same as for normal wvua . EPROM programming, except that P2.6 is held at a oe | at vet logic high, Port 0, Port 1, and pins P2.0-P2.3maybe |. a in any state. The other pins should be held at the CI = . “Security” levels indicated in Table 1. ve . Once the Security Bit has been programmed, it can 210053-16 be cleared only by full erasure of the Program Mem- . Figure 7. Programming the Security Bit EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS Ta = 28°C, Voc = 5V £10%, Veg = OV . [“symbor [Parameter | win_ | Max [Unite Programming SuppiyVotage | 208 [ats |v | top | Programming Supply Curent [| go | ma wToicl | Oseilator Frequency ee ee Address SeuptoPAGGLow | aeroce [| Adress Hold after PROG aro, | | Tovar | dataseuptoPAOGiow | aerate [| Data Hold after PROG | aru | | TEHSH P2.7 (ENABLE) High to Vep aroce || Cid sid TSHGL VepSouptoPROGLow [to | ns T@HSL Vep Hold after PROG a ee ee PROG width ee ee [_tavav | “AddresstoDatavais || aero TeLav | ERABUELowtDatavaid [| aorcuce | [_tenaz | pataFioatanerenmste || aercuce | 10-24

INTEL CORP (UP/PRPHLS) 20e D WM 4426175 0081760 0 mm” intel ‘ M8751H-8 PRELIMINARY : — T99-19-5F Erasure Characteristic: 19 recommended erasure procedure is exposure id to ultraviolet light (at 2537 Angstroms) to an integrat- Erasure of the EPROM begins to occur when the ed dose of at least 15 W-sec/cm2. Exposing the chip is exposed to light with wavelengths shorter © EPROM to an ultraviolet lamp of 12,000 wW/cm2 than approximately 4,000 Angstroms. Since sunlight rating for 20 to 30 minutes, at a distance of about 1 and fluorescent lighting have wavelengths in this inch, should be sufficient. range, exposure to these light sources over an ex- tended time (about 1 week in sunlight, or 3 years in Erasure leaves the array in an all 1s state. room-level fluorescent lighting) could cause inadver- tent erasure. if an application subjects the device to this type of exposure, it is suggested that an opaque label be placed over the window. . EPROM PROGRAMMING AND VERIFICATION WAVEFORMS .- PROGRAMMING VERIFICATION P2023 ( » { . Tovar TaHOX TAVGL TGHAX ‘ ALE PROT TsHOL Tons. TaLGH . avs sv TILHGH Two Tm Won TL Mal Ewer ‘ TEHSH — TELQV | TEHOZ Par 21085316 For Programming Conditions See Figure 8. For Verification Conditions See Figure 6. 10-25

INTEL CORP (UP/PRPHLS) ece pm” 4YB2b175 0061741 2 mm Wiel M8751H-8 PRELIMINARY TF ST . Table 1. MCS®-51 Instruction Set Description : ARITHMETIC OPERATIONS LOGICAL OPERATIONS (Continued) . Mnemonic Description Byte Cyc Mnemonic ° Deseription Byte Cyc . ADD AAA Add register to ORL A,@RI OR indirect RAM to Accumulator 1 1 Accumulator 1 1 ADD Adirect Add direct byte to ORLA,#data © OR immediate data to Accumulator 2 1 Accumulator 2 1 ADD A,@RI Add Indirect RAM to. ORL direct,A OR Accumulator to Accumulator 1 1 direct byte “2 1 ADDA,#data - Add immediate data to ORL direct,#data OR immediate data to Accumulator 2 1 direct byte 3 2 ADOC A,Rn Add register to XRLA,An Exclusive-OR register to Accumulator with Carry 1 1 Accumulator 1 1 ADDC A,direct Add direct byte to A XAL Adirect ‘Exclusive-OR direct “ . . with Carry flag 2 1 byte to Accumulator 2-1 ADDCA,@RI Add indirect RAM to A. . XRL A,@RI Exclusive-OR Indirect with Carry flag 14 RAMtoA 104 ADDCA,#data Add immediate data to XRL A,#data Exclusive-OR Awith Cany flag 2 1 immediate data to A 2 1 ‘SUBBA,An ‘Subtract register from A XRL direct,A Exclusive-OR Accumu- with Borrow 1 1 Jator to direct byte 2 1 ‘SUBB A,direct ‘Subtract direct byte XRL direct,#data Exclusive-OR im- from A with Borrow 2 1 mediate data to direct 3 2 ‘SUBBA,@RI ‘Subtract Indirect RAM CLRA Clear Accumulator 1 1 from A with Borrow: 1 1 CPLA Complement SUBBA,#data Subtract immed data Accumulator 1 1 from A with Borrow 2 1 RLA Rotate Accumulator Left 1 1 INCA {Increment Accumulator 1 1 RLCA Rotate A Left through INC Ra ‘Increment regiater 1 1 the Carry flag 1 1 INC direct Increment direct byte 2 1 RRA Rotate Accumulator INC @RI Increment Indirect RAM 1 1 Right 1 1 INC DPTR Increment Data Pointer 1 2 RRC A Rotate A Right through: DECA Decrement Accumulator 1 1 Carry flag 1 1 DEC Rn Decrement register 1 1 SWAPA ‘Swap nibbles within the DEC direct Decrement direct byte 2 17 Accumulator 1 1 DEC @Ri Decrement indirect DATA TRANSFER RAM 1 1 Mnemonic Description . Byte Cyc MUL AB Multiply A & 8 1 4 - | MOV A,Rn Move register to DIVAB Divide AbyB 1 4 Accumulator 1 1 DAA Decimal Adjust MOV Adirect Move direct byte to . Accumulator 1 1 Accumulator 2 1 LOGICAL OPERATIONS MOV A,@RI Move indirect RAM to Mnemonic Destination Byte Cyc Accumulator 1 1 ANLA,An AND register to MOV A, #data Move immediate data Accumulator 1 1 to Accumulator 2 1 ANL Adirect AND direct byte to MOV RNA Move Accumulator to Accumulator 2 1 register 1 1 ANLA,GRI AND indirect RAM to: MOV Rn.direct Move direct byte to Accumulator 1 1 register 2 2 ANLA, #data AND immediate data to MOV Rn,#data Move immediate data to Accumulator 2 1 register 2 1 . ANL direct,A AND Accumulator to MOV direct,A Move Accumulator to direct byte 2 1 direct byte 2 1 ANL direct, #data AND immediate data to MOV direct,Ra Move register to direct direct byte 3 2 byte 2 2 ORLA,Rn OR register to MOV direct,direct Move direct byte to ° Accumulator 1 1 direct 3 2 ORL A,direct OR direct byte to MOV direct,@Ri ~~ Move indirect RAM to Accumulator 2 1 direct byte 2 2 10-26

Table 1. MCS®-51 Instruction Set Description (Continued) : with Accumulator 21 DUNZ Rn,ret Decrement register & . CLA bit Clear direct bit 204 eR! - tyregsterneer at location addressed . addr16 — Destination address for LCALL & LIMP.

Table 2. Instruction Opcodes in Hexadecimal Order 05 2 ING data addr 98 1 ADDC ARO.

INTEL CORP (UP/PRPHLS) 206 P mm 4éeb17s 081784 & = intel M8751H-8 PRELIMINARY STF of FSF : Table 2. Instruction Opcodes In Hexadecimal Order (Continued) 668 1 XRL A.@RO 99 1 SUBB ARI. er 1 XAL A@Rt 9A 1 SUBB AR2 68 1 XAL ARO 9B 1 SUBB ARS 69 1 XAL ARI 9c 1 SUBB ARS 6A 1 XRL AR2 90 1 SUBB ARS 68 1 XRL ARS 9 + SUBB ARG ec 1 XRL ARS oF 1 SUB AR? @D 1 XRL ARS A0 2 ORL G,/bit addr 6E 1 xRL ARE At 2 AJMP code addr oF 1 XRL ART Az 2 MOV Gybit addr 70 2 NZ > code addr a3 1 ING OPTR 71 2 ACALL code addr Aa 1 MUL ° AB 72 2 ORL bit addr AS reserved 73 1 MP @A+DPTR As 2 MOV @RO,data addr 74 2 Mov A,#data : AT 2 MOV @Ri data addr 7 3 Mov data addr, #data AB 2 MOV ROdata addr 76 2 Mov @RO, #data 9 2 Mov Ri.data addr . 7 2 Mov ORI, #data AA 2 MOV R2,data addr 78 2 Mov RO, #data AB 2 Mov R3jdata addr . 79 2 Mov Ri,#data AC 2 Mov Rédata addr 7A 2 Mov R2,#data AD 2 Mov Ré,data addr 78 2 Mov: Ra, #data AE 2 MOV Re,data addr 7c 2 Mov R4,#data AF 2 MOV Ri7,data addr. 7D 2 Mov AS, #data Bo 2 ANL G,/bit addr 7E 2 Mov Re, #data Bt 2 ACALL ~— code addr 7F 2 Mov R7,#data B2 2 CPL bit addr 80 2 SJMP code addr 83 1 CPL o 81 2 AJMP code addr B4 3 GUNE A, #data,code addr 82 2 ANL bit addr 85 3 GINE A.data addr,code addr 83 1 Movc A@A+PC 86 3 GUNE @RO, #data,code addr 84 1 ov - AB 87 3 GUNE @Ri, #data,code addr 85 3 Mov data addr, data addr 88 3 CINE RO, #data,code addr 8 2 Mov data addr,@RO 89 3 CINE Ri, #data,code addr 87 2 MoV data addr,@R1 BA 3 CINE 2, #data,code addr 88 2 MOV data addr,RO - 8B 3 CINE R, #data,code addr 89 2 MoV data addr,A1 BC 3° CINE 4, #data,code addr 8A 2 MoV data addr,R2 8D 3 QJNE RS, #data,code addr 8B 2 MOV data addr,R3 BE 3 INE 6, #data,code addr ac 2 Mov data addr,R4 BF 3 GJNE 7, #data,code addr ep 2 MOV data addr,RS co 2 PUSH data addr ee 2 Mov data addr,R6 ct 2 AJMP code addr 8F 2 Mov data addr,R7 c2 2 cR bitaddr 90 3 Mov DPTR, #data C3 1 CLR c a1 2 ACALL code addr C4 1 SWAP A ‘ 92 2 Mov bitaddr,c cs 2 XCH A.data addr 93 1 Move A@A+OPTR ce 1 XCH A.@RO o4 2 SUBB A.#data o7 1 XCH A@RI 95 2 susB A,data addr ca 1 XCH ARO 96 1 susB A@RO co 1 XCH ARI 97 1 susB A@Rt CA 1 XCH AR2 98 1 SUBB ARO cB 1__XCH ARS 10-29

Table 2. Instruction Opcodes In Hexadecimal Order (Continued) : £0 1 MOVX A@DPTR FA 1 MOV R2,A .