M82380

M82380 INTEL | Alldatasheet

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November 1992 Order Number: 271070-006 M82380 HIGH PERFORMANCE 32-BIT DMA CONTROLLER WITH INTEGRATED SYSTEM SUPPORT PERIPHERALS Y High Performance 32-Bit DMA Controller Ð 40 Mbytes/sec Maximum Data Transfer Rate at 20 MHz Ð 8 Independently Programmable Channels Y 20-Source Interrupt Controller Ð Individually Programmable Interrupt Vectors Ð 15 External, 5 Internal Interrupts Ð M8259A Superset Y Four 16-Bit Programmable Interval Timers Ð M82C54 Compatible Y Programmable Wait State Generator Ð 0 to 15 Wait States Pipelined Ð 1 to 16 Wait States Non-Pipelined Y DRAM Refresh Controller Y i386TM Processor Shutdown Detect and Reset Control Ð Software/Hardware Reset Y High Speed CHMOS III Technology Y 132-Pin PGA Package and 164-Pin Quad Flat Pack (See Packaging Specification Order Ý 231369) Y Optimized for use with the i386 TM Microprocessor Ð Resides on Local Bus for Maximum Bus Bandwidth Y Available in Three Product Grades: Ð MIL-STD-883, b55§Ct o a125§C( T C) Ð Military Temperature Only, b55§Ct o a125§C( T C) Ð Extended Temperature, b40§Ct o a110§C( T C) The M82380 is a multi-function support peripheral that integrates system functions necessary in an i386 processor environment. It has eight channels of high performance 32-bit DMA with the most efficient transfer rates possible on the i386 microprocessor bus. System support peripherals integrated into the M82380 provide Interrupt Control, Timers, Wait State generation, DRAM Refresh Control, and System Reset logic. The M82380’s DMA Controller can transfer data between devices of different data path widths using a single channel. Each DMA channel operates independently in any of several modes. Each channel has a temporary data storage register for handling non-aligned data without the need for external alignment logic. 271070–1 M82380 Internal Block Diagram

HIGH PERFORMANCE 32-BIT DMA CONTROLLER WITH INTEGRATED SYSTEM SUPPORT PERIPHERALS CONTENTS PAGE

1.0 FUNCTIONAL OVERVIEW ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6

1.1 M82380 Architecture ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6

1.1.1 DMA Controller ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7

1.1.2 Programmable Interval Timers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8

1.1.3 Interrupt Controller ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9

1.1.4 Wait State Generator ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 10

1.1.5 DRAM Refresh Controller ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 10

1.1.6 CPU Reset Function ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 11

1.1.7 Register Map Relocation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 11

1.2 Host Interface ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 11

2.0 i386 TM PROCESSOR HOST INTERFACE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12

2.1 Master and Slave Modes ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 13

2.2 M80386 Interface Signals ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 13

2.2.1 Clock (CLK2) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 13

2.2.2 Data Bus (D0–D31) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 13

2.2.3 Address Bus (A31–A2) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14

2.2.4 Byte Enable (BE3 –BE0) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14

2.2.5 Bus Cycle Definition Signals (D/C , W/R , M/IO ) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 15

2.2.6 Address Status (ADS ) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 15

2.2.7 Transfer Acknowledge (READY ) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 15

2.2.8 Next Address Request (NA ) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 15

2.2.9 Reset (RESET, CPURST) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 15

2.2.10 Interrupt Out (INT) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 17

2.3 M82380 Bus Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 17

2.3.1 Address Pipelining ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 17

2.3.2 Master Mode Bus Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 17

2.3.3 Slave Mode Bus Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 20

3.0 DMA CONTROLLER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21

3.1 Functional Description ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22

3.2 Interface Signals ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23

3.2.1 DREQn and EDACK (0–2) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24

3.2.2 HOLD and HLDA ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24

3.2.3 EOP ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24

3.3 Modes of Operation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24

3.3.1 Target/Requester Definition ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 25

3.3.2 Buffer Transfer Processes ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 25

3.3.3 Data Transfer Modes ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 26

3.3.4 Channel Priority Arbitration ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 30

3.3.5 Combining Priority Modes ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 32

3.3.6 Bus Operation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 33

3.4 Bus Arbitration and Handshaking ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 34

3.4.1 Synchronous and Asynchronous Sampling of DREQn and EOP ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 37

3.4.2 Arbitration of Cascaded Master Requests ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 39

3.4.3 Arbitration of Refresh Requests ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 41

3.0 DMA CONTROLLER (Continued)

3.5 DMA Controller Register Overview ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 41

3.5.1 Control/Status Registers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 41

3.5.2 Channel Registers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 42

3.5.3 Temporary Registers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 43

3.6 DMA Controller Programming ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 44

3.6.1 Buffer Processes ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 44

3.6.2 Data Transfer Modes ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 45

3.6.3 Cascaded Bus Masters ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 45

3.6.4 Software Commands ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 45

3.7 Register Definitions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 46

4.0 PROGRAMMABLE INTERRUPT CONTROLLER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 53

4.1 Functional Description ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 53

4.1.1 Internal Block Diagram ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 53

4.1.2 Interrupt Controller Banks ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 54

4.2 Interface Signals ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 55

4.2.1 Interrupt Inputs ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 55

4.2.2 Interrupt Output (INT) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 56

4.3 Bus Functional Description ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 56

4.4 Mode of Operation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 57

4.4.1 End-Of-Interrupt ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 57

4.4.2 Interrupt Priorities ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 58

4.4.3 Interrupt Masking ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 61

4.4.4 Edge Or Level Interrupt Triggering ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 61

4.4.5 Interrupt Cascading ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 61

4.4.6 Reading Interrupt Status ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 62

4.5 Register Set Overview ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 62

4.5.1 Initialization Command Words (ICW) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 64

4.5.2 Operation Control Words (OCW) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 64

4.5.3 Poll/Interrupt Request/In-Service Status Register ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 65

4.5.4 Interrupt Mask Register (IMR) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 65

4.5.5 Vector Register (VR) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 65

4.6 Programming ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 65

4.6.1 Initialization (ICW) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 65

4.6.2 Vector Registers (VR) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 66

4.6.3 Operation Control Words (OCW) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 66

4.7 Register Bit Definition ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 67

4.8 Register Operational Summary ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 70

5.0 PROGRAMMABLE INTERVAL TIMER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 71

5.1 Functional Description ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 71

5.1.1 Internal Architecture ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 72

5.2 Interface Signals ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 73

5.2.1 CLKIN ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 73

5.2.2 TOUT1, TOUT2 , TOUT3 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 73

5.2.3 GATE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 73

5.3 Modes of Operation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 74

5.3.1 Mode 0ÐInterrupt on Terminal Count ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 74

5.3.2 Mode 1ÐGate Retriggerable One-Shot ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 74

5.3.3 Mode 2ÐRate Generator ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 76

5.3.4 Mode 3ÐSquare Wave Generator ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 77

5.3.5 Mode 4ÐInitial Count Triggered Strobe ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 79

5.3.6 Mode 5ÐGate Retriggerable Strobe ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 80

5.3.7 Operation Common to All Modes ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 81

5.4 Register Set Overview ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 81

5.4.1 Counter 0, 1, 2, 3 Registers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 82

5.4.2 Control Word Registe rI&I I ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 82

5.5 Programming ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 82

5.5.1 Initialization ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 82

5.5.2 Read Operation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 82

5.6 Register Bit Definitions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 84

6.0 WAIT STATE GENERATOR ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 86

6.1 Functional Description ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 86

6.2 Interface Signals ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 87

6.2.1 READY ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 87

6.2.2 READYO ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 87

6.2.3 WSC(0–1) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 87

6.3 Bus Function ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 88

6.3.1 Wait States in Non-Pipelined Cycle ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 88

6.3.2 Wait States in Pipelined Cycle ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 89

6.3.3 Extending and Early Terminating Bus Cycle ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 90

6.4 Register Set Overview ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 91

6.5 Programming ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 92

6.6 Register Bit Definition ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 92

6.7 Application Issues ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 92

6.7.1 External ‘READY’ Control Logic ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 92

7.0 DRAM REFRESH CONTROLLER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 94

7.1 Functional Description ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 94

7.2 Interface Signals ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 94

7.2.1 TOUT1/REF ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 94

7.3 Bus Function ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 95

7.3.1 Arbitration ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 95

7.4 Modes of Operation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 95

7.4.1 Word Size and Refresh Address Counter ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 95

7.5 Register Set Overview ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 96

7.6 Programming ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 96

7.7 Register Bit Definition ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 96

8.0 RELOCATION REGISTER AND ADDRESS DECODE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 96

8.1 Relocation Register ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 96

8.1.1 I/O-Mapped M82380 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 97

8.1.2 Memory-Mapped M82380 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 97

8.2 Address Decoding ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 97

9.0 CPU RESET AND SHUTDOWN DETECT ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 97

9.1 Hardware Reset ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 97

9.2 Software Reset ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 97

9.3 Shutdown Detect ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 98

10.0 INTERNAL CONTROL AND DIAGNOSTIC PORTS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 98

10.1 Internal Control Port ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 98

10.2 Diagnostic Ports ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 98

11.0 INTEL RESERVED I/O PORTS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 99

12.0 MECHANICAL DATA ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 100

12.1 Pin Assignment ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 100

12.2 Package Dimensions and Mounting ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 102

13.0 ELECTRICAL DATA ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 104

13.1 Power and Grounding ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 104

13.2 Power Decoupling ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 104

13.3 Unused Pin Recommendations ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 104

13.4 ICE TM-386 Support ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 104

13.5 Maximum Ratings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 105

13.6 DC Specifications ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 106

13.7 AC Specifications ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 107

APPENDIX AÐPorts Listed by Address ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ A-1 APPENDIX BÐPorts Listed by Function ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ B-1 APPENDIX CÐPin Descriptions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ C-1 APPENDIX DÐM82380 System Notes ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ D-1

1.0 FUNCTIONAL OVERVIEW

to for design and programming information.

1.1 M82380 Architecture

ance operation with the i386 microprocessor. requests and processor shutdown status. registers within the M82380 are accessed as bytes. are automatically inserted into the access cycle. distinct sections of the M82380. Figure 1. Architecture of the M82380

1.1.1 DMA CONTROLLER

physical address space of the i386 microprocessor. via a 32-bit internal temporary data storage register. the operation of the other channels. Clear Byte Pointer Flip-Flop. Figure 2. M82380 DMA Controller

grammed to transfer one particular block of data. there is a contiguous block of data area available. without having to reprogram the channel. erals access to the bus on a shared basis.

1.1.2 PROGRAMMABLE INTERVAL TIMERS

any time, making these very versatile event timers. Programmable Interval Timers. generate time-keeping interrupts. which defaults to the highest priority (IRQ0). Figure 3. Programmable Interval TimersÐBlock Diagram

1.1.3 INTERRUPT CONTROLLER

but the priority is always as if they were cascaded. gram of the M82380 Interrupt Controller. system of unsolicited interrupts of the M80386. gramming the interrupt vectors as mentioned above. edge or level triggered and are software maskable. Figure 4. M82380 Interrupt ControllerÐBlock Diagram

1.1.4 WAIT STATE GENERATOR

State Generator is shown in Figure 5. programmed with the desired number of wait states. the Wait State Generator is currently active. wait state select inputs are active.

1.1.5 DRAM REFRESH CONTROLLER

cycles to execute on an i386 processor bus. Figure 5. M82380 Wait State GeneratorÐBlock Diagram

The M82380 DRAM Refresh Controller has the high- est priority when requesting bus access and will in- terrupt any active DMA process. This allows large blocks of data to be moved by the DMA controller without affecting the refresh function. Also the DMA controller is not required to completely relinquish the bus, the refresh controller simply steals a bus cycle between DMA accesses. The amount by which the refresh address is incre- mented is programmable to allow for different bus widths and memory bank arrangements.

1.1.6 CPU RESET FUNCTION

The M82380 contains a special reset function which can respond to hardware reset signals from the M82384, as well as a software reset command. The circuit will hold the i386 processor’s RESET line ac- tive while an external hardware reset signal is pres- ent at its RESET input. It can also reset the i386 processor as the result of a software command. The software reset command causes the M82380 to hold the processor’s RESET line active for a mini- mum of 62 CLK2 cycles; enough time to allow an M80386 to re-initialize. The M82380 can be programmed to sense the shut- down detect code on the status lines from the M80386. If the Shutdown Detect function is enabled, the M82380 will automatically reset the processor. A diagnostic register is available which can be used to determine the cause of reset.

1.1.7 REGISTER MAP RELOCATION

After a hardware reset, the internal registers of the M82380 are located in I/O space beginning at port address 0000H. The map of the M82380’s registers is relocatable via a software command. The default mapping places the M82380 between I/O address- es 0000H and 00DBH. The relocation register allows this map to be moved to any even 256-byte bounda- ry in the processor’s 16-bit I/O address space or any even 16-Mbyte boundary in the 32-bit memory ad- dress space.

1.2 Host Interface

The M82380 is designed to operate efficiently on the local bus of an M80386 microprocessor. The control signals of the M82380 are identical in function to those of the i386 processor. As a slave, the M82380 operates with all of the features available on the i386 processor bus. When the M82380 is in the Mas- ter Mode, it looks identical to the i386 processor to the connected devices. The M82380 monitors the bus at all times, and de- termines whether the current bus cycle is a pipelined or non-pipelined access. All of the status signals of the processor are monitored. The control, status, and data registers within the M82380 are located at fixed addresses relative to each other, but the group can be relocated to either memory or I/O space and to different locations with- in those spaces. As a Slave device, the M82380 monitors the con- trol/status lines of the CPU. The M82380 will gener- ate all of the wait states it needs whenever it is ac- cessed. This allows the programmer the freedom of accessing M82380 registers without having to insert NOPs in the program to wait for slower M82380 in- ternal registers. The M82380 can determine if a current bus cycle is a pipelined or a non-pipelined cycle. It does this by monitoring the ADS and READY signals and thereby keeping track of the current state of the i386 proces- sor. As a bus master, the M82380 looks like an i386 processor to the rest of the system. This enables the designer greater flexibility in systems which include the M82380. The designer does not have to alter the interfaces of any peripherals designed to operate with the i386 processor to accommodate the M82380. The M82380 will access any peripherals on the bus in the same manner as the i386 processor, including recognizing pipelined bus cycles. The M82380 is accessed as an 8-bit peripheral. This is done to maintain compatibility with existing system architectures and software. The i386 processor places the data of all 8-bit accesses either on D (0– 7) or D (8–15). The M82380 will only accept data on these lines when in the Slave Mode. When in the Master Mode, the M82380 is a full 32-bit machine, sending and receiving data in the same manner as the i386 processor.

2.1 Master and Slave Modes

programmed into the M82380 during Slave Mode. tion of DMA transfers, or when HLDA is negated.

2.2 M80386 INTERFACE SIGNALS

face to the i386 host processor.

2.2.1 CLOCK (CLK2)

share a common clock source. i386 processor will wake up in phase with PHI1.

2.2.2 DATA BUS (D0–D31)

Figure 7. CLK2 and M82380 Internal Clock

and I/O devices (or memory) via the Data Bus.

2.2.3 ADDRESS BUS (A31–A2)

addresses (00000000H to 0000FFFFH).

2.2.4 BYTE ENABLE (BE3

dress memory and I/O locations. Mode. These definitions are depicted in Table 1. Table 1. Byte Enable Signals *During READ, data will be duplicated on D0–D7, D8–D15, D16–D23, and D24–D31. M82380 is concerned only with the lower half of the Data Bus. *Actual number of bytes accessed depends upon the programmed data path width.

2.2.5 BUS CYCLE DEFINITION SIGNALS (D/C ,

guishes between processor data and control cycles.

1. Note that some combinations are recognized as

2.2.6 ADDRESS STATUS (ADS )

T1 and T2P bus states (see Bus State Definition).

2.2.7 TRANSFER ACKNOWLEDGE (READY )

2.2.8 NEXT ADDRESS REQUEST (NA )

is already pending internally. This input pin is monitored only in the Master Mode. cles, and NA will be ignored.

2.2.9 RESET (RESET, CPURST)

Table 2. Bus Cycle Definition

2.2.10 INTERRUPT OUT (INT)

This output pin is used to signal the i386 host proc- essor that one or more interrupt requests (either in- ternal or external) are pending. The processor is ex- pected to respond with an Interrupt Acknowledge cycle. This signal should be connected directly to the Maskable Interrupt Request (INTR) input of the i386 host processor.

2.3 M82380 Bus Timing

The M82380 internally divides the CLK2 signal by two to generate its internal clock. Figure 7 shows the relationship of CLK2 and the internal clock. The in- ternal clock consists of two phases: PHI1 and PHI2. Each CLK2 period is a phase of the internal clock. In Figure 7, both PHI1 and PHI2 of the M82380 internal clock are shown. In the M82380, whether it is in the Master or Slave Mode, the shortest time unit of bus activity is a bus state. A bus state, which is also referred as a ‘T-state’, is defined as one M82380 PHI2 clock peri- od (i.e., two CLK2 periods). Recall in Table 2, there are six different types of bus cycles in the M82380 as defined by the M/IO , D/C and W/R signals. Each of these bus cycles is composed of two or more bus states. The length of a bus cycle depends on when the READY input is asserted (i.e., driven LOW).

2.3.1 ADDRESS PIPELINING

The M82380 supports Address Pipelining as an op- tion in both the Master and Slave Mode. This feature typically allows a memory or peripheral device to op- erate with one less wait state than would otherwise be required. This is possible because during a pipe- lined cycle, the address and bus cycle definition of the next cycle will be generated by the bus master while waiting for the end of the current cycle to be acknowledged. The pipelined bus is especially well suited for interleaved memory environment. For

16 MHz interleaved memory designs with 100 ns ac-

cess time DRAMs, zero wait state memory accesses can be achieved when pipelined addressing is se- lected. In the Master Mode, the M82380 is capable of initiat- ing, on a cycle-by-cycle basis, either a pipelined or non-pipelined access depending upon the state of the NA input. If a pipelined cycle is requested (indi- cated by NA being driven LOW), the M82380 will drive the address and bus cycle definition of the next cycle as soon as there is an internal bus request pending. In the Slave Mode, the M82380 is constantly moni- toring the ADS and READY signals on the processor local bus to determine if the current bus cycle is a pipelined cycle. If a pipelined cycle is detected, the M82380 will request one less wait state from the processor if the Wait State Generator feature is se- lected. On the other hand, during an M82380 inter- nal register access in a pipelined cycle, it will make use of the advance address and bus cycle informa- tion. In all cases, Address Pipelining will result in a savings of one wait state.

2.3.2 MASTER MODE BUS TIMING

When the M82380 is in the Master Mode, it will be in one of six bus states. Figure 10 shows the complete bus state diagram of the Master Mode, including pipelined address states. As seen in the figure, the M82380 state diagram is very similar to that of the i386 processor. The major difference is that in the M82380, there is no Hold state. Also, in the M82380, the conditions for some state transitions depend upon whether it is the end of a DMA process. NOTE: The term ‘end of a DMA process’ is loosely defined here. It depends on the DMA modes of operation as well as the state of the EOP and DREQ inputs. This is explained in detail in section 3ÐDMA Con- troller.

during T2 and NA is negated, T2 will be repeated. take one T1 and one T2 state. Figure 10. Master Mode State Diagram

2.3.3 SLAVE MODE BUS TIMING

than in a non-pipelined cycle. identical (see Wait State Generator). NA is shown here only for timing reference. It is not sampled by the M82380 during Slave Mode. non-pipelined cycle to complete the internal access. Figure 13. Slave Read/Write Timing

3.0 DMA CONTROLLER

many different modes of data transfer available. provide a very versatile DMA controller. Figure 14. M82380 DMA Controller Block Diagram

3.1 Functional Description

In describing the operation of the M82380’s DMA Controller, close attention to terminology is required. Before entering the discussion of the function of the M82380 DMA Controller, the following explanations of some of the terminology used herein may be of benefit. First, a few terms for clarification: DMA PROCESSÐA DMA process is the execution of a programmed DMA task from beginning to end. Each DMA process requires initial programming by the host M80386 microprocessor. BUFFERÐA contiguous block of data. BUFFER TRANSFERÐThe action required by the DMA to transfer an entire buffer. DATA TRANSFERÐThe DMA action in which a group of bytes, words, or double words are moved between devices by the DMA Controller. A data transfer operation may involve movement of one or many bytes. BUS CYCLEÐAccess by the DMA to a single byte, word, or double word. Each DMA channel consists of three major compo- nents. These components are identified by the con- tents of programmable registers which define the memory or I/O devices being serviced by the DMA. They are the Target, the Requester, and the Byte Count. They will be defined generically here and in greater detail in the DMA register definition section. The Requester is the device which requires service by the M82380 DMA Controller, and makes the re- quest for service. All of the control signals which the DMA monitors or generates for specific channels are logically related to the Requester. Only the Re- quester is considered capable of initiating or termi- nating a DMA process. The Target is the device with which the Requester wishes to communicate. As far as the DMA process is concerned, the Target is a slave which is incapa- ble of control over the process. The direction of data transfer can be either from Re- quester to Target or from Target to Requester; i.e., each can be either a source or a destination. The Requester and Target may each be either I/O or memory. Each has an address associated with it that can be incremented, decremented, or held con- stant. The addresses are stored in the Requester Address Registers and Target Address Registers, respectively. These registers have two parts: one which contains the current address being used in the DMA process (Current Address Register), and one which holds the programmed base address (Base Address Register). The contents of the Base Regis- ters are never changed by the M82380 DMA Con- troller. The Current Registers are incremented or decremented according to the progress of the DMA process. The Byte Count is the component of the DMA pro- cess which dictates the amount of data which must be transferred. Current and Base Byte Count Regis- ters are provided. The Current Byte Count Register is decremented once for each byte transferred by the DMA process. When the register is decremented past zero, the Byte Count is considered ‘expired’ and the process is terminated or restarted, depend- ing on the mode of operation of the channel. The point at which the Byte Count expires is called ‘Ter- minal Count’ and several status signals are depen- dent on this event. Each channel of the M82380 DMA Controller also contains a 32-bit Temporary Register for use in as- sembling and disassembling non-aligned data. The operation of this register is transparent to the user, although the contents of it may affect the timing of some DMA handshake sequences. Since there is data storage available for each channel, the DMA Controller can be interrupted without loss of data. The M82380 DMA Controller is a slave on the bus until a request for DMA service is received via either a software request command or a hardware request signal. The host processor may access any of the control/status or channel registers at any time the M82380 is a bus slave. Figure 15 shows the flow of operations that the DMA Controller performs. At the time a DMA service request is received, the DMA Controller issues a bus hold request to the host processor. The M82380 becomes the bus mas- ter when the host relinquishes the bus by asserting a hold acknowledge signal. The channel to be serv- iced will be the one with the highest priority at the time the DMA Controller becomes the bus master. The DMA Controller will remain in control of the bus until the hold acknowledge signal is removed, or un- til the current DMA transfer is complete. While the M82380 DMA Controller has control of the bus, it will perform the required data transfer(s). The type of transfer, source and destination addresses, and amount of data to transfer are programmed in the control registers of the DMA channel which re- ceived the request for service.

Figure 15. Flow of DMA Controller Operation bus arbitration and switching process.

3.2 Interface Signals

Figure 16. Requester, Target, and DMA Controller Interconnection

3.2.1 DREQn and EDACK(0–2)

cess after finishing other higher priority processes. DMA channel which is accessing the Requester. the number of the channel presently being serviced. Table 4. EDACK Encoding

3.2.2 HOLD and HLDA

an output from the M82380 and HLDA is an input. the slave mode when HLDA is active. the DRAM Refresh Controller.

3.2.3 EOP

cycle for which a channel is programmed to execute. described later in this data sheet.

3.3 Modes of Operation

Table 5. DMA Operating Modes

3.3.1 TARGET/REQUESTER DEFINITION

source and the Target in the destination.

3.3.2 BUFFER TRANSFER PROCESSES

cesses require special programming considerations. on setting up the Buffer Transfer Processes. channel is either disabled or re-programmed.

The Buffer Chaining Process is useful for transfer- ring large quantities of data into non-contiguous buffer areas. In this process, a single channel is used to process data from several buffers, while having to program the channel only once. Each new buffer is programmed in a pipelined operation that provides the new buffer information while the old buffer is being processed. The chain is created by loading new buffer information while the M82380 DMA Controller is processing the Current Buffer. When the Current Buffer expires, the M82380 DMA Controller automatically restarts the channel using the new buffer information. Loading the new buffer information is done by an interrupt routine which is requested by the M82380. Interrupt Request 1 (IRQ1) is tied internally to the M82380 DMA Controller for this purpose. IRQ1 is generated by the M82380 when the new buffer infor- mation is loaded into the channel’s Current Regis- ters, leaving the Base Registers ‘empty’. The inter- rupt service routine loads new buffer information into the Base Registers. The host processor is required to load the information for another buffer before the current Byte Count expires. The process repeats un- til the host programs the channel back to single buff- er operation, or until the channel runs out of buffers. The channel runs out of buffers when the Current Buffer expires and the Base Registers have not yet been loaded with new buffer information. When this occurs, the channel must be reprogrammed. If an external EOP is encountered while executing a Buffer Chaining Process, the current buffer is con- sidered expired and the new buffer information is loaded into the Current Registers. If the Base Regis- ters are ‘empty’, the chain is terminated. The channel uses the Base Target Address Register as an indicator of whether or not the Base Registers are full. When the most significant byte of the Base Target Register is loaded, the channel considers all of the Base Registers loaded, and removes the in- terrupt request. This requires that the other Base Registers (Base Requester Address, Last Byte Count) must be loaded before the Base Target Ad- dress Register. The reason for implementing the re- loading process this way is that, for most applica- tions, the Byte Count and the Requester will not change from one buffer to the next, and therefore do not need to be reprogrammed. The details of pro- gramming the channel for the Buffer Chaining Pro- cess can be found in the section of DMA program- ming.

3.3.3 DATA TRANSFER MODES

Three Data Transfer modes are available in the M82380 DMA Controller. They are the Single Trans- fer, Block Transfer, and Demand Transfer Modes. These transfer modes can be used in conjunction with any one of three Buffer Transfer modes: Single Buffer, Auto-Initialized Buffer, and Buffer Chaining. Any Data Transfer Modes can be used under any of the Buffer Transfer Modes. These modes are inde- pendently available for all DMA channels. Different devices being serviced by the DMA Con- troller require different handshaking sequences for data transfers to take place. Three handshaking modes are available on the M82380, giving the de- signer the opportunity to use the DMA Controller as efficiently as possible. The speed at which data can be presented or read by a device can affect the way a DMA controller uses the host’s bus, thereby affect- ing not only data throughput during the DMA pro- cess, but also affecting the host’s performance by limiting its access to the bus. SINGLE TRANSFER MODE In the Single Transfer Mode, one data transfer to or from the Requester is performed by the DMA Con- troller at a time. The DREQn input is arbitrated and the HOLD/HLDA sequence is executed for each transfer. Transfers continue in this manner until the Byte Count expires, or until EOP is sampled active. If the DREQn input is held active continuously, the en- tire DREQ-HOLD-HLDA-DACK sequence is repeat- ed over and over until the programmed number of bytes has been transferred. Bus control is released to the host between each transfer. Figure 17 shows the logical flow of events which make up a buffer transfer using the Single Transfer Mode.

quishing the bus, if necessary. extra idle states at the end of the transfer process. DMA Controller de-activates the HOLD signal.

3.3.4 CHANNEL PRIORITY ARBITRATION

Figure 23. DMA Priority Grouping setting of the Programmable Priority. priority levels while operating with Fixed Priority. group (between channels 4 and 7). Figure 24. Example of Programmed Priority tating Priority preserves the current priority levels. by use of Programmable Priority. most recently serviced inherits the lowest priority. This rotation occurs each time a channel is serviced.

4567 3012 Ðchannel 2 drops to lowest priority within group. Lower group drops to lowest priority within upper group. Figure 25. Rotating Channel Priority. Lower and Upper groups are programmed for the Rotating Priority Mode.

3.3.5 COMBINING PRIORITY MODES

two combined priority methods. Figure 26. Combining Priority Modes

3.3.6 BUS OPERATION

Data may be transferred by the DMA Controller us- ing two different bus cycle operations: Fly-By (one- cycle) and Two-Cycle. These bus handshake meth- ods are selectable independently for each channel through a command register. Device data path widths are independently programmable for both Target and Requester. Also selectable through soft- ware is the direction of data transfer. All of these parameters affect the operation of the M82380 on a bus-cycle by bus-cycle basis. FLY-BY TRANSFERS The Fly-By Transfer Mode is the fastest and most efficient way to use the M82380 DMA Controller to transfer data. In this method of transfer, the data is written to the destination device at the same time it is read from the source. Only one bus cycle is used to accomplish the transfer. In the Fly-By Mode, the DMA acknowledge signal is used to select the Requester. The DMA Controller simultaneously places the address of the Target on the address bus. The state of M/IO and W/R during the Fly-By transfer cycle indicate the type of Target and whether the target is being written to or read from. The Target’s Bus Size is used as an incremen- ter for the Byte Count. The Requester address regis- ters are ignored during Fly-By transfers. Note that memory-to-memory transfers cannot be done using the Fly-By Mode. Only one memory or I/O address is generated by the DMA Controller at a time during Fly-By transfers. Only one of the devices being accessed can be selected by an address. Also, the Fly-By method of data transfer limits the hardware to accesses of devices with the same data bus width. The Temporary Registers are not affect- ed in the Fly-By Mode. Fly-By transfers also require that the data paths of the Target and Requester be directly connected. This requires that successive Fly-By accesses be to doubleword boundaries, or that the Requester be capable of switching its connections to the data bus. TWO-CYCLE TRANSFERS Two-Cycle transfers can also be performed by the M82380 DMA Controller. These transfers require at least two bus cycles to execute. The data being transferred is read into the DMA Controller’s Tempo- rary Register during the first bus cycle(s). The sec- ond bus cycle is used to write the data from the Temporary Register to the destination. If the addresses of the data being transferred are not word or doubleword aligned, the M82380 will recognize the situation and read and write the data in groups of bytes, placing them always at the proper destination. This process of collecting the desired bytes and putting them together is called ‘byte as- sembly’. The reverse process (reading from aligned locations and writing to non-aligned locations) is called ‘byte disassembly’. The assembly/disassembly process takes place transparent to the software, but can only be done while using the Two-Cycle transfer method. The M82380 will always perform the assembly/disas- sembly process as necessary for the current data transfer. Any data path widths for either the Re- quester or Target can be used in the Two-Cycle Mode. This is very convenient for interfacing existing 8- and 16-bit peripherals to the i386 processor’s 32-bit bus. The M82380 DMA Controller always attempts to fill the Temporary Register from the source before writ- ing any data to the destination. If the process is ter- minated before the Temporary Register is filled (TC or EOP ), the M82380 will write the partial data to the destination. If a process is temporarily suspended (such as when DREQn is de-activated during a de- mand transfer), the contents of a partially filled Tem- porary Register will be stored within the M82380 un- til the process is restarted. For example, if the source is specified as an 8-bit device and the destination as a 32-bit device, there will be four reads as necessary from the 8-bit source to fill the Temporary Register. Then the M82380 will write the 32-bit contents to the destination. This cy- cle will repeat until the process is terminated or sus- pended. Note that for a Single-Cycle transfer mode of opera- tion, the internal circuitry of the DMA Controller actu- ally executes single transfers by removing the DREQ from the internal arbitration. Thus single transfers from an 8-bit requester to a 32-bit target will consist of four complete and independent 8-bit requester cy- cles, between which bus control is released and re- requested. Finally, the 32-bit data will be transferred to the target device from the temporary register be- fore the fifth requester cycle. With Two-Cycle transfers, the devices that the M82380 accesses can reside at any address within I/O or memory space. The device must be able to decode the byte-enables (BEn ). Also, if the device cannot accept data in byte quantities, the program- mer must take care not to allow the DMA Controller to access the device on any address other than the device boundary.

or the Fly-By (Single-Cycle) transfer method is used. the M82380 operates on the data to be transferred. quester is assumed to be the opposite. The Verify Cycle is used to perform a data read only. vided to do any comparisons on the data read.

3.4 Bus Arbitration and Handshaking

with no change in the sequence. Figure 27. Bus Arbitration and DMA Sequence

completely, including a new Buffer Transfer Mode. way as if the byte count expired. respond to HLDA without extra idle bus states. Figure 28. Beginning of a DMA Process

or Byte Count expiring (Terminal Count). Table 6. DMA Channel Activity Due to Terminal Count or External EOP Figure 29. Termination of a DMA Process Due to Expiration of Current Byte Count

sert HOLD again. This is illustrated in Figure 30.

3.4.1 SYNCHRONOUS AND ASYNCHRONOUS

start of a DMA process due to a DREQn input. to signal the end of a transfer. signals be valid one clock cycle earlier. Figure 30. Switching between Active DMA Channels

another, possibly undesired, transfer. alternative is the Synchronous Mode.

3.4.2 ARBITRATION OF CASCADED MASTER

Figure 33. Cascaded Bus Master

idle state until the new master relinquishes control. Figure 34. Cascade Cycle Termination

ler offers a much better solution.

3.4.3 ARBITRATION OF REFRESH REQUESTS

of the bus is transferred back to the host. for the corresponding DREQn input to go inactive. cascaded master loses its priority.

3.5 DMA Controller Register Overview

Table 7. DMA Controller Registers

3.5.1 CONTROL/STATUS REGISTERS

Enables or disables the DMA channels as a group. , and channels 3 and 7 lowest priority.

Type of TransferÐread, write, verify AutoÐInitializeÐenable or disable Target Address CountÐincrement or decrement Data Transfer ModeÐdemand, single, block, cascade Mode Register I functions default to the following after reset: verify transfer, Auto-Initialize disabled, In- crement Target address, Demand Mode. Mode Register II Programs the following functions for an individually selected channel: Target Address HoldÐenable or disable Requester Address CountÐincrement or decrement Requester Address HoldÐenable or disable Target Device TypeÐI/O or Memory Requester Device TypeÐI/O or Memory Transfer CyclesÐTwo-Cycle or Fly-By Mode Register II functions are defined as follows after a hardware reset: Disable Target Address Hold, Increment Requester Address, Target (and Re- quester) in memory, Fly-By Transfer Cycles. Note: Requester Device Type ignored in Fly-By Transfers. Software Request Register The DMA Controller can respond to service requests which are initiated by software. Each channel has an internal request status bit associated with it. The host processor can write to this register to set or reset the request bit of a selected channel. The status of the group’s software DMA service re- quests can be read from this register as well. Each request bit is cleared upon Terminal Count or exter- nal EOP The software DMA requests are non-maskable and subject to priority arbitration with all other software and hardware requests. The entire register is cleared by a hardware reset. Mask Registers Each channel has associated with it a mask bit which can be set/reset to disable/enable that chan- nel. Two methods are available for setting and clear- ing the mask bits. The Mask Set/Reset Register is a write-only register which allows the host to select an individual channel and either set or reset the mask bit for that channel only. The Mask Read/Write Reg- ister is available for reading the mask bit status and for writing mask bits in groups of four. The mask bits of a group may be cleared in one step by executing the Clear Mask Command. See the DMA Programming section for details. A hardware reset sets all of the channel mask bits, disabling all channels. Status Register The Status register is a read-only register which con- tains the Terminal Count (TC) and Service Request status for a group. Four bits indicate the TC status and four bits indicate the hardware request status for the four channels in the group. The TC bits are set when the Byte Count expires, or when an exter- nal EOP is asserted. These bits are cleared by read- ing from the Status Register. The Service Request bit for a channel indicates when there is a hardware DMA request (DREQn) asserted for that channel. When the request has been removed, the bit is cleared. Bus Size Register This write-only register is used to define the bus size of the Target and Requester of a selected channel. The bus sizes programmed will be used to dictate the sizes of the data paths accessed when the DMA channel is active. The values programmed into this register affect the operation of the Temporary Regis- ter. Any byte-assembly required to make the trans- fers using the specified data path widths will be done in the Temporary Register. The Bus Size register of the Target is used as an increment/decrement value for the Byte Counter and Target Address when in the Fly-By Mode. Upon reset, all channels default to 8-bit Targets and 8-bit Requesters. Chaining Register As a command or write register, the Chaining regis- ter is used to enable or disable the Chaining Mode for a selected channel. Chaining can either be dis- abled or enabled for an individual channel, indepen- dently of the Chaining Mode status of other chan- nels. After a hardware reset, all channels default to Chaining disabled. When read by the host, the Chaining Register pro- vides the status of the Chaining Interrupt of each of the channels. These interrupt status bits are cleared when the new buffer information has been loaded.

3.5.2 CHANNEL REGISTERS

Each channel has three individually programmable registers necessary for the DMA process; they are the Base Byte Count, Base Target Address, and Base Requester Address registers. The 24-bit Base

rent registers are loaded from the Base registers. the corresponding Current register. next logical byte to be accessed of a pair of bytes. by any accesses to this byte. 16-bit Byte Count Registers.

3.5.3 TEMPORARY REGISTERS

Figure 35. Transfer of Data between Memory the result, independent of data path width.

3.6 DMA Controller Programming

Programming a DMA Channel to perform a needed DMA function is in general a four step process. First the global attributes of the DMA Controller are pro- grammed via the two Command Registers. These global attributes include: priority levels, channel group enables, priority mode, and DREQn/EOP in- put sampling. The second step involves setting the operating modes of the particular channel. The Mode Regis- ters are used to define the type of transfer and the handshaking modes. The Bus Size Register and Chaining Register may also need to be programmed in this step. The third step is setting up the channel is to load the Base Registers in accordance with the needs of the operating modes chosen in step two. The Current Registers are automatically loaded from the Base Registers, if required by the Buffer Transfer Mode in effect. The information loaded and the order in which it is loaded depends on the operating mode. A channel used for cascading, for example, needs no buffer information and this step can be skipped en- tirely. The last step is to enable the newly programmed channel using one of the Mask Registers. The chan- nel is then available to perform the desired data transfer. The status of the channel can be observed at any time through the Status Register, Mask Reg- ister, Chaining Register, and Software Request reg- ister. Once the channel is programmed and enabled, the DMA process may be initiated in one of two ways, either by a hardware DMA request (DREQn) or a software request (Software Request Register). Once programmed to a particular Process/Mode configuration, the channel will operate in that config- uration until programmed otherwise. For this reason, restarting a channel after the current buffer expires does not require complete reprogramming of the channel. Only those parameters which have changed need to be reprogrammed. The Byte Count Register is always changed and must be repro- grammed. A Target or Requester Address Register which is incremented or decremented should be re- programmed also.

3.6.1 BUFFER PROCESSES

The Buffer Process is determined by the Auto-Initial- ize bit of Mode Register I and the Chaining Register. If Auto-Initialize is enabled, Chaining should not be used. SINGLE BUFFER PROCESS The Single Buffer Process is programmed by dis- abling Chaining via the Chaining Register and pro- gramming Mode Register I for non-Auto-Initialize. BUFFER AUTO-INITIALIZE PROCESS Setting the Auto-Initialize bit in Mode Register I is all that is necessary to place the channel in this mode. Buffer Auto-Initialize must not be enabled simulta- neous to enabling the Buffer Chaining Mode as this will have unpredictable results. Once the Base Registers are loaded, the channel is ready to be enabled. The channel will reload its Cur- rent Registers from the Base Registers each time the Current Buffer expires, either by an expired Byte Count or an external EOP BUFFER CHAINING PROCESS The Buffer Chaining Process is entered into from the Single Buffer Process. The Mode Registers should be programmed first, with all of the Transfer Modes defined as if the channel were to operate in the Sin- gle Buffer Process. The channel’s Base and Current Registers are then loaded. When the channel has been set up in this way, and the chaining interrupt service routine is in place, the Chaining Process can be entered by programming the Chaining Register. Figure 36 illustrates the Buffer Chaining Process.

spond to IRQ1 before the Current Buffer expires. Figure 36. Flow of Events in the setting the channel’s Mask bit in the Mask Register. nated and act on that information.

3.6.2 DATA TRANSFER MODES

3.6.3 CASCADED BUS MASTERS

3.6.4 SOFTWARE COMMANDS

are descriptions of the command function.

Clear Byte Pointer Flip-FlopÐlocation 000CH Resets the Byte Pointer Flip-Flop. This command should be performed at the beginning of any access to the channel registers in order to be assured of beginning at a predictable place in the register pro- gramming sequence. Master ClearÐlocation 000DH All DMA functions are set to their default states. This command is the equivalent of a hardware reset to the DMA Controller. Functions other than those in the DMA Controller section of the M82380 are not affected by this command. Clear Mask Register ÐChannels 0–3Ðlocation 000EH Channels 4–7Ðlocation 00CEH This command simultaneously clears the Mask Bits of all channels in the addressed group, enabling all of the channels in the group. Clear TC Interrupt RequestÐlocation 001EH This command resets the Terminal Count Interrupt Request Flip-Flop. It is provided to allow the pro- gram which made a software DMA request to ac- knowledge that it has responded to the expiration of the requested channel(s).

3.7 Register Definitions

The following diagrams outline the bit definitions and functions of the M82380 DMA Controller’s Status and Control Registers. The function and program- ming of the registers is covered in the previous sec- tion on DMA Controller Programming. An entry of ‘X’ as a bit value indicates ‘‘don’t care.’’ Channel Registers (Read Current, Write Base) Channel Register Name Address Byte Bits (Hex) Pointer Accessed Channel 0 Target Address 00 0 0–7 1 8–15 87 x 16–23 10 0 24–31 Byte Count 01 0 0–7 1 8–15 11 0 16–23 Requester Address 90 0 0-7 1 8–15 91 0 16–23 1 24–31 Channel 1 Target Address 02 0 0–7 1 8–15 83 x 16–23 12 0 24–31 Byte Count 03 0 0–7 1 8–15 13 0 16–23 Requester Address 92 0 0-7 1 8–15 93 0 16–23 1 24–31

Channel Registers (Read Current, Write Base) Channel Register Name Address Byte Bits (Hex) Pointer Accessed Channel 2 Target Address 04 0 0–7 1 8–15 81 x 16–23 14 0 24–31 Byte Count 05 0 0–7 1 8–15 15 0 16–23 Requester Address 94 0 0-7 1 8–15 95 0 16–23 1 24–31 Channel 3 Target Address 06 0 0–7 1 8–15 82 x 16–23 16 0 24–31 Byte Count 07 0 0–7 1 8–15 17 0 16–23 Requester Address 96 0 0-7 1 8–15 97 0 16–23 1 24–31 Channel 4 Target Address C0 0 0–7 1 8–15 8F x 16–23 D0 0 24–31 Byte Count C1 0 0–7 1 8–15 D1 0 16–23 Requester Address 98 0 0-7 1 8–15 99 0 16–23 1 24–31 Channel 5 Target Address C2 0 0–7 1 8–15 8B x 16–23 D2 0 24–31 Byte Count C3 0 0–7 1 8–15 D3 0 16–23 Requester Address 9A 0 0-7 1 8–15 9B 0 16–23 1 24–31

Channel Registers (Read Current, Write Base) Channel Register Name Address Byte Bits (Hex) Pointer Accessed Channel 6 Target Address C4 0 0–7 1 8–15 89 x 16–23 D4 0 24–31 Byte Count C5 0 0–7 1 8–15 D5 0 16–23 Requester Address 9C 0 0-7 1 8–15 9D 0 16–23 1 24–31 Channel 7 Target Address C6 0 0–7 1 8–15 8A x 16–23 D6 0 24–31 Byte Count C7 0 0–7 1 8–15 D7 0 16–23 Requester Address 9E 0 0-7 1 8–15 9F 0 16–23 1 24–31 Command Register I (Write Only) Port AddressÐChannels 0–3Ð0008H Channels 4–7Ð00C8H 271070–36 Command Register II (Write Only) Port AddressesÐChannels 0–3Ð-001AH Channels 4–7Ð00DAH 271070–37

Mode Register I (Write Only) Port AddressesÐChannels 0–3Ð000BH Channels 4–7Ð00CBH 271070–38 * Target and Requester DECREMENT is allowed only for byte transfers. Mode Register II (Write Only) Port AddressesÐChannels 0–3Ð001BH Channels 4–7Ð00DBH 271070–39 * Target and Requester DECREMENT is allowed only for byte transfers.

Software Request Register (Read/Write) Port AddressesÐChannels 0–3Ð0009H Channels 4–7Ð00C9H Write Format: Software DMA Service Request 271070–40 Read Format: Software Requests Pending 271070–41 Mask Set/Reset Register Individual Channel Mask (Write Only) Port AddressesÐChannels 0–3Ð000AH Channels 4–7Ð00CAH 271070–42

Mask Read/Write Register Group Channel Mask (Read/Write) Port AddressesÐChannels 0–3Ð000FH Channels 4–7Ð00CFH 271070–43 Status Register Channel Process Status (Read Only) Port AddressesÐChannels 0–3Ð0008H Channels 4–7Ð00C8H 271070–44 Bus Size Register Set Data Path Width (Write Only) Port AddressesÐChannels 0–3Ð0018H Channels 4–7Ð00D8H 271070–45 Bus Size Encoding: 00 e Reserved by Intel 10 e 16-bit Bus 01 e 32-bit Bus 11 e 8-bit Bus

Chaining Register (Read/Write) Port AddressesÐChannels 0–3Ð0019H Channels 4–7Ð00D9H Write Format: Set Chaining Mode 271070–46 Read Format: Channel Interrupt Status 271070–47

4.0 PROGRAMMABLE INTERRUPT

4.1 Functional Description

15 external and 5 internal interrupt request inputs. (15 x 8) external interrupt request inputs. est priority pending request on the data bus.

4.1.1 INTERNAL BLOCK DIAGRAM

Masking IRQ1.5 also masks IRQ2 . Figure 37. Interrupt Controller Block Diagram

4.1.2 INTERRUPT CONTROLLER BANKS

The block diagram of a bank is shown in Figure 38. functional description of each block follows. Figure 38. Interrupt Bank Block Diagram

an Interrupt Acknowledge cycle. affect the interrupt request lines of lower priority. of the other internal blocks within the same bank. bank to which this bank is cascaded (see Figure 37).

4.2 Interface Signals

4.2.1 INTERRUPT INPUTS

weak internal pull-up resistors. following paragraphs describe these interrupts. Table 8. M82380 Internal Interrupt Requests requests is generated by an edge-detector flip-flop.

cates that a software DMA request was cleared. er priority than the Cascaded Request.

4.2.2 INTERRUPT OUTPUT (INT)

The INT output pin is taken directly from bank A.

4.3 Bus Functional Description

What is actually driven on the Data Bus depends on if the current interrupt request is a Slave Request. *Slave will place a vector at this time. Figure 39. Interrupt Acknowledge Cycle

After activating the INT signal, the M82380 monitors the status lines (M/IO , D/C , W/R ) and waits for the i386 processor to initiate the first interrupt acknowl- edge cycle. In the i386 processor environment, two successive interrupt acknowledge cycles (INTA) marked by M/IO e LOW, D/C e LOW, and W/R e LOW are performed. During the first INTA cycle, the PIC will determine the highest priority request. As- suming this interrupt input has no external Slave Controller cascaded to it, the M82380 will drive the Data Bus with 00H in the first INTA cycle. During the second INTA cycle, the M82380 PIC will drive the Data Bus with the corresponding preprogrammed in- terrupt vector. If the PIC determines (from the ICW3) that this inter- rupt input has an external Slave Controller cascaded to it, it will drive the Data Bus with the specific Slave Cascade Address (instead of 00H) during the first INTA cycle. This Slave Cascade Address is the pre- programmed content in the corresponding Vector Register. This means that no Slave Address should be chosen to be 00H. Note that the Slave Address and Interrupt Vector are different interpretations of the same thing. They are both the contents of the programmable Vector Register. During the second INTA cycle, the Data Bus will be floated so that the external Slave Controller can drive its interrupt vec- tor on the bus. Since the Slave Interrupt Controller resides on the system bus, bus transceiver enable and direction control logic must take this into consid- eration. In order to have a successful interrupt service, the interrupt request input must be held active (LOW) until the beginning of the first interrupt acknowledge cycle. If there is no pending interrupt request when the first INTA cycle is generated, the PIC will gener- ate a default vector, which is the IRQ7 vector (bank A level 7). According to the Bus Cycle definition of the i386 processor, there will be four Bus Idle States be- tween the two interrupt acknowledge cycles. These idle bus cycles will be initiated by the i386 processor. Also, during each interrupt acknowledge cycle, the internal Wait State Generator of the M82380 will au- tomatically generate the required number of wait states for internal delays.

4.4 Mode of Operation

A variety of modes and commands are available for controlling the M82380 PIC. All of them are pro- grammable; that is, they may be changed dynamical- ly under software control. In fact, each bank can be programmed individually to operate in different modes. With these modes and commands, many possible configurations are conceivable, giving the user enough versatility for almost any interrupt con- trolled application. This section is not intended to show how the M82380 PIC can be programmed. Rather, it de- scribes the operation in different modes.

4.4.1 END-OF-INTERRUPT

Upon completion of an interrupt service routine, the interrupted bank needs to be notified so its ISR can be updated. This allows the PIC to keep track of which interrupt levels are in the process of being serviced and their relative priorities. Three different End-Of-Interrupt (EOI) formats are available. They are: Non-Specific EOI Command, Specific EOI Com- mand, and Automatic EOI Mode. Selection of which EOI to use is dependent upon the interrupt opera- tions the user wishes to perform. If the M82380 is NOT programmed in the Automatic EOI Mode, an EOI command must be issued by the i386 processor to the specific M82380 PIC Control- ler Bank. Also, if this controller bank is cascaded to another internal bank, an EOI command must also be sent to the bank to which this bank is cascaded. For example, if an interrupt request of Bank C in the M82380 PIC is serviced, an EOI should be written into Bank C, Bank B and Bank A. If the request comes from an external interrupt controller cascad- ed to Bank C, then an EOI should be written into the external controller as well. NON-SPECIFIC EOI COMMAND A Non-Specific EOI command sent from the i386 processor lets the M82380 PIC bank know when a service routine has been completed, without specifi- cation of its exact interrupt level. The respective in- terrupt bank automatically determines the interrupt level and resets the correct bit in the ISR. To take advantage of the Non-Specific EOI, the in- terrupt bank must be in a mode of operation in which it can predetermine its in-service routine levels. For this reason, the Non-Specific EOI command should only be used when the most recent level acknowl- edged and serviced is always the highest priority lev- el (i.e., in the Fully Nested Mode structure to be de- scribed below). When the interrupt bank receives a Non-Specific EOI command, it simply resets the highest priority ISR bit to indicate that the highest priority routine in service is finished. Special consideration should be taken when decid- ing to use the Non-Specific EOI command. Here are two operating conditions in which it is best NOT

used since the Fully Nested Mode structure will be destroyed: Ð Using the Set Priority command within an inter- rupt service routine. Ð Using a Special Mask Mode. These conditions are covered in more detail in their own sections, but are listed here for reference. SPECIFIC EOI COMMAND Unlike a Non-Specific EOI command which automat- ically resets the highest priority ISR bit, a Specific EOI command specifies an exact ISR bit to be reset. Any one of the IRQ levels of an interrupt bank can be specified in the command. The Specific EOI command is needed to reset the ISR bit of a completed service routine whenever the interrupt bank is not able to automatically determine it. The Specific EOI command can be used in all conditions of operation, including those that prohibit Non-Specific EOI command usage mentioned above. AUTOMATIC EOI MODE When programmed in the Automatic EOI Mode, the M80386 no longer needs to issue a command to notify the interrupt bank it has completed an inter- rupt routine. The interrupt bank accomplishes this by performing a Non-Specific EOI automatically at the end of the second INTA cycle. Special consideration should be taken when decid- ing to use the Automatic EOI Mode because it may disturb the Fully Nested Mode structure. In the Auto- matic EOI Mode, the ISR bit of a routine in service is reset right after it is acknowledged, thus leaving no designation in the ISR that a service routine is being executed. If any interrupt request within the same bank occurs during this time and interrupts are en- abled, it will get serviced regardless of its priority. Therefore, when using this mode, the M80386 should keep its interrupt request input disabled dur- ing execution of a service routine. By doing this, higher priority interrupt levels will be serviced only after the completion of a routine in service. This guideline restores the Fully Nested Mode structure. However, in this scheme, a routine in service cannot be interrupted since the host’s interrupt request in- put is disabled.

4.4.2 INTERRUPT PRIORITIES

The M82380 PIC provides various methods for ar- ranging the interrupt priorities of the interrupt re- quest inputs to suit different applications. The follow- ing sub-sections explain these methods in detail. FULLY NESTED MODE The Fully Nested Mode of operation is a general pur- pose priority mode. This mode supports a multi-level interrupt structure in which all of the Interrupt Re- quest (IRQ) inputs within one bank are arranged from highest to lowest. Unless otherwise programmed, the Fully Nested Mode is entered by default upon initialization. At this time, IRQ0 is assigned the highest priority (priority e 0) and IRQ7 the lowest (priority e 7). This default priority can be changed, as will be explained later in the Rotating Priority Mode. When an interrupt is acknowledged, the highest pri- ority request is determined from the Interrupt Re- quest Register (IRR) and its vector is placed on the bus. In addition, the corresponding bit in the In-Serv- ice Register (ISR) is set to designate the routine in service. This ISR bit will remain set until the M80386 issues an End Of Interrupt (EOI) command immedi- ately before returning from the service routine; or alternately, if the Automatic End Of Interrupt (AEOI) bit is set, the ISR bit will be reset at the end of the second INTA cycle.

based on the newly assigned low priority. plishes both tasks in one single command. their summary of operations. Table 9. Interrupt Priority Mode Summary Fully-Nested Mode IRQ0 -Highest Priority No change in priority. Not Applicable. IRQ7-Lowest Priority Highest ISR bit is reset. Automatic Rotation Interrupt level just serviced Highest ISR bit is reset and the Not Applicable. priorities rotate to conform lowest priority. priority level. Other priorities(Specific Priority ‘Operation Summary’.

4.4.3 INTERRUPT MASKING

pabilities. This IMR allows individual IRQ masking. 0 masks IRQ0, Bit 1 masks IRQ1 and so forth. the interrupt acknowledge cycle. interrupts from all levels except the level in service.

4.4.4 EDGE OR LEVEL INTERRUPT

sition from an inactive (HIGH) to active (LOW) state. ond false interrupt from occurring. tor will be generated at level 7 of Bank A.

4.4.5 INTERRUPT CASCADING

cycle (instead of 00H during a non-slave service). tor should be programmed to 00H. Figure 41. Slave Cascade Address Capturing

Since the external Slave Cascade Address is provid- ed on the Data Bus during INTA cycle 1, an external latch is required to capture this address for the Slave Controller. A simple scheme is depicted in Figure 41. SPECIAL FULLY NESTED MODE This mode will be used where cascading is em- ployed and the priority is to be conserved within each Slave Controller. The Special Fully Nested Mode is similar to the ‘regular’ Fully Nested Mode with the following exceptions: Ð When an interrupt request from a Slave Control- ler is in service, this Slave Controller is not locked out from the Master’s priority logic. Fur- ther interrupt requests from the higher priority logic within the Slave Controller will be recog- nized by the M82380 PIC and will initiate inter- rupts to the i386 processor. In comparing to the ‘regular’ Fully Nested Mode, the Slave Controller is masked out when its request is in service and no higher requests from the same Slave Control- ler can be serviced. Ð Before exiting the interrupt service routine, the software has to check whether the interrupt serv- iced was the only request from the Slave Con- troller. This is done by sending a Non-Specific EOI Command to the Slave Controller and then reading its In Service Register. If there are no requests in the Slave Controller, a Non-Specific EOI can be sent to the corresponding M82380 PIC bank also. Otherwise, no EOI should be sent.

4.4.6 READING INTERRUPT STATUS

The M82380 PIC provides several ways to read dif- ferent status of each interrupt bank for more flexible interrupt control operations. These include polling the highest priority pending interrupt request and reading the contents of different interrupt status reg- isters. POLL COMMAND The M82380 PIC supports status polling operations with the Poll Command. In a Poll Command, the pending interrupt request with the highest priority can be determined. To use this command, the INT output is not used, or the i386 processor interrupt is disabled. Service to devices is achieved by software using the Poll Command. This mode is useful if there is a routine command common to several levels so that the INTA se- quence is not needed. Another application is to use the Poll Command to expand the number of priority levels. Notice that the ICW2 mechanism is not supported for the Poll Command. However, if the Poll Com- mand is used, the programmable Vector Registers are of no concern since no INTA cycle will be gener- ated. READING INTERRUPT REGISTERS The contents of each interrupt register (IRR, ISR, and IMR) can be read to update the user’s program on the present status of the M82380 PIC. This can be a versatile tool in the decision making process of a service routine, giving the user more control over interrupt operations. The reading of the IRR and ISR contents can be performed via the Operation Control Word 3 by us- ing a Read Status Register Command and the con- tent of IMR can be read via a simple read operation of the register itself.

4.5 Register Set Overview

Each bank of the M82380 PIC consists of a set of 8-bit registers to control its operations. The address map of all the registers is shown in Table 10. Since all three register sets are identical in functions, only one set will be described. Functionally, each register set can be divided into five groups. They are: the four Initialization Com- mand Words (ICW’s), the three Operation Control Words (OCW’s), the Poll/Interrupt Request/In-Serv- ice Register, the Interrupt Mask Register, and the Vector Registers. A description of each group fol- lows.

Table 10. Interrupt Controller Register Address Map

4.5.1 INITIALIZATION COMMAND WORDS (ICW)

Before normal operation can begin, the M82380 PIC must be brought to a known state. There are four 8-bit Initialization Command Words in each interrupt bank to setup the necessary conditions and modes for proper operation. Except for the second common word (ICW2) which is a read/write register, the other three are write-only registers. Without going into de- tail of the bit definitions of the command words, the following subsections give a brief description of what functions each command word controls. ICW1 The ICW1 has three major functions. They are: Ð To select between the two IRQ input triggering modes (edge-or level-triggered); Ð To designate whether or not the interrupt bank is to be used alone or in the cascade mode. If the cascade mode is desired, the interrupt bank will accept ICW3 for further cascade mode program- ming. Otherwise, no ICW3 will be accepted; Ð To determine whether or not ICW4 will be issued; that is, if any of the ICW4 operations are to be used. ICW2 ICW2 is provided for compatibility with the M8259A only. Its contents do not affect the operation of the interrupt bank in any way. Whenever the ICW2 of any of the three banks is written into, an interrupt is generated from Bank A at level 1.5. The interrupt request will be cleared after the ICW2 register has been read by the M80386. The user is expected to program the corresponding vector register or to use it as an indicator that an attempt was made to alter the contents. Note that each ICW2 register has dif- ferent addresses for read and write operations. ICW3 The interrupt bank will only accept an ICW3 if pro- grammed in the external cascade mode (as indicat- ed in ICW1). ICW3 is used for specific programming within the cascade mode. The bits in ICW3 indicate which interrupt request inputs have a Slave cascad- ed to them. This will subsequently affect the inter- rupt vector generation during the interrupt acknowl- edge cycles as described previously. ICW4 The ICW4 is accepted only if it was selected in ICW1. This command word register serves two func- tions: Ð To select either the Automatic EOI mode or soft- ware EOI mode; Ð To select if the Special Nested mode is to be used in conjunction with the cascade mode.

4.5.2 OPERATION CONTROL WORDS (OCW)

Once initialized by the ICW’s, the interrupt banks will be operating in the Fully Nested Mode by default and they are ready to accept interrupt requests. However, the operations of each interrupt bank can be further controlled or modified by the use of OCW’s. Three OCW’s are available for programming various modes and commands. Note that all OCW’s are 8-bit write-only registers. The modes and operations controlled by the OCW’s are: Ð Fully Nested Mode; Ð Rotating Priority Mode; Ð Special Mask Mode; Ð Poll Mode; Ð EOI Commands; Ð Read Status Commands. OCW1 OCW1 is used solely for masking operations. It pro- vides a direct link to the Interrupt Mask Register (IMR). The M80386 can write to this OCW register to enable or disable the interrupt inputs. Reading the pre-programmed mask can be done via the Interrupt Mask Register which will be discussed shortly. OCW2 OCW2 is used to select End-Of-Interrupt, Automatic Priority Rotation, and Specific Priority Rotation oper- ations. Associated commands and modes of these operations are selected using the different combina- tions of bits in OCW2. Specifically, the OCW2 is used to: Ð Designate an interrupt level (0–7) to be used to reset a specific ISR bit or to set a specific priori- ty. This function can be enabled or disabled; Ð Select which software EOI command (if any) is to be executed (i.e., Non-Specific or Specific EOI); Ð Enable one of the priority rotation operations (i.e., Rotate On Non-Specific EOI, Rotate On Au- tomatic EOI, or Rotate on Specific EOI). OCW3 There are three main categories of operation that OCW3 controls. That are summarized as follows:

Ð To select and execute the Read Status Register Commands, either reading the Interrupt Request Register (IRR) or the In-Service Register (ISR); Ð To issue the Poll Command. The Poll Command will override a Read Register Command if both functions are enabled simultaneously; Ð To set or reset the Special Mask Mode.

4.5.3 POLL/INTERRUPT REQUEST/IN-SERVICE

As the name implies, this 8-bit read-only register has multiple functions. Depending on the command is- sued in the OCW3, the content of this register re- flects the result of the command executed. For a Poll Command, the register read contains the binary code of the highest priority level requesting service (if any). For a Read IRR Command, the register con- tent will show the current pending interrupt re- quest(s). Finally, for a Read ISR Command, this reg- ister will specify all interrupt levels which are being serviced.

4.5.4 INTERRUPT MASK REGISTER (IMR)

This is a read-only 8-bit register which, when read, will specify all interrupt levels within the same bank that are masked.

4.5.5 VECTOR REGISTER (VR)

Each interrupt request input has an 8-bit read/write programmable vector register associated with it. The registers should be programmed to contain the inter- rupt vector for the corresponding request. The con- tents of the Vector Register will be placed on the Data Bus during the INTA cycles as described previ- ously.

4.6 Programming

Programming the M82380 PIC is accomplished by using two types of command words: ICW’s and OCW’s. All modes and commands explained in the previous sections are programmable using the ICW’s and OCW’s. The ICW’s are issued from the M80386 in a sequential format and are used to set- up the banks in the M82380 PIC in an initial state of operation. The OCW’s are issued as needed to vary and control the M82380 PIC’s operations. Both ICW’s and OCW’s are sent by the i386 proces- sor to the interrupt banks via the Data Bus. Each bank distinguishes between the different ICW’s and OCW’s by the I/O address map, the sequence they are issued (ICW’s only), and by some dedicated bits among the ICW’s and OCW’s. All three interrupt banks are programmed in a similar way. Therefore, only a single bank will be described.

4.6.1 INITIALIZATION (ICW)

Before normal operation can begin, each bank must be initialized by programming a sequence of two to four bytes written into the ICW’s. Figure 42 shows the initialization flow for an interrupt bank. Both ICW1 and ICW2 must be issued for any form of operation. However, ICW3 and ICW4 are used only if designated in ICW1. Once initialized, if any programming changes within the ICW’s are to be made, the entire ICW sequence must be repro- grammed, not just an individual ICW. Note that although the ICW2’s in the M82380 PIC do not affect the Bank’s operation, they still must be programmed in order to preserve the compatibility with the M8259A. The contents programmed are not relevant to the overall operations of the interrupt banks. Also, whenever one of the three ICW2’s is programmed, an interrupt level 1.5 in Bank A will be generated. This interrupt request will be cleared upon reading of the ICW2 registers. Since the three ICW2’s share the same interrupt level and the sys- tem may not know the origin of the interrupt, all three ICW2’s must be read. However, it is not necessary to provide an interrupt service routine for the ICW2 interrupt. One way to avoid this is as follows. At the beginning of the initial- ization of the interrupt banks, the i386 processor in- terrupt should be disabled. After each ICW2 register write operation is performed during the initialization, the corresponding ICW2 register is read. This read operation will clear the interrupt request of the M82380. At the end of the initialization, the i386 processor interrupt is re-enabled. With this method, the i386 processor will not detect the ICW2 interrupt request, thus eliminating the need of an interrupt service routine. Certain internal setup conditions occur automatically within the interrupt bank after the first ICW (ICW1) has been issued. They are: Ð The edge sensitive circuit is reset, which means that following initialization, an interrupt request input must make a HIGH-to-LOW transition to generate an interrupt; Ð The Interrupt Mask Register (IMR) is cleared; that is, all interrupt inputs are enabled; Ð IRQ7 input of each bank is assigned priority 7 (lowest); Ð Special Mask Mode is cleared and Status Read is set to IRR; Ð If no ICW4 is needed, then no Automatic-EOI is selected.

*ICW2 vector address must be programmed now. Other vector addresses may be programmed via ICW2 interrupt service routine. Figure 42. Initialization Sequence

4.6.2 VECTOR REGISTERS (VR)

programmed with the predefined vector numbers.

4.6.3 OPERATION CONTROL WORDS (OCW)

erations on the interrupt banks.

same read-only Status Register, a special Read Status/Poll Command must be issued before the Poll/Interrupt Request/In-Service Status Register is read. This command can be specified by writing the required control word into OCW3. As mentioned ear- lier, if both the Poll Command and the Status Read Command are enabled simultaneously, the Poll Command will override the Status Read. That is, af- ter the command execution, the Status Register will contain the result of the Poll Command. Note that for reading IRR and ISR, there is no need to issue a Read Status Command to the OCW3 ev- ery time the IRR or ISR is to be read. Once a Read Status Command is received by the interrupt bank, it ‘remembers’ which register is selected. However, this is not true when the Poll Command is used. In the Poll Command, after the OCW3 is written, the M82380 PIC treats the next read to the Status Reg- ister as an interrupt acknowledge. This will set the appropriate IS bit if there is a request and read the priority level. Interrupt Request input status remains unchanged from the Poll Command to the Status Read. In addition to the above read commands, the Inter- rupt Mask Register (IMR) can also be read. When read, this register reflects the contents of the pre- programmed OCW1 which contains information on which interrupt request(s) is(are) currently disabled.

4.7 Register Bit Definition

INITIALIZATION COMMAND WORD 1 (ICW1) 271070–55 INITIALIZATION COMMAND WORD 2 (ICW2) 271070–56

INITIALIZATION COMMAND WORD 3 (ICW3) ICW3 for Bank A: 271070–57 ICW3 for Bank B: 271070–58 ICW3 for Bank C: 271070–59 INITIALIZATION COMMAND WORD 4 (ICW4) 271070–60 OPERATION CONTROL WORD 1 (OCW1) 271070–61

OPERATION CONTROL WORD 2 (OCW2) 271070–62 OPERATION CONTROL WORD 3 (OCW3) 271070–63 ESMMÐEnable Special Mask Mode. When this bit is set to 1, it enables the SMM bit to set or reset the Special Mask Mode. When this bit is set to 0, SMM bit becomes don’t care. SMMÐSpecial Mask Mode. If ESMM e 1 and SMM e 1, the interrupt controller bank will enter Special Mask Mode. If ESMM e 1 and SMM e 0, the bank will revert to normal mask mode. When ESMM e 0, SMM has no effect. Poll/Interrupt Request/In-Service Status Register POLL COMMAND STATUS 271070–64

4.8 Register Operational Summary

Table 11. Register Operational Summary

5.0 PROGRAMMABLE INTERVAL

5.1 Functional Description

timer. Table 12 depicts the functions of each timer. A brief description of each timer’s function follows. Table 12. Programmable

0 IRQ8 Event Based

2 TOUT2

Timer 0 is intended to be used as an Event Counter. er 0 output is not available as an external signal. Figure 43. Block Diagram of Programmable Interval Timer

5.1.1 INTERNAL ARCHITECTURE

ing is a description of each block. tional blocks within the timer section. The Control Word Registers are write-only registers.

1. Detailed description of the Control Word Regis-

gram of one counter is shown in Figure 44. Figure 44. Internal Block Diagram of A Counter

The Status Register, when latched, contains the cur- rent contents of the Control Word Register and status of the output and Null Count Flag (see Read Back Command). The Counting Element (CE) is the actual counter. It is a 16-bit presettable synchronous down counter. The Output Latches (OL) contain two 8-bit latches (OLM and OLL). Normally, these latches ‘follow’ the content of the CE. OLM contains the most signifi- cant byte of the counter and OLL contains the least significant byte. If the Counter Latch Command is sent to the counter, OL will latch the present count until read by the i386 processor and then return to follow the CE. One latch at a time is enabled by the timer’s Control Logic to drive the internal bus. This is how the 16-bit Counter communicates over the 8-bit internal bus. Note that CE cannot be read. Whenev- er the count is read, it is one of the OL’s that is being read. When a new count is written into the counter, the value will be stored in the Count Registers (CR), and transferred to CE. The transferring of the contents from CR’s to CE is defined as ‘loading’ of the coun- ter. The Count Register contains two 8-bit registers: CRM (which contains the most significant byte) and CRL (which contains the least significant byte). Simi- lar to the OL’s, the Control Logic allows one register at a time to be loaded from the 8-bit internal bus. However, both bytes are transferred from the CR’s to the CE simultaneously. Both CR’s are cleared when the Counter is programmed. This way, if the Counter has been programmed for one byte count (either the most significant or the least significant byte only), the other byte will be zero. Note that CE cannot be written into directly. Whenever a count is written, it is the CR that is being written. As shown in the diagram, the Control Logic consists of three signals: CLKIN, GATE, and OUT. CLKIN and GATE will be discussed in detail in the section that follows. OUT is the internal output of the coun- ter. The external outputs of some timers (TOUT) are the inverted version of OUT (see TOUT1, TOUT2 TOUT3). The state of OUT depends on the mode of operation of the timer.

5.2 Interface Signals

5.2.1 CLKIN

CLKIN is an input signal used by all four timers for internal timing reference. This signal can be inde- pendent of the M82380 system clock, CLK2. In the following discussion, each ‘CLK Pulse’ is defined as the time period between a rising edge and a falling edge, in that order, of CLKIN. During the rising edge of CLKIN, the state of GATE is sampled. All new counts are loaded and counters are decremented on the falling edge of CLKIN. Please note that there are no restrictions on the CLKIN signal during WRITE cycles to the M82380 timer unit. Refer to Appendix D for details on this issue.

5.2.2 TOUT1, TOUT2

, TOUT3 TOUT1, TOUT2 and TOUT3 are the external output signals of Timer 1, Timer 2 and Timer 3, respective- ly. TOUT2 and TOUT3 are the inverted signals of their respective counter outputs, OUT. There is no external output for Timer 0. If Timer 2 is to be used as a tone generator of a speaker, external buffering must be used to provide sufficient drive capability. The Outputs of Timer 2 and 3 are dual function pins. The output pin of Timer 2 (TOUT2 /IRQ3), which is a bidirectional open-collector signal, can also be used as interrupt request input. When the interrupt func- tion is enabled (through the Programmable Interrupt Controller), a LOW on this input will generate an In- terrupt Request 3 (IRQ3 ) to the M82380 Program- mable Interrupt Controller. This pin has a weak inter- nal pull-up resistor. To use the IRQ3 function, Timer 2 should be programmed so that OUT2 is LOW. Ad- ditionally, OUT3 of Timer 3 is connected to an edge detector which will generate an Interrupt Request 0 (IRQ0) to the M82380 after the rising edge of OUT3 (see Figure 43).

5.2.3 GATE

GATE is not an externally controllable signal. Rath- er, it can be software controlled with the Internal Control Port. The state of GATE is always sampled on the rising edge of CLKIN. Depending on the mode of operation, GATE is used to enable/disable counting or trigger the start of an operation. For Timer 0 and 1, GATE is always enabled (HIGH). For Timer 2 and 3, GATE is connected to Bit 0 and 6, respectively, of an Internal Control Port (at ad- dress 61H) of the M82380. After a hardware reset, the state of GATE of Timer 2 and 3 is disabled (LOW).

5.3 Modes of Operation

Each timer can be independently programmed to operate in one of six different modes. Timers are programmed by writing a Control Word into the con- trol Word Register followed by an Initial Count (see Programming). The following are defined for use in describing the different modes of operation. CLK PulseÐA rising edge, then a falling edge, in that order of CLKIN. TriggerÐA rising edge of a timer’s GATE input. Timer/Counter LoadingÐThe transfer of a count from Count Register (CR) to Count Element (CE).

5.3.1 MODE 0ÐINTERRUPT ON TERMINAL

Mode 0 is typically used for event counting. After the Control Word is written, OUT is initially LOW, and will remain LOW until the counter reaches zero. OUT then goes HIGH and remains HIGH until a new count or a new Mode 0 Control Word is written into the counter. In this mode, GATE e HIGH enables counting; GATE e LOW disables counting. However, GATE has no effect on OUT. After the Control Word and initial count are written to a timer, the initial count will be loaded on the next CLK pulse. This CLK pulse does not decrement the count, so for an initial count of N, OUT does not go HIGH until N a 1 CLK pulses after the initial count is written. If a new count is written to the timer, it will be loaded on the next CLK pulse and counting will continue from the new count. If a two-byte count is written, the following happens: 1. Writing the first byte disables counting, OUT is set LOW immediately (i.e., no CLK pulse required). 2. Writing the second byte allows the new count to be loaded on the next CLK pulse. This allows the counting sequence to be synchroniz- ed by software. Again, OUT does not go HIGH until N a 1 CLK pulses after the new count of N is writ- ten. If an initial count is written while GATE is LOW, the counter will be loaded on the next CLK pulse. When GATE goes HIGH, OUT will go HIGH N CLK pulses later; no CLK pulse is needed to load the counter as this has already been done.

5.3.2 MODE 1ÐGATE RETRIGGERABLE

In this mode, OUT will be initially HIGH. OUT will go LOW on the CLK pulse following a trigger to start the one-shot operation. The OUT signal will then remain LOW until the timer reaches zero. At this point, OUT will stay HIGH until the next trigger comes in. Since the state of GATE signals of Timer 0 and 1 are inter- nally set to HIGH. After writing the Control Word and initial count, the timer is considered ‘armed’. A trigger results in load- ing the timer and setting OUT LOW on the next CLK pulse. Therefore, an initial count of N will result in a one-shot pulse width of N CLK cycles. Note that this one-shot operation is retriggerable; i.e., OUT will re- main LOW for N CLK pulses after every trigger. The one-shot operation can be repeated without rewrit- ing the same count into the timer. If a new count is written to the timer during a one- shot operation, the current one-shot pulse width will not be affected until the timer is retriggered. This is because loading of the new count to CE will occur only when the one-shot is triggered.

The following conventions apply to all mode timing diagrams.

1. Counters are programmed for binary (not BCD) counting and for reading/writing least significant byte (LSB) only.
2. The counter is always selected (CS
3. CW stands for ‘‘Control Word’’; CW e 10 means a control word of 10, Hex is written to the counter.
4. LSB stands for ‘‘least significant byte’’ of count.
5. Numbers below diagrams are count values.

The lower number is the least significant byte. most significant byte cannot be read. N stands for an undefined count. Vertical lines show transitions between count values. Figure 43. Mode 0

Figure 44. Mode 1

5.3.3 MODE 2ÐRATE GENERATOR

GATE can be used to synchronize the timer.

A GATE transition should not occur one clock prior to terminal count. Figure 45. Mode 2 timer may be synchronized by software. continue with the new count.

5.3.4 MODE 3ÐSQUARE WAVE GENERATOR

Mode 3 is typically used for Baud Rate generation. pired, OUT goes low for the remainder of the count.

initial count on the next CLK pulse. lows the timer to be synchronized by software. pulse and counting will continue from the new count. A-GATE transition should not occur one clock prior to terminal count. Figure 46. Mode 3

ceeding CLK pulses decrement the count by two. a 1)/2 counts and LOW for (N b 1)/2 counts.

5.3.5 MODE 4ÐINITIAL COUNT TRIGGERED

LOW for one CLK pulse and then go HIGH again. CLK pulses after initial count is written. Figure 47. Mode 4

1. Writing the first byte has no effect on counting.
2. Writing the second byte allows the new count to

be loaded on the next CLK pulse. value of the initial count loaded.

5.3.6 MODE 5ÐGATE RETRIGGERABLE

by writing an initial count. Initially, OUT will be HIGH. Counting is triggered by a rising edge of GATE. Figure 48. Mode 5

0 Disable Count No Effect Enable Count

4 Disable Count No Effect Enable Count

5 No Effect Initiate Count No Effect

count on the next CLK pulse. count sequence will start from there.

5.3.7 OPERATION COMMON TO ALL MODES

the GATE input is both edge and level sensitive. for binary counting and 10 **4 for BCD counting.

5.4 Register Set Overview

dress map of these registers is shown in Table 13. Table 13. Timer Register Port Address Map

5.4.1 COUNTER 0, 1, 2, 3 REGISTERS

These four 8-bit registers are functionally identical. They are used to write the initial count value into the respective timer. Also, they can be used to read the latched count value of a timer. Since they are 8-bit registers, reading and writing of the 16-bit initial count must follow the count format specified in the Control Word Registers; i.e., least significant byte only, most significant byte only, or least significant byte then most significant byte (see Programming).

5.4.2 CONTROL WORD REGISTE RI&I I

There are two Control Word Registers associated with the Timer section. One of the two registers (Control Word Register I) is used to control the oper- ations of Counters 0, 1, and 2 and the other (Control Word Register II) is for Counter 3. The major func- tions of both Control Word Registers are listed be- low: Ð Select the timer to be programmed. Ð Define which mode the selected timer is to oper- ate in. Ð Define the count sequence; i.e., if the selected timer is to count as a Binary Counter or a Binary Coded Decimal (BCD) Counter. Ð Select the byte access sequence during timer read/write operations; i.e., least significant byte only, most significant byte only, or least signifi- cant byte first, then most significant byte. Also, the Control Word Registers can be pro- grammed to perform a Counter Latch Command or a Read Back Command which will be described later.

5.5 Programming

5.5.1 INITIALIZATION

Upon power-up or reset, the state of all timers is undefined. The mode, count value, and output of all timers are random. From this point on, how each timer operates is determined solely by how it is pro- grammed. Each timer must be programmed before it can be used. Since the outputs of some timers can generate interrupt signals to the M82380, all timers should be initialized to a known state. Timers are programmed by writing a Control Word into their respective Control Word Registers. Then, an Initial Count can be written into the correspond- ing Count Register. In general, the programming pro- cedure is very flexible. Only two conventions need to be remembered: 1. For each timer, the Control Word must be written before the initial count is written. 2. The 16-bit initial count must follow the count for- mat specified in the Control Word (least signifi- cant byte only, most significant byte only, or least significant byte first, followed by most significant byte). Since the two Control Word Registers and the four Counter Registers have separate addresses, and each timer can be individually selected by the appro- priate Control Word Register, no special instruction sequence is required. Any programming sequence that follows the conventions above is acceptable. A new initial count may be written to a timer at any time without affecting the timer’s programmed mode in any way. Count sequence will be affected as de- scribed in the Modes of Operation section. Note that the new count must follow the programmed count format. If a timer is previously programmed to read/write two-byte counts, the following precaution applies. A program must not transfer control between writing the first and second byte to another routine which also writes into the same timer. Otherwise, the read/write will result in incorrect count. Whenever a Control Word is written to a timer, all control logic for that timer(s) is immediately reset (i.e., no CLK pulse is required). Also, the corre- sponding output pin, TOUT ), goes to a known initial state.

5.5.2 READ OPERATION

Three methods are available to read the current count as well as the status of each timer. They are: Read Counter Registers, Counter Latch Command and Read Back Command. Following is a descrip- tion of these methods. READ COUNTER REGISTERS The current count of a timer can be read by perform- ing a read operation on the corresponding Counter Register. The only restriction of this read operation is that the CLKIN of the timers must be inhibited by

using external logic. Otherwise, the count may be in the process of changing when it is read, giving an undefined result. Note that since all four timers are sharing the same CLKIN signal, inhibiting CLKIN to read a timer will unavoidably disable the other timers also. This may prove to be impractical. Therefore, it is suggested that either the Counter Latch Com- mand or the Read Back Command be used to read the current count of a timer. Another alternative is to temporarily disable a timer before reading its Counter Register by using the GATE input. Depending on the mode of operation, GATE e LOW will disable the counting operation. However, this option is available on Timer 2 and 3 only, since the GATE signals of the other two timers are internally enabled all the time. COUNTER LATCH COMMAND A Counter Latch Command will be executed when- ever a special Control Word is written into a Control Word Register. Two bits written into the Control Word Register distinguish this command from a ‘reg- ular’ Control Word (see Register Bit Definition). Also, two other bits in the Control Word will select which counter is to be latched. Upon execution of this command, the selected counter’s Output Latch (OL) latches the count at the time the Counter Latch Command is received. This count is held in the latch until it is read by the M80386, or until the timer is reprogrammed. The count is then unlatched automatically and the OL returns to ‘following’ the Counting Element (CE). This allows reading the contents of the counters ‘on the fly’ without affecting counting in progress. Multi- ple Counter Latch Commands may be used to latch more than one counter. Each latched count is held until it is read. Counter Latch Commands do not af- fect the programmed mode of the timer in any way. If a counter is latched, and at some time later, it is latched again before the prior latched count is read, the second Counter Latch Command is ignored. The count read will then be the count at the time the first command was issued. In any event, the latched count must be read ac- cording to the programmed format. Specifically, if the timer is programmed for two-byte counts, two bytes must be read. However, the two bytes do not have to be read right after the other. Read/write or programming operations of other timers may be per- formed between them. Another feature of this Counter Latch Command is that read and write operations of the same timer may be interleaved. For example, if the timer is pro- grammed for two-byte counts, the following se- quence is valid. 1. Read least significant byte. 2. Write new least significant byte. 3. Read most significant byte. 4. Write new most significant byte. If a timer is programmed to read/write two-byte counts, the following precaution applies. A program must not transfer control between reading the first and second byte to another routine which also reads from that same timer. Otherwise, an incorrect count will be read. READ BACK COMMAND The Read Back Command is another special Com- mand Word operation which allows the user to read the current count value and/or the status of the se- lected timer(s). Like the Counter Latch Command, two bits in the Command Word identify this as a Read Back Command (see Register Bit Definition). The Read Back Command may be used to latch multiple counter Output Latches (OL’s) by selecting more than one timer within a Command Word. This single command is functionally equivalent to several Counter Latch Commands, one for each counter to be latched. Each counter’s latched count will be held until it is read by the M80386 or until the timer is reprogrammed. The counter is automatically un- latched when read, but other counters remain latched until they are read. If multiple Read Back commands are issued to the same timer without reading the count, all but the first are ignored; i.e., the count read will correspond to the very first Read Back Command issued. As mentioned previously, the Read Back Command may also be used to latch status information of the selected timer(s). When this function is enabled, the status of a timer can be read from the Counter Reg- ister after the Read Back Command is issued. The status information of a timer includes the following: 1. Mode of timer: This allows the user to check the mode of opera- tion of the timer last programmed. 2. State of TOUT pin of the timer: This allows the user to monitor the counter’s out- put pin via software, possibly eliminating some hardware from a system.

1. Null Count/Count available: The Null Count Bit in the status byte indicates if the last count written to the Count Register (CR) has been loaded into the Counting Element (CE). The exact time this happens depends on the mode of the timer and is described in the Pro- gramming section. Until the count is loaded into the Counting Element (CE), it cannot be read from the timer. If the count is latched or read before this occurs, the count value will not reflect the new count just written. If multiple status latch operations of the timer(s) are performed without reading the status, all but the first command are ignored; i.e., the status read in will correspond to the first Read Back Command issued. Both the current count and status of the selected timer(s) may be latched simultaneously by enabling both functions in a single Read Back Command. This is functionally the same as issuing two separate Read Back Commands at once. Once again, if multi- ple read commands are issued to latch both the count and status of a timer, all but the first command will be ignored. If both count and status of a timer are latched, the first read operation of that timer will return the latched status, regardless of which was latched first. The next one or two (if two count bytes are to be read) read operations return the latched count. Note that subsequent read operations on the Counter Register will return the unlatched count (like the first read method discussed).

5.6 Register Bit Definitions

COUNTER 0, 1, 2, 3 REGISTER (READ/WRITE) Port Address Description 40H Counter 0 Register (read/write) 41H Counter 1 Register (read/write) 42H Counter 2 Register (read/write) 44H Counter 3 Register (read/write) 45H Reserved 46H Reserved 271070–76

Note that these 8-bit registers are for writing and reading of one byte of the 16-bit count value, either the most significant or the least significant byte. CONTROL WORD REGISTER I & II (WRITE-ONLY) Port Address Description 43H Control Word Register I (Counter 0, 1, 2) (write-only) 47H Control Word Register II (Counter 3) (write-only) CONTROL WORD REGISTER I 271070–77 CONTROL WORD REGISTER II 271070–78 COUNTER LATCH COMMAND FORMAT (Write to Control Word Register) 271070–79 Timer Gate Mode Trigger 0 1 2 3 Edge Level

0 X Interrupt on Terminal Count

jj X Gate Retriggerable One Shot

2 X X Rate Generator

3 X X Square Wave Generator

4 X Initial Count Triggered Strobe

5N A N A jj X Gate Retriggerable Strobe j e Must use Port 61 to generate L edge. NA e Not Applicable

(Write to Control Word Register) 271070–80 STATUS FORMAT (Returned from Read Back Command) 271070–81

6.0 WAIT STATE GENERATOR

6.1 Functional Description

The M82380 contains a programmable Wait State Generator which can generate a pre-programmed number of wait states during both CPU and DMA initiated bus cycles. This Wait State Generator is ca- pable of generating 1 to 16 wait states in non-pipe- lined mode, and 0 to 15 wait states in pipelined mode. Depending on the bus cycle type and the two Wait State Control inputs (WSC 0–1), a pre-pro- grammed number of wait states in the selected Wait State Register will be generated. The Wait State Generator can also be disabled to allow the use of devices capable of generating their own READY signals. Figure 49 is a block diagram of the Wait State Generator.

6.2 Interface Signals

affect the operation of the Wait State Generator. , WSC0 and WSC1 signals are inputs.

6.2.1 READY

cates to the M82380 the completion of a bus cycle.

6.2.2 READYO

nal and is the output of the Wait State Generator. account the command recovery time of the register. the Refresh Wait State Register.

6.2.3 WSC(0–1)

cesses, the least significant half to I/O accesses. Figure 49. Wait State Generator Block Diagram

Figure 50. Wait States in Non-Pipelined Cycles

6.3 Bus Function

6.3.1 WAIT STATES IN NON-PIPELINED CYCLE

Figure 50. In this diagram, it is assumed that the internal registers of the M82380 are not addressed. (Address Status) is asserted.

1. Access the M82380 internal registers: 2 to 5 wait

terrupt Controller will require 7 wait states.

1. Interrupt Acknowledge to the M82380: 5 wait
2. Refresh: As programmed in the Refresh Wait
3. Other bus cycles: Depending on WSC(0–1) and

tion is defined as follows (Table 14).

Table 14. Wait State Register Selection Write control signals as shown in Figure 51. Figure 51. WSC(0–1) Generation

6.3.2 WAIT STATES IN PIPELINED CYCLE

than in the non-pipelined cycle). Figure 52. Wait State in Pipelined Cycles

pipelined case discussed in the previous section. by the Wait State Generator.

6.3.3 EXTENDING AND EARLY TERMINATING

analysis of the external circuit. Figure 53. External ‘READY’ Control Logic Figure 54. Early Termination of Bus Cycle by ‘READY ’

Figure 55. Extending Bus Cycle by ‘READY ’ internal registers are accessed is not recommended.

1. Erroneous data may be read from or written into
2. The M82380 must be allowed to recover either

maining wait states that were avoided plus 4.

6.4 Register Set Overview

ble 15. A detailed description of each follows. Table 15. Register Address Map equal to the wait state count in the selected register. mode, and 0 to 15 wait states in pipelined mode.

chosen whenever a DRAM refresh cycle occurs. If the Wait State Generator is disabled during the re- fresh cycle (WSC(0–1) e 11), READYO will stay inactive and the Refresh Wait State Register is ig- nored.

6.5 Programming

Using the Wait State Generator is relatively straight- forward. No special programming sequence is re- quired. In order to ensure the expected number of wait states will be generated when a register is se- lected, the registers to be used must be pro- grammed after power-up by writing the appropriate wait state count into each register. Note that upon hardware reset, all Wait State Registers are initial- ized with the value FFH, giving the maximum num- ber of wait states possible. Also, each register can be read to check the wait state count previously stored in the register.

6.6 Register Bit Definition

WAIT STATE REGISTER 0, 1, 2 Port Address Description 72H Wait State Register 0 (read/write) 73H Wait State Register 1 (read/write) 74H Wait State Register 2 (read/write) 271070–89 REFRESH WAIT STATE REGISTER Port Address: 75H (Read/Write) 271070–90

6.7 Application Issues

6.7.1 EXTERNAL ‘READY’ CONTROL LOGIC

As mentioned previously, wait state cycles generat- ed by the M82380 can be terminated early or ex- tended longer by means of additional external logic (see Figure 53). In order to ensure that the READY input timing requirement of the i386 processor and the M82380 is satisfied, special care must be taken when designing this external control logic. This sec- tion addresses the design requirements.

1. The purpose is to determine the maximum delay

to meet the READY setup timing requirement. Figure 56. ‘READY’ Timing Consideration

7.0 DRAM REFRESH CONTROLLER

7.1 Functional Description

can be programmed to be 8-, 16-, or 32-bit wide. the M82380 is already a bus master.

7.2 Interface Signals

7.2.1 TOUT1/REF

cycle has taken place, or by a hardware reset. Timer, and will not be repeated here. Figure 57. DRAM Refresh Controller

7.3 Bus Function

7.3.1 ARBITRATION

be resumed after the refresh is done. bus. This is done by deasserting the EDACK signal. ‘steals’ a bus cycle between DMA accesses. for five plus ‘n’ bus states. well as TIMER1’s programmed mode of operation. TOUT1 changes to LOW to HIGH).

7.4 Modes of Operation

7.4.1 WORD SIZE AND REFRESH

A24–A31 e 1 during Refresh cycle. Figure 58. M82380 Refresh Cycle

mented by 1, 2, or 4, respectively.

7.5 Register Set Overview

port address map is shown in Table 16 below. Table 16. Register Address Map will be incremented after each refresh operation.

7.6 Programming

disabled (the Refresh Control Register is cleared). fresh interval (see Programming Interval Timer). abled and the DRAM bus width should be defined. should not be active after reset.

7.7 Register Bit Definition

8.0 RELOCATION REGISTER AND

8.1 Relocation Register

isters into either the memory or I/O address space. ter is depicted in Figure 59. Figure 59. Relocation Register

Note that the Relocation Register is part of the inter- nal register set of the M82380. It has a port address of 7FH. Therefore, any time the content of the Relo- cation Register is changed, the physical location of this register will also be moved. Upon reset of the M82380, the content of the Relocation Register will be cleared. This implies that the M82380 will re- spond to its I/O addresses in the range of 0000H to 00FFH.

8.1.1 I/O-MAPPED M82380

As shown in Figure 59, Bit 0 of the Relocation Regis- ter determines whether the M82380 registers are to be memory-mapped or I/O-mapped. When Bit 0 is set to ‘0’, the M82380 will respond to I/O Address- es. Address signals BE0 –BE3, A2–A7 will be used to select one of the internal registers to be ac- cessed. Bit 1 to Bit 7 of the Relocation Register will correspond to A9 to A15 of the Address bus, respec- tively. Together with A8 implied to be ‘0’, A15 to A8 will be fully decoded by the M82380. The following shows how the M82380 is mapped into the I/O ad- dress space. Example Relocation Register e 11001110 (0CEH) M82380 will respond to I/O address range from 0CE00H to 0CEFFH. Therefore, this I/O mapping mechanism allows the M82380 internal registers to be located on any even, contiguous, 256 byte boundary of the system I/O space. Port Address: 7FH (Read/Write)

8.1.2 MEMORY-MAPPED M82380

When Bit 0 of the Relocation Register is set to ‘1’, the M82380 will respond to memory addresses. Again, Address signals BE0 –BE3, A2–A7 will be used to select one of the internal registers to be accessed. Bit 1 to Bit 7 of the Relocation Register will correspond to A25–A31, respectively. A24 is as- sumed to be ‘0’, and A8–A23 are ignored. Consider the following example. Example Relocation Register e 10100111 (0A7H) The M82380 will respond to memory addresses in the range of 0A6XXXX00H to 0A6XXXXFFH (where ‘X’ is don’t care). This scheme implies that the internal register can be located in any even, contiguous, 2 **24 byte page of the memory space.

8.2 Address Decoding

As mentioned previously, the M82380 internal regis- ters do not occupy the entire contiguous 256 ad- dress locations. Some of the locations are ‘unoccu- pied’. The M82380 always decodes the lower 8 ad- dress bits (A0–A7) to determine if any one of its registers is being accessed. If the address does not correspond to any of its registers, the M82380 will not respond. This allows external devices to be lo- cated within the ‘holes’ in the M82380 address space. Note that there are several unused address- es reserved for future Intel peripheral devices.

9.0 CPU RESET AND SHUTDOWN

The M82380 will activate the CPURST signal to re- set the host processor when one of the following conditions occurs: Ð M82380 RESET is active; Ð M82380 detects a i386 processor Shutdown cy- cle (this feature can be disabled); Ð CPURST software command is issued to i386 processor. Whenever the CPURST signal is activated, the M82380 will reset its own internal Slave-Bus state machine.

9.1 Hardware Reset

Following a hardware reset, the M82380 will assert its CPURST output to reset the host processor. This output will stay active for as long as the RESET input is active. During a hardware reset, the M82380 inter- nal registers will be initialized as defined in the corre- sponding functional descriptions.

9.2 Software Reset

CPURST can be generated by writing the following bit pattern into M82380 register location 64H. D7 D0 1111XXX0 X e Don’t Care

ing the completion of the Write cycle to this port. not respond to a Read operation to this location. Internal Control and Diagnostic Ports).

9.3 Shutdown Detect

for 62 CLK2 periods to reset the host processor. same manner as other non-M82380 bus cycle.

10.0 INTERNAL CONTROL AND

10.1 Internal Control Port

10.2 Diagnostic Ports

nostic Ports is shown in Figure 61. Figure 61. Address Map of Diagnostic Ports Figure 60. Internal Control Port

11.0 INTEL RESERVED I/O PORTS

Figure 62. M82380 PGA PinoutÐView from TOP side

12.0 MECHANICAL DATA

12.1 Pin Assignment

be connected to the appropriate plane. ments for the Quad Flat Pack. Figure 63. M82380 PGA PinoutÐView from PIN side

Table 17. M82380 PGA PinoutÐFunctional Grouping

12.2 Package Dimensions and

Figure 64. M8238 164-Lead CQFP Pinout (View from Top Side)

Table 18. M82380 CQFP Pin Cross-Reference

10 V SS

11 A10

12 A11

13 A12

14 A13

15 V CC

16 V SS

17 A14

18 A15

19 A16

20 A17

23 V CC

24 A18

25 A19

26 A20

27 A21

28 A22

29 V SS

30 V CC

31 A23

32 A24

33 A25

34 A26

35 A27

36 A28

37 A29

38 A30

39 A31

40 V CC

41 D31

42 D23

43 D15

45 D30

46 V SS

47 V CC

48 D22

49 D14

51 V SS

52 V CC

53 D29

54 D21

55 D13

57 D28

58 D20

59 D12

60 V CC

61 V SS

64 V CC

66 D27

67 D19

68 D11

70 D26

71 D18

72 D10

74 V SS

75 V CC

76 D25

77 D17

79 V SS

80 CLK2

81 V SS

83 D24

84 D16

87 V SS

88 V CC

89 READYO

90 TOUT1/REF

91 HOLD

92 M/IO

93 V SS

94 V CC

97 W/R

98 D/C

99 TOUT3

100 TOUT2 /IRQ3

101 CPURST

103 V CC

104 V SS

105 V CC

107 V SS

108 V CC

109 READY

110 RESET

111 WSC1

112 WSC0

113 V SS

114 CLKIN

115 V CC

116 IRQ11

117 IRQ12

118 IRQ13

119 IRQ14

120 IRQ15

121 IRQ16

122 IRQ17

123 IRQ18

124 IRQ19

125 IRQ20

126 IRQ21

127 IRQ22

128 IRQ23

129 V CC

130 V SS

131 DREQ0

132 DREQ1

133 DREQ2

134 DREQ3

135 DREQ4/IRQ9

136 DREQ5

138 DREQ6

139 DREQ7

140 V CC

141 V SS

146 HLDA

147 INT

150 EDACU0

151 EDACU1

152 EDACU2

153 V CC

154 V SS

155 EOP

156 ADS

157 BE0

158 BE1

159 BE2

160 BE3

161 V CC

162 V SS

13.0 ELECTRICAL DATA

13.1 Power and Grounding

The large number of output buffers (address, data and control) can cause power surges as multiple output buffers drive new signal levels simultaneous- ly. The 22 V CC and V SS pins of the M82380 each feed separate functional units to minimize switching induced noise effects. All V CC pins of the M82380 must be connected on the circuit board.

13.2 Power Decoupling

Liberal decoupling capacitance should be placed close to the M82380. The M82380 driving its 32-bit parallel address and data buses at high frequencies can cause transient power surges when driving large capacitive loads. Low inductance capacitors and inter- connects are recommended for the best reliability at high frequencies. Low inductance capacitors are available specifically for Pin Grid Array packages.

13.3 Unused Pin Recommendations

For reliable operation, ALWAYS connect unused in- puts to a valid logic level. As is the case with most other CMOS processes, a floating input will increase the current consumption of the component and give an indeterminate state to the component.

13.4 ICE TM -386 Support

The M82380 specifications provide sufficient drive capability to support the ICE386. On the pins that are generally shared between the i386 processor and the M82380, the additional loading represented by the ICE386 was allowed for in the design of the M82380. 104

13.5 Maximum Ratings

Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b65§Ct o a150§C Supply Voltage with Respect to V SS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀb0.5V to a6.5V Voltage on any other Pin ÀÀÀÀÀ b0.5V to V CC a0.5V NOTE: Stress above those listed above may cause perma- nent damage to the device. This is a stress rating only and functional operation at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Al- though the M82380 contains protective circuitry to reset damage from static electric discharges, always take precautions against high static voltages or elec- tric fields. OPERATING CONDITIONS MIL-STD-883 Symbol Description Min Max Units TC Case Temperature (Instant On) b55 a125 §C VCC Digital Supply Voltage 4.75 5.25 V Extended Temperature Symbol Description Min Max Units TC Case Temperature (Instant On) b40 a110 §C VCC Digital Supply Voltage 4.75 5.25 V Military Temperature Only (MTO) Symbol Description Min Max Units TC Case Temperature (Instant On) b55 a125 §C VCC Digital Supply Voltage 4.75 5.25 V 105

13.6 DC Specifications (Over Specified Operating Conditions)

Symbol Parameter Min Max Unit Notes VIL Input Low Voltage b0.3 0.8 V VIH Input High Voltage 2.0 V CC a 0.3 V VILC CLK2 Input Low Voltage b0.3 0.8 VIHC CLK2 Input High Voltage 2.0 V CC a 0.3 V VOL Output Low Voltage IOL e 4 mA: A2–A31, D0–D31 0.45 V IOL e 5 mA: All Others 0.45 V VOH Output High Voltage I OH e 1 mA: A2–A31, D0–D31 2.4 V IOH eb 0.9 mA: All Others 2.4 V ILI Input Leakage Current for all inputs except: IRQ11–IRQ23, TOUT2 /IRQ3, EOP, DREQ4/IRQ9 g15 mA0 V kVINkVCC ILI1 Input Leakage Current for 10 b300 mA0 V kVINkVCC pins: IRQ11 –IRQ23, (Note 1) @ 16 MHz and 20 MHz TOUT2/IRQ3, EOP , 10 b325 mA0 V kVINkVCCDREQ4/IRQ9 (Note 1) @ 25 MHz ILO Output Leakage Current g15 mA0 k VIN k VCC ICC Supply Current 375 mA CLK2 e 32 MHz (Note 2) CI Capacitance (Input/IO) 12 pF f c e 1 MHz CCLK CLK2 Capacitance 20 pF f c e 1 MHz NOTES: 1. These pins have internal pullups on them. 2. I CC is specified with inputs driven to CMOS levels. I CC may be higher if driven to TTL levels. 106

13.7 AC Specifications

appropriate functional section. Figure 65. Drive Levels and Measurement Points for AC Specification

AC SPECIFICATION TABLES (Over Specified Operating Conditions) Symbol Parameter M82380-16 M82380-20 M82380-25 Notes Min Max Min Max Min Max Operating Frequency 4 MHz 16 MHz 4 MHz 20 MHz 4 MHz 25 MHz Half CLK2 Frequency t1 CLK2 Period 31 ns 125 ns 25 ns 125 ns 20 ns 125 ns t2a CLK2 High Time 9 8 7 at 2.0V t2b CLK2 High Time 5 5 4 at (V CC –0.8)V t3a CLK2 Low Time 9 8 7 at 2.0V t3b CLK2 Low Time 7 6 4 at 0.8V t4 CLK2 Fall Time 8 8 7 (V CC –0.8)V to 0.8V t5 CLK2 Rise Time 8 8 7 0.8V to (V CC –0.8)V EDACK (0–2) t6 Valid Delay 4 36 4 30 4 20 C L e 120 pF t7 Float Delay 4 40 4 32 4 27 (Note 1) A (2–31), BE (0–3) t8 Setup Time 6 6 6 t9 Hold Time 4 4 4 W/R, M/IO , D/C , t10 Valid Delay 6 33 6 28 4 20 C L e 75 pF t11 Float Delay 4 35 4 30 4 29 (Note 1) t12 Setup Time 6 6 6 t13 Hold Time 4 4 4 C L e 75 pF t14 ADS Valid Delay 6 33 6 28 4 19 C L e 75 pF t15 Float Delay 4 35 4 30 4 29 C L e 75 pF t16 Setup Time 21 15 12 t17 Hold Time 4 4 4 Slave ModeÐ D(0–31) Read t18 Valid Delay 3 46 4 46 4 31 C L e 120 pF t19 Float Delay 6 35 6 29 6 21 (Note 1) Slave ModeÐ D(0–31) Write t20 Setup Time 31 29 20 t21 Hold Time 26 26 20 108

AC SPECIFICATION TABLES (Over Specified Operating Conditions) (Continued) Symbol Parameter M82380-16 M82380-20 M82380-25 Notes Min Max Min Max Min Max Master ModeÐ D(0–31) Write t22 Valid Delay 4 48 4 38 8 27 C L e 120 pF t23 Float Delay 4 35 4 27 4 19 (Note 1) Master ModeÐ D(0–31) Read t24 Setup Time 11 11 7 t25 Hold Time 6 6 4 t26 READY Setup Time 21 12 9 t27 Hold Time 4 4 4 t28 WSC (0–1) Setup 6 6 6 t29 Hold 21 21 15 t31 RESET Setup Time 13 12 9 t30 Hold Time 4 4 4 t32 READYO Valid Delay 4 31 4 28 3 21 C L e 25 pF t33 CPU Reset From CLK2 2 18 2 16 2 14 C L e 50 pF t34 HOLD Valid Delay 5 33 5 30 4 22 C L e 100 pF t35 HLDA Setup Time 21 17 17 t36 Hold Time 6 6 4 t37a EOP Setup Time 21 17 13 Synch. EOP t38a EOP Hold Time 4 4 4 t37b EOP Setup Time 11 11 10 Asynch. EOP t38b EOP Hold Time 11 11 10 t39 EOP Valid Delay 5 38 5 30 4 21 C L e 100 pF t40 EOP Float Delay 5 40 5 32 4 21 C L e 100 pF t41a DREQ Setup Time 21 19 17 Synchronous DREQ t42a Hold Time 4 4 4 t41b DREQ Setup Time 11 11 10 Asynchronous DREQ t42b Hold Time 11 11 10 t43 INT Valid Delay 500 500 500 From IRQ Input

15 C L e 75 pF

t46 CLKIN Frequency 0 MHz 10 MHz 0 MHz 10 MHz 0 MHz 10 MHz t47 CLKIN High Time 30 30 30 At 2.0V t48 CLKIN Low Time 50 50 50 At 0.8V NOTE: 1. Float conditions occur when the maximum output current becomes less than ILO in magnitude. Float delay is not tested. For testing purposes, the float condition occurs when the dynamic output driven voltage changes with current loads. 109

Port Address (HEX) Description

00 Read/Write DMA Channel 0 Target Address, A0–A15

01 Read/Write DMA Channel 0 Byte Count, B0–B15

02 Read/Write DMA Channel 1 Target Address, A0–A15

03 Read/Write DMA Channel 1 Byte Count, B0–B15

04 Read/Write DMA Channel 2 Target Address, A0–A15

05 Read/Write DMA Channel 2 Byte Count, B0–B15

06 Read/Write DMA Channel 3 Target Address, A0–A15

07 Read/Write DMA Channel 3 Byte Count, B0–B15

08 Read/Write DMA Channel 0–3 Status/Command I Register

09 Read/Write DMA Channel 0–3 Software Request Register

0A Write DMA Channel 0–3 Set-Reset Mask Register 0B Write DMA Channel 0–3 Mode Register I 0C Write Clear Byte-Pointer FF 0D Write DMA Master-Clear 0E Write DMA Channel 0–3 Clear Mask Register 0F Read/Write DMA Channel 0–3 Mask Register

10 Read/Write DMA Channel 0 Target Address, A24–A31

11 Read/Write DMA Channel 0 Byte Count, B16–B23

12 Read/Write DMA Channel 1 Target Address, A24–A31

13 Read/Write DMA Channel 1 Byte Count, B16–B23

14 Read/Write DMA Channel 2 Target Address, A24–A31

15 Read/Write DMA Channel 2 Byte Count, B16–B23

16 Read/Write DMA Channel 3 Target Address, A24–A31

17 Read/Write DMA Channel 3 Byte Count, B16–B23

18 Write DMA Channel 0–3 Bus Size Register

19 Read/Write DMA Channel 0–3 Chaining Register

1A Write DMA Channel 0–3 Command Register II 1B Write DMA Channel 0–3 Mode Register II 1C Read/Write Refresh Control Register 1E Reset Software Request Interrupt

20 Write Bank B ICW1, OCW2, or OCW3

Read Bank B Poll, Interrupt Request or In-Service Status Register

21 Write Bank B ICW2, ICW3, ICW4 or OCW1

Read Bank B Interrupt Mask Register

22 Read Bank B ICW2

28 Read/Write IRQ8 Vector Register

29 Read/Write IRQ9 Vector Register

2B Read/Write IRQ11 Vector Register 2C Read/Write IRQ12 Vector Register 2D Read/Write IRQ13 Vector Register 2E Read/Write IRQ14 Vector Register 2F Read/Write IRQ15 Vector Register A-1

APPENDIX AÐPorts Listed by Address (Continued) Port Address (HEX) Description

30 Write Bank A ICW1, OCW2 or OCW3

Read Bank A Poll, Interrupt Request or In-Service Status Register

31 Write Bank A ICW2, ICW3, ICW4 or OCW1

Read Bank A Interrupt Mask Register

32 Read Bank A ICW2

38 Read/Write IRQ0 Vector Register

39 Read/Write IRQ1 Vector Register

3A Read/Write IRQ1.5 Vector Register 3B Read/Write IRQ3 Vector Register 3C Read/Write IRQ4 Vector Register 3D Reserved 3E Reserved 3F Read/Write IRQ7 Vector Register

40 Read/Write Counter 0 Register

41 Read/Write Counter 1 Register

42 Read/Write Counter 2 Register

43 Write Control Word Register IÐCounter 0, 1, 2

44 Read/Write Counter 3 Register

45 Reserved

46 Reserved

47 Write Word Register IIÐCounter 3

61 Write Internal Control Port

64 Write CPU Reset Register (Data-1111XXX0H)

72 Read/Write Wait State Register 0

73 Read/Write Wait State Register 1

74 Read/Write Wait State Register 2

75 Read/Write Refresh Wait State Register

76 Reserved

77 Reserved

7F Read/Write Relocation Register

80 Read/Write Internal Diagnostic Port 0

81 Read/Write DMA Channel 2 Target Address, A16–A23

82 Read/Write DMA Channel 3 Target Address, A16–A23

83 Read/Write DMA Channel 1 Target Address, A16–A23

87 Read/Write DMA Channel 0 Target Address, A16–A23

88 Read/Write Internal Diagnostic Port 1

89 Read/Write DMA Channel 6 Target Address, A16–A23

8A Read/Write DMA Channel 7 Target Address, A16–A23 8B Read/Write DMA Channel 5 Target Address, A16–A23 8F Read/Write DMA Channel 4 Target Address, A16–A23 A-2

APPENDIX AÐPorts Listed by Address (Continued) Port Address (HEX) Description

90 Read/Write DMA Channel 0 Requester Address, A0–A15

91 Read/Write DMA Channel 0 Requester Address, A16–A31

92 Read/Write DMA Channel 1 Requester Address, A0–A15

93 Read/Write DMA Channel 1 Requester Address, A16–A31

94 Read/Write DMA Channel 2 Requester Address, A0–A15

95 Read/Write DMA Channel 2 Requester Address, A16–A31

96 Read/Write DMA Channel 3 Requester Address, A0–A15

97 Read/Write DMA Channel 3 Requester Address, A16–A31

98 Read/Write DMA Channel 4 Requester Address, A0–A15

99 Read/Write DMA Channel 4 Requester Address, A16–A31

9A Read/Write DMA Channel 5 Requester Address, A0–A15 9B Read/Write DMA Channel 5 Requester Address, A16–A31 9C Read/Write DMA Channel 6 Requester Address, A0–A15 9D Read/Write DMA Channel 6 Requester Address, A16–A31 9E Read/Write DMA Channel 7 Requester Address, A0–A15 9F Read/Write DMA Channel 7 Requester Address, A16–A31 A0 Write Bank C ICW1, OCW2 or OCW3 Read Bank C Poll, Interrupt Request or In-Service Status Register A1 Write Bank C ICW2, ICW3, ICW4 or OCW1 Read Bank C Interrupt Mask Register A2 Read Bank C ICW2 A8 Read/Write IRQ16 Vector Register A9 Read/Write IRQ17 Vector Register AA Read/Write IRQ18 Vector Register AB Read/Write IRQ19 Vector Register AC Read/Write IRQ20 Vector Register AD Read/Write IRQ21 Vector Register AE Read/Write IRQ22 Vector Register AF Read/Write IRQ23 Vector Register C0 Read/Write DMA Channel 4 Target Address, A0–A15 C1 Read/Write DMA Channel 4 Byte Count, B0–B15 C2 Read/Write DMA Channel 5 Target Address, A0–A15 C3 Read/Write DMA Channel 5 Byte Count, B0–B15 C4 Read/Write DMA Channel 6 Target Address, A0–A15 C5 Read/Write DMA Channel 6 Byte Count, B0–B15 C6 Read/Write DMA Channel 7 Target Address, A0–A15 C7 Read/Write DMA Channel 7 Byte Count, B0–B15 C8 Read DMA Channel 4–7 Status/Command I Register C9 Read/Write DMA Channel 4–7 Software Request Register CA Write DMA Channel 4–7 SetÐReset Mask Register CB Write DMA Channel 4–7 Mode Register I CC Reserved CD Reserved CE Write DMA Channel 4–7 Clear Mask Register CF Read/Write DMA Channel 4–7 Mask Register A-3

APPENDIX AÐPorts Listed by Address (Continued) Port Address (HEX) Description D0 Read/Write DMA Channel 4 Target Address, A24–A31 D1 Read/Write DMA Channel 4 Byte Count, B16–B23 D2 Read/Write DMA Channel 5 Target Address, A24–A31 D3 Read/Write DMA Channel 5 Byte Count, B16–B23 D4 Read/Write DMA Channel 6 Target Address, A24–A31 D5 Read/Write DMA Channel 6 Byte Count, B16–B23 D6 Read/Write DMA Channel 7 Target Address, A24–A31 D7 Read/Write DMA Channel 7 Byte Count, B16–B23 D8 Write DMA Channel 4–7 Bus Size Register D9 Read/Write DMA Channel 4–7 Chaining Register DA Write DMA Channel 4–7 Command Register II DB Write DMA Channel 4–7 Mode Register II A-4

Port Address (HEX) Description DMA CONTROLLER 0D Write DMA Master-Clear 0C Write DMA Clear Byte-Pointer FF C8 Read/Write DMA Channel 4–7 Status/Command I Register 1A Write DMA Channel 0–3 Command Register II DA Write DMA Channel 4–7 Command Register II 0B Write DMA Channel 0–3 Mode Register I CB Write DMA Channel 4–7 Mode Register I 1B Write DMA Channel 0–3 Mode Register II DB Write DMA Channel 4–7 Mode Register II C9 Read/Write DMA Channel 4–7 Software Request Register 1E Reset Software Request Interrupt 0E Write DMA Channel 0–3 Clear Mask Register CE Write DMA Channel 4–7 Clear Mask Register 0F Read/Write DMA Channel 0–3 Mask Register CF Read/Write DMA Channel 4–7 Mask Register 0A Write DMA Channel 0–3 Set-Reset Mask Register CA Write DMA Channel 4–7 Set-Reset Mask Register D8 Write DMA Channel 4–7 Bus Size Register D9 Read/Write DMA Channel 4–7 Chaining Register

APPENDIX BÐPorts Listed by Function (Continued) Port Address (HEX) Description DMA CONTROLLER C0 Read/Write DMA Channel 4 Target Address, A0–A15 8F Read/Write DMA Channel 4 Target Address, A16–A23 D0 Read/Write DMA Channel 4 Target Address, A24–A31 C1 Read/Write DMA Channel 4 Byte Count, B0–B15 D1 Read/Write DMA Channel 4 Byte Count, B16–B23 C2 Read/Write DMA Channel 5 Target Address, A0–A15 8B Read/Write DMA Channel 5 Target Address, A16–A23 D2 Read/Write DMA Channel 5 Target Address, A24–A31 C3 Read/Write DMA Channel 5 Byte Count, B0–B15 D3 Read/Write DMA Channel 5 Byte Count, B16–B23 9A Read/Write DMA Channel 5 Requester Address, A0–A15 9B Read/Write DMA Channel 5 Requester Address, A16–A31 C4 Read/Write DMA Channel 6 Target Address, A0–A15 D4 Read/Write DMA Channel 6 Target Address, A24–A31 C5 Read/Write DMA Channel 6 Byte Count, B0–B15 D5 Read/Write DMA Channel 6 Byte Count, B16–B23 9C Read/Write DMA Channel 6 Requester Address, A0–A15 9D Read/Write DMA Channel 6 Requester Address, A16–A31 C6 Read/Write DMA Channel 7 Target Address, A0–A15 8A Read/Write DMA Channel 7 Target Address, A16–A23 D6 Read/Write DMA Channel 7 Target Address, A24–A31 C7 Read/Write DMA Channel 7 Byte Count, B0–B15 D7 Read/Write DMA Channel 7 Byte Count, B16–B23 9E Read/Write DMA Channel 7 Requester Address, A0–A15 9F Read/Write DMA Channel 7 Requester Address, A16–A31 B-2

APPENDIX BÐPorts Listed by Function (Continued) Port Address (HEX) Description INTERRUPT CONTROLLER Read Bank B Poll, Interrupt Request or In-Service Status Register Read Bank B Interrupt Mask Register 2B Read/Write IRQ11 Vector Register 2C Read/Write IRQ12 Vector Register 2D Read/Write IRQ13 Vector Register 2E Read/Write IRQ14 Vector Register 2F Read/Write IRQ15 Vector Register A0 Write Bank C ICW1, OCW2 or OCW3 Read Bank C Poll, Interrupt Request or In-Service Status Register A1 Write Bank C ICW2, ICW3, ICW4 or OCW1 Read Bank C Interrupt Mask Register A2 Read Bank C ICW2 A8 Read/Write IRQ16 Vector Register A9 Read/Write IRQ17 Vector Register AA Read/Write IRQ18 Vector Register AB Read/Write IRQ19 Vector Register AC Read/Write IRQ20 Vector Register AD Read/Write IRQ21 Vector Register AE Read/Write IRQ22 Vector Register AF Read/Write IRQ23 Vector Register Read Bank A Poll, Interrupt Request oor In-Service Status Register Read Bank A Interrupt Mask Register 3A Read/Write IRQ1.5 Vector Register 3B Read/Write IRQ3 Vector Register 3C Read/Write IRQ4 Vector Register 3D Reserved 3E Reserved 3F Read/Write IRQ7 Vector Register B-3

APPENDIX BÐPorts Listed by Function (Continued) Port Address (HEX) Description PROGRAMMABLE INTERVAL TIMER 1C Read/Write Refresh Control Register INTERNAL CONTROL AND DIAGNOSTIC PORTS 7F Read/Write Relocation Register INTEL RESERVED PORTS 2A Reserved 3D Reserved 3E Reserved

The M82380 provides all of the signals necessary to interface it to an i386 processor. It has separate 32-bit address and data buses. It also has a set of control signals to support operation as a bus master or a bus slave. Several special function signals exist on the M82380 for interfacing the system support peripherals to their respective system counterparts. Following are the definitions of the individual pins of the M82380. These brief descriptions are provided as a reference. Each signal is further defined within the sections which describe the associated M82380 function. A2-A31 I/O ADDRESS BUS This is the 32-bit address bus. The addresses are doubleword memory and I/O addresses. These are three-state signals which are active only during Mas- ter mode. The address lines should be connected directly to the i386’s local bus. BE0 I/O BYTE-ENABLE 0 BE0 active indicates that data bits D0–D7 are being accessed or are valid. It is connected directly to the i386’s BE0 . The byte enable signals are active out- puts when the M82380 is in the Master mode. BE1 I/O BYTE-ENABLE 1 BE1 active indicates that data bits D8–D15 are be- ing accessed or are valid. It is connected directly to the i386’s BE1 . The byte enable signals are active only when the M82380 is in the Master mode. BE2 I/O BYTE-ENABLE 2 BE2 active indicates that data bits D15–D23 are be- ing accessed or are valid. It is connected directly to the i386’s BE2 . The byte enable signals are active only when the M82380 is in the Master mode. BE3 I/O BYTE-ENABLE 3 BE3 active indicates that data bits D24–D31 are be- ing accessed or are valid. The byte enable signals are active only when the M82380 is in the Master mode. This pin should be connected directly to the i386’s BE3 . This pin is used for factory testing and must be low during reset. The M80386 drives BE3 low during reset. D0–D31 I/O DATA BUS This is the 32-bit data bus. These pins are active outputs during interrupt acknowledges, during Slave accesses, and when the M82380 is in the Master mode. CLK2 I PROCESSOR CLOCK This pin must be connected to CLK2. The M82380 monitors the phase of this clock in order to remain synchronized with the i386 processor. This clock drives all of the internal synchronous circuitry. D/C I/O DATA/CONTROL D/C is used to distinguish between i386 processor control cycles and DMA or i386 processor data ac- cess cycles. It is active as an output only in the Mas- ter mode. W/R I/O WRITE/READ W/R is used to distinguish between write and read cycles. It is active as an output only in the Master mode. M/IO I/O MEMORY/IO M/IO is used to distinguish between memory and IO accesses. It is active as an output only in the Master mode. ADS I/O ADDRESS STATUS This signal indicates presence of a valid address on the address bus. It is active as output only in the Master mode. ADS is active during the first T-state where addresses and control signals are valid. NA I NEXT ADDRESS Asserted by a peripheral or memory to begin a pipe- lined address cycle. This pin is monitored only while the M82380 is in the Master mode. In the Slave mode, pipelining is determined by the current and past status of the ADS and READY signals. C-1

This is an active-high signal to the i386 processor to request control of the system bus. When control is granted, the i386 processor activates the hold ac- knowledge signal (HLDA). HLDA I HOLD ACKNOWLEDGE This input signal tells the DMA controller that the i386 processor has relinquished control of the sys- tem bus to the DMA controller. DREQ (0–3, 5–7) I DMA REQUEST The DMA Request inputs monitor requests from pe- ripherals requiring DMA service. Each of the eight DMA channels has one DREQ input. These active- high inputs are internally synchronized and priori- tized. Upon reset, channel 0 has the highest priority and channel 7 the lowest. DREQ4/IRQ9 I DMA/INTERRUPT RE- QUEST This is the DMA request input for channel 4. It is also connected to the interrupt controller via interrupt re- quest 9. This internal connection is available for DMA channel 4 only. The interrupt input is active low and can be programmed as either edge of level trig- gered. Either function can be masked by the appro- priate mask register. Priorities of the DMA channel and the interrupt request are not related but follow the rules of the individual controllers. Note that this pin has a weak internal pull-up. This causes the interrupt request to be inactive, but the DMA request will be active if there is no external connection made. Most applications will require that either one or the other of these functions be used, but not both. For this reason, it is advised that DMA channel 4 be used for transfers where a software request is more appropriate (such as memory-to- memory transfers). In such an application, DREQ4 can be masked by software, freeing IRQ9 for other purposes. EOP I/O END OF PROCESS As an output, this signal indicates that the current Requester access is the last access of the currently operating DMA channel. It is activated when Termi- nal Count is reached. As an input, it signals the DMA channel to terminate the current buffer and proceed to the next buffer, if one is available. This signal may be programmed as an asynchronous or synchro- nous input. EOP must be connected to a pull-up resistor. This will prevent erroneous external requests for termina- tion of a DMA process. EDACK (0–2) O ENCODED DMA ACKNOWL- EDGE These signals contain the encoded acknowledge- ment of a request for DMA service by a peripheral. The binary code formed by the three signals indi- cates which channel is active. Channel 4 does not have a DMA acknowledge. The inactive state is indi- cated by the code 100. During a Requester access, EDACK presents the code for the active DMA chan- nel. During a Target access, EDACK presents the inactive code 100. IRQ (11–23) I INTERRUPT REQUEST These are active low interrupt request inputs. The inputs can be programmed to be edge or level sensi- tive. Interrupt priorities are programmable as either fixed or rotating. These inputs have weak internal pull-up resistors. Unused interrupt request inputs should be tied inactive externally. INT O INTERRUPT OUT INT signals the i386 processor that an interrupt re- quest is pending. CLKIN I TIMER CLOCK INPUT This is the clock input signal to all of the M82380’s programmable timers. It is independent of the sys- tem clock input (CLK2). TOUT1/REF O TIMER 1 OUTPUT/REFRESH This pin is software programmable as either the di- rect output of Timer 1, or as the indicator of a refresh cycle in progress. As REF , this signal is active during the memory read cycle which occurs during refresh. TOUT2/IRQ3 I/O TIMER 2 OUTPUT/INTER- RUPT REQUEST3 This is the inverted output of Timer 2. It is also con- nected directly to interrupt request 3. External hard- ware can use IRQ3 if Timer 2 is programmed as OUTe0 (TOUT2 e1) TOUT3 O TIMER 3 OUTPUT This is the inverted output of Timer 3. C-2

mode, and while it is in the Slave mode. required by the currently accessed memory or I/O. 11 disables the wait-state generator. directly the i386 processor’s READY input. Table 18. Wait-State Select Inputs

M82380 TIMER UNIT SYSTEM NOTES The M82380 DMA controller with Integrated System Peripherals is functionally inconsistent with the data sheet. This document explains the behavior of the M82380 Timer Unit and outlines subsequent limita- tions of the timer unit. This document also provides recommended workarounds. Overview There are two areas in which the M82380 timer unit exhibits non-specified behavior: 1. Mode 0 operation 2. Write Cycles to the M82380 Timer Unit MODE 0 OPERATION

Description

For Mode 0 operation, the M82380 timer is specified as follows: ‘‘1. Writing the first byte disables counting, OUT is set LOW immediately . . . ’’ Due to mode 0 errata, this should read as follows: ‘‘1. Writing the first byte sets OUT LOW imme- diately. If the counter has not yet expired, writ- ing the first byte also disables counting. How- ever, if the counter has expired, writing the first count does not disable counting, although OUT still behaves correctly (set LOW immedi- ately).’’ Consequences Software errors will occur if algorithms depend on the M82380 timer unit to stop counting after writing the first byte. Thus, software that is based on the M8254 core will not function reliably on the M82380 timer unit. Note, however, that the external signal of the timer behaves correctly. Solution As long as software algorithms are aware of this be- havior, there should be no problems, as the external signal behaves correctly. Long Term Plans Currently, Intel has no plans to fix this behavior of the M82380 timer unit. WRITE CYCLES TO THE M82380 TIMER UNIT This errata applies only to SLAVE WRITE cycles to the M82380 timer unit. During these cycles, the data being written into the M82380 timer unit may be cor- rupted if CLKIN is not inhibited during a certain ‘‘win- dow’’ of the write cycle. Please refer to Figure 1. During write cycles to the M82380 timer unit, the M82380 translates the 386DX interface signals such as ADS , W/R , M/IO , and D/C into several internal signals that control the operation of the internal sub- blocks (e.g., Timer Unit). The M82380 timer unit is controlled by such internal signals. These internal signals are generated and sampled with respect to two separate clock signals: CLK2 (the system clock) and CLKIN (the M82380 timer unit clock). Since the CLKIN and CLK2 clock signals are used internally to generate control signals for the inter- face to the timer unit, some timing parameters must be met in order for the interface logic to function properly. Those timing parameters are met by inhibiting the CLKIN signal for a specific window during Write Cy- cles to the M82380 Timer Unit. The CLKIN signal must be inhibited using external logic, as the GATE function of the M82380 timer unit is not guaranteed to totally inhibit CLKIN. D-1

This CLKIN inhibit circuitry guarantees proper write cycles to the M82380 timer unit. Without this solution, write cycles to the M82380 tim- er unit could place corrupted data into the timer unit registers. This, in turn, could yield inaccurate results and improper timer operation. The proposed solution would involve a hardware modification for existing systems. Solution A timing waveform (Figure 2) shows the specific win- dow during which CLKIN must be inhibited. Please note that CLKIN must only be inhibited during the window shown in Figure 2. This window is defined by two AC timing parameters: ta e 9n s tb e 28 ns The proposed solution provides a certain amount of system ‘‘guardband’’ to make sure that this window is avoided. PAL equations for a suggested workaround are also included. Please refer to the comments in the PAL codes for stated assumptions of this particular work- around. A state diagram (Figure 3) is provided to help clarify how this PAL is designed. Figure 4 shows how this PAL would fit into a system workaround. In order to show the effect of this work- around on the CLKIN signal, Figure 5 shows how CLKIN is inhibited. Note that you must still meet the CLKIN AC timing parameters (e.g., t 47 (min), t 48 (min)) in order for the timer unit to function properly. Please note that this workaround has not been test- ed. It is provided as a suggested solution. Actual solutions will vary from system to system. Long Term Plans Intel has no plans to fix this behavior in the M82380 timer unit. module Timer 82380 Fix title ’M82380 Timer Unit CLKIN INHIBIT signal PAL Solution ’ Timer Unit Fix device ’P16R6’; ‘This PAL inhibits the CLKIN signal (that comes from an oscillator) ‘during Slave Writes to the M82380 Timer unit. ‘ASSUMPTION: This PAL assumes that an external system address ‘ decoder provides a signal to indicate that an 82380 ‘ Timer Unit access is taking place. This input ‘ signal is called TMR in this PAL. This PAL also ‘ assumes that this TMR signal occurs during a ‘ specific T-State. Please see Figure 3 of this ‘ document to see when this signal is expected to ‘ be active by this PAL. ‘NOTE: This PAL does not support pipelined 82380 SLAVE ‘ cycles. ‘(c) Intel Corporation 1989. This PAL is provided as a proposed ‘method of solving a certain M82380 Timer Unit problem. This PAL ‘has not been tested or validated. Please validate this solution ‘for your system and application. D-2

‘Input Pins‘ CLK2 pin 1; ‘System Clock RESET pin 2; ‘Microprocessor RESET signal TMR pin 3; ‘Input from Address Decoder, indicating ‘an access to the timer unit of the ‘82380. !RDY pin 4; ‘End of Cycle indicator !ADS pin 5; ‘Address and control strobe CLK pin 6; ‘PHI2 clock W R pin 7; ‘Write/Read Signal‘ nc1 pin 8; ‘No Connect 0‘ nc3 pin 9; ‘No Connect 1‘ GNDa pin 10; ‘Tied to ground, documentation only GNDb pin 11; ‘Output enable, documentation only CLKIN IN pin 12; ‘Input–CLKIN directly from oscillator ‘Output Pins‘ Q 0 pin 18; ‘Internal signal only, fed back to ‘PAL logic‘ CLKIN OUT pin 17; ‘CLKIN signal fed to 82380 Timer Unit INHIBIT pin 16; ‘CLKIN Inhibit signal S0 pin 15; ‘Unused State Indicator Pin S1 pin 14; ‘Unused State Indicator Pin ‘Declarations‘ Valid ADS 4 ADS & CLK ; ‘ADS # sampled in PHI1 of 386DX T-State Valid RDY 4 RDY & CLK ; ‘RDY # sampled in PHI1 of 386DX T-State Timer Acc 4 TMR & CLK ; ‘Timer Unit Access, as provided by ‘external Address Decoder ‘ State Diagram [INHIBIT, S1, S0 ] state 000: if RESET then 000 else if Valid A D S&W R then 001 else 000; state 001: if RESET then 000 else if Timer Acc then 010 else if !Timer Acc then 000 else 001; state 010: if RESET then 000 else if CLK then 110 else 010; state 110: if RESET then 000 else if CLK then 111 else 110; D-3

state 111: if RESET then 000 else if CLK then 011 else 111; state 011: if RESET then 000 else if Valid RDY then 000 else 011; state 100: if RESET then 000 else 000; state 101: if RESET then 000 else 000; EQUATIONS Q 0: 4 CLKIN IN ; ‘Latched incoming clock. This signal is used ‘internally to feed into the MUX-ing logic‘ CLKIN OUT : 4 (INHIBIT & CLKIN OUT & !RESET) 0(!INHIBIT & Q 0 & !RESET); ‘Equation for CLKIN OUT. This ‘feeds directly to the 82380 Timer Unit.‘ END Page 1 ABEL(tm) 3.10 - Document Generator 30-June 89 03:17 PM

82380 Timer Unit CLKIN

INHIBIT signal PAL Solution Equations for Module Timer

82380 Fix

• Reduced Equations: !INHIBIT : 4 (!CLK & !INHIBIT # C L K&S 0 # RESET # !S1); !S1 : 4 (RESET # INHIBIT & !S1 # CLK & !INHIBIT & ! ER D Y&S 0&S 1 # !CLK & !S1 # !S1 & !TMR # !S0 & !S1); !S0 : 4 (RESET # INHIBIT & !S1 # CLK & !INHIBIT & ! ER D Y&S 1 # !CLK & !S0 # S0 & !S1 # ! S 1&! W R # EADS & !S1); D-4

Figure 1. Translation of i386 TM DX Signals to Internal M82380 Timer Unit Signals

Figure 2. M82380 Timer Unit Write Cycle