M80C86 INTEL | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 19
Technical content
1 MByte of Memory
systems and MAXimum for larger applications such as multiprocessing. It is available in 40-pin DIP package. Figure 1. M80C86 CPU Block Diagram Figure 2. M80C86 40-Lead DIP Configuration
Table 1. Pin Description regard to additional bus buffers). being used for data accessing. ‘‘hold.’’ It is LOW during T 1 for the first interrupt acknowledge cycle.
Table 1. Pin Description (Continued) memory of I/O read cycle, depending on the state of the S 2 pin. setup and hold times are not met. resetting the interrupt enable bit. INTR is internally synchronized. cycle on the leading edge of CLK. VCC 40 VCC: a5V power supply pin. GND 1, 20 GROUND: Both must be connected. operate in. The two modes are discussed in the following sections.
tions are as described above. passive state in T 3 or T W is used to indicate the end of a bus cycle. status lines are encoded as shown.
- A pulse of 1 CLK wide from another local bus master indicates a
local bus request (‘‘hold’’) to the M80C86 (pulse 1).
- During a T 4 or T 1 clock cycle, a pulse 1 CLK wide from the
- A pulse 1 CLK wide from the requesting master indicates to the
M80C86 can reclaim the local bus at the next CLK. pulses. There must be one dead CLK cycle after each bus exchange.
- Request occurs on or before T 2.
- Current cycle is not the low byte of a word (on an odd address).
- Current cycle is not the first acknowledge of an interrupt
- A locked instruction is not currently executing.
- Local bus will be released during the next clock.
- A memory cycle will start within 3 clocks. Now the four rules for a
after which the queue operation is performed. pin functions which are unique to minimum mode are described; all other pin functions are described above. T1 of any bus cycle. Note that ALE is never floated.
- See the section on Bus Hold Circuitry.
for system debug or power critical applications. for bringing up your system. dissipation is directly related to operating frequency.
The internal functions of the M80C86 processor are partitioned logically into two processing units. The first is the Bus Interface Unit (BIU) and the second is the Execution Unit (EU) as shown in the block dia- gram of Figure 1. These units can interact directly but for the most part perform as separate asynchronous operational processors. The bus interface unit provides the func- tions related to instruction fetching and queuing, op- erand fetch and store, and address relocation. This unit also provides the basic bus control. The overlap of instruction pre-fetching provided by this unit serves to increase processor performance through improved bus bandwidth utilization. Up to 6 bytes of the instruction stream can be queued while waiting for decoding and execution. The instruction stream queuing mechanism allows the BIU to keep the memory utilized very efficiently. Whenever there is space for at least 2 bytes in the queue, the BIU will attempt a word fetch memory cycle. This greatly reduces ‘‘dead time’’ on the memory bus. The queue acts as a First-In-First Out (FIFO) buffer, from which the EU extracts instruction bytes as required. If the queue is empty (following a branch instruction, for example), the first byte into the queue immediately becomes available to the EU. The execution units receives pre-fetched instruc- tions from the BIU queue and provides un-relocated operand addresses to the BIU. Memory operands are passed through the BIU for processing by the EU, which passes results to the BIU for storage. See the Instruction Set description for further register set and architectural descriptions. NOTE: Additional information on memory organization, re- quirements for supporting minimum and maximum modes, bus operation, basic system timing, and ex- ternal interface of the M80C86 is described in the Microsystems Components Handbook. DEVIATION DESCRIPTION A 20–25 ns glitch occurs on the 80C86/80C88 RD pin immediately following a read cycle. The problem has been fully characterized with the following re- sults: 1. The read cycle must be 4 clocks followed by 2 passive clocks. 2. Cycle following the read cycle must be a data read/write or an I/O read/write. 3. The Ý of bytes in the queue required to cause the glitch varies by instruction. 4. The glitch appears on the falling edge of the first passive clock. 5. The magnitude of the glitch depends on the ca- pacitive loading of the RD Ý pin. 6. The glitch occurs for both Min and Max mode operations. 7. V CC variations from 4.5V through 5.5V have no effect on the glitch. 8. Temperature variations (within allowed tempera- ture range) also have no effect on the glitch. IMPACT ON SYSTEM DESIGN Systems which use the RD strobe to clock a state machine or any other edge triggered device are most vulnerable and most likely to malfunction. The problem may also impact other Min mode sys- tems, particularly those in which the system address latches are enabled all the time (such as the exam- ple minimum mode system illustrated in the 80C86 data sheet). In such designs, the RD signal is used to turn off the output buffers of the memory and pe- ripheral devices connected to the local bus at the end of a bus cycle. A false pulse on the RD pin in a TP or a T1 state following a read cycle may not allow for sufficient recovery time for a previously accessed device. The probability of a failure is higher for low speed designs using slow memory and peripheral devices which require high recovery times between successive accesses. The problem will not be seen if the address latches are disabled at the end of any bus cycle since all the devices connected to the bus will then be deselected when the false pulse occurs. Most Max mode systems do not use the RD signal and are therefore not likely to be affected.
ABSOLUTE MAXIMUM RATINGS * Supply Voltage (With respect to ground) ÀÀÀÀÀÀÀÀÀÀÀ b0.5 to 8.0V Input Voltage Applied Output Voltage Applied Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.0W Storage TemperatureÀÀÀÀÀÀÀÀÀÀÀÀÀ b65§Ct o1 5 0 §C Case Temperature Under BiasÀÀÀ b55§Ct o a125§C NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. Operating Conditions Symbol Description Min Max Units TC Case Temperature (Instant On) b55 a125 §C VCC Digital Supply Voltage (M80C86) 4.50 5.50 V VCC Digital Supply Voltage (M80C86-2) 4.75 5.25 V D.C. CHARACTERISTICS (Over Specified Operating Conditions) Symbol Parameter Min Max Units Comments VIL Input Low Voltage a0.8 V VIH Input High Voltage 2.2 V (All inputs except clock and MN/MX VCH Clock and MN/MX VCCb0.8 V Input High Voltage VOL Output Low Voltage 0.4 V I OL e 2.5 mA VOH Output High Voltage 3.0 V I OH eb 2.5 mA VCCb0.4 I OH eb 100 mA ICC Power Supply Current 10 mA/MHz V IL e GND, V IH e VCC ICCS Standby Supply Current 500 mAV IN e VCC or GND Outputs Unloaded CLK e GND or V CC ILI Input Leakage Current g1.0 mA0 V s VIN s VCC IBHL Input Leakage Current 40 400 mAV IN e 0.8V (Bus Hold Low) (Note 2) IBHH Input Leakage Current b40 b400 mAV IN e 3.0V (Bus Hold High) (Note 3) ILO Output Leakage Current g10 mAV OUT e GND or V CC CIN Capacitance of Input Buffer 10 pF (Note 1) (All inputs except AD 0 –AD15,R Q /GT) CIO Capacitance of I/O Buffer 20 pF (Note 1) (AD0 –AD15,R Q /GT) COUT Output Capacitance 15 pF (Note 1) NOTES: 1. Characterization conditions are a) Frequency e 1 MHz; b) Unmeasured pins at GND; c) V IN at a5.0V or GND. 2. I BHL should be measured after lowering V IN to GND and then raising V IN to 0.8V on the following pins: 2–16, 34–39. 3. I BHH should be measured after raising V IN to V CC and then lowering V IN to 3.0V on the following pins: 2–16, 26–32, 34–39.
A.C. CHARACTERISTICS (Over Specified Operating Conditions) MINIMUM COMPLEXITY SYSTEM TIMING REQUIREMENTS Symbol Parameter M80C86 M80C86-2 Units Comments Min Max Min Max TCLCL CLK Cycle Period 200 D.C. 125 D.C. ns TCLCH CLK Low Time 118 68 ns TCHCL CLK High Time 69 44 ns TCH1CH2 CLK Rise Time 10 10 ns From 1.0V to 3.5V TCL2CL1 CLK Fall Time 10 10 ns From 3.5V to 1.0V TDVCL Data in Setup Time 30 20 ns TCLDX Data in Hold Time 10 10 ns TR1VCL RDY Setup Time 35 35 ns into M82C84A (Notes 1, 2) TCLR1X RDY Hold Time 0 0 ns into M82C84A (Notes 1, 2) TRYHCH READY Setup 118 68 ns Time into M80C86 TCHRYX READY Hold Time 30 20 ns into M80C86 TRYLCL READY Inactive to b5 b5n s CLK (Note 3) THVCH HOLD Setup Time 35 20 ns TINVCH INTR, NMI, TEST 30 15 ns Setup Time (Note 2) TILIH Input Rise Time 15 15 ns From 0.8V to 2.0V (Except CLK) TIHIL Input Fall Time 15 15 ns From 2.0V to 0.8V (Except CLK)
A.C. CHARACTERISTICS (Over Specified Operating Conditions) (Continued) Timing Responses Symbol Parameter M80C86 M80C86-2 Units Comments Min Max Min Max TCLAV Address Valid Delay 10 110 10 60 ns TCLAX Address Hold Time 10 10 ns TCLAZ Address Float TCLAX 80 TCLAX 50 ns Delay TLHLL ALE Width TCLCH b20 TCLCH b10 ns TCLLH ALE Active Delay 80 50 ns TCHLL ALE Inactive Delay 85 55 ns TLLAX Address Hold Time TCHCL b10 TCHCL b10 ns to ALE Inactive TCLDV Data Valid Delay 10 110 10 60 ns TCHDX Data Hold Time 10 10 ns TWHDX Data Hold Time TCLCH b30 TCLCH b30 ns After WR TCVCTV Control Active 10 110 10 70 ns Delay 1 TCHCTV Control Active 10 110 10 60 ns Delay 2 TCVCTX Control Inactive 10 110 10 70 ns Delay TAZRL Address Float to 0 0 ns READ Active TCLRL RD Active Delay 10 165 10 100 ns TCLRH RD Inactive Delay 10 150 10 80 ns TRHAV RD Inactive to Next TCLCL b45 TCLCL b40 ns Address Active TCLHAV HLDA Valid Delay 10 160 10 100 ns TRLRH RD Width 2TCLCL b75 2TCLCL b50 ns TWLWH WR Width 2TCLCL b60 2TCLCL b40 ns TAVAL Address Valid to TCLCH b60 TCLCH b40 ns ALE Low TOLOH Output Rise Time 15 15 ns From 0.8V to 2.0V TOHOL Output Fall Time 15 15 ns From 2.0V to 0.8V NOTES: 1. Signal at M82C84A shown for reference only. See M82C84A data sheet for the most recent specifications. 2. Setup requirement for asynchronous signal only to guarantee recognition at next CLK. 3. Applies only to T2 state. (5 ns into T3).
A.C. TESTING INPUT, OUTPUT WAVEFORM INPUT/OUTPUT 271058–3 A.C. Testing inputs are driven at V IH a 0.4V for a logic ‘‘1’’ and VIL b 0.4V for a logic ‘‘0’’. The clock is driven at V CH a 0.4V and VCL b 0.4V. Timing measurements are made at 1.5V. A.C. TESTING LOAD CIRCUIT 271058–4 CL Includes Jig Capacitance WAVEFORMS MINIMUM MODE 271058–5
WAVEFORMS (Continued) MINIMUM MODE (Continued) 271058–6 NOTES: 1. All output timing measurements are made at 1.5V. 2. RDY is sampled near the end of T 2,T 3,T W to determine if T W machines states are to be inserted. 3. Two INTA cycles run back-to-back. The M80C86 local ADDR/DATA BUS is floating during both INTA cycles. Control signals shown for second INTA cycle. 4. Signals at M82C84A are shown for reference only. 13
A.C. CHARACTERISTICS MAX MODE SYSTEM (USING M82C88 BUS CONTROLLER) TIMING REQUIREMENTS Symbol Parameter M80C86 M80C86-2 Units Comments Min Max Min Max TCLCL CLK Cycle Period 200 D.C. 125 D.C. ns TCLCH CLK Low Time 118 68 ns TCHCL CLK High Time 69 44 ns TCH1CH2 CLK Rise Time 10 10 ns From 1.0V to 3.5V TCL2CL1 CLK Fall Time 10 10 ns From 3.5V to 1.0V TDVCL Data in Setup Time 30 20 ns TCLDX Data in Hold Time 10 10 ns TR1VCL RDY Setup Time into M82C84A 35 35 ns (Notes 1, 2) TCLR1X RDY Hold Time into M82C84A 0 0 ns (Notes 1, 2) TRYHCH READY Setup Time into M80C86 118 68 ns TCHRYX READY Hold Time into M80C86 30 20 ns TRYLCL READY Inactive to b5 b5n s CLK (Note 4) TINVCH Setup Time for Recognition 30 15 ns (INTR, NMI, TEST ) (Note 2) TGVCH RQ /GT Setup Time 30 15 ns TCHGX RQ Hold Time into M80C86 40 30 ns TILIH Input Rise Time 15 15 ns From 0.8V to 2.0V (Except CLK) TIHIL Input Fall Time 15 15 ns From 2.0V to 0.8V (Except CLK)
A.C. CHARACTERISTICS (Continued) TIMING RESPONSES Symbol Parameter M80C86 M80C86-2 Units Comments Min Max Min Max TCLML Command Active 5 45 5 35 ns Delay (Note 1) TCLMH Command Inactive 5 45 5 35 ns Delay (Note 1) TRYHSH READY Active to 110 65 ns Status Passive (Note 3) TCHSV Status Active Delay 10 110 10 60 ns TCLSH Status Inactive Delay 10 130 10 70 ns TCLAV Address Valid Delay 10 110 10 60 ns TCLAX Address Hold Time 10 10 ns TCLAZ Address Float Delay TCLAX 80 TCLAX 50 ns TSVLH Status Valid to ALE High (Note 1) 35 20 ns TSVMCH Status Valid to 35 30 ns MCE High (Note 1) TCLLH CLK Low to ALE Valid (Note 1) 35 20 ns TCLMCH CLK Low to MCE High (Note 1) 35 25 ns TCHLL ALE Inactive Delay (Note 1) 4 35 4 25 ns TCLDV Data Valid Delay 10 110 10 60 ns TCHDX Data Hold Time 10 10 ns TCVNV Control Active Delay (Note 1) 5 45 5 45 ns TCVNX Control Inactive Delay (Note 1) 5 45 10 45 ns TAZRL Address Float to Read Active 0 0 ns TCLRL RD Active Delay 10 165 10 100 ns TCLRH RD Inactive Delay 10 150 10 80 ns TRHAV RD Inactive to TCLCL b45 TCLCL b40 ns Next Address Active TCHDTL Direction Control 50 50 ns Active Delay (Note 1) TCHDTH Direction Control 35 30 ns Inactive Delay (Note 1) TCLGL GT Active Delay 0 85 0 50 ns TCLGH GT Inactive Delay 0 85 0 50 ns TRLRH RD Width 2TCLCL b75 2TCLCL b50 ns TOLOH Output Rise Time 15 15 ns From 0.8V to 2.0V TOHOL Output Fall Time 15 15 ns From 2.0V to 0.8V NOTES: 1. Signal at M82C84A or M82C88 shown for reference only. See M82C84A and M82C88 for the most recent specifications. 2. Setup requirement for asynchronous signal only to guarantee recognition at next CLK. 3. Applies only to T3 and wait states. 4. Applies only to T2 state (5 ns into T3).
A.C. TESTING INPUT, OUTPUT WAVEFORM INPUT/OUTPUT 271058–7 A.C. Testing inputs are driven at V IH a 0.4V for a logic ‘‘1’’ and VIL b 0.4V for a logic ‘‘0’’. The clock is driven at V CH a 0.4V and VCL b 0.4V. Timing measurements are made at 1.5V. A.C. TESTING LOAD CIRCUIT 271058–8 CL Includes Jig Capacitance WAVEFORMS MAXIMUM MODE 271058–9
WAVEFORMS (Continued) MAXIMUM MODE (Continued) 271058–10 NOTES: 1. All timing measurements are made at 1.5V. 2. RDY is sampled near the end of T 2,T 3,T W to determine if T W machines states are to be inserted. 3. Cascade address is valid between first and second INTA cycle. 4. Two INTA cycles run back-to-back. The M80C86 local ADDR/DATA BUS is floating during both INTA cycles. Control for pointer address is shown for second INTA cycle. 5. Signals at M82C84A or M82C88 are shown for reference only. 6. The issuance of the M82C88 command and control signals (MRDC , MWTC , AMWC , IORC , IOWC , AIOWC , INTA and DEN) lags the active high M82C88 CEN. 7. Status inactive in state just prior to T
WAVEFORMS (Continued) ASYNCHRONOUS SIGNAL RECOGNITION 271058–11 NOTE: Setup requirements for asynchronous signals only to guarantee recognition at next CLK. BUS LOCK SIGNAL TIMING (MAXIMUM MODE ONLY) 271058–12 RESET TIMING 271058–13 REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY) 271058–14 NOTE: The coprocessor may not drive the buses outside the region shown without risking contention.
WAVEFORMS (Continued) HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY) 271058–15 A.C. TESTING VFLOAT TIMING 271058–16 NOTE: 1. V L for High to float tests is 0V and V L for Low to float tests is 4.0V. VFLOAT TIMING TESTING LOAD CIRCUIT 271058–17