M80C51

M80C51FB INTEL | Alldatasheet

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October 1994 Order Number: 271172-002 M80C51FB CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER Military M80C51FB Ð 3.5 MHz to 12 MHz, V CC e 5V g20% M80C51FB-16 Ð 3.5 MHz to 16 MHz, V CC e 5V g20% Y Three 16-Bit Timer/Counters Y Programmable Clock Out Y Programmable Counter Array with: Ð High Speed Output, Ð Compare/Capture, Ð Pulse Width Modulator, Ð Watchdog Timer capabilities Y Up/Down Timer/Counter Y 256 Bytes of On-Chip Data RAM Y Boolean Processor Y ONCE (On-Circuit Emulation) Mode Y Available in 40-pin CERDIP and 44-pin Leadless Chip Carrier Packages Y Gull Wing and J-Lead Packages also Available Y 32 Programmable I/O Lines Y 7 Interrupt Sources Y Programmable Serial Channel with: Ð Framing Error Detection Ð Automatic Address Recognition Y TTL and CMOS Compatible Logic Levels Y 64K External Program Memory Space Y 64K External Data Memory Space Y MCSÉ 51 Microcontroller Fully Compatible Instruction Set Y Power Saving Idle and Power Down Modes Y Military Temperature Range: b55§Ct o a125§C( T C) MEMORY ORGANIZATION PROGRAM MEMORY: The M80C51FB can address up to 64K of program memory external to the chip. DATA MEMORY: This microcontroller has a 25 6 x 8 on-chip RAM. In addition it can address up to 64K bytes of external data memory. The Intel M80C51FB is a single-chip control-oriented microcontroller which is fabricated on Intel’s reliable CHMOS III-E technology. Being a member of the family of MCS 51 microcontrollers, the M80C51FB uses the same powerful instruction set, has the same architecture, and is pin for pin compatible with the existing MCS 51 microcontroller family of products. The M80C51FB is an enhanced version of the M80C51. Its added features make it an even more powerful microcontroller for applications that require Pulse Width Modulation, High Speed I/O, and up/down counting capabilities such as motor control or fin actuation. It also has a more versatile serial channel that facilitates multi-processor communications.

Figure 1. M80C51FB Block Diagram

Figure 2. M80C51FB Pin Connections

Figure 4. External Clock Drive Configuration ues until the Power Down Mode is terminated. and stabilize (normally less than 10 ms). puts the device into Power Down. writes to a port pin or to external memory. 2) Hold ALE low as RST is deactivated. Table 1. Status of the External Pins during Idle and Power Down

ABSOLUTE MAXIMUM RATINGS * Case Temperature under Bias (6)ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀb55§Ct o a125§C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b65§Ct o a150§C Voltage on EA /VPP Pin to V SS ÀÀÀÀÀÀÀ0V to a13.0V Voltage on Any Other Pin to V SS ÀÀb0.5V to a6.5V Maximum I OL Per I/O Pin ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ15 mA Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W (based on PACKAGE heat transfer limitations, not device power consumption) NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. Operating Conditions Symbol Description Min Max Unit TC Case Temperature (Instant On) b55 a125 §C VCC Digital Supply Voltage 4.0 6.0 V fOSC Oscillator Frequency 3.5 16 MHz D.C. CHARACTERISTICS: (Over Specified Operating Conditions) Symbol Parameter Min Max Unit Test Conditions VIL Input Low Voltage b0.5 0.2 V CCb0.1 V VIH Input High Voltage 0.2 V CCa0.9 V CCa0.5 V (Except XTAL1, RST) VIH1 Input High Voltage (XTAL1, RST) 0.7 V CC VCCa0.5 V VOL Output Low Voltage (5) 0.3 V I OL e 100 mA (Note 1) (Ports 1, 2, and 3) 0.45 V I OL e 1.6 mA (Note 1) 1.0 V I OL e 3.5 mA (Notes 1, 4) VOL1 Output Low Voltage (5) 0.3 V I OL e 200 mA (Note 1) (Port 0, ALE, PSEN ) 0.45 V I OL e 3.2 mA (Note 1) 1.0 V I OL e 7.0 mA (Note 1, 4) VOH Output High Voltage V CCb0.3 V I OH eb 10 mA (Ports 1, 2, and 3) VCCb0.7 V I OH eb 30 mA VCCb1.5 V I OH eb 60 mA

A.C. CHARACTERISTICS (Over Specified Operating Conditions) EXTERNAL PROGRAM MEMORY CHARACTERISTICS

12 MHz 16 MHz Variable

Symbol Parameter Oscillator Oscillator Oscillator Unit Min Max Min Max Min Max 1/TCLCL Oscillator Frequency M80C51FB 3.5 12 MHzM80C51FB-16 3.5 16 TLHLL ALE Pulse Width 127 85 2TCLCL b40 ns TAVLL Address Valid to ALE Low 43 23 TCLCL b40 ns TLLAX Address Hold After ALE Low 53 33 TCLCL b30 ns TLLIV ALE Low to 234 150 4TCLCL b110 ns Valid Instruction In TLLPL ALE Low to PSEN Low 53 33 TCLCL b30 ns TPLPH PSEN Pulse Width 205 143 3TCLCL b45 ns TPLIV PSEN Low to 145 83 3TCLCL b115 ns Valid Instruction In TPXIX Input Instruction Hold 0 0 0 ns After PSEN TPXIZ Input Instruction Float 59 38 TCLCL b25 ns After PSEN TAVIV Address to 312 208 5TCLCL b115 ns Valid Instruction In TPLAZ PSEN Low to Address Float 10 10 20 ns TRLRH RD Pulse Width 400 275 6TCLCL b100 ns TWLWH WR Pulse Width 400 275 6TCLCL b100 ns TRLDV RD Low to Valid Data In 252 147.5 5TCLCL b175 ns TRHDX Data Hold After RD 00 0 n s TRHDZ Data Float After RD 107 65 2TCLCL b60 ns TLLDV ALE Low to Valid Data In 517 350 8TCLCL b160 ns TAVDV Address to Valid Data In 585 398 9TCLCL b175 ns TLLWL ALE Low to RD or WR Low 200 300 138 238 3TCLCL b50 3TCLCL a50 ns TAVWL Address Valid to WR Low 203 120 4TCLCL b130 ns TQVWX Data Valid before WR 33 13 TCLCL b50 ns TWHQX Data Hold after WR 33 13 TCLCL b50 ns TQVWH Data Valid to WR High 433 288 7TCLCL b150 ns TRLAZ RD Low to Address Float 0 0 0 ns TWHLH RD or WR High to ALE High 43 123 23 103 TCLCL b40 TCLCL a40 ns NOTE: 7. Case temperatures are ‘‘instant on’’.

EXTERNAL PROGRAM MEMORY READ CYCLE 271172–10 EXTERNAL DATA MEMORY READ CYCLE 271172–11 EXTERNAL DATA MEMORY WRITE CYCLE 271172–12

SERIAL PORT TIMING - SHIFT REGISTER MODE Test Conditions: (Over Specified Operating Conditions) Symbol Parameter Oscillator Oscillator Oscillator Units Min Max Min Max Min Max TXLXL Serial Port Clock Cycle Time 1 0.75 12TCLCL ms TQVXH Output Data Setup to Clock 700 492 10TCLCL b133 ns Rising Edge TXHQX Output Data Hold after 50 8 2TCLCL b117 ns Clock Rising Edge TXHDX Input Data Hold After Clock 0 0 0 ns Rising Edge TXHDV Clock Rising Edge to Input 700 492 10TCLCL b133 ns Data Valid SHIFT REGISTER MODE TIMING WAVEFORMS 271172–13

Symbol Parameter Min Max Units 1/TCLCL Oscillator Frequency M80C51FB 3.5 12 MHz M80C51FB-16 3.5 16 TCHCX High Time 20 ns TCLCX Low Time 20 ns TCLCH Rise Time 20 ns TCHCL Fall Time 20 ns EXTERNAL CLOCK DRIVE WAVEFORM 271172–14 A.C. TESTING INPUT Input, Output Waveforms 271172–15 AC Inputs during testing are driven at V CCb0.5V for a Logic ‘‘1’’ and 0.45V for a Logic ‘‘0’’. Timing measurements are made at V IH min for a Logic ‘‘1’’ and V IL max for a Logic ‘‘0’’. Float Waveforms 271172–16 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, and begins to float when a 100 mV change from the loaded V OH/VOL level occurs. IOL/IOH t g20 mA.