M80C186 INTEL | Alldatasheet
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November 1993 Order Number: 270500-008 M80C186 CHMOS HIGH INTEGRATION 16-BIT MICROPROCESSOR Military Y Operation Modes Include: Ð Enhanced Mode Which Has Ð DRAM Refresh Ð Power-Save Logic Ð Direct Interface to New CMOS Numerics Coprocessor Ð Compatible Mode Ð NMOS M80186 Pin-for-Pin Replacement for Non-Numerics
Applications
Ð Enhanced M80C86/C88 CPU Ð Clock Generator Ð 2 Independent DMA Channels Ð Programmable Interrupt Controller Ð 3 Programmable 16-Bit Timers Ð Dynamic RAM Refresh Control Unit Ð Programmable Memory and Peripheral Chip Select Logic Ð Programmable Wait State Generator Ð Local Bus Controller Ð Power Save Logic Ð System-Level Testing Support (High Impedance Test Mode) Y Available in 10 MHz and 12.5 MHz Versions Y Direct Addressing Capability to
1 Mbyte and 64 Kbyte I/O
Y Completely Object Code Compatible with All Existing M8086/M8088 Software and Also Has 10 Additional Instructions over M8086/M8088 Y Complete System Development Support Ð All M8086 and NMOS M80186 Software Development Tools Can Be Used for M80C186 System Development Ð Assembler, PL/M, Pascal, Fortran, and System Utilities Ð In-Circuit-Emulator (ICE TM-C186) Y Available in 68-Pin Ceramic Pin Grid Array (PGA) and 68-Lead Ceramic Quad Flat Pack (See Packaging Outlines and Dimensions, Order Ý231369) Y Available in Two Product Grades: Ð MIL-STD-883, b55§Ct o a125§C( T C) Ð Military Temperature Only (MTO), b55§Ct o a125§C( T C) The Intel M80C186 is a CHMOS high integration microprocessor. It has features which are new to the M80186 family which include a DRAM refresh control unit, power-save mode and a direct numerics interface. When used in ‘‘compatible’’ mode, the M80C186 is 100% pin-for-pin compatible with the NMOS M80186 (except for M8087 applications). The ‘‘enhanced’’ mode of operation allows the full feature set of the M80C186 to be used. The M80C186 is upward compatible with M8086 and M8088 software and fully compatible with M80186 and M80188 software. 270500–1 Figure 1. M80C186 Block Diagram
Figure 2. M80C186 Pinout Diagram
Table 1. M80C186 Pin Description VCC,V CC 9, 43 1, 35 I System Power: a5 volt power supply. VSS,V SS 26, 60 52, 18 I System Ground. forces the M80C186 into enhanced mode. generate the clock signal (CLKOUT). the Numeric Processor Extension. inactive level for one clock, and then float them. clocks until it goes LOW, at which time execution will resume. , interrupts will be serviced. accept a new command. BUSY is active HIGH.
Table 1. M80C186 Pin Description (Continued) active HIGH. Interrupt Requests are synchronized internally. (see Interrupt Controller section of this data sheet). S3, S4, and S5 are defined as LOW during T 2 –T4.
M80C186 to latch the address. ALE is active HIGH. information about processor/instruction queue interaction. should be connected to GND to provide Queue-Status data.
tied LOW to yield control to the SRDY pin. yield control to the ARDY pin. clock during RESET, and then floated. The status pins float during HOLD/HLDA. Reset, and then floated until a bus cycle begins.
weak internal pullup for normal operation. weak internal pullup for normal operation. MCS0–3 are software programmable.
–4 are software programmable. during a bus HOLD. A1 is active HIGH.
The following Functional Description describes the base architecture of the M80C186. This architecture is common to the M8086, M8088, M80186 and M80286 microprocessor families as well. The M80C186 is a very high integration 16-bit microproc- essor. It combines 15–20 of the most common mi- croprocessor system components onto one chip. The M80C186 is object code compatible with the M8086/M8088 microprocessors and adds 10 new instruction types to the existing M8086/M8088 in- struction set. The M80C186 has two major modes of operation, Compatible and Enhanced. In Compatible Mode the M80C186 is completely compatible with NMOS M80186, with the exception of M8087 support. All pin functions, timings, and drive capabilities are identical. The Enhanced mode adds three new fea- tures to the system design. These are Power-Save control, Dynamic RAM refresh, and an asynchro- nous Numerics Co-processor interface. M80C186 BASE ARCHITECTURE The M8086, M8088, M80186, and M80286 family all contain the same basic set of registers, instructions, and addressing modes. The M80C186 processor is upward compatible with the M8086, M8088, and M80286 CPUs. Register Set The M80C186 base architecture has fourteen regis- ters as shown in Figures 3a and 3b. These registers are grouped into the following categories. General Registers Eight 16-bit general purpose registers may be used to contain arithmetic and logical operands. Four of these (AX, BX, CX, and DX) can be used as 16-bit registers or split into pairs of separate 8-bit registers. Segment Registers Four 16-bit special purpose registers select, at any given time, the segments of memory that are imme- diately addressable for code, stack, and data. (For usage, refer to Memory Organization.) Base and Index Registers Four of the general purpose registers may also be used to determine offset addresses of operands in memory. These registers may contain base address- es or indexes to particular locations within a seg- ment. The addressing mode selects the specific reg- isters for operand and address calculations. Status and Control Registers Two 16-bit special purpose registers record or alter certain aspects of the M80C186 processor state. These are the Instruction Pointer Register, which contains the offset address of the next sequential instruction to be executed, and the Status Word Register, which contains status and control flag bits (see Figures 3a and 3b). Status Word Description The Status Word records specific characteristics of the result of logical and arithmetic instructions (bits 0, 2, 4, 6, 7, and 11) and controls the operation of the M80C186 within a given operating mode (bits 8, 9, and 10). The Status Word Register is 16-bits wide. The function of the Status Word bits is shown in Table 2.
Table 2. Status Word Bit Functions
0 CF Carry FlagÐSet on high-order
2 PF Parity FlagÐSet if low-order 8
4 AF Set on carry from or borrow to
6 ZF Zero FlagÐSet if result is zero;
7 SF Sign FlagÐSet equal to high-
8 TF Single Step FlagÐOnce set, a
9 IF Interrupt-enable FlagÐWhen
10 DF Direction FlagÐCauses string
11 OF Overflow FlagÐSet if the
cussed later in this data sheet. 5). This allows fo r a 1 MByte physical address size. extra segments may coincide for simple programs.
Figure 4. M80C186 Instruction Set
The M80C186 provides eight categories of address- ing modes to specify operands. Two addressing modes are provided for instructions that operate on register or immediate operands: # Register Operand Mode: The operand is located in one of the 8- or 16-bit general registers. # Immediate Operand Mode: The operand is in- cluded in the instruction. Six modes are provided to specify the location of an operand in a memory segment. A memory operand address consists of two 16-bit components: a seg- ment base and an offset. The segment base is sup- plied by a 16-bit segment register either implicitly chosen by the addressing mode or explicitly chosen by a segment override prefix. The offset, also called the effective address, is calculated by summing any combination of the following three address ele- ments: # the displacement (an 8- or 16-bit immediate value contained in the instruction); # the base (contents of either the BX or BP base registers); and # the index (contents of either the SI or DI index registers). Any carry out from the 16-bit addition is ignored. Eight-bit displacements are sign extended to 16-bit values. Combinations of these three address elements de- fine the six memory addressing modes, described below. # Direct Mode: The operand’s offset is contained in the instruction as an 8- or 16-bit displacement el- ement. # Register Indirect Mode: The operand’s offset is in one of the registers SI, DI, BX, or BP. # Based Mode: The operand’s offset is the sum of an 8- or 16-bit displacement and the contents of a base register (BX or BP). # Indexed Mode: The operand’s offset is the sum of an 8- or 16-bit displacement and the contents of an index register (SI or DI). # Based Indexed Mode: The operand’s offset is the sum of the contents of a base register and an Index register. # Based indexed Mode with Displacement: The op- erand’s offset is the sum of a base register’s con- tents, an index register’s contents, and an 8- or 16-bit displacement. Data Types The M80C186 directly supports the following data types: # Integer: A signed binary numeric value contained in an 8-bit byte or a 16-bit word. All operations assume a 2’s complement representation. Signed 32- and 64-bit integers are supported us- ing a Numeric Data Coprocessor with the M80C186. # Ordinal: An unsigned binary numeric value con- tained in an 8-bit byte or a 16-bit word. # Pointer: A 16- or 32-bit quantity, composed of a 16-bit offset component or a 16-bit segment base component in addition to a 16-bit offset compo- nent. # String: A contiguous sequence of bytes or words. A string may contain from 1 to 64K bytes. # ASCII: A byte representation of alphanumeric and control characters using the ASCII standard of character representation. # BCD: A byte (unpacked) representation of the decimal digits 0–9. # Packed BCD: A byte (packed) representation of two decimal digits (0–9). One digit is stored in each nibble (4-bits) of the byte. # Floating Point: A signed 32-, 64-, or 80-bit real number representation. (Floating point operands are supported using a Numeric Data Coprocessor with the M80C186.) In general, individual data elements must fit within defined segment limits. Figure 7 graphically repre- sents the data types supported by the M80C186. I/O Space The I/O space consists of 64K 8-bit or 32K 16-bit ports. Separate instructions address the I/O space with either an 8-bit port address, specified in the in- struction, or a 16-bit port address in the DX register. 8-bit port addresses are zero extended such that A 15 –A8 are LOW. I/O port addresses 00F8(H) through 00FF(H) are reserved. Interrupts An interrupt transfers execution to a new program location. The old program address (CS:IP) and ma- chine state (Status Word) are saved on the stack to allow resumption of the interrupted program. Inter- rupts fall into three classes: hardware initiated, INT instructions, and instruction exceptions. Hardware initiated interrupts occur in response to an external input and are classified as non-maskable or maska- ble.
Figure 7. M80C186 Supported Data Types own vectors through the internal interrupt controller. during an interrupt acknowledge bus sequence. priority can interrupt the service routine in progress.
Table 4. M80C186 Interrupt Vectors
- These are generated as the result of an instruction exe-
- This is handled as in the M8086.
- All three timers constitute one source of request to the
Each Timer interrupt has a separate vector type number.
- Default priorities for the interrupt sources are used only if
- An escape opcode will cause a trap if the M80C186 is in
(because it is a type 3 interrupt). cates the value of the index to be checked. address will point to the segment override prefix. of the main line program will be executed. A non-maskable interrupt (NMI) is also provided. interrupts from being serviced.
occur after the next instruction has been executed. registers to predefined values as shown in Table 5. Table 5. M80C186 Initial Register State ready inputs, and reset circuitry. LC or RC circuit is not recommended. tal configurations are shown in Figures 8b and 8c. external source as shown in Figure 8d or Figure 8e. middle of each T W until ARDY is sampled HIGH. One-half CLKOUT cycle of resolution time is used.
Figure 8. M80C186 Oscillator Configurations
antee proper operation of the circuit. cussed in the Chip Select/Ready Logic description. the integrated chip-select circuitry. tion of these signals is shown in Table 6. Table 6. Transceiver Control Signals Description to drive these lines directly.
dress to an odd address. This is a total of 16 clocks or more, if WAIT states are required. In addition, if locked transfers are performed, the HOLD latency time will be increased by the length of the locked transfer. Local Bus Controller and Reset Upon receipt of a RESET pulse from the RES input, the local bus controller will perform the following ac- tion: # Drive DEN ,R D , and WR HIGH for one clock cy- cle, then float. NOTE: RD is also provided with an internal pull-up device to prevent the processor from inadvertently enter- ing Queue Status mode during reset. # Drive S0 –S2 to the passive state (all HIGH) and then float. # Drive LOCK HIGH and then float. # Float AD0–15, A16–19, BHE , DT/R . # Drive ALE LOW (ALE is never floated). # Drive HLDA LOW. INTERNAL PERIPHERAL INTERFACE All the M80C186 integrated peripherals are con- trolled via 16-bit registers contained within an inter- nal 256-byte control block. This control block may be mapped into either memory or I/O space. Internal logic will recognize the address and respond to the bus cycle. During bus cycles to internal registers, the bus controller will signal the operation externally (i.e., the RD ,W R , status, address, data, etc., lines will be driven as in a normal bus cycle), but D 15–0 , SRDY, and ARDY will be ignored. The base address of the control block must be on an even 256-byte boundary (i.e., the lower 8 bits of the base address are all zeros). All of the defined registers within this control block may be read or written by the M80C186 CPU at any time. The location of any reg- ister contained within the 256-byte control block is determined by the current base address of the con- trol block. The control block base address is programmed via a 16-bit relocation register contained within the control block at offset FEH from the base address of the control block (see Figure 9). It provides the upper 12 bits of the base address of the control block. The control block is effectively an internal chip select range and must abide by all the rules concerning chip selects (the chip select circuitry is discussed later in this data sheet). Any access to the 256 bytes of the control block activates an internal chip select. Other chip selects may overlap the control block only if they are programmed to zero wait states and ignore external ready. In addition, bit 12 of this regis- ter determines whether the control block will be mapped into I/O or memory space. If this bit is 1, the control block will be located in memory space, whereas if the bit is 0, the control block will be locat- ed in I/O space. If the control register block is mapped into I/O space, the upper 4 bits of the base address must be programmed as 0 (since I/O ad- dresses are only 16 bits wide). In addition to providing relocation information for the control block, the relocation register contains bits which place the interrupt controller into slave mode, and cause the CPU to interrupt upon encountering ESC instructions. At RESET, the relocation register is set to 20FFH. This causes the control block to start at FF00H in I/O space. An offset map of the 256-byte control register block is shown in Figure 10. The integrated M80C186 peripherals operate semi- autonomously from the CPU. Access to them for the most part is via software read/write of the control block. Most of these registers can be both read and written. A few dedicated lines, such as interrupts and DMA request provide real-time communication be- tween the CPU and peripherals as in a more con- ventional system utilizing discrete peripheral blocks. The overall interaction and function of the peripheral blocks has not substantially changed. CHIP-SELECT/READY GENERATION LOGIC The M80C186 contains logic which provides programmable chip-select generation for both memories and peripherals. In addition, it can be pro- grammed to provide READY (or WAIT state) genera- tion. It can also povide latched address bits A1 and A2. The chip-select lines are active for all memory and I/O cycles in their programmed areas, whether they be generated by the CPU or by the integrated DMA unit. Memory Chip Selects The M80C186 provides 6 memory chip select out- puts for 3 address areas; upper memory, lower memory, and midrange memory. One each is provid- ed for upper memory and lower memory, while four are provided for midrange memory. The range for each chip select is user-programma- ble and can be set to 2K, 4K, 8K, 16K, 32K, 64K, 128K (plus 1K and 256K for upper and lower chip selects). In addition, the beginning or base address
Table 10. PCS Address Ranges Table 11. MS, EX Programming Values MS 1 e Peripherals mapped into memory space. 0 e Peripherals mapped into I/O space. EX 0 e 5 PCS lines. A1, A2 provided. 1 e 7 PCS lines. A1, A2 are not provided. PCS4–PCS6 as outlined below. pretation of the ready bits is shown in Table 12. Table 12. READY Bits Programming cessing internal peripherals. # All chip-select outputs will be driven HIGH. eration (i.e., UMCS resets to FFFBH).
cycle to fetch data and the other to store data.
- The Transfer Count Register (TC) specifies the
may be modified or altered during any DMA activity. ed immediately in DMA operation. Table 13. DMA Control Block Format Figure 16. DMA Unit Block Diagram
Figure 17. DMA Control Register B/W: Byte/Word (0/1) Transfers. ST/STOP: Start/stop (1/0) Channel. (2 bits) 01 Source synchronization. 10 Destination synchronization. or 2 (B /W) after each transfer. both set at same priority level.
when the transfer count register reaches zero. transfer rates shown in Table 14. Table 14. Maximum DMA Figure 18. DMA Memory Pointer Register Format
No explicit DMA acknowledge pulse is provided. suffer during sequences of continuous DMA cycles. must be programmed before this bit is set. tween updates to the channel registers. # Any transfer in progress is aborted. two, or as a DMA request source. Figure 19. Timer Block Diagram
determines which is used for the comparison. nal timers and the internal bus. The timers have several programmable options. the three integrated timers. Table 15. Timer Control Block Format Figure 20. Timer Mode/Control Register
ALT: The ALT bit determines which of two MAX COUNT registers is used for count comparison. If ALT e 0, register A for that timer is always used, while if ALT e 1, the comparison will alternate between register A and register B when each maximum count is reached. This alternation allows the user to change one MAX COUNT register while the other is being used, and thus provides a method of generating non-repetitive waveforms. Square waves and pulse outputs of any duty cycle are a subset of available signals obtained by not changing the final count reg- isters. The ALT bit also determines the function of the timer output pin. If ALT is zero, the output pin will go LOW for one clock, the clock after the maximum count is reached. If ALT is one, the output pin will reflect the current MAX COUNT register being used (0/1 for B/A). CONT: Setting the CONT bit causes the associated timer to run continuously, while resetting it causes the timer to halt upon maximum count. If COUNT e 0 and ALT e 1, the timer will count to the MAX COUNT register A value, reset, count to the register B value, reset, and halt. EXT: The external bit selects between internal and exter- nal clocking for the timer. The external signal may be asynchronous with respect to the M80C186 clock. If this bit is set, the timer will count LOW-to- HIGH transitions on the input pin. If cleared, it will count an internal clock while using the input pin for control. In this mode, the function of the external pin is defined by the RTG bit. The maximum input to output transition latency time may be as much as 6 clocks. However, clock inputs may be pipelined as closely together as every 4 clocks without losing clock pulses. The prescaler bit is ignored unless internal clocking has been selected (EXT e 0). If the P bit is a zero, the timer will count at one-fourth the internal CPU clock rate. If the P bit is a one, the output of timer 2 will be used as a clock for the timer. Note that the user must initialize and start timer 2 to obtain the prescaled clock. RTG: Retrigger bit is only active for internal clocking (EXT e 0). In this case it determines the control function provided by the input pin. If RTG e 0, the input level gates the internal clock on and off. If the input pin is HIGH, the timer will count; if the input pin is LOW, the timer will hold its value. As indicated previously, the input signal may be asynchronous with respect to the M80C186 clock. When RTG e 1, the input pin detects LOW-to-HIGH transitions. The first such transition starts the timer running, clearing the timer value to zero on the first clock, and then incrementing thereafter. Further transitions on the input pin will again reset the timer to zero, from which it will start counting up again. If CONT e 0, when the timer has reached maximum count, the EN bit will be cleared, inhibiting further timer activity. EN: The enable bit provides programmer control over the timer’s RUN/HALT status. When set, the timer is enabled to increment subject to the input pin con- straints in the internal clock mode (discussed previ- ously). When cleared, the timer will be inhibited from counting. All input pin transistions during the time EN is zero will be ignored. If CONT is zero, the EN bit is automatically cleared upon maximum count. INH The inhibit bit allows for selective updating of the enable (EN) bit. If INH is a one during the write to the mode/control word, then the state of the EN bit will be modified by the write. If INH is a zero during the write, the EN bit will be unaffected by the operation. This bit is not stored; it will always b ea0o na read. INT: When set, the INT bit enables interrupts from the timer, which will be generated on every terminal count. If the timer is configured in dual MAX COUNT register mode, an interrupt will be generated each time the value in MAX COUNT register A is reached, and each time the value in MAX COUNT register B is reached. If this enable bit is cleared after the inter- rupt request has been generated, but before a pend- ing interrupt is serviced, the interrupt request will still be in force. (The request is latched in the Interrupt Controller). MC: The Maximum Count bit is set whenever the timer reaches its final maximum count value. If the timer is configured in dual MAX COUNT register mode, this bit will be set each time the value in MAX COUNT register A is reached, and each time the value in MAX COUNT register B is reached. This bit is set
regardless of the timer’s interrupt-enable bit. The MC bit gives the user the ability to monitor timer status through software instead of through inter- rupts. Programmer intervention is required to clear this bit. RIU: The Register In Use bit indicates which MAX COUNT register is currently being used for compari- son to the timer count value. A zero value indicates register A. The RIU bit cannot be written, i.e., its value is not affected when the control register is writ- ten. It is always cleared when the ALT bit is zero. Not all mode bits are provided for timer 2. Certain bits are hardwired as indicated below: ALT e 0, EXT e 0, P e 0, RTG e 0, RIU e 0 Count Registers Each of the three timers has a 16-bit count register. The current contents of this register may be read or written by the processor at any time. If the register is written into while the timer is counting,the new value will take effect in the current count cycle. Max Count Registers Timers 0 and 1 have two MAX COUNT registers, while timer 2 has a single MAX COUNT register. These contain the number of events the timer will count. In timers 0 and 1, the MAX COUNT register used can alternate between the two max count val- ues whenever the current maximum count is reached. The condition which causes a timer to re- set is equivalent between the current count value and the max count being used. This means that if the count is changed to be above the max count value, or if the max count value is changed to be below the current value, the timer will not reset to zero, but rather will count to its maximum value, ‘‘wrap around’’ to zero, then count until the max count is reached. Timers and Reset Upon RESET, the Timers will perform the following actions: # All EN (Enable) bits are reset preventing timer counting. # All SEL (Select) bits are reset to zero. This se- lects MAX COUNT register A, resulting in the Timer Out pins going HIGH upon RESET. INTERRUPT CONTROLLER The M80C186 can receive interrupts from a number of sources, both internal and external. The internal interrupt controller serves to merge these requests on a priority basis, for individual service by the CPU. Internal interrupt sources (Timers and DMA chan- nels) can be disabled by their own control registers or by mask bits within the interrupt controller. The M80C186 interrupt controller has its own control register that set the mode of operation for the con- troller. The interrupt controller will resolve priority among requests that are pending simultaneously. Nesting is provided so interrupt service routines for lower priori- ty interrupts may themselves be interrupted by high- er priority interrupts. A block diagram of the interrupt controller is shown in Figure 21. The M80C186 has a special slave mode in which the internal interrupt controller acts as a slave to an ex- ternal master. The controller is programmed into this mode by setting bit 14 in the peripheral control block relocation register. (See Slave Mode section.) MASTER MODE OPERATION Interrupt Controller External Interface For external interrupt sources, five dedicated pins are provided. One of these pins is dedicated to NMI, non-maskable interrupt. This is typically used for power-fail interrupts, etc. The other four pins may function either as four interrupt input lines with inter- nally generated interrupt vectors, as an interrupt line and an interrupt acknowledge line (called the ‘‘cas- cade mode’’) along with two other input lines with internally generated interrupt vectors, or as two in- terrupt input lines and two dedicated interrupt ac- knowledge output lines. When the interrupt lines are configured in cascade mode, the M80C186 interrupt controller will not generate internal interrupt vectors. External sources in the cascade mode use external- ly generated interrupt vectors. When an interrupt is acknowledged, two INTA cycles are initiated and the vector is read into the M80C186 on the second cy- cle. The capability to interface to external M82C59A programmable interrupt controllers is thus provided when the inputs are configured in cascade mode.
troller in master mode are similar to the M82C59A. abled, higher-priority interrupts will be serviced. the corresponding vectors are generated internally. pairs. The interconnection is shown in Figure 23. the use of external master and slave M82C59As. mands must be issued by the programmer. Figure 21. Interrupt Controller Block Diagram
Figure 22. Fully Nested (Direct) Mode Interrupt lower-priority M80C186 interrupt sources. ting IS bits at the end of interrupt service routines. and the next interrupt service routine is entered. In-Service bit of the highest priority source to be set. the conventional Poll Word to allow this to be done. service routine in progress. mode (LTM) bit. All interrupt inputs are active HIGH.
Figure 33. Slave Mode Interrupt Controller Connections suitable to drive the INTA input of an M82C59A. with equal or higher priority. ing to the Interrupt Vector register at offset 20H. shows the offsets of these registers. when written by the M80C186 CPU.
Bits 2–14: Reserved, read back as zero. Bit 15: Enable Power Save Mode. Set to zero on RESET. Figure 44. Power-Save Control Register Table 16. MCS Assignments cessible by using the M80C186 I/O instructions. Table 17. Numerics Coprocessor I/O Port pled on the low-to-high transition of the RES pin. to guarantee proper normal operation.
ABSOLUTE MAXIMUM RATINGS * Case Temperature under Bias ÀÀÀ b55§Ct o a125§C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b65§Ct o a150§C Voltage on Any Pin with Respect to Ground ÀÀÀÀÀÀÀÀÀÀÀÀ b1.0V to a7.0V Package Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1W NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. OPERATING CONDITIONS MIL-STD-883 Symbol Description Min Max Units TC Case Temperature (Instant On) b55 a125 §C VCC Digital Supply Voltage 4.75 5.25 V MILITARY TEMPERATURE ONLY (MTO) Symbol Description Min Max Units TC Case Temperature (Instant On) b55 a125 §C VCC Digital Supply Voltage 4.75 5.25 V DC CHARACTERISTICS (Over Specified Operating Conditions) Symbol Parameter Min Max Units Comments VIL Input Low Voltage b0.5 0.2 V CC b 0.3 V VIH Input High Voltage 0.2 V CC a 1.1 V CC V (All except X1 and RES ) VIH1 Input High Voltage (RES ) 3.0 V CC V VIH2 Input High Voltage 0.2 V CC a 1.3 V CC V(ARDY/SRDY) VOL Output Low Voltage 0.45 V I OL e 2.5 mA (S0, 1, 2) IOL e 2.0 mA (others) VOH Output High Voltage 2.4 V CC VI OH eb 2.4 mA @ 2.4V(4) 0.8 V CC VCC VI OH eb 200 mA @ 0.8 V CC(4) ICC Power Supply Current 160 mA 12.5 MHz (3) 140 mA 10 MHz (3) IPS Power Save Current 10 mA per MHz a 20 mA Typical @25§C, V CC e 5.0V ILI Input Leakage Current g10 mA 0.45V s VIN s VCC ILO Output Leakage Current g10 mA 0.45V s VOUT s VCC(1) VCLO Clock Output Low 0.5 V I CLO e 4.0 mA VCHO Clock Output High 0.8 V CC VI CHO eb 500 mA NOTES: 1. Pins being floated during HOLD or by invoking the ONCE Mode. 2. Characterization conditions are a) Frequency e 1 MHz; b) Unmeasured pins at GND; V IN at a5.0V or a0.45V. 3. Current is measured with the device in RESET with X1 and X2 driven and all other non-power pins open. 4. RD /QSMD, UCS , MSC0 /PEREQ, MCSL /ERROR, and TEST /BUSY pins have internal pullup devices that are active at RESET. Excessive loading on these pins can cause the M80C186 to go into undesired modes of operation (e.g., Queue Status, ONCE) upon RESET.
DC CHARACTERISTICS (Over Specified Operating Conditions) (Continued) Symbol Parameter Min Max Units Comments VCLI Clock Input Low Voltage (X1) b0.5 0.6 V VCHI Clock Input High Voltage (X1) 3.9 V CC V CIN Input Capacitance 10 pF @ 1 MHz (2) CIO I/O Capacitance 20 pF @ 1 MHz (2) NOTES: 1. Pins being floated during HOLD or by invoking the ONCE Mode. 2. Characterization conditions are a) Frequency e 1 MHz; b) Unmeasured pins at GND; V IN at a5.0V or a0.45V. 3. Current is measured with the device in RESET with X1 and X2 driven and all other non-power pins open. 4. RD /QSMD, UCS , MSC0 /PEREQ, MCSL /ERROR, and TEST /BUSY pins have internal pullup devices that are active at RESET. Excessive loading on these pins can cause the M80C186 to go into undesired modes of operation (e.g., Queue Status, ONCE) upon RESET. PIN TIMINGS AC CHARACTERISTICS (Over Specified Operating Conditions) All timings are measured at 1.5V and 100 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C L e 50–200 pF (10 MHz) and C L e 50–100 pF (12.5 MHz). For AC tests, input V IL e 0.45V and V IN e 2.4V except at X 1 where V IH e VCC b 0.5V. Symbol Parameter M80C186-10 M80C186-12 Unit CommentsMin Max Min Max M80C186 TIMING REQUIREMENTS TDVCL Data In Setup (A/D) 20 20 ns TCLDX Data In Hold (A/D) 5 5 ns TARYCH ARDY Resolution 20 20 ns Transition Setup Time (1) TARYLCL Asynchronous Ready 30 30 ns (ARDY) Setup Time TCLARX ARDY Active Hold Time 15 15 ns TARYCHL ARDY Inactive Hold Time 15 15 ns TSRYCL Synchronous Ready (SRDY) 20 20 ns Transition Setup Time TCLSRY SRDY Transition Hold Time 20 20 ns THVCL HOLD Setup (1) 20 20 ns TINVCH INTR, NMI, TEST, TMR IN 20 20 ns Setup Time (1) TINVCL DRQ0, DRQ1, Setup Time (1) 20 20 ns M80C186 MASTER INTERFACE TIMING RESPONSES TCLAV Address Valid Delay 5 50 5 37 ns CL eTCLAX Address Hold 0 0 ns 50 pF–200 pFTCLAZ Address Float Delay T CLAX 30 T CLAX 25 ns all outputs (except T CLTMV)TCHCZ Command Lines Float Delay 40 33 ns @ 10 MHzTCHCV Command Lines Valid 45 37 ns Delay (after Float) CL e TLHLL ALE Width (min) T CLCL b 30 T CLCL b 30 ns 50 pF–100 pF all outputsTCHLH ALE Active Delay 30 25 ns @ 12.5 MHz TCHLL ALE Inactive Delay 30 25 ns
PIN TIMINGS (Continued) AC CHARACTERISTICS (Over Specified Operating Conditions) (Continued) All timings are measured at 1.5V and 100 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C L e 50–200 pF (10 MHz) and C L e 50–100 pF (12.5 MHz). For AC tests, input V IL e 0.45V and V IN e 2.4V except at X 1 where V IH e VCC b 0.5V. Symbol Parameter M80C186-10 M80C186-12 Unit Comments Min Max Min Max M80C186 MASTER INTERFACE TIMING RESPONSES (Continued) TLLAX Address Hold to T CHCL b 20 T CHCL 15 ns 50 pF–100 pF @ 10 MHz all outputs C L e (except T CLTMV) 50 pF–200 pF b @ 12.5 MHz CL e all outputs ALE Inactive (min) TCLDV Data Valid Delay 5 40 5 36 ns TCLDOX Data Hold Time 3 3 ns TWHDX Data Hold after WR (min) T CLCL b 34 T CLCL b 20 ns TCVCTV Control Active Delay 1 3 56 3 47 ns TCHCTV Control Active Delay 2 5 44 5 37 ns TCVCTX Control Inactive Delay 4 44 5 37 ns TCVDEX DEN Inactive Delay 5 56 5 47 ns (Non-Write Cycle) TAZRL Address Float to 0 0 ns RD Active TCLRL RD Active Delay 5 44 5 37 ns TCLRH RD Inactive Delay 5 44 5 37 ns tRHLH RD Inactive to ALE High T CLCH b 14 T CLCH b 14 ns TRHAV RD Inactive to T CLCL b 40 T CLCL b 20 ns Address Active (min) TCLHAV HLDA Valid Delay 5 40 4 33 ns TRLRH RD Pulse Width (min) 2T CLCL b 46 2T CLCL b 40 ns TRVCH RD Valid to 25 25 ns Clock High TWLWH WR Pulse Width (min) 2T CLCL b 34 2T CLCL b 30 ns tWHLH WR Inactive to AEE High T CLCH b 14 T CLCH b 14 ns TWHDEX WR Inactive to T CLCH b 10 T CLCH b 10 ns DEN Inactive TCSVLL Chip Select Valid T CLCH b 14 T CLCH b 14 ns to ALE Low TAVLL Address Valid to T CLCH b 19 T CLCH b 15 ns ALE Low (min) TCHSV Status Active Delay 5 45 5 35 ns TCLSH Status Inactive Delay 5 50 5 35 ns TCLTMV Timer Output Delay 48 40 ns 100 pF max @ 10 MHz
AC CHARACTERISTICS (Over Specified Operating Conditions) (Continued) All timings are measured at 1.5V and 100 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C L e 50–200 pF (10 MHz) and C L e 50–100 pF (12.5 MHz). For AC tests, input V IL e 0.45V and V IN e 2.4V except at X 1 where V IH e VCC b 0.5V. Symbol Parameter M80C186-10 M80C186-12 Unit Comments Min Max Min Max M80C186 MASTER INTERFACE TIMING RESPONSES (Continued) TCLRO Reset Delay 48 40 ns C L e 50–200 pF TCHQSV Queue Status Delay 28 28 ns All outputs TCHDX Status Hold Time 5 5 ns (except T CLTMV) TAVCH Address Valid to 0 0 C L e 50–100 pF @ 10 MHz Clock High All Outputs TCLLV LOCK Valid/Invalid 5 45 5 40 ns @ 12.5 MHz Delay TDXDL DEN Inactive to 0 0 ns DT/R Low M80C186 CHIP-SELECT TIMING RESPONSES TCLCSV Chip-Select 45 33 ns Active Delay TCXCSX Chip-Select Hold from T CLCH b 10 T CLCH b 10 ns Command Inactive TCHCSX Chip-Select 5 40 5 36 ns Inactive Delay M80C186 CLKIN REQUIREMENTS Measurements taken with following conditions: External clock input to X1 and X2 not connected (float) TCKIN CLKIN Period 50 1000 40 1000 ns TCKHL CLKIN Fall Time 5 5 ns 3.5 to 1.0V (1) TCKLH CLKIN Rise Time 5 5 ns 1.0 to 3.5V (1) TCLCK CLKIN Low Time 23 18 ns 1.5V (2) TCHCK CLKIN High Time 23 18 ns 1.5V (2) M80C186 CLKOUT TIMING 200 pF load maximum for 10 MHz or less TCICO CLKIN to 25 21 ns CLKOUT Skew TCLCL CLKOUT Period 100 2000 80 2000 ns TCLCH CLKOUT 0.5 T CLCLb8 0.5 T CLCLb7 ns 1.5V Low Time (min) TCHCL CLKOUT 0.5 T CLCLb8 0.5 T CLCLb7 ns 1.5V High Time (min) TCH1CH2 CLKOUT Rise Time 10 10 ns 1.0 to 3.5V TCL2CL1 CLKOUT Fall Time 10 10 ns 3.5 to 1.0V NOTE: 1. These values are supplied for design purposes. 2. T CLCK and T CHCK (CLKIN Low and High times) should not have a duration less than 45% of T CKIN.
270500–16
WAVEFORMS (Continued) MAJOR CYCLE TIMING (Continued) 270500–17 NOTES: 1. The data hold time last only until INTA goes inactive, even if the INTA transition occurs prior to T CLDX (min). 2. INTA occurs one clock later in slave mode. 3. Status inactive just prior to T 4. Latched A1 and A2 have the same timings as PCS5 and PCS6 . 5. For Write cycle followed by Read.
WAVEFORMS (Continued) 270500–18 270500–32
WAVEFORMS (Continued) READY TIMING 270500–23 HOLD-HLDA TIMING 270500–20
WAVEFORMS (Continued) TIMER ON M80C186 270500–21
Figure 45. Capacitive Derating Curve cution unit cycles necessary to execute instructions. # No wait states or bus HOLDs occur. shake between the BIU and execution unit. the instruction timings shown.
Function Format Clock CommentsCycles DATA TRANSFER MOV e Move: Register to Register/Memory 1000100w m o dr e g r / m 2/12 Register/memory to register 1000101w m o dr e g r / m 2 / 9 Immediate to register/memory 1100011w m o d0 0 0 r / m data data if w e1 12–13 8/16-bit Immediate to register 1011w r e g data data if w e1 3–4 8/16-bit Memory to accumulator 1010000w addr-low addr-high 8 Accumulator to memory 1010001w addr-low addr-high 9 Register/memory to segment register 10001110 m o d0r e g r / m 2 / 9 Segment register to register/memory 10001100 m o d0r e g r / m 2/11 PUSH e Push: Memory 11111111 m o d110 r / m 1 6 Register 01010 r e g 1 0 Segment register 000r e g110 9 Immediate 011010s0 data data if s e01 0 PUSHA e Push All 01100000 3 6 POP e Pop: Memory 10001111 m o d000 r / m 2 0 Register 01011 r e g 1 0 Segment register 000r e g111 (regi01) 8 POPA e P o pA l l 01100001 5 1 XCHG e Exchange: Register/memory with register 1000011w m o dr e g r / m 4/17 Register with accumulator 10010 r e g 3 IN e Input from: Fixed port 1110010w port 10 Variable port 1110110w 8 OUT e Output to: Fixed port 1110011w port 9 Variable port 1110111w 7 XLAT e Translate byte to AL 11010111 1 1 LEA e Load EA to register 10001101 m o dr e g r / m 6 LDS e Load pointer to DS 11000101 m o dr e g r / m (modi11) 18 LES e Load pointer to ES 11000100 m o dr e g r / m (modi11) 18 LAHF e Load AH with flags 10011111 2 SAHF e Store AH into flags 10011110 3 PUSHF e Push flags 10011100 9 POPF e Pop flags 10011101 8 Shaded areas indicate instructions not available in M8086, M8088 microsystems.
INSTRUCTION SET SUMMARY (Continued) Function Format Clock CommentsCycles DATA TRANSFER (Continued) SEGMENT e Segment Override: CS 00101110 2 SS 00110110 2 DS 00111110 2 ES 00100110 2 ARITHMETIC ADD e Add: Reg/memory with register to either 000000dw m o dr e g r / m 3/10 Immediate to register/memory 100000sw m o d000 r / m data data if s w e01 4/16 Immediate to accumulator 0000010w data data if w e1 3/4 8/16-bit ADC e Add with carry: Reg/memory with register to either 000100dw m o dr e g r / m 3/10 Immediate to register/memory 100000sw m o d010 r / m data data if s w e01 4/16 Immediate to accumulator 0001010w data data if w e1 3/4 8/16-bit INC e Increment: Register/memory 1111111w m o d000 r / m 3/15 Register 01000 r e g 3 SUB e Subtract: Reg/memory and register to either 001010dw m o dr e g r / m 3/10 Immediate from register/memory 100000sw m o d101 r / m data data if s w e01 4/16 Immediate from accumulator 0010110w data data if w e1 3/4 8/16-bit SBB e Subtract with borrow: Reg/memory and register to either 000110dw m o dr e g r / m 3/10 Immediate from register/memory 100000sw m o d011 r / m data data if s w e01 4/16 Immediate from accumulator 0001110w data data if w e1 3/4 8/16-bit DEC e Decrement Register/memory 1111111w m o d001 r / m 3/15 Register 01001 r e g 3 CMP e Compare: Register/memory with register 0011101w m o dr e g r / m 3/10 Register with register/memory 0011100w m o dr e g r / m 3/10 Immediate with register/memory 100000sw m o d111 r / m data data if s w e01 3/10 Immediate with accumulator 0011110w data data if w e1 3/4 8/16-bit NEG e Change sign register/memory 1111011w m o d011 r / m 3/10 AAA e ASCII adjust for add 00110111 8 DAA e Decimal adjust for add 00100111 4 AAS e ASCII adjust for subtract 00111111 7 DAS e Decimal adjust for subtract 00101111 4 MUL e Multiply (unsigned): 1111011w m o d1 0 0 r / m Register-Byte 26–28 Register-Word 35–37 Memory-Byte 32–34 Memory-Word 41–43 Shaded areas indicate instructions not available in M8086, M8088 microsystems.
INSTRUCTION SET SUMMARY (Continued) Function Format Clock CommentsCycles ARITHMETIC (Continued) IMUL e Integer multiply (signed): 1111011w m o d101 r / m Register-Byte 25–28 Register-Word 34–37 Memory-Byte 31–34 Memory-Word 40–43 IMUL e Integer Immediate multiply 011010s1 m o dr e g r / m data data if s e0 22–25/ (signed) 29–32 DIV e Divide (unsigned): 1111011w m o d110 r / m Register-Byte 29 Register-Word 38 Memory-Byte 35 Memory-Word 44 IDIV e Integer divide (signed): 1111011w m o d111 r / m Register-Byte 44–52 Register-Word 53–61 Memory-Byte 50–58 Memory-Word 59–67 AAM e ASCII adjust for multiply 11010100 00001010 1 9 AAD e ASCII adjust for divide 11010101 00001010 1 5 CBW e Convert byte to word 10011000 2 CWD e Convert word to double word 10011001 4 LOGIC Shift/Rotate Instructions: Register/Memory by 1 1101000w m o dT T Tr / m 2/15 Register/Memory by CL 1101001w m o dT T Tr / m 5 an/17an Register/Memory by Count 1100000w m o dT T Tr / m count 5 an/17an TTT Instruction
000 R O L
001 R O R
010 R C L
011 R C R
101 S H R
111 S A R
AND e And: Reg/memory and register to either 001000dw m o dr e g r / m 3/10 Immediate to register/memory 1000000w m o d100 r / m data data if w e1 4/16 Immediate to accumulator 0010010w data data if w e1 3/4 8/16-bit TESTeAnd function to flags, no result: Register/memory and register 1000010w m o dr e g r / m 3/10 Immediate data and register/memory 1111011w m o d000 r / m data data if w e1 4/10 Immediate data and accumulator 1010100w data data if w e1 3/4 8/16-bit OReOr: Reg/memory and register to either 000010dw m o dr e g r / m 3/10 Immediate to register/memory 1000000w m o d001 r / m data data if w e1 4/16 Immediate to accumulator 0000110w data data if w e1 3/4 8/16-bit Shaded areas indicate instructions not available in M8086, M8088 microsystems.
INSTRUCTION SET SUMMARY (Continued) Function Format Clock CommentsCycles LOGIC (Continued) XOR e Exclusive or: Reg/memory and register to either 001100dw m o dr e g r / m 3/10 Immediate to register/memory 1000000w m o d110 r / m data data if w e1 4/16 Immediate to accumulator 0011010w data data if w e1 3/4 8/16-bit NOT e Invert register/memory 1111011w m o d010 r / m 3/10 STRING MANIPULATION MOVS e Move byte/word 1010010w 1 4 CMPS e Compare byte/word 1010011w 2 2 SCAS e Scan byte/word 1010111w 1 5 LODS e Load byte/wd to ALAX 1010110w 1 2 STOS e Stor byte/wd from ALA 1010101w 1 0 INS e Input byte/wd from DX port 0110110w 1 4 OUTS e Output byte/wd to DX port 0110111w 1 4 Repeated by count in CX MOVS e Move string 11110010 1010010w 8 a8n CMPS e Compare string 1111001z 1010011w 5 a22n SCAS e Scan string 1111001z 1010111w 5 a15n LODS e Load string 11110010 1010110w 6 a11n STOS e Store string 11110010 1010101w 6 a9n INS e Input string 11110010 0110110w 8 a8n OUTS e Output string 11110010 0110111w 8 a8n CONTROL TRANSFER CALL e Call: Direct within segment 11101000 disp-low disp-high 15 Register/memory 11111111 m o d010 r / m 13/19 indirect within segment Direct intersegment 10011010 segment offset 23 segment selector Indirect intersegment 11111111 m o d011 r / m (mod i 11) 38 JMP e Unconditional jump: Short/long 11101011 disp-low 14 Direct within segment 11101001 disp-low disp-high 14 Register/memory 11111111 m o d100 r / m 11/17 indirect within segment Direct intersegment 11101010 segment offset 14 segment selector Indirect intersegment 11111111 m o d101 r / m (mod i 11) 26 Shaded areas indicate instructions not available in M8086, M8088 microsystems.
INSTRUCTION SET SUMMARY (Continued) Function Format Clock CommentsCycles CONTROL TRANSFER (Continued) RET e Return from CALL: Within segment 11000011 1 6 Within seg adding immed to SP 11000010 data-low data-high 18 Intersegment 11001011 2 2 Intersegment adding immediate to SP 11001010 data-low data-high 25 JE/JZ e Jump on equal/zero 01110100 disp 4/13 JMP not JL/JNGE e Jump on less/not greater or equal 01111100 disp 4/13 taken/JMP JLE/JNG e Jump on less or equal/not greater 01111110 disp 4/13 taken JB/JNAE e Jump on below/not above or equal 01110010 disp 4/13 JBE/JNA e Jump on below or equal/not above 01110110 disp 4/13 JP/JPE e Jump on parity/parity even 01111010 disp 4/13 JO e Jump on overflow 01110 000 disp 4/13 JS e Jump on sign 01111000 disp 4/13 JNE/JNZ e Jump on not equal/not zero 01110101 disp 4/13 JNL/JGE e Jump on not less/greater or equal 01111101 disp 4/13 JNLE/JG e Jump on not less or equal/greater 01111111 disp 4/13 JNB/JAE e Jump on not below/above or equal 01110011 disp 4/13 JNBE/JA e Jump on not below or equal/above 01110111 disp 4/13 JNP/JPO e Jump on not par/par odd 01111011 disp 4/13 JNO e Jump on not overflow 01110001 disp 4/13 JNS e Jump on not sign 01111001 disp 4/13 JCXZ e Jump on CX zero 11100011 disp 5/15 LOOP e Loop CX times 11100010 disp 6/16 LOOP not LOOPZ/LOOPE e Loop while zero/equal 11100001 disp 6/16 taken/LOOP LOOPNZ/LOOPNE e Loop while not zero/equal 11100000 disp 6/16 taken ENTER e Enter Procedure 11001000 data-low data-high L L e 0 15 L e 1 25 L l 1 22a16(nb1) LEAVE e Leave Procedure 11001001 8 INT e Interrupt: Type specified 11001101 type 47 Type 3 11001100 4 5 i f INT. taken/ INTO e Interrupt on overflow 11001110 48/4 if INT. not taken IRET e Interrupt return 11001111 2 8 BOUND e Detect value out of range 01100010 m o dr e g r / m 3 3 – 3 5 Shaded areas indicate instructions not available in M8086, M8088 microsystems.
INSTRUCTION SET SUMMARY (Continued) Function Format Clock CommentsCycles PROCESSOR CONTROL CLC e Clear carry 11111000 2 CMC e Complement carry 11110101 2 STC e Set carry 11111001 2 CLD e Clear direction 11111100 2 STD e Set direction 11111101 2 CLI e Clear interrupt 11111010 2 STI e Set interrupt 11111011 2 HLT e Halt 11110100 2 WAIT e Wait 10011011 6 i f test e 0 LOCK e Bus lock prefix 11110000 2 ESC e Processor Extension Escape 11011TTT m o dL L L r / m 6 (TTT LLL are opcode to processor extension) Shaded areas indicate instructions not available in M8086, M8088 microsystems. FOOTNOTES The Effective Address (EA) of the memory operand is computed according to the mod and r/m fields: if mod e 11 then r/m is treated as a REG field if mod e 00 then DISP e 0*, disp-low and disp- high are absent if mod e 01 then DISP e disp-low sign-ex- tended to 16-bits, disp-high is absent if mod e 10 then DISP e disp-high: disp-low if r/m e 000 then EA e (BX) a (SI) a DISP if r/m e 001 then EA e (BX) a (DI) a DISP if r/m e 010 then EA e (BP) a (SI) a DISP if r/m e 011 then EA e (BP) a (DI) a DISP if r/m e 100 then EA e (SI) a DISP if r/m e 101 then EA e (DI) a DISP if r/m e 110 then EA e (BP) a DISP* if r/m e 111 then EA e (BX) a DISP DISP follows 2nd byte of instruction (before data if required) *except if mod e 00 and r/m e 110 then EA e disp-high: disp-low. EA calculation time is 4 clock cycles for all modes, and is included in the execution times given whenev- er appropriate. Segment Override Prefix 0 0 1 reg 1 1 0 reg is assigned according to the following: Segment reg Register 00 ES 01 CS 10 SS 11 DS REG is assigned according to the following table: 16-Bit (w e 1) 8-Bit (w e 0)
000 AX 000 AL
001 CX 001 CL
010 DX 010 DL
011 BX 011 BL
100 SP 100 AH
101 BP 101 CH
110 SI 110 DH
111 DI 111 BH
The physical addresses of all operands addressed by the BP register are computed using the SS seg- ment register. The physical addresses of the desti- nation operands of the string primitive operations (those addressed by the DI register) are computed using the ES segment, which may not be overridden.