M8085AH INTEL | Alldatasheet
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(RAM/IO), M2764A (EPROM), and M8282 (Octal Latch)] while maintaining total system expandability. provided for the M8080A, thereby offering a high level of system integration. Figure 1. M8085AH CPU Functional Block Diagram
Table 1. Pin Description V/O address, 3-stated during Hold and Halt modes and during RESET. ‘ADp-7 vO MULTIPLEXED ADDRESS/DATA BUS: Lower 8 bits of the memory address (or 1/0. then becomes the data bus during the second and third clock cycles. of ALE may be used to latch the state of these lines. and Halt modes and during RESET. stated during Hold and Halt modes and during RESET. number of clock cycles for READY to go high before completing the read or write cycle. READY must conform to specified setup and hald times. soon as the completion of the curront bus transfer. intemal processing can continue. acknowledged, the Address, Data RD, WR, and |O/M lines are 3-stated. aquest is removed. The cpu takes the bus one half clock cycle after HLDA goes low. during the next to the last clock cycle of an instruction and during Hold and Halt states. M8259A interrupt chip or some other interrupt port. AST 6.5 ‘except they cause an internal RESTART to be automatically inserted. out using the SIM instruction.
Table 1. Pin Description (Continued) X1,Xe X4 and Xg: Are connected to a crystal LC or RC network to drive the internal clock generator. to give the processor's internal operating frequency. & RIM instruction is executed. SERIAL OUTPUT DATA LINE: The output SOD is eet or reset as specified by the SIM. Table 2. Interrupt Priority, Restart Address and Sensitivi
- The processor pushes the PC on the stack before branching to the indicated address.
- The address branched to depends on the instruction provided to the cpu when the interrupt is acknowledged.
Figure 3. Power-On Reset Circult how to generate wait states; and driving the X; and X2 (clock) inputs. Basic system timing and interface techniques are also described.
ABSOLUTE MAXIMUM RATINGS* cations are subject to change without notice. Case Temperature Under Bias(1). — 55°C to + 125°C ‘WARNING: Stressing the device bayond the “Absolute D.C. CHARACTERISTICS Tell) = —§5°C to + 125°C, Veg = 5V +10%, Vgg = OV; unless otherwise specified [_symbor | Parameter | min | Max | Units | TestConaitions | [vu | tnputtowvottage | 05 | tos | ov [| [vn | routtign vonage | 22 | ve+os| v |_| | vo. | Ouputtowvortage | Tos TV i = 2ma | tcc | Powersupply Curent || z00 Toma | Pius | rputtaatage:exoeptPnt | | #0 | wa | OSvwevec | [ne | tnputteakagePint | | 270 | #A_| 0=VwVoo | [vn [ctoputtoweveiReseT [os] vos |v |_| [vu | roitbigh Lovet RESET [94 | Vo+os |v |_| Lvwv | Hysteresissneser |] ozs [| vy fT A.C. CHARACTERISTICS Tc(1) = —55°C to + 125°C, Vog = 5V +10%, Vgg = OV pom fe | | min | Max | | tore | CikClockPeoa | 20 | 2000 [ns [iu | GLK Low Time (Standard GLK Loading) | so || | t | CiKHigh Tima Standard CLK Loading) | 120 | ns | wu | GikAiseandrautime | Ts | tun | Xi RisingtocK Rising | to t20 | . Le | xr risingtocucrating zo 50s [Tine | Ao-15Vali to Leading E650 ofConrox) | 70 | | ne [wor | Aor Vatoto Leasing Ea5eofconwoi = aw || ns [to | AontsVaidiovaldDenin «Sid Ca] [sn [Adress Float ner LeaangEoge of EADONTA) |__| 0 | me | tu | Ag-r5 Valid Botore Tralingedgo tare) | 0 | ns [wu | Ao-rVaiaBetoretraling Edge orale | 70 | ns NOTE: 1, Case temperatures are “instant on." 17-4
A.C. CHARACTERISTICS (Continued) ee [min | max _| ame | RENO Vad tom naioovaid om [ica | Address (Aas) Vaid ter Control | tao || ns | [ice [watt Conot ow 0 WF, TA Eape TATE | a0 || | [ tc. | Traling Edge of ControlioLeadingEdge ot ate | 60 | ns iow | BataVatao Tang Ege WATE aoe | F ease | HDA weisemie | a tase _| _Bus Float After HLDA [ [20 [ ns | taack __| _HLDA Valid to Trailing Edge of CLK [ 10 | | ns | | tuos __| _HOLD Setup Time to Tralling Edge of CLK [17% | | ns | | ts | _INTR,AST, and TRAP Setup Time toFalingEdgeotcix | 160 | | __ns | re Trailing Edge of ALE to Leading Edge of Control | i309 | | ns | Face ALE Low Bungcuxtign 00 | | [une [ALE vais Oa Ourarasa |__| #0 | ns _| Puan [A te VahsDwe Ouinguite tf ae] Pa Aewan we || [uny | ALEtoREADYStabie Tt ns me] Tel Ege ot ER oe Crating ot aaaans [wo |__| mw | [tao | READ(oriNTA)tovaidData || 00 |r ee Faxon] bata Hoi Tine ater ERDINTA 0] Fw READY WodTine |] [ tas | READY SetupTimetoLeadngtdgeotcik | to | ns [ino [alae Ator Tang Ege or WATE] roo | | rw | [vor [LEADING ape WRITE Daavate | |e | NOTES: _ " 1. Ag—Ais address Specs apply 1O/M, So, and S; except Ag—Ars are undefined during T4-Tg of OF cycle whereas IO/M, So, and S are stable. 2. Test Conditions: tev. = 320 ns (MBOB5AH); CL = 150 pF. 3. For all output timing where C, + 150 pF use the following correction factors: 25 pF < C, < 150 pF: —0.10 ns/pF 450 pF < C, < 900 pF; + 0.90 ns/pF 4. Output timings are measured with purely capacitive load. 5. To calculate timing specifications at other values of tcyc use Table 5. 17-5
Table 5. Bus Timing Specification as Tcyc Dependent N is equal to the total WAIT states. T = tcyc.
a WAVEFORMS (Continued) READ sen eo CO SRR CL a —— 4 Ay ao, S| aoness > QT MMS |S ae — AD/INTA cel “ y a 271018-7 WRITE \\ 5 ] " ! 4 ' y ~ al (i {- a ; fo tee | ‘ (aie Yea “FL -_ ied 271019-8 HOLD ety _—— ox [Cocomcomon | _ 271019-9 17-7
WAVEFORMS (Continued) READ OPERATION WITH WAIT CYCLE (TYPICAL) — SAME READY TIMING APPLIES TO WRITE ee: ae Ce C7 | Le onm |S PoP | PT sor es me 271019-10 NOTE: 1. Ready must romain stable during setup and hold times. INTERRUPT AND HOLD fv fe fa fe [se fa fue fa fa CT) wove Me ; ‘wos, ‘HOM LOA [| ‘ware ‘waar “HOA I'S ALSO FLOATING DURING THIS TIME 271019-11 17-8