M80287 INTEL | Alldatasheet
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Table 1. M80287 Pin Description CLK outputs are compatible to this input. LOW 20 CLK cycles before RESET goes LOW. asynchronous to the M80287 clock. indicates that an unmasked error condition exists. actual data transfer, whichever occurs first, if no more transfers are required. NPRD I NUMERIC PROCESSOR READ: Enables transfer of data from the M80287. This input may be asynchronous to the M80287 clock. NPWR I NUMERIC PROCESSOR WRITE: Enables transfer of data to the M80287. This input may be asynchronous to the M80287 clock. HIGH. These inputs may be asynchronous to the M80287 clock. controls the local bus. It must be connected to the M80286 HLDA output. connected to the M80286 READY input. VSS I GROUND: System ground, both pins must be connected to ground.
completely software compatible with M8086, 88/20. Figure 3. M80286/20 Architecture
ABSOLUTE MAXIMUM RATINGS * Storage Temperature under Bias b65§Ct o a150§C Case Temperature ÀÀÀÀÀÀÀÀÀÀÀÀÀ b55§Ct o a125§C Voltage on any Pin with Respect to Ground ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b1.0 to a7V Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ3.0 Watt NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. Operating Conditions Symbol Description Min Max Units TC Case Temperature (Instant On) b55 a125 §C VCC Digital Supply Voltage 4.75 5.25 V D.C. CHARACTERISTICS (Over Specified Operating Conditions) Symbol Parameter Min Max Unit Test Conditions VIL Input LOW Voltage b0.5 0.8 V VIH Input HIGH Voltage 2.0 V CC a 0.5 V VILC Clock Input LOW Voltage CKM e 1: 2.0 V CC a 1V CKM e 0: 3.8 V CC a 1V VOL Output LOW Voltage 0.45 V I OL e 3.0 mA VOH Output HIGH Voltage 2.4 V I OH eb 400 mA ILI Input Leakage Current g10 mA0 V s VIN s VCC ILO Output Leakage Current g10 mA 0.45V s VOUT s VCC ICC Power Supply Current 600 mA T C eb 55§C CIN Input Capacitance 10 pF F C e 1 MHz CO Input/Output Capacitance 20 pF F C e 1 MHz (D0–D15) CCLK CLK Capacitance 12 pF F C e 1 MHz
A.C. CHARACTERISTICS (Over Specified Operating Conditions) TIMING REQUIREMENTS Symbol Parameter
6 MHz 8 MHz 10 MHz
-6 Min -6 Max -8 Min -8 Max -10 Min -10 Max TCLCL CLK Period CKM e 1 165 500 125 500 100 500 ns CKM e 0 62.5 166 50 166 40 166 ns TCLCH CLK LOW Time CKM e 1 100 343 68 343 53 343 ns At 0.8V CKM e 0 15 146 15 146 11 146 ns At 0.6V TCHCL CLK HIGH Time CKM e 1 50 230 43 230 28 230 ns At 2.0V CKM e 0 20 151 20 151 18 151 ns At 3.6V TCH1CH2 CLK Rise Time 10 10 10 ns 1.0V to 3.6V if CKM e 1 TCL2CL1 CLK Fall Time 10 10 10 ns 3.6V to 1.0V if CKM e 1 TDVWH Data Setup to NPWR Inactive 75 75 75 ns TWHDX Data Hold from NPWR Inactive 30 18 18 ns TWLWH NPWR NPRD Active Time 95 90 90 ns At 0.8V TRLRH TAVRL Command Valid to NPWR or 0 0 0 ns TAVWL NPRD Active TMHRL Minimum Delay from PEREQ 130 130 100 ns Active to NPRD Active TKLKH PEAK Active Time 85 85 60 ns At 0.8V TKHKL PEAK Inactive Time 250 250 200 ns At 2.0V TKHCH PEAK Inactive to NPWR ,5 0 4 0 4 0 n s NPRD Inactive TCHKL NPWR NPRD Inactive to b30 b30 b30 ns PEAK Inactive TWHAX Command Hold from NPWR 30 30 22 ns TRHAX NPRD Inactive TKLCL PEAK Active Setup to NPWR 50 40 40 ns NPRD Active TIVCL NPWR, NPRD , RESET 70 70 53 ns to CLK Setup Time TCLIH NPWR, NPRD, RESET 45 45 37 ns from CLK Hold Time TRSCL RESET to CLK Setup Time 20 20 20 ns TCLRS RESET from CLK Hold Time 20 20 20 ns NOTE: Tja e 41§C/W Tjc e 14§C/W
A.C. CHARACTERISTICS (Over Specified Operating Conditions) TIMING RESPONSES Symbol Parameter -6 Min -6 Max -8 Min -8 Max -10 Min -10 Max TRHQZ NPRD Inactive to Data Float 37.5 35 25 ns (Note 2) TRLQV NPRD Active to Data Valid 60 60 60 ns (Note 3) TILBH ERROR Active to BUSY 100 100 100 ns (Note 4) Inactive TWLBV NPWR Active to BUSY Active 100 100 100 ns (Note 5) TKLML PEACK Active to PEREQ 127 127 127 ns (Note 6) Inactive TCMDI Command Inactive Time Write-to-Write 95 95 75 ns At 2.0V Read-to-Read 95 95 75 ns At 2.0V Write-to-Read 95 95 75 ns At 2.0V Read-to-Write 95 95 75 ns At 2.0V TRHCH Data Hold from NPRD 3 3 3 ns (Note 7) Inactive NOTES: 2. Float condition occurs when output current is less than I LO on D0–D15. 3. D0–D15 loading: CL e 100 pF. 4. BUSY loading: CL e 100 pF. 5. BUSY loading: CL e 100 pF. 6. On last data transfer of numeric instruction. 7. D0–D15 loading: CL e 100 pF.
DATA TRANSFER TIMING (Initiated by M80286) 271029–16 DATA CHANNEL TIMING (Initiated by M80287) 271029–17
WAVEFORMS (Continued) ERROR OUTPUT TIMING 271029–18 CLK, RESET TIMING (CKM e 1) 271029–19 NOTE: Reset, NPWR , NPRD are inputs asynchronous to CLK. Timing requirements for RESET, NPWR , and NPRD are given for testing purposes only, to assure recognition at a specific CLK edge.
WAVEFORMS (Continued) CLK, NPRD , NPWR TIMING (CKM e 1) 271029–20 CLK, RESET TIMING (CKM e 0) 271029–21 NOTE: Reset must meet timing shown to guarantee known phase of internal d3 circuit. CLK, NPRD , NPWR TIMING (CKM e 0) 271029–22 NOTE: Reset, NPWR , NPRD are inputs asynchronous to CLK. Timing requirements for RESET, NPWR , and NPRD are given for testing purposes only, to assure recognition at a specific CLK edge.
WAVEFORMS (Continued) 271029–23 AC Drive and Measurement PointsÐCLK Input 271029–24 AC Setup, Hold and Delay Time MeasurementÐGeneral 271029–25 AC Test Loading on Outputs
Figure 4. The data channel control signals (PEREQ, M80286 memory management and protection unit. the same manner as for an M8087. transfer when it is connected to the M80386 CPU. operand have been transferred. are used by the M80286 for this communication. be connected to latched M80286 A2. form any I/O operations to these ports.
Figure 4. M80286/20 System Configuration operating on explicitly designated registers.
Table 2. M80287 Datatype Representation in Memory
- S e Sign bit (0 e positive, 1 e negative)
- d n e Decimal digit (two per byte)
- X e Bits have no significance; M8087 ignores when loading, zeros when storing.
- U e Position of implicit binary point
- I e Integer bit of significand; stored in temporary real, implicit in short and long real.
- Exponent Bias (normalized values):
CPU are available for use by the NPX.
Table 3. Execution Time for Selected M80287 Instructions rupts and their functions are shown in Table 4. error notification, respectively. M80286 use the same timing as any other bus cycle. requirements shown in the AC requirements section.
Table 4. Interrupt Vectors
7 An ESC instruction was encountered when EM or TS of the M80286 MSW was
that the current NPX context may not belong to the current task.
9 The second or subsequent words of a numeric operand in memory exceeded a
saved return address will not point at the numeric instruction causing this interrupt. must execute FNINIT before any other ESC or WAIT instruction. M80287 refer to a previous, correctly executed, instruction. may be restarted after clearing the error condition in the NPX. scendental, constant and data transfer instructions. responding to the NPX’s temporary real data type. toward lower-addressed registers. in Figure 6 reflects the overall state of the M80287. marized in Tables 5a and 5b.
Bits 14–12 of the status word point to the M80287 register that is the current top-of-stack (TOP) as de- scribed above. Figure 6 shows the six error flags in bits 5–0 of the status word. Bits 5–0 are set to indi- cate that the NEU has detected an exception while executing an instruction. The section on exception handling explains how they are set and used. Bit 7 is the error status bit. This bit is set if any un- masked exception bit is set and cleared otherwise. If this bit is set, the ERROR signal is asserted. Tag Word The tag word marks the content of each register as shown in Figure 7. The principal function of the tag word is to optimize the NPX’s performance. The tag word can be used, however, to interpret the con- tents of M80287 registers. Instruction and Data Pointers The instruction and data pointers (see Figures 8a and 8b) are provided for user-written error handlers. Whenever the M80287 executes a new instruction, the BIU saves the instruction address, the operand address (if present) and the instruction opcode. M80287 instructions can store this data into memo- ry. The instruction and data pointers appear in one of two formats depending on the operating mode of the M80287. In real mode, these values are the 20-bit physical address and 11-bit opcode formatted like the M8087. In protected mode, these values are the 32-bit virtual addresses used by the program which executed an ESC instruction. The same FLDENV/ FSTENV/FSAVE/FRSTOR instructions as those of the M8087 are used to transfer these values be- tween the M80287 registers and memory. Table 5a. Condition Code Interpretation Instruction C3 C2 C1 C0 InterpretationType Compare, Test 0 0 X 0 ST l Source or 0 (FTST) 00X1 S T k Source or 0 (FTST) 10X0 S T e Source or 0 (FTST) 1 1 X 1 ST is not comparable Remainder Q 1 0Q 0 Q2 Complete reduction with three low bits of quotient (See Table 5b) U 1 U U Incomplete Reduction Examine 0 0 0 0 Valid, positive unnormalized 0 0 0 1 Invalid, positive, exponent e 0 0 0 1 0 Valid, negative, unnormalized 0 0 1 1 Invalid, negative, exponent e 0 0 1 0 0 Valid, positive, normalized 0 1 0 1 Infinity, positive 0 1 1 0 Valid, negative, normalized 0 1 1 1 Infinity, negative 1 0 0 0 Zero, positive 1 0 0 1 Empty 1 0 1 0 Zero, negative 1 0 1 1 Empty 1 1 0 0 Invalid, positive, exponent e 0 1 1 0 1 Empty 1 1 1 0 Invalid, negative, exponent e 0 1 1 1 1 Empty NOTES: 1. ST e Top of stack 2. X e value is not affected by instruction 3. U e value is undefined following instruction 4. Q n e Quotient bit n
field refers to logical top of stack. Figure 7. M80287 Tag Word
- Previous value of indicated bit, not affected by FPREM
point at any prefixes which preceded the instruction. ed at the ESCAPE instruction opcode. ing of fields in the control word. of the six exceptions that the M80287 recognizes. ed as unsigned, may be specified). tions that can occur during instruction execution. ready existing NANs as the calculation result. encoding for infinity if this exception is masked. process is called gradual underflow.
271029–13 Figure 8a. Protected Mode Instruction and Data Pointer Image in Memory Denormalized Operand: At least one of the oper- ands is denormalized; it has the smallest exponent but a non-zero significand. Normal processing con- tinues if this exception is masked off. Inexact Result: If the true result is not exactly repre- sentable in the specified format, the result is round- ed according to the rounding mode, and this flag is set. If this exception is masked, processing will sim- ply continue. If the error is not masked, the corresponding error bit and the error status bit (ES) in the control word will be set, and the ERROR output signal will be as- serted. If the CPU attempts to execute another ESC or WAIT instruction, exception 7 will occur. The error condition must be resolved via an interrupt service routine. The M80287 saves the address of the floating point instruction causing the error as well as the address of the lowest memory location of any memory operand required by that instruction. M8086/20 COMPATIBILITY M80286/20 supports portability of M8086/20 pro- grams when it is in the real address mode. However, because of differences in the numeric error handling techniques, error handling routines may need to be changed. The differences between an M80286/20 and M8086/20 are: 1. The NPX error signal does not pass through an interrupt controller (M8087 INT signal does). Therefore, any interrupt controller oriented instruc- tions for the M8086/20 may have to be deleted. 2. Interrupt vector 16 must point at the numeric error handler routine. 3. The saved floating point instruction address in the M80287 includes any leading prefixes before the ESCAPE opcode. The corresponding saved address of the M8087 does not include leading prefixes. 4. In protected mode, the format of the saved in- struction and operand pointers is different than for the M8087. The instruction opcode is not savedÐit must be read from memory if needed. 5. Interrupt 7 will occur when executing ESC instruc- tions with either TS or EM of MSW e 1. If TS of MSW e 1 then WAIT will also cause interrupt 7. An interrupt handler should be added to handle this situ- ation. 6. Interrupt 9 will occur if the second or subsequent words of a floating point operand fall outside a seg- ment’s size. Interrupt 13 will occur if the starting ad- dress of a numeric operand falls outside a seg- ment’s size. An interrupt handler should be added to report these programming errors. In the protected mode, M8086/20 application code can be directly ported via recompilation if the 286 memory protection rules are not violated.
Table 6. M80287 Extensions to the M80286 Instruction Set
Table 6. M80287 Extensions to the M80286 Instruction Set (Continued)
- If P e 1 then add 5 clocks.
- if mod e 00 then DISP e 0*, disp-low and disp-high are absent
- if r/m e 000 then EA e (BX) a (SI) a DISP
*except if mod e 000 and r/m e 110 then EA e disp-high; disp-low.
- ESCAPE bit pattern is 11011.