M80186

M8288 INTEL | Alldatasheet

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Table 1. Pin Descriptio transition. ALE |s intended for use with D D type latches. storm data bus. This signal is active HIGH. LOW indicates Receive (Read). is in the I/O bus mode (108 tied HIGH). HIGH, these same outputs are enabled. mode. (See sections on I/O Bus and System Bus modes). earlier in the machine cycle to give I/O devices an early indication of a write instruction. Its timing is the same as a read command signal, AIOWC is active LOW. the data bus. This signal is actwe LOW. data present on the data bus. This signal is active LOW. onto the data bus. This signal is active LOW. data bus, This signal is active LOW. MCE/POER This is a dual function pin. ‘onto the data bus. The MCE signal is active HIGH. for the |/O bus that DEN performs for the system bus. PDEN is active LOW.

FUNCTIONAL DESCRIPTION Bye mode the OB pin'ts stepped LOW. inthis mode no command is issued until 115 ns after the Command and Control Logic AEN Line is activated (LOW). This mode assumes bus arbitration logic will inform the bus controller (on The command logic decodes the three M8086, the AEN line) when the bus is free for use. Both M8088, M8089 or M80186 CPU status lines (So, S;, memory and 1/O commands wait for bus arbitration. 2) to determine what command is to be issued. This mode is used when only one bus exists. Here, both I/O and memory are shared by more than one This chart shows the meaning of each status processor. $e £1 S| Posen State _[m8268Commend] — COMMAND OUTPUTS werrupt Acknowledge [INTA | [oo 1 [reivorot [iors | [Pe asanced wit commands ae made evlable Port to initiate write procedures early in the machine cy- [o 1 0|Wrte/OPot _|YOWC,AIOWC | —_ cle. This signal can be used to prevent the proces- [os + [rat [None ——|-—_—80¢ fom entering an unnecessary wat stato. [10 0 [Codeaccess | MADT |The command outputs are: [10 1 [ReadMemory | MROC |S. - Memory Read Command [1+ 0 [Write Memory [MWC AMWC | — MWTC - Memory Write Command [11 Trassve [none ‘TOHE.” = 70 Read Command TOWS_ - 1/0 Write Command ‘The command is issued in one of two ways depen. AMWC. - Advanced Memory Write Command KIOWC - Advanced I/O Write Command dent on the mode of the M8288 Bus Controller. INTA - Interrupt Ac VO Bus Mode — The M8288 is in the /O Bus Tg mode if the IOB pin is strapped HIGH. In the I/O Bus ‘A (interrupt Acknowledge) acts as an I/O read mod hs during an interrupt cycle. Its purpose is to inform an Jo all |/0 command lines (TOR, IOWC, ATOWC, {uring an neerux cycle. is purpose fo ta INTA) are always enabled (.e., not dependent on aoaq\\ and thet should pee upt ing information AEN). When an 1/O command is initiated by the So? the data bus, vector processor, the M8288 immediately activates the command lines using PDEN and DT/F to control the \\/O bus transceiver. The 1/0 command lines should CONTROL OUTPUTS not be used to control the system bus in this config- uration because no arbitration is present. This mode The control outputs of the M6288 are Data Enable allows one M8268 Bus Controller to handle two ex- (DEN), Data Transmit/Receive (DT/R) and Master ternal busses. No waiting is involved when the CPU Cascade __Enable/Peripheral Data Enable wants to gain access to the I/O bus. Normal memo- (MCE/PDEN). The DEN signal determines when the Ty access requires a “Bus Ready” signal (AEN external bus should be enabled onto the local bus LOW) before it will proceed. It is advantageous to _and the DT/ determines the direction of data trans- use the OB mode if /O or peripherals dedicated to fer. These two signals usually go to the chip select ‘one processor exist in a multi-processor system. and direction pins of a transceiver. 18-120

The MCE/PDEN pin changes function with the two _f the system contains only one PIC, the MCE signal modes of the M8288. When the M8288 is in the IOB_—_is not used. In this case the second Interrupt Ac- mode (OB HIGH) the PDEN signal serves as adedi- _ knowledge signal gates the interrupt vector onto the cated data enable signal for the 1/O or Peripheral —_ processor bus. ‘System bus. ADDRESS LATCH ENABLE AND HALT INTERRUPT ACKNOWLEDGE AND MCE . Address Latch Enable (ALE) occurs during each ma- The MCE signal is used during an interrupt acknowl-__ chine cycle and serves to strobe the current address edge cycle if the M8288 is in the System Bus mode _ into the address latches. ALE also serves to strobe (1OB LOW). During any interrupt sequence there are —_the status (So, 51, Sz) into a latch for halt state de- two interrupt acknowledge cycles that occur back to coding. back. During the first interrupt cycle no data or ad- dress transfers take place. Logic should be provided to mask off MCE during this cycle. Just before the © COMMAND ENABLE second cycle begins the MCE signal gates a master The Command Enable (CEN) input acts as a com- Priority Interrupt Controller's (PIC) cascade address mand qualifier for the 9 (cen) tine CEN pin is high conto the processor's local bus where ALE (Address the Maza functions normally. If the CEN pin is Laich Enable) strobes it into the address latches.On —uited LOW, all command lines are held in their inac- the leading edge of the second interrupt cycle the tive state (not 3-state). This feature can be used to addressed slave PIC gates an interrupt vector onto Fs ition 4 ei implement memory partitioning and to eliminate ad- the system data bus where it is read by the proces- ress conflicts between system bus devices and Sor. resident bus devices. ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi- : ast!) —55 . cations are subject to change without notice. Case Temperaturé Under Bias("). ~55°C 10 + 125°C yapwina: Sessing tho devi he 7 “Operating Conditions” is not recommended and ex- D.C. CHARACTERISTICS Voc = 5V + 10%, Tol!) = —55°C to + 125°C [_Symbor_[ Parameter [| min | Max | unit | Test Conditions InpurclampVotage | | 1 |v | e=-sm | | toc | Powersupply Curent [| 230 | maf | ie | Forward inputGurrent_ | | 07 | ma | Ve=045v | ta | Reseneinputcurent | | so | nA | Va = Sisov Vor Output Low Voltage Command Outputs v lo. = 20mA Control Outputs v lo. = 16mA Von Output High Voltage Command Outputs v lon = —5mA 18 Control Outputs v lon = —1 mA Inputtow Voltage | | oe | ov PT InputHigh Voltage | 20 | |v PT [torr | outpurorcurent | | 100 fA | Vorr = o4vt0 525v NOTE: 1. Case temperatures are “instant on.” 18-121

A.C. CHARACTERISTICS Voc = 5V + 10%, Tol!) = —55°C to + 125°C TIMING REQUIREMENTS [_symbot_[_Parameter_—[ Win Wax [Unt Test Conatons | [crocs | eiKGyctororod [as [me [ouch |“ cixtowtine [es fe [rowic. [eux igh time [a0 [ne [sven | stats Acwwoseup tine | 05 [| ne | [Trevis | status Actworioa time [10 ff me | “tsHou—[Statusinactve Seuptime [95 [| ms [Trois] siatusinaciverioi timo [10 [fre NOTE: 1. Case temperatures are “instant on.” TIMING RESPONSES [symbol | Parameter [Win] Max [Unit] Test Gonatons | [Tov | GonworActve Delays [48 fs | [Tovx | Gontotinactve Delay | 10. 80 | ns | [TOLL TOLNGH | ALE MCE Active Delay rom Gu [| 25 | ns | [TSVLH-TSVMGH | ALE MCE Actve Delay (rom Sats) | | 28 | ns | MDE [Tow » | AcEinactveDeley | a | 15 _| ns | ORC [Tout | Command acive bay | 10.[ 95 ns | Re | ot = 0m, [ToLMa | CommardinactveDeley | 10.{ 35 [os | wna | C= a00pr [ToHOTL [ Drestion Cont Acive Dey |__| s0_| ns | AMWE [ToHOTH | Brecion ontrlneeive Delay | | 30 | ns | NOWE [TAELGH | CommandEnable Time |_| «0 | 1s | [rasicz | Gonnaraateting [JL | oy {= a [Tact [enable Detained 16 200 [ns] °°" 1B cor [Tacvv[AENtopen | 20 | | [ToELRH | CEN to Command |_| Tout [ns | [TotoH | ouputfisotine || 20 [rs | Fromoavezov | [rono. [oupuFaitime |_| 12 [rs [Fromaovwosv | A.C, TESTING INPUT, OUTPUT WAVEFORM INPUT/OUTPUT ow 271026-5 18-122

TEST LOAD CIRCUITS—3-STATE COMMAND OUTPUT TEST LOAD T 300 oF T wor conrnot ourrut WAVEFORMS DEN, PDEN QUALIFICATION TIMING Lid v ADDRESS ENABLE (AEN) TIMING (3-STATE ENABLE/DISABLE) L von ms —_=t. oem TEER NOTE: CEN must be low or valid prior to T2 to prevent the command from being generated. 18-123

WAVEFORMS (Continued) om Y V vomomoee TT XX fee oT J if ool | Meat en wns mms PER cwnites remot ova mean i wee { lye venom Al zrv02e-10 NOTES: 1. Address/data bus is shown only for reference purposes. 2. Leading edge of ALE and MCE is determined by the falling edge of CLK or status going active, whichever occurs last. 3. All timing measurements are made at 1.5V unless specified otherwise. 18-124