M28F010

M28F010 INTEL | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 22

Technical content

system during final test; and 5) in-system after-sale. impractical or too time consuming. Figure 1. M28F010 Block Diagram

Figure 2. M28F010 Pin Configurations Table 1. Pin Description latched during a write cycle. are disabled. Data is internally latched during a write cycle. memory device and reduces power consumption to standby levels. during a read cycle. OE is active low. WE INPUT WRITE ENABLE: Controls writes to the control register and the array. Note: With V PP s VCC a 2V, memory contents cannot be altered. register, erasing the entire array, or programming bytes in the array.

Figure 3. M28F010 in a M80C186 System put data for erase and program verification. mand, making the M28F010 a read-only memory. Memory contents cannot be altered.

Table 2. M28F010 Bus Operations

1. V PPL may be ground, a no-connect with a resistor tied to ground, or as defined in the Characteristics Section. V PPH is the

read but not written or erased.

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. All other

PP e VPPH may access array data or the intelligent Identifier codes.

1. With V PP at high voltage, the standby current equals I CC a IPP (standby).
2. Refer to Table 3 for valid Data-In during a write operation.
3. V ID is the intelligent Identifier high voltage. Refer to DC Characteristics.

formed in conjunction with the command register. the processor-memory interface. receiving the appropriate verify or reset command. mode, the memory contents cannot be altered. of the processor-memory interface.

When V PP is high (V PPH), the read operation can be used to access array data, to output the intelligent Identifier codes, and to access data for program/ erase verification. When V PP is low (V PPL), the read operation can only access the array data. Output Disable With Output-Enable at a logic-high level (V IH), output from the device is disabled. Output pins are placed in a high-impedance state. Standby With Chip-Enable at a logic-high level, the standby operation disables most of the M28F010’s circuitry and substantially reduces device power consump- tion. The outputs are placed in a high-impedance state, independent of the Output-Enable signal. If the M28F010 is deselected during erasure, pro- gramming, or program/erase verification, the device draws active current until the operation is terminated. intelligent Identifier Operation The intelligent Identifier operation outputs the manu- facturer code (89H) and device code (B4H). Pro- gramming equipment automatically matches the de- vice with its proper erase and programming algo- rithms. With Chip-Enable and Output-Enable at a logic low level, raising A9 to high voltage V ID activates the operation. Data read from locations 0000H and 0001H represent the manufacturer’s code and the device code, respectively. The manufacturer- and device-codes can also be read via the command register, for instances where the M28F010 is erased and reprogrammed in the target system. Following a write of 90H to the com- mand register, a read from address location 0000H outputs the manufacturer code (89H). A read from address 0001H outputs the device code (B4H). Write Device erasure and programming are accomplished via the command register, when high voltage is ap- plied to the V PP pin. The contents of the register serve as input to the internal state-machine. The state-machine outputs dictate the function of the device. The command register itself does not occupy an ad- dressable memory location. The register is a latch used to store the command, along with address and data information needed to execute the command. The command register is written by bringing Write- Enable to a logic-low level (V IL), while Chip-Enable is low. Addresses are latched on the falling edge of Write-Enable, while data is latched on the rising edge of the Write-Enable pulse. Standard microproc- essor write timings are used. The three high-order register bits (R7, R6, R5) en- code the control functions. All other register bits, R4 to R0, must be zero. The only exception is the reset command, when FFH is written to the register. Reg- ister bits R7–R0 correspond to data inputs D7–D0. Refer to AC Write Characteristics and the Erase/ Programming Waveforms for specific timing parameters.

abling read-only operations. Table 3. Command Definitions

1. Bus operations are defined in Table 2.

e Identifier address: 00H for manufacturer code, 01H for device code. EA e Address of memory location to be read during erase verify. PA e Address of memory location to be programmed. Addresses are latched on the falling edge of the Write-Enable pulse.

1. ID e Data read from location IA during device identification (Mfr e 89H, Device e B4H).

EVD e Data read from location EA during erase verify. PD e Data to be programmed at location PA. Data is latched on the rising edge of Write-Enable. PVD e Data read from location PA during program verify. PA is latched on the Program command.

1. Following the Read int eligent ID command, two read operations access manufacturer and device codes.
2. Figure 5 illustrates the Quick-Erase Algorithm.
3. Figure 4 illustrates the Quick-Pulse Programming Algorithm.
4. The second bus cycle must be followed by the desired command register write.

While V PP is high, for erasure and programming, memory contents can be accessed via the read command. The read operation is initiated by writing 00H into the command register. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the command register con- tents are altered. The default contents of the register upon V PP pow- er-up is 00H. This default value ensures that no spu- rious alteration of memory contents occurs during the V PP power transition. Where the V PP supply is hard-wired to the M28F010, the device powers-up and remains enabled for reads until the command- register contents are changed. Refer to the AC Read Characteristics and Waveforms for specific timing parameters. Intelligent Identifier Command Flash-memories are intended for use in applications where the local CPU alters memory contents. As such, manufacturer- and device-codes must be ac- cessible while the device resides in the target sys- tem. PROM programmers typically access signature codes by raising A9 to a high voltage. However, mul- tiplexing high voltage onto address lines is not a de- sired system-design practice. The M28F010 contains an intelligent Identifier oper- ation to supplement traditional PROM-programming methodology. The operation is initiated by writing 90H into the command register. Following the com- mand write, a read cycle from address 0000H re- trieves the manufacturer code of 89H. A read cycle from address 0001H returns the device code of B4H. To terminate the operation, it is necessary to write another valid command into the register. Set-up Erase/Erase Commands Set-up Erase is a command-only operation that stages the device for electrical erasure of all bytes in the array. The set-up erase operation is performed by writing 20H to the command register. To commence chip-erasure, the erase command (20H) must again be written to the register. The erase operation begins with the rising edge of the Write-Enable pulse and terminates with the rising edge of the next Write-Enable pulse (i.e., Erase-Veri- fy Command). This two-step sequence of set-up followed by execu- tion ensures that memory contents are not acciden- tally erased. Also, chip-erasure can only occur when high voltage is applied to the V PP pin. In the absence of this high voltage, memory contents are protected against erasure. Refer to AC Erase Characteristics and Waveforms for specific timing parameters. Erase-Verify Command The erase command erases all bytes of the array in parallel. After each erase operation, all bytes must be verified. The erase verify operation is initiated by writing A0H into the command register. The address for the byte to be verified must be supplied as it is latched on the falling edge of the Write-Enable pulse. The register write terminates the erase opera- tion with the rising edge of its Write-Enable pulse. The M28F010 applies an internally-generated mar- gin voltage to the addressed byte. Reading FFH from the addressed byte indicates that all bits in the byte are erased. The erase-verify command must be written to the command register prior to each byte verification to latch its address. The process continues for each byte in the array until a byte does not return FFH data, or the last address is accessed. In the case where the data read is not FFH, another erase operation is performed. (Refer to Set-up Erase/Erase). Verification then resumes from the address of the last-verified byte. Once all bytes in the array have been verified, the erase step is com- plete. The device can be programmed. At this point, the verify operation is terminated by writing a valid command (e.g. Program Set-up) to the command register. Figure 5, the Quick-Erase algorithm, illus- trates how commands and bus operations are com- bined to perform electrical erasure of the M28F010. Refer to AC Erase Characteristics and Waveforms for specific timing parameters. Set-up Program/Program Commands Set-up program is a command-only operation that stages the device for byte programming. Writing 40H into the command register performs the set-up operation. Once the program set-up operation is performed, the next Write-Enable pulse causes a transition to an active programming operation. Addresses are in- ternally latched on the falling edge of the Write-En- able pulse. Data is internally latched on the rising edge of the Write-Enable pulse. The rising edge of Write-Enable also begins the programming opera- tion. The programming operation terminates with the next rising edge of Write-Enable, used to write the program-verify command. Refer to AC Program-

ming Characteristics and Waveforms for specific timing parameters. Program-Verify Command The M28F010 is programmed on a byte-by-byte ba- sis. Byte programming may occur sequentially or at random. Following each programming operation, the byte just programmed must be verified. The program-verify operation is initiated by writing C0H into the command register. The register write terminates the programming operation with the ris- ing edge of its Write-Enable pulse. The program-ver- ify operation stages the device for verification of the byte last programmed. No new address information is latched. The M28F010 applies an internally-generated mar- gin voltage to the byte. A microprocessor read cycle outputs the data. A successful comparison between the programmed byte and true data means that the byte is successfully programmed. Programming then proceeds to the next desired byte location. Figure 4, the M28F010 Quick-Pulse Programming algorithm, illustrates how commands are combined with bus operations to perform byte programming. Refer to AC Programming Characteristics and Waveforms for specific timing parameters. Reset Command A reset command is provided as a means to safely abort the erase- or program-command sequences. Following either set-up command (erase or program) with two consecutive writes of FFH will safely abort the operation. Memory contents will not be altered. A valid command must then be written to place the device in the desired state. EXTENDED ERASE/PROGRAM CYCLING EEPROM cycling failures have always concerned users. The high electrical field required by thin oxide EEPROMs for tunneling can literally tear apart the oxide at defect regions. To combat this, some sup- pliers have implemented redundancy schemes, re- ducing cycling failures to insignificant levels. Howev- er, redundancy requires that cell size be doubledÐ an expensive solution. Intel has designed extended cycling capability into its ETOX-II flash memory technology. Resulting im- provements in cycling reliability come without in- creasing memory cell size or complexity. First, an advanced tunnel oxide increases the charge carry- ing ability ten-fold. Second, the oxide area per cell subjected to the tunneling electric field is one-tenth that of common EEPROMs, minimizing the probabili- ty of oxide defects in the region. Finally, the peak electric field during erasure is approximately 2 MV/ cm lower than EEPROM. The lower electric field greatly reduces oxide stress and the probability of failureÐincreasing time to wearout by a factor of 100,000,000. The device is programmed and erased using Intel’s Quick-Pulse Programming and Quick-Erase algo- rithms. Intel’s algorithmic approach uses a series of operations (pulses), along with byte verification, to completely and reliably erase and program the de- vice. QUICK-PULSE PROGRAMMING ALGORITHM The Quick-Pulse Programming algorithm uses pro- gramming operations of 10 ms duration. Each opera- tion is followed by a byte verification to determine when the addressed byte has been successfully pro- grammed. The algorithm allows for up to 25 pro- gramming operations per byte, although most bytes verify on the first or second operation. The entire sequence of programming and byte verification is performed with V PP at high voltage. Figure 4 illus- trates the Quick-Pulse Programming algorithm. QUICK-ERASE ALGORITHM Intel’s Quick-Erase algorithm yields fast and reliable electrical erasure of memory contents. The algo- rithm employs a closed-loop flow, similar to the Quick-Pulse Programming algorithm, to simulta- neously remove charge from all bits in the array. Erasure begins with a read of memory contents. The M28F010 is erased when shipped from the factory. Reading FFH data from the device would immedi- ately be followed by device programming. For devices being erased and reprogrammed, uni- form and reliable erasure is ensured by first pro- gramming all bits in the device to their charged state (Data e 00H). This is accomplished, using the Quick-Pulse Programming algorithm, in approxi- mately two seconds. Erase execution then continues with an initial erase operation. Erase verification (data e FFH) begins at address 0000H and continues through the array to the last address, or until data other than FFH is en- countered. With each erase operation, an increasing number of bytes verify to the erased state. Erase efficiency may be improved by storing the address of the last byte verified in a register. Following the next erase operation, verification starts at that stored ad- dress location. Erasure typically occurs in one sec- ond. Figure 5 illustrates the Quick-Erase algorithm.

1. See DC Characteristics for value of V
2. Program Verify is only performed after byte program-

al) after the register is written with the Read command.

1. CAUTION: The algorithm MUST BE FOLLOWED

Figure 4. M28F010 Quick-Pulse Programming Algorithm

1. See DC Characteristics for value of V PPH. The V PP
2. Erase Verify is performed only after chip-erasure. A

the register is written with the read command.

1. CAUTION: The algorithm MUST BE FOLLOWED

Figure 5. M28F010 Quick-Erase Algorithm

determine the rnagnitudes of these peaks. selection will suppress transient voltage peaks. charge to the smaller capacitors as needed. crease V PP voltage spikes and overshoots. CC voltages above V LKO when V PP is active. Table 4. M28F010 Typlcal Update Power Dissipation

1. Formula to calculate typical Program/Program Verify Power e [VPP c Ý Bytes c typical Ý Prog Pulses (t WHWH1 c
2. Formula to calculate typical Erase/Erase Verify Power e [VPP (VPP3 typical c tERASE typical a IPP5 typical c tWHGL c

Ý Bytes)] a [VCC (ICC3 typical c tERASE typical a ICC5 typical c tWHGL c Ý Bytes)].

1. One Complete Cycle e Array Preprogram a Array Erase a Program.
2. ‘‘Typicals’’ are not guaranteed, but based on a limited number of samples from production lots.

ABSOLUTE MAXIMUM RATINGS * Case Temperature Under BiasÀÀÀ b55§Ct o a125§C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b65§Ct o a150§C Voltage on Any Pin with Respect to Ground ÀÀÀÀÀÀÀÀÀÀ b2.0V to a7.0V(1) Voltage on Pin A 9 with Respect to Ground ÀÀÀÀÀÀÀ b2.0V to a13.5V(1, 2) VPP Supply Voltage with Respect to Ground During Erase/Program ÀÀÀÀ b2.0V to a14.0V(1, 2) VCC Supply Voltage with Respect to Ground ÀÀÀÀÀÀÀÀÀÀ b2.0V to a7.0V(1) Output Short Circuit CurrentÀÀÀÀÀÀÀÀÀÀÀÀÀ100 mA (3) NOTICE: This data sheet contains preliminary infor- mation on new products in production. The specifica- tions are subject to change without notice. Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. NOTES: 1. Minimum DC input voltage is b0.5V. During transitions, inputs may undershoot to b2.0V for periods less than 20 ns. Maximum DC voltage on output pins is V CC a 0.5V, which may overshoot to V CC a 2.0V for periods less than 20 ns. 2. Maximum DC voltage on A 9 or V PP may overshoot to a14.0V for periods less than 20 ns. 3. Output shorted for no more than one second. No more than one output shorted at a time. OPERATING CONDITIONS Symbol Description Min Max Units Comments VPPL VPP during Read-Only Operations 0.00 V CC a 2.0V V NOTE: Erase/Program are Inhibited when V PP e VPPL VPPH VPP during Read/Write Operations 11.40 12.60 V MIL-STD-883 Symbol Description Min Max Units TC Operating Temperature b55 a125 §C (Instant On) VCC Digital Supply Voltage 4.50 5.50 V Extended Temperature Symbol Description Min Max Units TC Case Temperature b40 a110 §C (Instant On) VCC Digital Supply Voltage 4.50 5.50 V Avionics Grade Symbol Description Min Max Units TC Case Temperature b40 a125 §C (Instant On) VCC Digital Supply Voltage 4.50 5.50 V

DC CHARACTERISTICSÐTTL/NMOS COMPATIBLE Symbol Parameter Limits Unit Comments Min Max ILI Input Leakage Current g1.0 mAV CC e VCC Max VIN e VCC or V SS ILO Output Leakage Current g10 mAV CC e VCC Max VOUT e VCC or V SS ICCS VCC Standby Current 1.0 mA V CC e VCC Max CE e VIH ICC1 VCC Active Read Current 30 mA V CC e VCC Max, CE e VIL f e 6 MHz, I OUT e 0m A ICC2 VCC Programming Current 30 mA Programming in Progress ICC3 VCC Erase Current 30 mA Erasure in Progress IPPS VPP Leakage Current g10 mAV PP e VPPL IPP1 VPP Read Current 200 mAV PP e VPPH Max g10 V PP e VPPL IPP2 VPP Programming Current 30 mA V PP e VPPH Max Programming in Progress IPP3 VPP Erase Current 30 mA V PP e VPPH Max Erasure in Progress VIL Input Low Voltage b0.5 0.8 V VIH Input High Voltage 2.0 V CC a 0.5 V VOL Output Low Voltage 0.45 V I OL e 2.1 mA VCC e VCC Min VOH1 Output High Voltage 2.4 V I OH eb 2.5 mA VCC e VCC Min VID A9 intelligent Identifer Voltage 11.50 13.00 V IID A9 intelligent Identifier Current 500 mAA 9 e VID

DC CHARACTERISTICSÐCMOS COMPATIBLE (Over Specified Operating Conditions) Symbol Parameter Limits Unit Comments Min Max ILI Input Leakage Current g1.0 mAV CC e VCC Max VIN e VCC or V SS ILO Output Leakage Current g10 mAV CC e VCC Max VOUT e VCC or V SS ICCS VCC Standby Current 100 mAV CC e VCC Max CE e VCC g0.2V ICC1 VCC Active Read Current 30 mA V CC e VCC Max, CE e VIL f e 6 MHz, I OUT e 0m A ICC2 VCC Programming Current 30 mA Programming in Progress ICC3 VCC Erase Current 30 mA Erasure in Progress IPPS VPP Leakage Current g10 mAV PP e VPPL IPP1 VPP Read Current 200 mAV PP e VPPH Max g10 V PP e VPPL IPP2 VPP Programming Current 30 mA V PP e VPPH Max Programming in Progress IPP3 VPP Erase Current 30 mA V PP e VPPH Max Erasure in Progress VIL Input Low Voltage b0.5 0.8 V VIH Input High Voltage 0.7 V CC VCC a 0.5 V VOL Output Low Voltage 0.45 V I OL e 2.1 mA VCC e VCC Min VOH1 Output High Voltage 0.85 V CC V IOH eb 2.5 mA, V CC e VCC Min VOH2 VCC b 0.4 I OH eb 100 mA, V CC e VCC Min VID A9 intelligent Identifer Voltage 11.50 13.00 V IID A9 intelligent Identifier Current 500 mAA 9 e VID CAPACITANCE TC e 25§C, f e 1.0 MHz Symbol Parameter Limits Unit Conditions Min Max CIN Address/Control Capacitance 6 pF V IN e 0V COUT Output Capacitance 12 pF V OUT e 0V

AC TESTING INPUT/OUTPUT WAVEFORM 271111–7 AC Testing: Inputs are driven at V OH1 for a logic ‘‘1’’ and V OL for a logic ‘‘0’’. Testing measurements are made at V IH for a logic ‘‘1’’ and V IL for a logic ‘‘0’’. Rise/Fall time s 10 ns. AC LOAD CIRCUIT 271111–8 CL e 100 pF CL includes Jig Capacitance AC TEST CONDITIONS Input Rise and Fall Times (10% to 90%)ÀÀÀÀÀÀ10 ns Input Pulse Levels ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀV OL and V OH1 Input Timing Reference Level ÀÀÀÀÀÀÀÀÀÀV IL and V IH Output Timing Reference Level ÀÀÀÀÀÀÀÀV IL and V IH AC CHARACTERISTICSÐRead-Only Operations Versions M28F010-90 M28F010-12 M28F010-15 M28F010-20 M28F010-25 Unit Symbol Characteristic Min Max Min Max Min Max Min Max Min Max tAVAV/tRC Read Cycle Time 90 120 150 200 250 ns tELQV/tCE Chip Enable 90 120 150 200 250 ns Access Time tAVQV/tACC Address Access 90 120 150 200 250 ns Time tGLQV/tOE Output Enable 40 50 55 60 65 ns Access Time tELQX/tLZ Chip Enable to 0 0 0 0 0 ns Output in Low Z tGLQX/tOLZ Output Enable to 0 0 0 0 0 ns Output in Low Z tGHQZ/tDF Output Disable to 30 30 35 45 60 ns Output in High Z tOH Output Hold from Address, CE ,0 0 0 0 0 n s or OE Change(1) tWHGL Write Recovery 6 6 6 6 6 ms Time before Read NOTE: 1. Whichever occurs first.

Figure 6. AC Waveforms for Read Operations

AC CHARACTERISTICSÐWrite/Erase/Program Operations (1,2) Versions M28F010-90 M28F010-12 M28F010-15 M28F010-20 M28F010-25 Unit Symbol Characteristic Min Max Min Max Min Max Min Max Min Max tAVAV/tWC Write Cycle Time 90 120 150 200 250 ns tAVWL/tAS Address Set-Up 0 0 0 0 0 ns Time tWLAX/tAH Address Hold Time 60 60 60 90 ns tDVWH/tDS Data Set-up Time 50 50 50 50 50 ns tWHDX/tDH Data Hold Time 10 10 10 10 10 ns tWHGL Write Recovery 6 6 6 6 6 ms Time before Read tGHWL Read Recovery 0 0 0 0 0 ms Time before Write tELWL/tCS Chip Enable 20 20 20 20 20 ns Set-Up Time before Write tWHEH/tCH Chip Enable 0 0 0 0 0 ns Hold Time tWLWH/tWP Write Pulse Width 80 80 80 80 80 ns tELEH Alternative Write 80 80 80 80 80 ns Pulse Width tWHWL/tWPH Write Pulse 20 20 20 20 20 ns Width High tWHWH1 Duration of 10 25 10 25 10 25 10 25 10 25 ms Programming Operation Erase Operation tVPEL VPP Set-Up 100 100 100 100 100 ns Time to Chip Enable Low NOTES: 1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Char- acteristics for Read-Only Operations. 2. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip-Enable and Write-Enable. In systems where Chip-Enable defines the write pulse width (within a longer Write-Enable timing waveform) all set-up, hold, and inactive Write-Enable times should be measured relative to the Chip-Enable waveform.

Figure 11. AC Waveforms for Programming Operations

Figure 12. AC Waveforms for Erase Operations

ER-20, ‘‘ETOX II Flash Memory Technology 294005 ER-24, ‘‘The Intel 28F010 Flash Memory’’ 294008 RR-60, ‘‘ETOX II Flash Memory Reliability 293002 Data Summary’’ AP-316, ‘‘Using Flash Memory for In-System 292046 Reprogrammable Nonvolatile Storage’’ AP-325, ‘‘Guide to Flash Memory 292059 Reprogramming’’