M28F008 INTEL | Alldatasheet
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*Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. November 1994COPYRIGHT © INTEL CORPORATION, 1995 Order Number: 271232-004 M28F008
8 MBIT (1 MBIT x 8) FLASH MEMORY
Y High-Density Symmetrically Blocked Architecture Ð Sixteen 64 Kbyte Blocks Y Extended Cycling Capability Ð 10K Block Erase Cycles Minimum Ð 160K Block Erase Cycles per Chip Y Automated Byte Write and Block Erase Ð Command User Interface Ð Status Register Y System Performance Enhancements Ð RY/BY Status Output Ð Erase Suspend Capability Y SRAM-Compatible Write Interface Y Very High-Performance Read Ð 100 ns Maximum Access Time Y Hardware Data Protection Feature Ð Erase/Write Lockout during Power Transitions Y Industry Standard Packaging Ð 40-Lead Sidebrazed DIP Ð 42-Lead Flatpack Y ETOXTM Nonvolatile Flash Technology Ð 12V Byte Write/Block Erase Y Independent Software Vendor Support Ð Microsoft * Flash File System (FFS) Intel’s M28F008 8-Mbit FlashFile Memory is the highest density nonvolatile read/write solution for solid state storage. The M28F008’s extended cycling, symmetrically blocked architecture, fast access time, write automa- tion and low power consumption provide a more reliable, lower power, lighter weight and higher performance alternative to traditional rotating disk technology. The M28F008 brings new capabilities to portable computing. Application and operating system software stored in resident flash memory arrays provide instant-on, rapid execute-in-place and protection from obsolescence through in-system software updates. Resident software also extends system battery life and increases reliability by reducing disk drive accesses. For high-density data acquisition applications, the M28F008 offers a more cost-effective and reliable alterna- tive to SRAM and battery. Traditional high density embedded applications, such as telecommunications, can take advantage of the M28F008’s nonvolatility, blocking and minimal system code requirements for flexible firmware and modular software designs. The M28F008 is offered in 40-lead sidebrazed DIP and 42-lead Flatpack packages. This device uses an integrated Command User Interface and state machine for simplified block erasure and byte write. The M28F008 memory map consists of 16 separately erasable 64 Kbyte blocks. Intel’s M28F008 employs advanced CMOS circuitry for systems requiring low power consumption and noise immunity. Its 100 ns access time provides superior performance when compared with magnetic storage media. A deep powerdown mode lowers power consumption to 500 mW maximum thru V CC. The RP power control input also provides absolute data protection during system powerup/down. Manufactured on Intel’s ETOX process technology, the M28F008 provides the highest levels of quality, reliabil- ity and cost-effectiveness. *Microsoft is a trademark of Microsoft Corporation.
The M28F008 is a high-performance 8 Mbit (8,388,608 bit) memory organized as 1 Mbyte (1,048,576 bytes) of 8 bits each. Sixteen 64 Kbyte (65,536 byte) blocks are included on the M28F008. A memory map is shown in Figure 4 of this specifica- tion. A block erase operation erases one of the six- teen blocks of memory in typically 1.6 seconds , in- dependent of the remaining blocks. Each block can be independently erased and written 10,000 cycles . Erase Suspend mode allows system software to suspend block erase to read data or execute code from any other block of the M28F008. The M28F008 is available in 40-lead sidebrazed DIP and 42-lead Flatpack packages. Pinouts are shown in Figures 2a and 2b of this specification. The Command User Interface serves as the inter- face between the microprocessor or microcontroller and the internal operation of the M28F008. Byte Write and Block Erase Automation allow byte write and block erase operations to be execut- ed using a two-write command sequence to the Command User Interface. The internal Write State Machine (WSM) automatically executes the algo- rithms and timings necessary for byte write and block erase operations, including verifications, thereby unburdening the microprocessor or micro- controller. Writing of memory data is performed in byte increments typically within 9 ms, an 80% im- provement over current flash memory products. I PP byte write and block erase currents are 30 mA maximum. V PP byte write and block erase volt- age is 11.4V to 12.6V . The Status Register indicates the status of the WSM and when the WSM successfully completes the desired byte write or block erase operation. The RY/BY output gives an additional indicator of WSM activity, providing capability for both hardware signal of status (versus software polling) and status masking (interrupt masking for background erase, for example). Status polling using RY/BY minimizes both CPU overhead and system power consump- tion. When low, RY/BY indicates that the WSM is performing a block erase or byte write operation. RY/BY high indicates that the WSM is ready for new commands, block erase is suspended or the device is in deep powerdown mode. Maximum access time is 100 ns (t ACC) over the mili- tary temperature range ( b55§Ct o a125§C) and over V CC supply voltage range 4.5V to 5.5V. ICC ac- tive current (CMOS Read) is 35 mA maximum at 8 MHz . When the CE and RP pins are at V CC, the ICC CMOS Standby mode is enabled. A Deep Powerdown mode is enabled when the RP pin is at GND, minimizing power consumption and providing write protection. ICC current in deep pow- erdown is 100 mA maximum . Reset time of 400 ns is required from RP switching high until outputs are valid to read attempts. Equivalently, the device has a wake time of 1 ms from RP high until writes to the Command User Interface are recognized by the M28F008. With RP at GND, the WSM is reset and the Status Register is cleared.
Figure 1. Block Diagram Table 1. Pin Description latched during a write cycle. disabled. Data is internally latched during a write cycle. memory device and reduces power consumption to standby levels. automation. Exit from Deep Powerdown sets device to read-array mode. during a read cycle. OE is active low. rising edge of the WE pulse.
Figure 3. M28F008 Array Interface to Intel386 TM SL Microprocessor Superset through PI Bus Resident O/S and Applications and Motherboard Solid-State Disk. verified thru the Status Register.
erase status for verification. data and execute code from any other block.
64 Kbyte Block
Figure 4. Memory Map VPP e VPPL, memory contents cannot be altered. optimization of the processor-memory interface. PP can be at either V PPL or V PPH. device powerup or after exit from deep powerdown.
Table 2. Bus Operations
- Refer to DC Characteristics. When V PP e VPPL, memory contents can be read but not written or erased.
- X can be V IL or V IH for control pins and addresses, and V PPL or V PPH for V PP. See DC Characteristics for V PPL and V PPH
WSM is not busy, in Erase Suspend mode or deep powerdown mode.
- Command writes involving block erase or byte write are only successfully executed when V
- Refer to Table 3 for valid D IN during a write operation.
must be logically active to obtain data at the outputs. when active enables the selected memory device. placed in a high-impedance state. down until initial memory access outputs are valid. valid as the data will be partially written or erased. quired before another command can be written. gent identifier from the Command User Interface.
Table 3. Command Definitions
- Bus operations are defined in Table 2.
e Identifier Address: 00H for manufacturer code, 01H for device code. BA e Address within the block being erased. WA e Address of memory location to be written.
- SRD e Data read from Status Register. See Table 4 for a description of the Status Register bits.
WD e Data to be written at location WA. Data is latched on the rising edge of WE . IID e Data read from intelligent identifiers.
- Following the intelligent identifier command, two read operations access manufacture and device codes.
- Either 40H or 10H are recognized by the WSM as the Byte Write Setup command.
- Commands other than those shown above are reserved by Intel for future device implementations and should not be
User Interface controls block erasure and byte write. to the internal write state machine. 3 defines the M28F008 commands.
Table 4. Status Register Definitions quence was entered. Attempt the operation again. back between V PPL and V PPH. bits indicate various failure conditions (see Table 4). the way the device may be used.
Erase is executed one block at a time, initiated by a two-cycle command sequence. An Erase Setup command (20H) is first written to the Command User Interface, followed by the Erase Confirm command (D0H). These commands require both appropriate sequencing and an address within the block to be erased to FFH. Block preconditioning, erase and verify are all handled internally by the Write State Machine, invisible to the system. After the two-com- mand erase sequence is written to it, the M28F008 automatically outputs Status Register data when read (see Figure 6; Block Erase Flowchart). The CPU can detect the completion of the erase event by analyzing the output of the RY/BY pin, or the WSM Status bit of the Status Register. When erase is completed, the Erase Status bit should be checked. If erase error is detected, the Status Register should be cleared. The Command User Interface remains in Read Status Register mode until further commands are issued to it. This two-step sequence of set-up followed by execu- tion ensures that memory contents are not acciden- tally erased. Also, reliable block erasure can only occur when V PP e VPPH. In the absence of this high voltage, memory contents are protected against era- sure. If block erase is attempted while V PP e VPPL, the V PP Status bit will be set to ‘‘1’’. Erase attempts while V PPL k VPP k VPPH produce spurious results and should not be attempted. Erase Suspend/Erase Resume Commands The Erase Suspend command allows block erase interruption in order to read data from another block of memory. Once the erase process starts, writing the Erase Suspend command (B0H) to the Com- mand User Interface requests that the WSM sus- pend the erase sequence at a predetermined point in the erase algorithm. The M28F008 continues to output Status Register data when read, after the Erase Suspend command is written to it. Polling the WSM status and Erase Suspend status bits will de- termine when the erase operation has been sus- pended (both will be set to ‘‘1’’). RY/BY will also transition to V OH. At this point, a Read Array command can be written to the Command User Interface to read data from blocks other than that which is suspended. The only other valid commands at this time are Read Status Register (70H) and Erase Resume (D0H), at which time the WSM will continue with the erase process. The Erase Suspend status and WSM status bits of the Status Register will be automatically cleared and RY/BY will return to V OL. After the Erase Resume command is written to it, the M28F008 automatically outputs Status Register data when read (see Figure 7; Erase Suspend/Resume Flowchart). V PP must re- main at V PPH while the M28F008 is in Erase Sus- pend. Byte Write Setup/Write Commands Byte write is executed by a two-command sequence. The Byte Write Setup command (40H) is written to the Command User Interface, followed by a second write specifying the address and data (latched on the rising edge of WE ) to be written. The WSM then takes over, controlling the byte write and write verify algorithms internally. After the two-command byte write sequence is written to it, the M28F008 auto- matically outputs Status Register data when read (see Figure 5; Byte Write Flowchart). The CPU can detect the completion of the byte write event by ana- lyzing the output of the RY/BY pin, or the WSM status bit of the Status Register. Only the Read Status Register command is valid while byte write is active. When byte write is complete, the Byte Write status bit should be checked. If byte write error is detected, the Status Register should be cleared. The internal WSM verify only detects errors for ‘‘1’’s that do not successfully write to ‘‘0’’s. The Command User In- terface remains in Read Status Register mode until further commands are issued to it. If byte write is attempted while V PP e VPPL, the V PP Status bit will be set to ‘‘1’’. Byte write attempts while VPPL k VPP k VPPH produce spurious results and should not be attempt- ed.
Intel has designed extended cycling capability into its ETOX flash memory technologies. The M28F008 is designed for 10,000 byte write/block erase cycles on each of the sixteen 64 Kbyte blocks. Low electric fields, advanced oxides and minimal oxide area per cell subjected to the tunneling electric field combine to greatly reduce oxide stress and the probability of failure. A 20 Mbyte solid-state drive using an array of M28F008s has a MTBF (Mean Time Between Fail- ure) of 3.33 million hours (1), over 600 times more reliable than equivalent rotating disk technology. AUTOMATED BYTE WRITE The M28F008 integrates the Quick-Pulse program- ming algorithm of prior Intel Flash devices on-chip, using the Command User Interface, Status Register and Write State Machine (WSM). On-chip integration dramatically simplifies system software and provides processor interface timings to the Command User Interface and Status Register. WSM operation, inter- nal verify and V PP high voltage presence are moni- tored and reported via the RY/BY output and appro- priate Status Register bits. Figure 5 shows a system software flowchart for device byte write. The entire sequence is performed with V PP at V PPH. Byte write abort occurs when RP transitions to V IL,o rV PP drops to V PPL. Although the WSM is halted, byte data is partially written at the location where byte write was aborted. Block erasure, or a repeat of byte write, is required to initialize this data to a known value. AUTOMATED BLOCK ERASE As above, the Quick-Erase algorithm of prior Intel Flash devices is now implemented internally, includ- ing all preconditioning of block data. WSM opera- tion, erase success and V PP high voltage presence are monitored and reported through RY/BY and the Status Register. Additionally, if a command other than Erase Confirm is written to the device following Erase Setup, both the Erase Status and Byte Write Status bits will be set to ‘‘1’’s. When issuing the Erase Setup and Erase Confirm commands, they should be written to an address within the address range of the block to be erased. Figure 6 shows a system software flowchart for block erase. Erase typically takes 1.6 seconds per block. The Erase Suspend/Erase Resume command sequence allows suspension of this erase operation to read data from a block other than that in which erase is being performed. A system software flowchart is shown in Figure 7. The entire sequence is performed with V PP at V PPH. Abort occurs when RP transitions to V IL or V PP falls to V PPL, while erase is in progress. Block data is partially erased by this operation, and a repeat of erase is required to obtain a fully erased block. DESIGN CONSIDERATIONS Three-Line Output Control The M28F008 will often be used in large memory arrays. Intel provides three control inputs to accom- modate multiple memory connections. Three-line control provides for: a) lowest possible memory power dissipation b) complete assurance that data bus contention will not occur To efficiently use these control inputs, an address decoder should enable CE , while OE should be con- nected to all memory devices and the system’s READ control line. This assures that only selected memory devices have active outputs while deselect- ed memory devices are in Standby Mode. Finally, RP should either be tied to the system RESET ,o r connected to V CC if unused. RY/BY and Byte Write/Block Erase Polling RY/BY is a full CMOS output that provides a hard- ware method of detecting byte write and block erase completion. It transitions low time t WHRL after a write or erase command sequence is written to the M28F008, and returns to V OH when the WSM has finished executing the internal algorithm. RY/BY can be connected to the interrupt input of the system CPU or controller. It is active at all times, not tri-stated if the M28F008 CE or OE inputs are brought to V IH. RY/BY is also V OH when the device is in Erase Suspend or deep powerdown modes. (1)Assumptions: 10 Kbyte file written every 10 minutes. (20 Mbyte array)/(10 Kbyte file) e 2,000 file writes before erase required. (2000 files writes/erase) c (10,000 cycles per M28F008 block) e 20 million file writes. (20 c 106 file writes) c (10 min/write) c (1 hr/60 min) e 3.33 c 106 MTBF.
attempting retry or other error recovery. Figure 5. Automated Byte Write Flowchart
attempting retry or other error recovery. Figure 6. Automated Block Erase Flowchart
Figure 7. Erase Suspend/Resume Flowchart
Flash memory power switching characteristics re- quire careful device decoupling. System designers are interested in 3 supply current issues; standby current levels (I SB), active current levels (I CC) and transient peaks produced by falling and rising edges of CE . Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 mF ceramic capacitor connected between each V CC and GND, and be- tween its V PP and GND. These high frequency, low inherent-inductance capacitors should be placed as close as possible to package leads. Additionally, for every 8 devices, a 4.7 mF electrolytic capacitor should be placed at the array’s power supply con- nection between V CC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances. VPP Trace on Printed Circuit Boards Writing flash memories, while they reside in the tar- get system, requires that the printed circuit board designer pay attention to the V PP power supply trace. The V PP pin supplies the memory cell current for writing and erasing. Use similar trace widths and layout considerations given to the V CC power bus. Adequate V PP supply traces and decoupling will de- crease V PP voltage spikes and overshoots. VCC,V PP,R P Transitions and the Command/Status Registers Byte write and block erase completion are not guar- anteed if V PP drops below V PPH. If the V PP Status bit of the Status Register (SR.3) is set to ‘‘1’’, a Clear Status Register command MUST be issued before further byte write/block erase attempts are allowed by the WSM. Otherwise, the Byte Write (SR.4) or Erase (SR.5) Status bits of the Status Register will be set to ‘‘1’’s if error is detected. RP transitions to VIL during byte write and block erase also abort the operations. Data is partially altered in either case, and the command sequence must be repeated after normal operation is restored. Device poweroff, or RP transitions to V IL, clear the Status Register to initial value 10000 for the upper 5 bits. The Command User Interface latches commands as issued by system software and is not altered by V PP or CE transitions or WSM actions. Its state upon powerup, after exit from deep powerdown or after V CC transitions below V LKO, is Read Array Mode. After byte write or block erase is complete, even after V PP transitions down to V PPL, the Command User Interface must be reset to Read Array mode via the Read Array command if access to the memory array is desired. Power Up/Down Protection The M28F008 is designed to offer protection against accidental block erasure or byte writing during power transitions. Upon power-up, the M28F008 is indiffer- ent as to which power supply, V PP or V CC, powers up first. Power supply sequencing is not required. Internal circuitry in the M28F008 ensures that the Command User Interface is reset to the Read Array mode on power up. A system designer must guard against spurious writes for V CC voltages above V LKO when V PP is active. Since both WE and CE must be low for a command write, driving either to V IH will inhibit writes. The Command User Interface architecture provides an added level of protection since altera- tion of memory contents only occurs after success- ful completion of the two-step command sequences. Finally, the device is disabled until RP is brought to VIH, regardless of the state of its control inputs. This provides an additional level of memory protection. Power Dissipation When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash nonvolatility increases us- able battery life, because the M28F008 does not consume any power to retain code or data when the system is off. In addition, the M28F008’s deep powerdown mode ensures low power dissipation even when system power is applied. For example, portable PCs and other power sensitive applications, using an array of M28F008s for solid-state storage, can lower RP to VIL in standby or sleep modes, reducing power con- sumption. If access to the M28F008 is again need- ed, the part can again be read, following the t PHQV and t PHWL wakeup cycles required after RP is first raised back to V IH. See AC CharacteristicsÐRead- Only and Write Operations and Figures 8 and 9 for more information.
ABSOLUTE MAXIMUM RATINGS * Operating TemperatureÀÀÀÀÀÀÀÀÀ b55§Ct o a125§C Temperature Under BiasÀÀÀÀÀÀÀÀ b55§Ct o a125§C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b65§Ct o a125§C Voltage on Any Pin (except V CC and V PP) with Respect to GND ÀÀÀÀÀÀÀÀ b2.0V to a7.0V(1) VPP Program Voltage with Respect to GND during Block Erase/Byte Write ÀÀÀ b2.0V to a14.0V(1, 2) VCC Supply Voltage with Respect to GND ÀÀÀÀÀÀÀÀ b2.0V to a7.0V(1) Output Short Circuit CurrentÀÀÀÀÀÀÀÀÀÀÀÀÀ100 mA (3) NOTICE: This data sheet contains preliminary infor- mation on new products in production. The specifica- tions are subject to change without notice. Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. NOTES: 1. Minimum DC voltage is b0.5V on input/output pins. During transitions, this level may undershoot to b2.0V for periods k20 ns. Maximum DC voltage on input/output pins is V CC a 0.5V which, during transitions, may overshoot to V CC a 2.0V for periods k20 ns. 2. Maximum DC voltage on V PP may overshoot to a14.0V for periods k20 ns. 3. Output shorted for no more than one second. No more than one output shorted at a time. OPERATING CONDITIONS Symbol Parameter Min Max Unit TC Operating Temperature b55 a125 §C VCC VCC Supply Voltage (10%) 4.50 5.50 V DC CHARACTERISTICS Symbol Parameter Notes MC28F008 and Unit Test ConditionsMF28F008 Min Max ILI Input Load Current 1 g1.0 mAV CC e VCC Max VIN e VCC or GND ILO Output Load Current 1 g10 mAV CC e VCC Max VOUT e VCC or GND ICCS VCC Standby Current 1, 3 2.0 mA V CC e VCC Max CE e RP e VIH 150 mAV CC e VCC Max CE e RP e VCC g0.2V ICCD VCC Deep Powerdown Current 1 100 mAR P e GND g0.2V IOUT (RY/BY) e 0m A ICCR VCC Read Current 1 35 mA V CC e VCC Max, CE e GND, F e 8 MHz, I OUT e 0 mA, CMOS Inputs 50 mA V CC e VCC Max, CE e VIL, F e 8 MHz, I OUT e 0 mA, TTL Inputs
DC CHARACTERISTICS (Continued) Symbol Parameter Notes MC28F008 and Unit Test ConditionsMF28F008 Min Max ICCW VCC Byte Write Current 1 30 mA Byte Write In Progress ICCE VCC Block Erase Current 1 30 mA Block Erase In Progress ICCES VCC Erase Suspend Current 1, 2 10 mA Block Erase Suspended CE e VIH IPPS VPP Standby Current 1 g15 mAV PP s VCC 200 mAV PP l VCC IPPD VPP Deep PowerDown Current 1 20 mAR P e GND g0.2V IPPW VPP Write Current 1 30 mA V PP e VPPH Byte Write in Progress IPPE VPP Block Erase Current 1 30 mA V PP e VPPH Block Erase in Progress IPPES VPP Erase Suspend Current 1 200 mAV PP e VPPH Block Erase Suspended VIL Input Low Voltage b0.5 0.8 V VIH Input High Voltage 2.0 V CCa0.5 V VOL Output Low Voltage 3 0.45 V V CC e VCC Min IOL e 5.8 mA VOH Output High Voltage 3 2.4 V V CC e VCC Min IOH eb 2.5 mA VPPL VPP during Normal Operations 4 0.0 6.5 V VPPH VPP during Erase/Write Operations 11.4 12.6 V VLKO VCC Erase/Write Lock Voltage 1.8 V CAPACITANCE(5) TA e 25§C, f e 1 MHz Symbol Parameter Typ Max Unit Condition CIN Input Capacitance 6 8 pF V IN e 0V COUT Output Capacitance 8 12 pF V OUT e 0V NOTES: 1. All currents are in RMS unless otherwise noted. 2. I CCES is specified with the device deselected. If the M28F008 is read while in Erase Suspend Mode, current draw is the sum of I CCES and I CCR. 3. Includes RY/BY . 4. Block Erases/Byte Writes are inhibited when V PP e VPPL and not guaranteed in the range between V PPH and V PPL.
AC INPUT/OUTPUT REFERENCE WAVEFORM 271232–9 AC test inputs are driven at V OH (2.4 V TTL) for a Logic ‘‘1’’ and V OL (0.45 V TTL) for a Logic ‘‘0’’. Input timing begins at V IH (2.0 V TTL) and V IL (0.8 V TTL). Output timing ends at V IH and VIL. Input rise and fall times (10% to 90%) k 10 ns. AC TESTING LOAD CIRCUIT CL e 100 pF CL Includes Jig 271232–10 Capacitance RL e 3.3 k X AC CHARACTERISTICSÐRead-Only Operations (1, 4) Symbol Parameter Notes M28F008-10(4) M28F008-12(4) Unit Min Max Min Max tAVAV tRC Read Cycle Time 100 120 ns tAVQV tACC Address to Output Display 100 120 ns tELQV tCE CE to Output Delay 2 100 120 ns tPHQV tPWH RP High to Output Delay 400 400 ns tGLQV tOE OE to Output Delay 2 60 60 ns tELQX tLZ CE to Output Low Z 3 0 0 ns tEHQZ tHZ CE High to Output High Z 3 55 55 ns tGLQX tOLZ OE to Output Low Z 3 0 0 ns tGHQZ tDF OE High to Output High Z 3 30 30 ns tOH Output Hold from 3 0 0 ns Addresses, CE or OE Change, Whichever is First NOTES: 1. See AC Input/Output Reference Waveform for timing measurements. 2. OE may be delayed up to t CE –tOE after the falling edge of CE without impact on t CE. 3. Sampled, not 100% tested. 4. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics.
Figure 8. AC Waveform for Read Operations
AC CHARACTERISTICSÐWrite Operations (1, 7) Symbol Parameter Notes M28F008-10(7) M28F008-12(7) Unit Min Max Min Max tAVAV tWC Write Cycle Time 100 120 ns tPHWL tPS RP High Recovery to WE 21 1 ms Going Low tELWL tCS CE Setup to WE Going Low 10 10 ns tWLWH tWP WE Pulse Width 40 40 ns tVPWH tVPS VPP Setup to WE Going 2 100 100 ns High tAVWH tAS Address Setup to WE Going 3 40 40 ns High tDVWH tDS Data Setup to WE Going 4 40 40 ns High tWHDX tDH Data Hold from WE High 5 5 ns tWHAX tAH Address Hold from WE High 5 5 ns tWHEH tCH CE Hold from WE High 10 10 ns tWHWL tWPH WE Pulse Width High 30 30 ns tWHRL WE High to RY/BY Going 100 100 ns Low tWHQV1 Duration of Byte Write 5, 6 6 6 ms Operation tWHQV2 Duration of Block Erase 5, 6 0.3 0.3 sec Operation tWHGL Write Recovery before 0 0 ms Read tQVVL tVPH VPP Hold from Valid SRD, 2, 6 0 0 ns RY/BY High NOTES: 1. Read timing characteristics during erase and byte write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations. 2. Sampled, not 100% tested. 3. Refer to Table 3 for valid A IN for byte write or block erasure. 4. Refer to Table 3 for valid D IN for byte write or block erasure. 5. The on-chip Write State Machine incorporates all byte write and block erase system functions and overhead of standard Intel flash memory, including byte program and verify (byte write) and block precondition, precondition verify, erase and erase verify (block erase). 6. Byte write and block erase durations are measured to completion (SR.7 e 1, RY/BY e VOH). V PP should be held at VPPH until determination of byte write/block erase success (SR.3/4/5 e 0) 7. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics.
BLOCK ERASE AND BYTE WRITE PERFORMANCE Parameter Notes M28F008-10 M28F008-12 Unit Min Typ Max Min Typ Max Block Erase Time 1, 2 1.6 10 1.6 10 sec Block Write Time 1, 2 0.6 2.1 0.6 2.1 sec NOTES: 1. 25 §C, 12.0 V PP. 2. Excludes System-Level Overhead.
Figure 9. AC Waveform for Write Operations
ALTERNATIVE CE -CONTROLLED WRITES (1) Symbol Parameter Notes M28F008-10(6) M28F008-12(6) Unit Min Max Min Max tAVAV tWC Write Cycle Time 100 120 ns tPHEL tPS RP High Recovery to CE 21 1 ms Going Low tWLEL tWS WE Setup to CE Going Low 0 0 ns tELEH tCP CE Pulse Width 50 50 ns tVPEH tVPS VPP Setup to CE Going High 2 100 100 ns tAVEH tAS Address Setup to CE Going 3 40 40 ns High tDVEH tDS Data Setup to CE Going High 4 40 40 ns tEHDX tDH Data Hold from CE High 5 5 ns tEHAX tAH Address Hold from CE High 5 5 ns tEHWH tWH WE Hold from CE High 0 0 ns tEHEL tEPH CE Pulse Width High 25 25 ns tEHRL CE High to RY/BY Going 100 100 ns Low tEHQV1 Duration of Byte Write 5 6 6 ms Operation tEHQV2 Duration of Block Erase 5 0.3 0.3 sec Operation tEHGL Write Recovery before Read 0 0 ms tQVVL tVPH VPP Hold from Valid SRD, 2, 5 0 0 ns RY/BY High NOTES: 1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE and WE . In systems where CE defines the write pulsewidth (within a longer WE timing waveform), all setup, hold and inactive WE times should be mea- sured relative to the CE waveform. 2. Sampled, not 100% tested. 3. Refer to Table 3 for valid A IN for byte write or block erasure. 4. Refer to Table 3 for valid D IN for byte write or block erasure. 5. Byte write and block erase durations are measured to completion (SR.7 e 1, RY/BY e VOH). V PP should be held at VPPH until determination of byte write/block erase success (SR.3/4/5 e 0) 6. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics.
Figure 10. Alternate AC Waveform for Write Operations
ORDERING INFORMATION
C e 40-Pin Sidebrazed DIP 10 e 100 ns F e 42-Lead Flatpack 12 e 120 ns X ä Y ADDITIONAL INFORMATION Order Number 28F008SA-L Data Sheet 290435 AP-359 ‘‘28F008SA Hardware Interfacing’’ 292094 AP-360 ‘‘28F008SA Software Drivers’’ 292095 AP-364 ‘‘28F008SA Automation and Algorithms’’ 292099 ER-27 ‘‘The Intel 28F008SA Flash Memory’’ 294011 ER-28 ‘‘ETOX III Flash Memory Technology’’ 290412
MC28F008 PACKAGE DIMENSIONS 271232–15 Symbol Millimeters Inches Min Max Notes Min Max Notes a 0§ 10§ 0§ 10§ A 3.30 5.51 Solid Lid 0.130 0.217 Solid Lid A1 1.02 1.52 0.040 0.060 A2 2.29 3.99 Solid Lid 0.090 0.157 Solid Lid A3 2.03 3.66 0.080 0.144 B 0.38 0.56 0.015 0.022 B1 1.27 Typical 0.050 Typical C 0.23 0.30 Typical 0.009 0.012 Typical D 50.29 51.31 1.980 2.020 D2 48.26 Reference 1.900 Reference E 15.24 15.75 0.600 0.620 E1 14.86 15.37 0.585 0.605 e1 2.29 2.79 0.090 0.110 eA 14.99 Reference 0.590 Reference eB 15.24 17.15 0.600 0.675 L 3.18 4.06 0.125 0.160 N4 0 4 0 S 0.76 1.78 0.030 0.070 S1 0.13 0.005 S2 0.13 0.005 ISSUE IWS
MF28F008 PACKAGE DIMENSIONS 271232–16 Symbol Millimeters Inches Min Max Notes Min Max Notes A 2.08 2.17 Solid Lid 0.082 0.103 Solid Lid B 0.43 0.58 Typical 0.017 0.023 Typical C 0.13 0.25 Typical 0.005 0.010 Typical D 26.67 27.18 1.050 1.070 D2 25.40 Reference 1.000 Reference E 16.00 16.51 0.630 0.650 E2 13.46 13.97 0.530 0.550 E3 0.89 1.65 0.035 0.065 e1 1.14 1.40 Typical 0.045 0.055 Typical H 32.77 Reference 1.29 Reference L 7.87 8.64 0.310 0.340 N4 2 4 2 Q 1.27 1.55 0.050 0.061 S 0.23 1.02 0.009 0.040 S1 0.00 1.27 0.000 0.050 ISSUE IWS 8/90
REVISION HISTORY
-002 Ð Revised Extended Cycling Capability to 10K Block Erase Cycles 160K Block Erase Cycles per Chip Ð Changed I PPS Standby current spec from g10 mAt o g15 mA Ð Removed typical Block Erase times Number Description -003 Ð PWD renamed RP for JEDEC stan- dardization compatibility Ð Added MF, 42-Lead Flatpack Ð Added 100 ns access time specs Ð Combined V PP Standby current and VPP Read current into one V PP Stand- by condition with two test conditions (DC Characteristics table) INTEL CORPORATION, 2200 Mission College Blvd., Santa Clara, CA 95052; Tel. (408) 765-8080 INTEL CORPORATION (U.K.) Ltd., Swindon, United Kingdom; Tel. (0793) 696 000 INTEL JAPAN k.k., Ibaraki-ken; Tel. 029747-8511 Printed in U.S.A./xxxx/1295/B10M/xx xx