M27256 INTEL | Alldatasheet
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with Intel’s M8051 family of microcontrollers. reliability, high-pertormance systems. ‘The M27256's large storage capability of 32K bytes enables it to function as a high density software carrier. access and ‘execution of software and eliminate the need for time consuming disk accesses and downloads. an efficient programming method. or choosing between nonvolatile memory alternatives. ‘The M27256 is manufactured using Intel's advanced HMOS* II-E technology. *HMOS Is a patented process ot Intel Corporation. Figure 1. Block Diagram fats M27256 OE ae spi) ite
ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi- Case T ature Unde cations are subject to change without notice. ‘ase Temperature Under — ese * WARNING: Stressing the device beyond the “Absolute Bias eee eeeeeeeseee “BEC tO +125°C | PARNING: Stressi Ratings” may cause permanent damage. All input or Output Voltages with “Operating Condiiions” is not recommended and ex- Voltage on Pin 24 with y device rekabiliy. Vpp Supply Voltage with Respect Operating Conditions [__symbot [Description min | Max [Units Case Temperature instantOn) | ss | +125 | Digital Supply Voltage [| 4s [| sso [ov | READ OPERATION D.C. CHARACTERISTICS (Over Specified Operating Conditions) [ur | Inputtoadourent ||| | v= sev | | to | OutoutLeakagecurent | | | to | wa | Vour= sav | [e® | Vor Curent RosarStancty | [| 5 | ma | Vop= sav | [ oor? | VocGurrentstanaby | | 20 | 50 | ma | EV | [coat | Veo urentactwe || «5 | 105 | ma] CE=OE=va | | vuS | inputtowvottage | -o1 | | toe |v [| | vine | tnputtighvotage | 20 | | oot | v [| [Yor | Ouputtowvorage | [| ome |v | etm | [vox | owputtign vonage | 2e [|__| von = 00 5 | See notes on next page. 7-53
a A.C. CHARACTERISTICS (Over Specified Operating Conditions) [ace | Aasrossto Outpurdey | [200 [| aso || 50 | ne | 0E= OE = vn | [tcc | CEtooupuoeay || 200 | | a0 || sso | ve [OE=w | [toc | CEtooutputdoay | o [75 | | too | [iso [ me [oe=w | [tort | OEHigh to Outmutetost | o [ss | o | oo | o | no] ns [oe-m | ton!4 Output Hold from. CE = OF = VL Addresses, CE or OE Whichever Ocourred First NOTES: 1. Voc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. 2. Vpp may be connected directly to Voc except during programming. The supply current would then be the sum of Ioc and lpr. 3. Typical values are for To = +25°C and nominal supply voltages. 4, Output Float is defined as the point where data is no longer driven. CAPACITANCE Tc = +25°C, f = 1 MHz [ symboi [Parameter | Typ(? | Max | units | Conaitions | [cn | infutCapactance [4 | 6 | oF | Vw=ov | [Cour | OuputCepactance |e | 12 | oF | Vour=ov | A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT sav Py J new ‘eet pose axa _ Xe = it. 230961-4 = io 100 pF AC, Testing: Inputs are Driven at 2.4V for a Logic "1" and 0.45V = for a Logic “0”. Timing Measurements are made at 2.0V for & C= 100 pF 290961-5 Logie "1" and 0.8V for @ Logic “0”. ei a 7-54
- Type! values are for Tc = 25°C and nominal supply voltages.
- OE may be delayed up to tacc-tog after the falling edge of CE without impact on tacc.
- Output float is defined as the point where data is no longer driven.
read mode. All inputs are TTL tevels except for Vpp and 12V on AQ for intgligent identifier mode. Table 1. Operating Modes
a vice. The associated transient voltage peaks can be Read Mode suppressed by complying with Intel's Two-Line Con- The M27256 has two control functions, both of trol and by properly selected decoupling capacitors. which must be logically active in order to obtain data It is recommended that a 0.1 BF ceramic capacitor at the outputs. Chip Enable (CE) is the power control be used on every device between Vcc and GND. and should be used for device selection. Output En- THis ‘should (be a oe bos be vcs al of Tow able is the output contro! and should be used rent it ince and st laced as close to cate ‘data from the output pins, independent of 10 the device as possible. In accion, 2.47 uF bulk device selection. Assuming that addresses are sta- electrolytic capacitor should be used between Vcc ble, the address access time (tacc) is equal to the and GND for every eight devices. The bulk capacitor delay from CE to output (tog). Data is available at should be located near where the power supply is the outputs aftr 8 delay of tog from the falling edge connected to the array. The purpose of the bulk ca- of OE, assuming that CE has been low and address- _pacitor is to overcome the voltage droop caused by es have been stable for at least tacc-toe. the inductive effects of PC board traces. Standby Mode Programming y Caution: Exceeding 13.0V on pin 1 will per- ‘The M27256 has a standby mode which reduces the —_manently damage the re (ee) maximum active current from 125 mA to 50. The M27256 is placed in the standby mode by applying a initially, and after each erasure, all bits of the TTL-high signal to the CE input. When in standby 127256 are in the “1” state. Data is introduced by mode, the outputs are in a high impedance state, selectively programming '‘0s" into the desired bit lo- independent of the OE input. cations. Although only “Os” will be programmed, both “1s” and “Os” can be present in the data word. The only way to change a “0” to a “1” is by ultravio- Output OR-Tieing let light erasure. Because EPROMs are usually used in larger memo- The M27256 is in the programming mode when the fy arrays, Intel has provided 2 control lines which pp input is at 12.5V ond GE is at TTL-Jow. The data accommodate this multiple memory connection. The 19 be programmed is applied 6 bits in parallel to the ‘two control lines allow for: data output pins. The levels required for the address a) the lowest possible memory power dissipation, and data inputs are TTL. and b) complete assurance that output bus contention complete ase inteligent Programming™ Algorithm , The M72756 inteligent Programming Algorithm rap- ana) these fied gent tines most en ciently, TE idly programs intel M27256 EPROMS using an offi- ae i fast Primary cient and reliable method particularly suited to the device selecting function, while OE (pin 22) should Fret eton programming environment. Typical pro- ee acc fo the READ ine rom tne sytem gramming tmes for individual device ar onthe o- ae iors “This aesures that all deselected memo, 8" of five minutes. Programming reliability is also devices are in their low standby mode and ‘ensured as the incremental program margin of each y " power byte is continually monitored to determine when it that the output pins are active only when data is 4 been successfully programmed. A flowchart of desired from a particular memory device. the M27256 inteligent Programming Algorithm is shown in Figure 3. System Considerations The intgligent Programming Algorithm utilizes two itchi ‘ «1.€ different pulse types: initial and overprogram. The Fee ae ee of tre devices, duration of the intial CE puise(s) is one milisecond, EPROMs require careful decoupling of the devices. which will then be followed by a longer overprogram The supply current, Icc, has three segments that are pulse of length SX meee. X is an oe aton Sounter Of interest to the ys om ene aa vayelant _andis equal to the number of the inal one-milisec- current peaks that are produced by the falling and ‘ond pulses applied to a particular M27256 location, risin in TT before a correct verify occurs. Up to 25 one-millisec- edges of Chip Enablo. The magnitude of these BSVOre & Correa vided tor before the over. transient current peaks is dependent on the output ulses per byte ave nt over capacitive and inductive loading of the de- — Program pulse is applied. 7-56
cle has been completed, all bytes should be com- __tifier Mode. pared to the original data with Voc = Vpp = 5.0V. different data is easily accomplished by using the (07) defined as the parity bit. " prevent unintentional erasure. grammed with its corresponding programming algo- —_for erasure should be a minimum of 15 Wsec/cm2. Table 2. M27256 Intgligent Identifler™ Bytes
- Ay~Ag, Aro-Arg, CE, OF = Vi,
Figure 3. M27256 inteligent Programming™ Flowchart
inteligent Programming™ Algorithm D.C. PROGRAMMING CHARACTERISTICS To = 25 58°C, Voc = 6.0V +0.25V, Vpp = 12.5V +0.3V form | teem eP| “S |__| input Gurentaninpuisy | Tt | v= Vor Vin | | Vu | imputtowLevel(atiinputsy | -o1 | op | v | | [vin | imputtightever | 20 | voc-1 | v [| | vor | Outputtow voltage During very | | os |v | i= 2tma | | Yon | Outputtiign Votage During venty | 24 [|v | tow = —400xA | [toca | VocSupply Curent (Program & very) | [00 | ma | | tee | VerSuppiy Curent Program || so | ma | CE= [vio | Aeinttoentcenitervotage | is | ws |v | | NOTE: 1. Voc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. A.C. PROGRAMMING CHARACTERISTICS To = 25 +5°C, Voc = 6.0V +0.25V, Vpp = 12.5V +0.3V [ore aaa sr | teem i [ ts | [ Address Setup Time | Setup Time Sa | toes | OESeupTime | | Ts TO | tos | Oatasetuptime | 2 || ws PO [wi | Address Hoistime ToT us | [ton | datatoistime |e TT ns | [tors |“ OvpuenabetoOuputFicstDewy | 0 | 10 | me |_| ves Veeseuptine [fs fd | wos | VooSewptime | 2] | Tos TO [tow | CE ntalProgamPucewan | 095 | 105 | ms | (ates) | | topw | CE OverprogramPuse wisn | a5 | 7075 | ms | (Note2) | [toc [daa vatsromoe Tso | me | “A.C, CONDITIONS OF TEST re rust be applied simultaneously or before Vpp and longer driven. 7-59
a Inteligent Programming™ WAVEFORMS PROGRAM VERIFY. Van > } va tas tan @ Lo) Vina . ‘om ‘orp i (0.13) ‘MAX. Ver Vpp ve ‘vps ec Le 6.0V “ ¥ in sev @ vin ze vie toe va 10.15) aE ‘oew wax, vi [285ms) 200061-8 NOTES: 1. All times shown in [] are minimum and in us unless otherwise specified. 2. The input timing reference level is 0.8V for a Vi, and 2V for a Vin. 3. tog and torp are characteristics of the device but must be ‘accommodated by the programmer. 4. When programming the M27256 a 0.1 4F capacitor is required across Vpp and ground to suppress spurious voltage transients which can damage the device, 7-60