T7600 INTEL | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1.1 Terminology
- 1.2 References
- 2 Low Power Features
- 2.1 Clock Control and Low Power States
- 2.1.1 Core Low Power State Descriptions
- 2.1.2 Package Low Power State Descriptions
- 2.2 Enhanced Intel SpeedStep® Technology
- 2.3 Extended Low Power States
- 2.4 FSB Low Power Enhancements
- 2.5 Processor Power Status Indicator (PSI#) Signal
- 3 Electrical Specifications
- 3.1 Power and Ground Pins
- 3.2 FSB Clock (BCLK[1:0]) and Processor Clocking
- 3.3 Voltage Identification
- 3.4 Catastrophic Thermal Protection
- 3.5 Reserved and Unused Pins
- 3.6 FSB Frequency Select Signals (BSEL[2:0])
- 3.7 FSB Signal Groups
- 3.8 CMOS Signals
- 3.9 Maximum Ratings
- 3.10 Processor DC Specifications
- 4 Package Mechanical Specific ations and Pin Information
- 4.1 Package Mechanical Specifications
- 4.2 Processor Pinout and Pin List
- 4.3 Alphabetical Signals Reference
- 5 Thermal Specifications and Design Considerations
- 5.1 Thermal Specifications
- 5.1.1 Thermal Diode
- 5.1.2 Thermal Diode Offset
- 5.1.3 Intel® Thermal Monitor
- 5.1.4 Digital Thermal Sensor
- 5.1.5 Out of Specification Detection
- 5.1.6 PROCHOT# Signal Pin
Document Number: 314078-004 Intel® Core™2 Duo Mobile Processor for Intel® Centrino® Duo Mobile Processor Technology Datasheet September 2007
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Legal Lines and Disclaimers INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information. The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Enhanced Intel SpeedStep® Technology for specified units of this processor available Q2/06. See the Processor Spec Finder at http://processorfinder.intel.com or contact your Intel representative for more information 64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled for Intel® 64 architecture. Processors will not operate (including 32-bit operation) without an Intel 64 architecture-enabled BIOS. Performance will vary depending on your hardware and software configurations. Consult with your system vendor for more information. Intel, Centrino, Pentium, Intel Core 2, Intel SpeedStep, MMX, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2006 - 2007, Intel Corporation. All rights reserved.
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4 Deeper Sleep V CC and ICC Loadline for Dual-core Low Voltage and
8 Voltage and Current Specifications for Single and Dual-core Ultra Low Voltage Processors ..32
12 The Coordinates of the Processor Pins as Viewed from the Top of the Package
13 The Coordinates of the Processor Pins as Viewed from the Top of the Package
Revision History
§ § Revision Number Description Revision Date -001 Initial release August 2006 -002
- Added Information for L7400 an d L7200 Low-Voltage Processors
- Updated Table 08 in Chapter 3
- Updated Table 17 in Chapter 5 December 2006 -003 • Added L-2 die package information May 2007 -004
- Added Information for U2200 and U2 100 Ultra Low-Voltage Processors
- Updated Electrical Specifications in Chapter 3 for ULV Processors
- Updated Thermal Specifications in Chapter 5 for ULV Processors
- Added A-1 die package information September 2007
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1 Introduction
The Intel® Core™2 Duo mobile processor for Intel® Centrino® Duo mobile technology based on the Intel® 945 Express Chipset family is built on 65-nanometer process technology and is the next generation high-performance, low-power mobile processor based on the Intel® Core™ architecture. Note: All references to the word “processor” in this document are references to the Intel Core
2 Duo mobile processor with 533- and 667-MHz front side bus (FSB), unless specified
otherwise. The following list provides some of the key features on this processor:
- Dual-core processor for mobile with enhanced performance
- Intel® 64 architecture
- Supports Intel Architecture with Dynamic Execution
- On-die, primary 32-kB instruction cache and 32-kB write-back data cache per core
- On-die, up to 4-MB second level shared cache with Advanced Transfer Cache Architecture
- Data Prefetch Logic
- Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3) and Supplemental Streaming SIMD Extensions 3 (SSSE3)
- 667-MHz, Source-Synchronous FSB for Standard Voltage processors
- Advanced Power Management features including Enhanced Intel SpeedStep® Technology
- Intel® Enhanced Deeper Sleep state and Dynamic Cache Sizing
- Digital Thermal Sensor
- Micro-FCPGA and Micro-FCBGA packaging technologies
- Intel® Virtualization Technology
- Execute Disable Bit support for enhanced security Note: 64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled for Intel 64 architecture. Processors will not operate (including 32-bit operation) without an Intel 64 architecture-enabled BIOS. Performance will vary depending on your hardware and software configurations. Consult with your system vendor for more information. The Intel Core 2 Duo mobile processor will be manufactured on Intel’s 65-nanometer process technology. The processor maintains support for MMX TM technology, Streaming SIMD instructions, and full compatibility with IA-32 software. In addition, the Intel Core
2 Duo mobile processor supports Intel 64 architecture which is enabled by 64-bit
operating systems and consists of 64-bit instructions and registers. Further details on Intel Extended Memory 64 Technology and its programming model can be found in the Intel Extended Memory 64 Technology Software Developer’s Guide. The Intel Core 2 Duo mobile processor features on-die, 32-kB level 1 instruction and data caches and features up to a 4-MB level 2 cache with Advanced Transfer Cache Architecture. The processor’s Data Prefetch Logic speculatively fetches data to the L2 cache before the L1 cache requests occurs, resulting in reduced bus cycle penalties. The processor includes the Data Cache Unit Streamer which enhances the performance of the L2 prefetcher by requesting L1 warm-ups earlier. In addition, the Write Order Buffer depth is enhanced to help with the write-back latency performance.
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In addition to supporting the existing Streaming SIMD Extensions 2 (SSE2) and Streaming SIMD Extensions 3 (SSE3), the processor supports Supplemental Streaming SIMD Extensions 3 (SSSE3) to speed up media algorithms like encoding and decoding. Advanced Dynamic Execution improves speculative execution and branch prediction internal to the processor. The floating point and multi-media units include 128-bit wide registers and a separate register for data movement. Streaming SIMD3 (SSE3) instructions provide highly efficient double-precision floating point, SIMD integer, and memory management operations. Also, these instructions enhance the performance of optimized applications for the digital home such as video, image processing and media compression technology. The processor features Enhanced Intel SpeedStep Technology, which enables real-time dynamic switching between multiple voltage and frequency points. The processor features the Auto Halt, Stop Grant, Deep Sleep, and Intel Enhanced Deeper Sleep C- states. Enhanced thermal management capabilities are implemented including Intel® Thermal Monitor 1 and Intel Thermal Monitor 2 to provide efficient and effective cooling in high temperatures. The Intel Core 2 Duo mobile processor utilizes socketable Micro Flip-Chip Pin Grid Array (Micro-FCPGA) and surface mount Micro Flip-Chip Ball Grid Array (Micro-FCBGA) package technology. The Micro-FCPGA package plugs into a 479-hole, surface-mount, Zero Insertion Force (ZIF) socket, which is referred to as the mPGA479M socket. Intel Core 2 Duo mobile processor supports the Execute Disable Bit capability. This feature combined with a supporting operating system allows memory to be marked as executable or non executable. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system. See the Intel® 64 and IA-32 Intel® Architectures Software Developer's Manual for more detailed information. Intel Virtualization Technology is a set of hardware enhancements to Intel server and client systems that combined with the appropriate software, will enable enhanced virtualization robustness and performance for both enterprise and consumer uses. Intel Virtualization Technology forms the foundation of Intel technologies focused on improved virtualization, safer computing, and system stability. For client systems, Intel Virtualization Technology’s hardware-based isolation helps provide the foundation for highly available and more secure client virtualization partitions.
1.1 Terminology
A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the “#” symbol implies that the signal is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and XXXX means that the specification or value is yet to be determined. AGTL+ Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+ signaling technology on some Intel processors. Front Side Bus (FSB) Refers to the interface between the processor and system core logic (also known as the chipset components). Intel® Virtualization Technology Processor virtualization which when used in conjunction with Virtual Machine Monitor software enables multiple, robust independent software environments inside a single platform. Processor Core Processor core die with integrated L1 and L2 cache. All AC timing and signal integrity specifications are at the pads of the processor core. Storage Conditions Refers to a non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor lands should not be connected to any supply voltages, have any I/Os biased or receive any clocks. Upon exposure to “free air” (i.e., unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material. VCC The processor core power supply VSS The processor ground reference
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1.2 References
Material and concepts available in the following documents may be beneficial when reading this document. Also note that with Intel Centrino Duo technology, the Intel Core 2 Duo mobile processor supports Mobile Intel® 945GM/GT/GMS/PM and 940GML Express Chipset family and Intel® 82801GBM (also known as ICH7M). § § Document Document Number Intel® Core™2 Duo Processor for Intel® Centrino® Duo Technology Specification Update 314079 Mobile Intel® 945 Express Chipset Family Chipset Datasheet 309219 Mobile Intel® 945 Express Chipset Family Chipset Specification Update 309220 Intel® I/O Controller Hub 7 (ICH7) Family Datasheet 307013 Intel® I/O Controller Hub 7 (ICH7) Family Specification Update 307014 Intel® 64 and IA-32 Intel® Architectures Software Developer's Manual Volume 1: Basic Architecture 253665 Volume 2A: Instruction Set Reference, A-M 253666 Volume 2B: Instruction Set Reference, N-Z 253667 Volume 3A: System Programming Guide 253668 Volume 3B: System Programming Guide 253669 Intel® 64 and IA-32 Architectures Software Developer's Manual Documentation Changes 252046 AP-485 Intel® Processor Identification and the CPUID Instruction 241618
2 Low Power Features
2.1 Clock Control and Low Power States
The Intel Core 2 Duo mobile processor supports low power states both at the individual core level and the package level for optimal power management. A core may independently enter the C1/AutoHALT, C1/MWAIT, C2, C3, and C4 low power states. Refer to Figure 1 for a visual representation of the core low power states for the processor. When both cores coincide in a common core low power state, the central power management logic ensures the entire Intel Core 2 Duo mobile processor enters the respective package low power state by initiating a P_LVLx (P_LVL2, P_LVL3, and P_LVL4) I/O read to the Intel 945GM/GT/GMS/PM and 940GML Express Chipset family. Package low power states include Normal, Stop Grant, Stop Grant Snoop, Sleep, Deep Sleep, and Deeper Sleep. Refer to Figure 2 for a visual representation of the package low power states for the Intel Core 2 Duo mobile processor and to Table 1 for a mapping of core low power states to package low power states. The Intel Core 2 Duo mobile processor implements two software interfaces for requesting low power states: MWAIT instruction extensions with sub-state hints and P_LVLx reads to the ACPI P_BLK register block mapped in the processor’s I/O address space. The P_LVLx I/O reads are converted to equivalent MWAIT C-state requests inside the processor and do not directly result in I/O reads on the processor FSB. The monitor address does not need to be setup before using the P_LVLx I/O read interface. The sub-state hints used for each P_LVLx read can be configured through a software programmable Model Specific Register (MSR). If a core encounters a chipset break event while STPCLK# is asserted, then it asserts the PBE# output signal. Assertion of PBE# when STPCLK# is asserted indicates to system logic that individual cores should return to the C0 state and the Intel Core 2 Duo mobile processor should return to the Normal state.
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Figure 1. Core Low Power States † — STPCLK# assertion and de-assertion have no effect if a core is in C2, C3, or C4. ‡ — Core C4 state includes the Intel Enhanced Deeper Sleep state.
2.1.1 Core Low Power State Descriptions
2.1.1.1 Core C0 State
This is the normal operating state for cores in the processor.
2.1.1.2 Core C1/AutoHALT Powerdown State
C1/AutoHALT is a low power state entered when a core executes the HALT instruction. immediately initialize itself. will return execution to the HALT state. Figure 2. Package Low Power States Table 1. Coordination of Core Low Power States at the Package Level † — Deeper Sleep includes the Deeper Sleep state and Intel Enhanced Deeper Sleep state.
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While in AutoHALT Powerdown state, the Intel Core 2 Duo mobile processor will process bus snoops and snoops from the other core. The processor core will enter a snoopable sub-state (not shown in Figure 1) to process the snoop and then return to the AutoHALT Powerdown state.
2.1.1.3 Core C1/MWAIT Powerdown State
C1/MWAIT is a low power state entered when the processor core executes the MWAIT(C1) instruction. Processor behavior in the MWAIT state is identical to the AutoHALT state except that Monitor events can cause the processor core to return to the C0 state. See the Intel® 64 and IA-32 Intel® Architectures Software Developer's Manual, Volume 2A/2B: Instruction Set Reference for more information.
2.1.1.4 Core C2 State
Individual cores of the Intel Core 2 Duo mobile processor can enter the C2 state by initiating a P_LVL2 I/O read to the P_BLK or an MWAIT(C2) instruction, but the processor will not issue a Stop-Grant Acknowledge special bus cycle unless the STPCLK# pin is also asserted. While in the C2 state, the Intel Core 2 Duo mobile processor will process bus snoops and snoops from the other core. The processor core will enter a snoopable sub-state (not shown in Figure 1) to process the snoop and then return to the C2 state.
2.1.1.5 Core C3 State
Individual cores of the Intel Core 2 Duo mobile processor can enter the C3 state by initiating a P_LVL3 I/O read to the P_BLK or an MWAIT(C3) instruction. Before entering C3, the processor core flushes the contents of its L1 caches into the processor’s L2 cache. Except for the caches, the processor core maintains all its architectural state in the C3 state. The Monitor remains armed if it is configured. All of the clocks in the processor core are stopped in the C3 state. Because the core’s caches are flushed the processor keeps the core in the C3 state when the processor detects a snoop on the FSB or when the other core of the Intel Core 2 Duo mobile processor accesses cacheable memory. The processor core will transition to the C0 state upon occurrence of a Monitor event, SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# will cause the processor core to immediately initialize itself.
2.1.1.6 Core C4 State
Individual cores of the Intel Core 2 Duo mobile processor can enter the C4 state by initiating a P_LVL4 I/O read to the P_BLK or an MWAIT(C4) instruction. The processor core behavior in the C4 state is nearly identical to the behavior in the C3 state. The only difference is that if both processor cores are in C4, then the central power management logic will request that the entire Intel Core 2 Duo mobile processor enter the Deeper Sleep package low power state (see Section 2.1.2.6). To enable the package level Intel® Enhanced Deeper Sleep state, Dynamic Cache Sizing and Intel Enhanced Deeper Sleep state fields must be configured in the software programmable MSR to enable the Intel Enhanced Deeper Sleep state.
2.1.2 Package Low Power State Descriptions
2.1.2.1 Normal State
This is the normal operating state for the processor. The Intel Core 2 Duo mobile processor remains in the Normal state when at least one of its cores is in the C0, C1/ AutoHALT, or C1/MWAIT state.
2.1.2.2 Stop-Grant State
When the STPCLK# pin is asserted, each core of the Intel Core 2 Duo mobile processor enters the Stop-Grant state within 20 bus clocks after the response phase of the processor-issued Stop-Grant Acknowledge special bus cycle. Processor cores that are already in the C2, C3, or C4 state remain in their current low power state. When the STPCLK# pin is deasserted, each core returns to its previous core low power state. Note: Since the AGTL+ signal pins receive power from the FSB, these pins should not be driven (allowing the level to return to V CCP) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the FSB should be driven to the inactive state. RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. When RESET# is asserted by the system, the STPCLK#, SLP#, DPSLP#, and DPRSTP# pins must be deasserted more than 480 µs prior to RESET# deassertion (AC Specification T45). When re-entering the Stop-Grant state from the Sleep state, STPCLK# should be deasserted ten or more bus clocks after the deassertion of SLP# (AC Specification T75). While in Stop-Grant state, the processor will service snoops and latch interrupts delivered on the FSB. The processor will latch SMI#, INIT# and LINT[1:0] interrupts and will service only one of each upon return to the Normal state. The PBE# signal may be driven when the processor is in Stop-Grant state. PBE# will be asserted if there is any pending interrupt or monitor event latched within the processor. Pending interrupts that are blocked by the EFLAGS.IF bit being clear will still cause assertion of PBE#. Assertion of PBE# indicates to system logic that the entire processor should return to the Normal state. A transition to the Stop-Grant Snoop state will occur when the processor detects a snoop on the FSB (see Section 2.1.2.3). A transition to the Sleep state (see Section 2.1.2.4) will occur with the assertion of the SLP# signal.
2.1.2.3 Stop-Grant Snoop State
The processor will respond to snoop or interrupt transactions on the FSB while in Stop- Grant state by entering the Stop-Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the FSB) or the interrupt has been latched. The processor will return to the Stop-Grant state once the snoop has been serviced or the interrupt has been latched.
2.1.2.4 Sleep State
The Sleep state is a low power state in which the processor maintains its context, maintains the phase-locked loop (PLL), and stops all internal clocks. The Sleep state is entered through assertion of the SLP# signal while in the Stop-Grant state. The SLP# pin should only be asserted when the processor is in the Stop-Grant state. SLP# assertions while the processor is not in the Stop-Grant state is out of specification and may result in unapproved operation.
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Note: In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals (with the exception of SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep state. Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will cause unpredictable behavior. Any transition on an input signal before the processor has returned to the Stop-Grant state will result in unpredictable behavior. If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor will reset itself, ignoring the transition through Stop-Grant state. If RESET# is driven active while the processor is in the Sleep state, the SLP# and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the processor correctly executes the Reset sequence. While in the Sleep state, the processor is capable of entering an even lower power the processor is in the Sleep state, the SLP# pin must be deasserted if another asynchronous FSB event needs to occur.
2.1.2.5 Deep Sleep State
The Deep Sleep state is entered through assertion of the DPSLP# pin while in the Sleep state. BCLK may be stopped during the Deep Sleep state for additional platform level power savings. BCLK stop/restart timings on Intel 945GM/GT/GMS/PM and 940GML Express Chipset family based platforms with the CK410M clock chip are as follows:
- Deep Sleep entry: the system clock chip may stop/tristate BCLK within 2 BCLKs of DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep.
- Deep Sleep exit: the system clock chip mu st drive BCLK to differential DC levels within 2-3 ns of DPSLP# deassertion and start toggling BCLK within 10 BCLK periods. To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be re- started after DPSLP# deassertion as described above. A period of 15 microseconds (to allow for PLL stabilization) must occur before the processor can be considered to be in the Sleep state. Once in the Sleep state, the SLP# pin must be deasserted to re-enter the Stop-Grant state. While in Deep Sleep state, the processor is incapable of responding tosnoop transactions or latching interrupt signals. No transitions of signals are allowed on the FSB while the processor is in Deep Sleep state. When the processor is in Deep Sleep state, it will not respond to interrupts or snoop transactions. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behavior.
2.1.2.6 Deeper Sleep State
The Deeper Sleep state is similar to the Deep Sleep state but reduces core voltage to one of two lower levels. One lower core voltage level is achieved by entering the base Deeper Sleep state. The Deeper Sleep state is entered through assertion of the DPRSTP# pin while in the Deep Sleep state. The other lower core voltage level, the lowest possible in the processor, is achieved by entering the Intel Enhanced Deeper Sleep state of Deeper Sleep state. The Intel Enhanced Deeper Sleep state is entered through assertion of the DPRSTP# pin while in the Deep Sleep only when the L2 cache further details on reducing the L2 cache and entering Intel Enhanced Deeper Sleep state. In response to entering Deeper Sleep, the Intel Core 2 Duo mobile processor will drive the VID code corresponding to the Deeper Sleep core voltage on the VID[6:0] pins.
Exit from the Deeper Sleep state or Intel Enhanced Deeper Sleep state is initiated by DPRSTP# deassertion when either core requests a core state other than C4 or either core requests a processor performance state other than the lowest operating point.
2.1.2.6.1 Intel Enhanced Deeper Sleep State
Intel Enhanced Deeper Sleep state is a sub-state of Deeper Sleep that extends power saving capabilities by allowing the processor to further reduce core voltage once the L2 cache has been reduced to zero ways and completely shut down. The following events occur when the processor enters Intel Enhanced Deeper Sleep state:
- The last core entering C4 issues a P_LVL4 I/O Read or an MWAIT(C4).
- The processor triggers a special chipset sequence to notify the chipset to redirect all FSB traffic, except APIC messages, to memory. The snoops are replied as misses by the chipset and are directed to main memory instead of the L2 cache.
- The processor will drive the VID code corresponding to the Intel Enhanced Deeper Sleep state core voltage on the VID[6:0] pins.
2.1.2.6.2 Dynamic Cache Sizing
Dynamic Cache Sizing allows the processor to flush and disable a programmable number of L2 cache ways upon each Deeper Sleep entry under the following conditions:
- The second core is already in C4 and core sub-state Intel Enhanced Deeper Sleep
- The C0 timer, which tracks continuous residency in the Normal package state, has not expired. This timer is cleared during the first entry into Deeper Sleep to allow consecutive Deeper Sleep entries to shrink the L2 cache as needed.
- The FSB speed to processor core speed ratio is below the predefined L2 shrink threshold. If the FSB speed to processor core speed ratio is above the predefined L2 shrink threshold, then L2 cache expansion will be requested. If the ratio is zero, then the ratio will not be taken into account for Dynamic Cache Sizing decisions. Upon STPCLK# deassertion, the first core exiting the Intel Enhanced Deeper Sleep state will expand the L2 cache to 2 ways and invalidate previously disabled cache ways. If the L2 cache reduction conditions stated above still exist when the last core returns to C4 and the package enters Intel Enhanced Deeper Sleep state, then the L2 will be shrunk to zero again. If a core requests a processor performance state resulting in a higher ratio than the predefined L2 shrink threshold, the C0 timer expires, or the second core (not the one currently entering the interrupt routine) requests the C1, C2, or C3 states, then the whole L2 will be expanded when the next INTR event would occur. L2 cache shrink prevention may be enabled as needed on occasion through an MWAIT(C4) sub-state field. If shrink prevention is enabled, then the Intel Core 2 Duo mobile processor does not enter the Intel Enhanced Deeper Sleep state since the L2 cache remains valid and in full size.
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2.2 Enhanced Intel SpeedStep® Technology
The Intel Core 2 Duo mobile processor features Enhanced Intel SpeedStep Technology. Following are the key features of Enhanced Intel SpeedStep Technology:
- Multiple voltage and frequency operating points provide optimal performance at the lowest power.
- Voltage and frequency selection is software controlled by writing to processor MSRs: — . If the target frequency is higher than the current frequency, Vcc is ramped up in steps by placing new values on the VID pins and the PLL then locks to the new frequency. — If the target frequency is lower than th e current frequency, the PLL locks to the new frequency and the VCC is changed through the VID pin mechanism. — Software transitions are accepted at any time. If a previous transition is in progress, the new transition is deferred until the previous transition completes.
- The processor controls voltage ramp rates internally to ensure glitch free transitions.
- Low transition latency and large number of transitions possible per second: — Processor core (including L2 cache) is unavailable for up to 10 μs during the frequency transition. — The bus protocol (BNR# mechanism) is used to block snooping.
- Improved Intel Thermal Monitor mode: — When the on-die thermal sensor indicates that the die temperature is too high, the processor can automatically perform a transition to a lower frequency and voltage specified in a software programmable MSR. — The processor waits for a fixed time period. If the die temperature is down to acceptable levels, an up transition to the previous frequency and voltage point occurs. — An interrupt is generated for the up and down Intel Thermal Monitor transitions enabling better system level thermal management.
- Enhanced thermal management features. — Digital Thermal Sensor and Out of Specification detection. — Intel Thermal Monitor 1 in addition to Intel Thermal Monitor 2 in case of unsuccessful Intel Thermal Monitor 2 transition. — Dual-core thermal management synchronization. Each core in the processor implements an independent MSR for controlling Enhanced Intel SpeedStep Technology, but both cores must operate at the same frequency and voltage. The processor has performance state coordination logic to resolve frequency and voltage requests from the two cores into a single frequency and voltage request for the package as a whole. If both cores request the same frequency and voltage, then the processor will transition to the requested common frequency and voltage. If the two cores have different frequency and voltage requests, then the processor will take the highest of the two frequencies and voltages as the resolved request and transition to that frequency and voltage.
2.3 Extended Low Power States
Extended low power states (C1E, C2E, C3E, C4E) optimize for power by forcibly reducing the performance state of the processor when it enters a package low power state. Instead of directly transitioning into the package low power state, the extended low power state first reduces the performance state of the processor by performing an Enhanced Intel SpeedStep Technology transition down to the lowest operating point. Upon receiving a break event from the package low power state, control will be returned to software while an Enhanced Intel SpeedStep Technology transition up to the initial operating point occurs. The advantage of this feature is that it significantly reduces leakage while in the package low power states. Note: Long-term reliability may not be assured if Extended Low Power States are not enabled. The processor implements two software interfaces for requesting extended package low power states: MWAIT instruction extensions with sub-state hints and via BIOS by configuring a software programmable MSR to automatically promote package low power states to extended package low power states. Note: Extended Stop-Grant and Extended Deeper Sleep must be enabled via the BIOS for the processor to remain within specification. Enhanced Intel SpeedStep Technology transitions are multistep processes that require clocked control. These transitions cannot occur when the processor is in the Sleep or Deep Sleep package low power states since processor clocks are not active in these states. Extended Deeper Sleep is an exception to this rule when the Hard C4E configuration is enabled through a software programmable MSR. This Extended Deeper Sleep state configuration will lower the core voltage to the Deeper Sleep level while in Deeper Sleep and, upon exit, will automatically transition to the lowest operating voltage and frequency to reduce snoop service latency. The transition to the lowest operating point or back to the original software requested point may not be instantaneous. Furthermore, upon very frequent transitions between active and idle states, the transitions may lag behind the idle state entry resulting in the processor either executing for a longer time at the lowest operating point or running idle at a high operating point. Observations and analyses show this behavior should not significantly impact total power savings or performance score while providing power benefits in most other cases.
2.4 FSB Low Power Enhancements
The processor incorporates FSB low power enhancements:
- Dynamic FSB Power Down
- BPRI# control for address and control input buffers
- Dynamic Bus Parking
- Dynamic On-die Termination disabling
- L o w V CCP (I/O termination voltage)
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The processor incorporates the DPWR# signal that controls the data bus input buffers on the processor. The DPWR# signal disables the buffers when not used and activates them only when data bus activity occurs, resulting in significant power savings with no performance impact. BPRI# control also allows the processor address and control input buffers to be turned off when the BPRI# signal is inactive. Dynamic Bus Parking allows a reciprocal power reduction in chipset address and control input buffers when the processor deasserts its BR0# pin. The On-die Termination on the processor FSB buffers is disabled when the signals are driven low, resulting in additional power savings. The low I/O termination voltage is on a dedicated voltage plane independent of the core voltage, enabling low I/O switching power at all times.
2.5 Processor Power Status Indicator (PSI#) Signal
The processor incorporates the PSI# signal that is asserted when the processor is in a reduced power consumption state. PSI# can be used to improve intermediate and light load efficiency of the voltage regulator, resulting in platform power savings and extended battery life. The algorithm that the processor uses for determining when to assert PSI# is different from the algorithm used in previous Intel® Pentium® M processors. For Intel Core 2 processor with Intel Centrino Duo mobile technology, PSI# signal functionality is supported only in idle state. § §
3 Electrical Specifications
3.1 Power and Ground Pins
For clean, on-chip power distribution, the processor will have a large number of VCC (power) and VSS (ground) inputs. All power pins must be connected to VCC power planes while all VSS pins must be connected to system ground planes. Use of multiple power and ground planes is recommended to reduce I*R drop. Please contact your Intel representative for more details. The processor V CC pins must be supplied the voltage determined by the VID (Voltage ID) pins.
3.2 FSB Clock (BCLK[1:0] ) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the core frequency is a multiple of the BCLK[1:0] frequency. The processor uses a differential clocking implementation.
3.3 Voltage Identification
The processor uses seven voltage identification pins, VID[6:0], to support automatic selection of power supply voltages. The VID pins for processor are CMOS outputs driven by the processor VID circuitry. Table 2 specifies the voltage level corresponding to the state of VID[6:0]. A 1 in this refers to a high-voltage level and a 0 refers to low- voltage level.
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Table 2. Voltage Identification Definition (Sheet 1 of 4)
Table 2. Voltage Identification Definition (Sheet 2 of 4)
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Table 2. Voltage Identification Definition (Sheet 3 of 4)
3.4 Catastrophic Thermal Protection
PWRGOOD signal is not asserted.
3.5 Reserved and Unused Pins
and the location of all RSVD pins. Table 2. Voltage Identification Definition (Sheet 4 of 4)
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GND via and is accessible through an oscilloscope connection.
3.6 FSB Frequency Select Signals (BSEL[2:0])
for BCLK[1:0] is shown in Table 3.
3.7 FSB Signal Groups
Table 3. BSEL[2:0] Encodi ng for BCLK Frequency
- Refer to Chapter 4, “Package Mechanical Specifications and Pin Information” for signal descriptions and
- In processor systems without a debu g port implemented on the board, these signals are used to support
- BPM[2:1]# and PRDY# are AG TL+ output only signals.
- PROCHOT# signal type is open drain output and CMOS input.
- On-die termination differs from other AGTL+ signals, please contact your Intel representative for more
- When paired with a chipset limited to 32-bit addressing, A[35:32] should remain unconnected.
Table 4. FSB Pin Groups
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3.8 CMOS Signals
3.9 Maximum Ratings
limits, functionality and long-term reliability can be expected.
- For functional operation, all processor electrical, signal quality, mechanical and thermal
specifications must be satisfied.
- Storage temperature is applicable to stor age conditions only. In this scenario, the
functional operation, please refer to the processor case temperature specifications.
- This rating applies to the processor and does not include any tray or packaging.
- Failure to adhere to this specification can a ffect the long term reliability of the processor.
Table 5. Processor Absolute Maximum Ratings
3.10 Processor DC Specifications
core (pads) unless noted otherwise. listed in Table 9. DC specifications for the CMOS group are listed in Table 10. Table 6. Voltage and Current Sp ecifications for Dual-core Standard Voltage Processors
2.33 GHz and HFM V
2.17 GHz and HFM VCC
2.00 GHz and HFM VCC
1.83 GHz and HFM VCC
1.67 GHz and HFM VCC
1.00 GHz and LFM VCC
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- Each processor is programmed with a maximum valid vo ltage identification value (VID), which is set at
Monitor 2, Enhanced Intel SpeedStep Technology, or Extended Halt State).
- The voltage specifications are assumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with
a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance. the system is not coupled in the scope probe.
- Specified at the VID voltage.
processor for Intel Centrino Duo mobile technology.
- Base on simulations and averaged over the durati on of any change in current. Specified by design/
characterization at nominal VCC. Not 100% tested.
- Measured at the bulk capacitors on the motherboard.
- Specified at nominal V CC.
- This is a steady-state I CC current specification, which is applicable when both VCCP and VCC_CORE are high.
- This is a power-up peak current spec ification, which is applicable when VCCP is high and VCC_CORE is low.
- If a given Operating System C-State model is not base d on the use of MWAIT or I/O Redirection, the Intel
Core 2 Duo mobile processor Deeper Sleep VID will be same as LFM VID.
- T7600, T7400, T7200 processors feature 4-MB cache.
- T5600, T5500 processors feature 2-MB cache.
Table 6. Voltage and Current Specifications for Dual-core Standard Voltage Processors
- Each processor is programmed with a maximum valid voltage identification value (VID), which is set at
Monitor 2, Enhanced Intel SpeedStep Technology, or Extended Halt State).
- The voltage specifications are as sumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with
a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance. the system is not coupled in the scope probe. Table 7. Voltage and Current Specificatio ns for Dual-core Low Voltage Processors
1.50 GHz and HFM VCC
1.33 GHz and HFM VCC
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- Specified at the VID voltage.
- The I CCDES(max) specification of 23 A comprehends only Intel Core 2 Duo mobile processor HFM
frequencies with Intel Centrino Duo mobile technology.
- Based on simulations and averaged over the durati on of any change in current. Specified by design/
characterization at nominal VCC. Not 100% tested.
- Measured at the bulk capacitors on the motherboard.
- V CC,BOOT tolerance shown in Figure 3.
- Specified at nominal V CC.
- This is a steady-state Icc current specification, which is applicable when both V CCP and VCC_CORE are high.
- This is a power-up peak current spec ification, which is applicable when VCCP is high and VCC_CORE is low.
- If a given Operating System C-State model is not base d on the use of MWAIT or I/O Redirection, the Intel
Table 8. Voltage and Current Specifications for Single and Dual-core Ultra Low Voltage
1.20 GHz and HFM V
1.06 GHz and HFM VCC
1.20 GHz and HFM VCC
0.80 GHz and LFM VCC
- Each processor is programmed with a maximum valid voltage identification value (VID), which is set at
Monitor 2, Enhanced Intel SpeedStep Technology, or Extended Halt State).
- The voltage specifications are as sumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with
a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance. the system is not coupled in the scope probe.
- Specified at the VID voltage.
frequencies on Intel Centrino Duo mobile technology.
- Based on simulations and averaged over the durati on of any change in current. Specified by design/
characterization at nominal VCC. Not 100% tested.
- Measured at the bulk capa citors on the motherboard.
- V CC,BOOT tolerance shown in Figure 3.
- Specified at nominal V CC.
- This is a steady-state Icc current specification, which is applicable when both VCCP and VCC_CORE are high.
- This is a power-up peak current spec ification, which is applicable when VCCP is high and VCC_CORE is low.
- If a given Operating System C-Stat e model is not based on the use of MWAIT or I/O Redirection, the Intel
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Figure 3. Deeper Sleep V CC and ICC Loadline for Dual-core Standard Voltage Processors Differential Remote Sense required.
- Unless otherwise noted, all specifications in this table apply to all processor frequencies.
- Crossing Voltage is de fined as absolute voltage where rising edge of BCLK0 is equal to the
- Threshold Region is defined as a region entered about the crossing voltage in which the
differential receiver switches. It includes input threshold hysteresis.
- For Vin (Input Voltage) between 0 V and V H.
- Cpad includes die capaci tance only. No package parasitics are included.
- ΔVCROSS is defined as the total variation of all crossing voltages as defined in note 2.
Figure 4. Deeper Sleep V CC and ICC Loadline for Dual-core Low Voltage and Differential Remote Sense required.
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Figure 5. Active V CC and ICC Loadline for Intel Core 2 Solo Processor, Ultra Low Voltage Differential Remote Sense required.
- Unless otherwise noted, all specifications in this table apply to all processor frequencies.
- V IL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low
- V IH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
- V IH and VOH may experience excursions above VCCP. However, input signal drivers must comply with the
signal quality specifications.
- GTLREF should be generated from V CCP with a 1% tolerance resistor divider. The VCCP referred to in these
specifications is the instantaneous VCCP.
- R TT is the on-die termination resistance measured at VOL of the AGTL+ output driver. Measured at
0.31*VCCP. RTT is connected to VCCP on-die.
- Specified with on-die R TT and RON are turned off. Vin (Input Voltage) between 0 and VCCP.
- Cpad includes die capacitance only. No package parasitics are included.
- This is the external resistor on the comp pins.
- On-die termination resistance, measured at 0.33*V CCP.
Table 9. AGTL+ Signal Group DC Specifications
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- Unless otherwise noted, all specifications in this table apply to all processor frequencies.
CCP referred to in these specifications refers to instantaneous VCCP.
- For Vin (Input Voltage) between 0 V and V CCP. Measured when the driver is tristated.
- Cpad1 includes die capa citance only for DPRSTP#, DPSLP#, PWRGOOD. No package parasitics are
- Cpad2 includes die capaci tance for all other CMOS input signals. No package parasitics are included.
- Unless otherwise noted, all specifications in this table apply to all processor frequencies.
OH is determined by value of the external pull-up resistor to VCCP.
- For Vin (Input Voltage) between 0 V and V OH.
- Cpad includes die capacitance only. No package parasitics are included.
Table 10. CMOS Signal Group DC Specifications Table 11. Open Drain Signal Group DC Specifications
Package Mechanical Specifications and Pin Information
4 Package Mechanical
4.1 Package Mechanical Specifications
The processor will be available in 4-MB and 2-MB L2 cache versions for 478-pin micro- FCPGA and 4-MB, 2-MB and 1-MB L2 Cache 479-ball micro-FCBGA packages. The package mechanical dimensions are shown in Figure 6 through Figure 14. Table 12 shows a top-view of package pinout. The micro-FCBGA package incorporates land-side capacitors. The land-side capacitors are electrically conductive so care should be taken to avoid contacting the capacitors with other electrically conductive materials on the motherboard. Doing so may short the capacitors and possibly damage the device or render it inactive.
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Figure 6. 4-MB and 2-MB Fused Micr o-FCPGA Processor Package Drawing
Figure 7. 4-MB and 2-MB Fused Micr o-FCPGA Processor Package Drawing
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Figure 8. 2-MB Micro-FCPGA Processor Package Drawing
478 Pins
0.65 MAX
0.37 MAX
31.75 BASICG2
31.75 BASICG1
15.875 BASICH2
15.875 BASICH1
1.27 BASICJ2
1.27 BASICJ1
Figure 9. 2-MB Micro-FCPGA Processor Package Drawing
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Figure 10. 4-MB and 2-MB Fused Micr o-FCBGA Processor Package Drawing
Figure 11. 4-MB and 2-MB Fused Micr o-FCBGA Processor Package Drawing
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Figure 12. 2-MB Micro-FCBGA Processor Package Drawing
Figure 13. 1-MB Micro-FCBGA Proc essor Package Drawing (2 of 2)
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Figure 14. 1-MB Micro-FCBGA Proc essor Package Drawing (2 of 2)
Package Mechanical Specifications and Pin Information
4.2 Processor Pinout and Pin List
Table 12 shows the top view pinout of the processor. The pin list, arranged in two different formats, is shown in the following pages.
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Table 12. The Coordinates of the Processor Pi ns as Viewed from the Top of the Package
Table 13. The Coordinates of the Processor Pi ns as Viewed from the Top of the Package
Package Mechanical Specifications and Pin Information
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Table 14. Pin Listin g by Pin Name Table 14. Pin Listing by Pin Name
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Table 15. Pin Listin g by Pin Number Table 15. Pin Listing by Pin Number
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4.3 Alphabetical Signals Reference
Table 16. Signal Description (Sheet 1 of 8) are sampled before RESET# is deasserted. A[35:32] should remain unconnected. Output Write bus transaction. reply ID match operations associated with the new transaction. outputs and latch their inputs. stall, the current bus owner cannot issue any new transactions.
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includes debug or performance monitoring tools. the FSB. It must connect the appropriate pins of both FSB agents. releases the bus by deasserting BPRI#. precision (1% tolerance) resistors. indicate a valid data transfer. group is inverted and therefore sampled active high. Table 16. Signal Descript ion (Sheet 2 of 8)
connect in the system. DBR# is not a processor signal. connect the appropriate pins on both FSB agents. signals are activated when the data on the data bus is inverted. deasserted. DPRSTP# is driven by the ICH7M chipset. driven by the ICH7M chipset. processor data bus input buffers. clock data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of both FSB agents. Table 16. Signal Description (Sheet 3 of 8)
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Data strobe used to latch in D[63:0]#. Data strobe used to latch in D[63:0]#. multiplexed signal and its meaning is qualified with STPCLK#. point when the processor detects an unmasked floating-point error. break event, it will remain asserted until STPCLK# is deasserted. GTLREF determines the signal reference level for AGTL+ input pins. receivers to determine if a signal is a logical 0 or logical 1. can be continued by reasserting HIT# and HITM# together. Table 16. Signal Descript ion (Sheet 4 of 8)
assertion of RESET#, BINIT#, or INIT#. no effect when the NE bit in control register 0 (CR0) is set. Output Write bus transaction. power-on Reset vector configured during power-on configuration. connect the appropriate pins of both FSB agents. Pentium processor. Both signals are asynchronous. Table 16. Signal Description (Sheet 5 of 8)
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processor has reached its maximum safe operating temperature. active until the system deasserts PROCHOT#. This signal may require voltage translation on the motherboard. then transition monotonically to a high state. should be driven high throughout boundary scan operation. source synchronous to ADSTB[0]#. must connect the appropriate pins of both FSB agents. pins on the board be kept open for possible future use. Table 16. Signal Descript ion (Sheet 6 of 8)
processor will tristate its outputs. signals to all processor core units except the FSB and APIC units. clock; STPCLK# is an asynchronous input. (also known as the Test Access Port). provides the serial input needed for JTAG specification support. TDO (Test Data Out) transfers serial test data out of the processor. THERMDA Other Thermal Diode Anode. THERMDC Other Thermal Diode Cathode. system by the THERMTRIP# (Thermal Trip) pin. Table 16. Signal Description (Sheet 7 of 8)
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must connect the appropriate pins of both FSB agents. must be driven low during power on Reset. CC Input Processor core power supply. VCCA Input V CCA provides isolated power for the internal processor core PLL’s. VCCP Input Processor I/O Power Supply. Intel® MVP 6 that control the 2.1-mΩ loadline at the processor die. specification variations. See Table 2 for definitions of these pins. Table 16. Signal Descript ion (Sheet 8 of 8)
Thermal Specifications and Design Considerations
5 Thermal Specifications and
The processor requires a thermal solution to maintain temperatures within operating limits as set forth in Section 5.1. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components in the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems. Maintaining the proper thermal environment is key to reliable, long-term system operation. A complete thermal solution includes both component and system level thermal management features. Component level thermal solutions include active or passive heatsinks or heat exchangers attached to the exposed processor die. The solution should make firm contact to the die while maintaining processor mechanical specifications such as pressure. A typical system level thermal solution may consist of a processor fan ducted to a heat exchanger that is thermally-coupled to the processor via a heat pipe or direct die attachment. A secondary fan or air from the processor fan may also be used to cool other platform components or to lower the internal ambient temperature within the system. To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed such that the processor remains within the minimum and maximum junction temperature (Tj) specifications at the corresponding thermal design power (TDP) value listed in Table 17. Thermal solutions not designed to provide this level of thermal capability may affect the long-term reliability of the processor and system. The maximum junction temperature is defined by an activation of the processor Intel Thermal Monitor. Refer to Section 5.1.3 for more details. Analysis indicates that real applications are unlikely to cause the processor to consume the theoretical maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the TDP indicated in Table 17. The Intel Thermal Monitor feature is designed to help protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained period of time. For more details on the usage of this feature, refer to Section 5.1.3. In all cases, the Intel Thermal Monitor feature must be enabled for the processor to remain within specification.
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- The TDP specification should be used to design the processor thermal solution. The TDP is
not the maximum theoretical power the processor can generate.
- Not 100% tested. These power specifications are determined by characterization of the
- As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal
Monitor’s automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details.
- The Intel Thermal Monitor automatic mode mu st be enabled for the processor to operate
- T7600, T7400, T7200 processors feature 4-MB cache.
- T5600, T5500 processors feature 2-MB cache.
Table 17. Power Specifications for the Dual-core Standard Voltage Processor
2.33 GHz & HFM V
2.17 GHz & HFM VCC
2.00 GHz & HFM VCC
1.83 GHz & HFM VCC
1.67 GHz & HFM VCC
1.00 GHz & LFM VCC
- The TDP specification should be used to design the processor thermal solution. The TDP is
not the maximum theoretical power the processor can generate.
- Not 100% tested. These power specifications are determined by characterization of the
- As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal
Monitor’s automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details.
- The Intel Thermal Monitor automatic mode mu st be enabled for the processor to operate
Table 18. Power Specifications for the Dual-core Low Voltage Processor
1.50 GHz & HFM VCC
1.33 GHz & HFM VCC
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- The TDP specification should be used to design the processor thermal solution. The TDP is
not the maximum theoretical power the processor can generate.
- Not 100% tested. These power specifications are determined by characterization of the
- As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal
Refer to Section 5.1 for more details.
- The Intel Thermal Monitor automatic mode mu st be enabled for the processor to operate
Table 19. Power Specifications for the Single and Dual-core Ultra Low Voltage Processor
1.20 GHz & HFM V
1.06 GHz & HFM VCC
1.20 GHz & HFM VCC
0.80 GHz & LFM VCC
Thermal Specifications and Design Considerations
5.1 Thermal Specifications
The processor incorporates three methods of monitoring die temperature: the digital thermal sensor, Intel Thermal Monitor and the thermal “diode.” The Intel Thermal Monitor (detailed in Section 5.1.3) must be used to determine when the maximum specified processor junction temperature has been reached.
5.1.1 Thermal Diode
The processor incorporates an on-die PNP transistor whose base emitter junction is used as a thermal diode, with its collector shorted to Ground. The thermal diode can be read by an off-die analog/digital converter (a thermal sensor) located on the motherboard or a stand-alone measurement kit. The thermal diode may be used to monitor the die temperature of the processor for thermal management or instrumentation purposes but is not a reliable indication that the maximum operating temperature of the processor has been reached. When using the thermal diode, a temperature offset value must be read from a processor Model Specific Register (MSR) diode usage recommendation when the PROCHOT# signal is not asserted. Note: The reading of the external thermal sensor (on the motherboard) connected to the processor thermal diode signals will not necessarily reflect the temperature of the hottest location on the die. This is due to inaccuracies in the external thermal sensor, on-die temperature gradients between the location of the thermal diode and the hottest location on the die, and time based variations in the die temperature measurement. Time based variations can occur when the sampling rate of the thermal diode (by the thermal sensor) is slower than the rate at which the T J temperature can change. Offset between the thermal diode based temperature reading and the Intel Thermal Monitor reading may be characterized using the Intel Thermal Monitor’s Automatic mode activation of the thermal control circuit. This temperature offset must be taken into account when using the processor thermal diode to implement power management events. This offset is different than the diode Toffset value programmed into the processor MSR. Table 20 through Table 23 provides the diode interface and specifications. Two different sets of diode parameters are listed in Table 22 and Table 23. The diode model parameters apply to the traditional thermal sensors that use the diode equation to determine the processor temperature. Transistor model parameters have been added to support thermal sensors that use the transistor equation method. The Transistor model may provide more accurate temperature measurements when the diode ideality factor is closer to the maximum or minimum limits. Please contact your external sensor supplier for their recommendation. The thermal diode is separate from the Intel Thermal Monitor’s thermal sensor and cannot be used to predict the behavior of the Intel Thermal Monitor.
5.1.2 Thermal Diode Offset
In order to improve the accuracy of the diode based temperature measurements, a temperature offset value (specified as Toffset) will be programmed in the processor Model Specific Register (MSR) which will contain thermal diode characterization data. During manufacturing each processor thermal diode will be evaluated for its behavior relative to the theoretical diode. Using the equation above, the temperature error created by the difference n trim and the actual ideality of the particular processor will be calculated.
86 Datasheet
defined in the temperature sensor manufacturer’s datasheet. The ntrim used to calculate the Diode Correction Toffset are listed in Table 20.
- Intel does not support or re commend operation of the thermal diode under reverse bias.
power supplies are not within their specified tolerance range.
- Characterized across a temperature range of 50-100 °C.
- Not 100% tested. Specified by design characterization.
- The ideality factor, n, represents the deviat ion from ideal diode behavior as exemplified by
Boltzmann Constant, and T = absolute temperature (Kelvin).
- The series resistance, R TT, is provided to allow for a more accurate measurement of the
Constant, and q = electronic charge. Table 20. Thermal Diode n trim and Diode Correction Toffset Table 21. Thermal Diode Interface Table 22. Thermal Diode Parameters using Diode Mode
- Intel does not support or recommend operation of the thermal diode under reverse bias.
- Characterized acro ss a temperature range of 50-100 °C.
- Not 100% tested. Specified by design characterization.
- The ideality factor, n Q, represents the deviation from ideal diode behavior as exemplified
- The series resistance, R TT, provided in the Diode Model Table (Table 22) can be used for
more accurate readings as needed.
5.1.3 Intel® Thermal Monitor
Table 23. Thermal Diode Parame ters Using Transistor Model
Thermal Specifications and Design Considerations
88 Datasheet
designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss and may affect the long-term reliability of the processor. In addition, a thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously. The Intel Thermal Monitor controls the processor temperature by modulating (starting and stopping) the processor core clocks or by initiating an Enhanced Intel SpeedStep Technology transition when the processor silicon reaches its maximum operating temperature. The Intel Thermal Monitor uses two modes to activate the TCC: Automatic mode and on-demand mode. If both modes are activated, automatic mode takes precedence. Note: The Intel Thermal Monitor automatic mode must be enabled through BIOS for the processor to be operating within specifications. There are two automatic modes called Intel Thermal Monitor 1 and Intel Thermal Monitor 2. These modes are selected by writing values to the MSRs of the processor. After automatic mode is enabled, the TCC will activate only when the internal die temperature reaches the maximum allowed value for operation. Likewise, when Intel Thermal Monitor 2 is enabled and a high temperature situation exists, the processor will perform an Enhanced Intel SpeedStep Technology transition to a lower operating point. When the processor temperature drops below the critical level, the processor will make an Enhanced Intel SpeedStep Technology transition to the last requested operating point. Intel Thermal Monitor 1 and Intel Thermal Monitor 2 can co-exist within the processor. If both Intel Thermal Monitor 1 and Intel Thermal Monitor 2 bits are enabled in the auto-throttle MSR, Intel Thermal Monitor 2 will take precedence over Intel Thermal Monitor 1. However, if Intel Thermal Monitor 2 is not sufficient to cool the processor below the maximum operating temperature then Intel Thermal Monitor 1 will also activate to help cool down the processor. Intel recommends Intel Thermal Monitor 1 and Intel Thermal Monitor 2 be enabled on the processors. If a processor load based Enhanced Intel SpeedStep Technology transition (through MSR write) is initiated when an Intel Thermal Monitor 2 period is active, there are two possible results: 1. If the processor load based Enhanced Intel SpeedStep Technology transition target frequency is higher than the Intel Thermal Monitor 2 transition based target frequency, the processor load-based transition will be deferred until the Intel Thermal Monitor 2 event has been completed. 2. If the processor load-based Enhanced Intel SpeedStep Technology transition target frequency is lower than the Intel Thermal Monitor 2 transition based target frequency, the processor will transition to the processor load-based Enhanced Intel SpeedStep Technology target frequency point. When Intel Thermal Monitor 1 is enabled while a high temperature situation exists, the clocks will be modulated by alternately turning the clocks off and on at a 50% duty cycle. Cycle times are processor speed dependent and will decrease linearly as processor core frequencies increase. Once the temperature has returned to a non- critical level, modulation ceases and TCC goes inactive. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near the trip point. The duty cycle is factory configured and cannot be modified. Also, automatic mode does not require any additional hardware, software drivers, or interrupt handling routines. Processor performance will be decreased by the same amount as the duty cycle when the TCC is active.
Thermal Specifications and Design Considerations The TCC may also be activated via on-demand mode. If bit 4 of the ACPI Intel Thermal Monitor control register is written to a 1, the TCC will be activated immediately independent of the processor temperature. When using on-demand mode to activate the TCC, the duty cycle of the clock modulation is programmable via bits 3:1 of the same ACPI Intel Thermal Monitor control register. In automatic mode, the duty cycle is fixed at 50% on, 50% off, however in on-demand mode, the duty cycle can be On-demand mode may be used at the same time automatic mode is enabled, however, if the system tries to enable the TCC via on-demand mode at the same time automatic mode is enabled and a high temperature condition exists, automatic mode will take precedence. An external signal, PROCHOT# (processor hot) is asserted when the processor detects that its temperature is above the thermal trip point. Bus snooping and interrupt latching are also active while the TCC is active. Besides the thermal sensor and thermal control circuit, the Intel Thermal Monitor also includes one ACPI register, one performance counter register, three MSR, and one I/O pin (PROCHOT#). All are available to monitor and control the state of the Intel Thermal Monitor feature. The Intel Thermal Monitor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#. Note: PROCHOT# will not be asserted when the processor is in the Stop Grant, Sleep, Deep Sleep, and Deeper Sleep low power states, hence the thermal diode reading must be used as a safeguard to maintain the processor junction temperature within maximum specification. If the platform thermal solution is not able to maintain the processor junction temperature within the maximum specification, the system must initiate an orderly shutdown to prevent damage. If the processor enters one of the above low power states with PROCHOT# already asserted, PROCHOT# will remain asserted until the processor exits the low power state and the processor junction temperature drops below the thermal trip point. If Intel Thermal Monitor automatic mode is disabled, the processor will be operating out of specification. Regardless of enabling the automatic or on-demand modes, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature of approximately 125°C. At this point the THERMTRIP# signal will go active. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles. When THERMTRIP# is asserted, the processor core voltage must be shut down within the time specified in Chapter 3.
5.1.4 Digital Thermal Sensor
The processor also contains an on-die digital thermal sensor that can be read via a MSR (no I/O interface). In a dual-core implementation of the processor, each core will have a unique digital thermal sensor whose temperature is accessible via processor MSR. The digital thermal sensor is the preferred method of reading the processor die temperature since it can be located much closer to the hottest portions of the die and can thus more accurately track the die temperature and potential activation of processor core clock modulation via the Intel Thermal Monitor. The digital thermal sensor is only valid while the processor is in the normal operating state (C0 state). Unlike traditional thermal devices, the Digital Thermal sensor will output a temperature relative to the maximum supported operating temperature of the processor (T J,max). It is the responsibility of software to convert the relative temperature to an absolute temperature. The temperature returned by the digital thermal sensor will always be at or below TJ,max. Over temperature conditions are detectable via an Out Of Spec status bit. This bit is also part of the Digital Thermal sensor MSR. When this bit is set, the processor is operating out of specification and immediate shutdown of the system should occur. The processor operation and code execution is not guaranteed once the activation of the Out of Spec status bit is set.
Thermal Specifications and Design Considerations
90 Datasheet
The Digital Thermal Sensor (DTS) relative temperature readout corresponds to the Intel Thermal Monitor (Intel Thermal Monitor 1/Intel Thermal Monitor 2) trigger point. When the DTS indicates maximum processor core temperature has been reached the Intel Thermal Monitor 1 or Intel Thermal Monitor 2 hardware thermal control mechanism will activate. The DTS and Intel Thermal Monitor 1/Intel Thermal Monitor 2 temperature may not correspond to the thermal diode reading since the thermal diode is located in a separate portion of the die and thermal gradient between the individual core DTS. Additionally, the thermal gradient from DTS to thermal diode can vary substantially due to changes in processor power, mechanical and thermal attach and software application. The system designer is required to use the DTS to guarantee proper operation of the processor within its temperature operating specifications. Changes to the temperature can be detected via two programmable thresholds located in the processor MSRs. These thresholds have the capability of generating interrupts via the core's local APIC. Refer to the Intel® 64 and IA-32 Intel® Architectures Software Developer's Manual for specific register and programming details.
5.1.5 Out of Specification Detection
Overheat detection is performed by monitoring the processor temperature and temperature gradient. This feature is intended for graceful shut down before the THERMTRIP# is activated. If the processor’s Intel Thermal Monitor 1 or Intel Thermal Monitor 2 are triggered and the temperature remains high, an “Out Of Spec” status and sticky bit are latched in the status MSR register and generates thermal interrupt.
5.1.6 PROCHOT# Signal Pin
An external signal, PROCHOT# (processor hot), is asserted when the processor die temperature has reached its maximum operating temperature. If the Intel Thermal Monitor 1 or Intel Thermal Monitor 2 is enabled (note that the Intel Thermal Monitor 1 or Intel Thermal Monitor 2 must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#. The processor implements a bi-directional PROCHOT# capability to allow system designs to protect various components from over-heating situations. The PROCHOT# signal is bi-directional in that it can either signal when the processor has reached its maximum operating temperature or be driven from an external source to activate the TCC. The ability to activate the TCC via PROCHOT# can provide a means for thermal protection of system components. In a dual-core implementation, only a single PROCHOT# pin exists at a package level. When either core's thermal sensor trips, PROCHOT# signal will be driven by the processor package. If only Intel Thermal Monitor 1 is enabled, PROCHOT# will be asserted and only the core that is above TCC temperature trip point will have its core clocks modulated. If Intel Thermal Monitor 2 is enabled, then regardless of which core(s) are above TCC temperature trip point, both cores will enter the lowest programmed Intel Thermal Monitor 2 performance state. It is important to note that Intel recommends both Intel Thermal Monitor 1 and Intel Thermal Monitor 2 to be enabled. When PROCHOT# is driven by an external agent, if only Intel Thermal Monitor 1 is enabled on both cores, then both processor cores will have their core clocks modulated. If Intel Thermal Monitor 2 is enabled on both cores, then both processor core will enter the lowest programmed Intel Thermal Monitor 2 performance state. One application is the thermal protection of voltage regulators (VR). System designers can create a circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR is reached. By asserting PROCHOT# (pulled-low) and
Thermal Specifications and Design Considerations activating the TCC, the VR can cool down as a result of reduced processor power consumption. Bi-directional PROCHOT# can allow VR thermal designs to target maximum sustained current instead of maximum current. Systems should still provide proper cooling for the VR, and rely on bi-directional PROCHOT# only as a backup in case of system cooling failure. The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its TDP. With a properly designed and characterized thermal solution, it is anticipated that bi-directional PROCHOT# would only be asserted for very short periods of time when running the most power intensive applications. An under- designed thermal solution that is not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may cause a noticeable performance loss. § §