IMC020FLSA

IMC002FLSA INTEL | Alldatasheet

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December 1996 Order Number: 290434-006 SERIES 2 FLASH MEMORY CARDS iMC002FLSA, iMC004FLSA, iMC010FLSA, iMC020FLSA Extended Temperature Specifications Included Y 2, 4, 10 and 20 Megabyte Capacities Y PCMCIA 2.1/JEIDA 4.1 68-Pin Standard Ð Hardwired Card Information Structure Ð Byte- or Word-Wide Selectable Y Component Management Registers for Card Status/Control and Flexible System Interface Y Automatic Erase/Write Ð Monitored with Ready/Busy Output Y Card Power-Down Modes Ð Deep-Sleep for Low Power

Applications

Y Mechanical Write Protect Switch Y Solid-State Reliability Y Intel FlashFile TM Architecture Y High-Performance Read Access Ð 150 ns Maximum Y High-Performance Random Writes Ð6 ms Typical Word Write Y Erase Suspend to Read Command Ð Keeps Erase as Background Task Y Nonvolatility (Zero Retention Power) Ð No Batteries Required for Back-up Y ETOXTM V 0.4 m Flash Memory Technology Ð 5V Read, 12V Erase/Write Ð High-Volume Manufacturing Experience Y Extended Temperature Version Ð b40§Ct o a85§C Intel’s Series 2 Flash Memory Card facilitates high-performance disk emulation in mobile PCs and dedicated equipment. Manufactured with Intel’s ETOX TM III 0.8 m, FlashFile Memory devices, the Series 2 Card allows code and data retention while erasing and/or writing other blocks. Additionally, the Series 2 Flash Memory Card features low power modes, flexible system interfacing and a 150 ns read access time. When coupled with Intel’s low-power microprocessors, these cards enable high-performance implementations of mobile comput- ers and systems. Series 2 Cards conform to the Personal Computer Memory Card International Association (PCMCIA 2.1)/Jap- anese Electronics Industry Development Association (JEIDA 4.1) 68-pin standard, providing electrical and physical compatibility. Data file management software, Flash Translation Layer (FTL), provides data file storage and memory man- agement, much like a disk operating system. Intel’s Series 2 Flash Memory Cards, coupled with flash file management software, effectively provide a removable, all-silicon mass storage solution with higher perform- ance and reliability than disk-based memory architectures. Designing with Intel’s FlashFile Architecture enables OEM system manufacturers to design and manufacture a new generation of mobile PCs and dedicated equipment where high performance, ruggedness, long battery life and lighter weight are a requirement. For large user groups in workstation environments, the Series 2 Cards provide a means to securely store user data and backup system configuration/status information.

Table 1. Series 2 Flash Memory Card Pinout

1 GND Ground

10 A 11 I Address Bit 11

11 A 9 I Address Bit 9

12 A 8 I Address Bit 8

13 A 13 I Address Bit 13

14 A 14 I Address Bit 14

15 WE Ý I Write Enable LO

16 RDY/BSY Ý Ready-Busy HI/LO

17 V CC Supply Voltage

18 V PP1 Supply Voltage

19 A 16 I Address Bit 16

20 A 15 I Address Bit 15

21 A 12 I Address Bit 12

22 A 7 I Address Bit 7

23 A 6 I Address Bit 6

24 A 5 I Address Bit 5

25 A 4 I Address Bit 4

26 A 3 I Address Bit 3

27 A 2 I Address Bit 2

28 A 1 I Address Bit 1

29 A 0 I Address Bit 0

30 DQ 0 I/O Data Bit 0

31 DQ 1 I/O Data Bit 1

32 DQ 2 I/O Data Bit 2

33 WP O Write Protect HI

34 GND Ground

35 GND Ground

36 CD 1Ý O Card Detect 1 LO

37 DQ 11 I/O Data Bit 11

38 DQ 12 I/O Data Bit 12

39 DQ 13 I/O Data Bit 13

40 DQ 14 I/O Data Bit 14

41 DQ 15 I/O Data Bit 15

42 CE 2Ý I Card Enable 2 LO

43 VS 1 O Voltage Sense 1 N.C.

44 RFU Reserved

45 RFU Reserved

46 A 17 I Address Bit 17

47 A 18 I Address Bit 18

48 A 19 I Address Bit 19

49 A 20 I Address Bit 20

50 A 21 I Address Bit 21

51 V CC Supply Voltage

52 V PP2 Supply Voltage

53 A 22 I Address Bit 22

54 A 23 I Address Bit 23

55 A 24 I Address Bit 24

56 A 25 No Connect

57 VS 2 O Voltage Sense 2 N.C.

58 RST I Reset HI

59 WAIT Ý O Extend Bus Cycle LO

60 RFU Reserved

61 REG Ý I Register Select LO

64 DQ 8 I/O Data Bit 8

65 DQ 9 I/O Data Bit 9

66 DQ 10 I/O Data Bit 10

67 CD 2Ý O Card Detect 2 LO

68 GND Ground

Table 2. Series 2 Flash Memory Card Pin Descriptions but should be provided on host side. bus. DQ 15 is the most significant bit. CE1Ý,C E 2Ý I CARD ENABLE 1, 2: CE1Ý enables even bytes, CE 2Ý enables odd bytes. OEÝ I OUTPUT ENABLE: Active low signal gating read data from the memory card. WEÝ I WRITE ENABLE: Active low signal gating write data to the memory card. CD1Ý &C D 2Ý O CARD DETECT 1, 2: These signals provide for correct card insertion detection. They are positioned at opposite ends of the card to detect proper alignment. circuitry shall supply 10K or larger pull-up resistors on these signal pins. hardware write lockout to the flash array. VCC CARD POWER SUPPLY (5V nominal) for all internal circuitry. GND I GROUND for all internal circuitry. and Card Information Structure in the Attribute Memory Plane. RST I RESET from system, active high. Places card in Power-On Default State. RESET pulse width must be t 200 ns. WAITÝ O WAIT (Extend Bus Cycle) is used by Intel’s I/O cards and is driven high. these signals are driven high to maintain SRAM-card compatibility. NC NO INTERNAL CONNECTION . Pin may be driven or left floating. VS1,V S 2 VOLTAGE SENSE: Notifies the host Socket of the card’s V CC requirements. VS1 and VS 2 are both open, indicating a 5V V CC card.

Figure 1. Detailed Block Diagram. The Card Control Logic Provides Decoding Buffering and Control Signals.

SERIES 2 FLASH MEMORY CARDS Intel’s second generation Series 2 Flash Memory Cards facilitate high performance disk emulation for the storage of data files and application programs on a purely solid-state removable medium. File man- agement software, Flash Translation Layer (FTL), in conjunction with the Series 2 Flash Memory Cards, enable the design of high-performance light-weight notebook, palmtop, and pen-based PCs that have the processing power of today’s desktop computers. Application software stored on the flash memory card substantially reduces the slow disk-to-DRAM download process. Replacing the mechanical disk results in a dramatic enhancement of read perform- ance and substantial reduction of power consump- tion, size and weightÐconsiderations particularly important in portable PCs and equipment. The Se- ries 2 Card’s high performance read access time al- lows the use of Series 2 Cards in an ‘‘execute-in- place’’ (XIP) architecture. XIP eliminates redundancy associated with DRAM/Disk memory system archi- tectures. Operating systems stored in Flash Memory decreases system boot or program load times, en- abling the design of PCs that boot, operate, store data files and execute application programs from/to nonvolatile memory without losing the ability to per- form an update. File management systems modify and store data files by allocating flash memory space intelligently. Wear leveling algorithms, employed to equally dis- tribute the number of rewrite cycles, ensure that no particular block is cycled excessively relative to oth- er blocks. This provides hundreds of thousands of hours of power on usage. This file management software enables the user to interact with the flash memory card in precisely the same way as a magnetic disk. Series 2 Flash Memory Cards provide durable non- volatile memory storage for mobile PCs on the road, facilitating simple transfer back into the desktop en- vironment. For systems currently using a static RAM/battery configuration for data acquisition, the Series 2 Flash Memory Card’s nonvolatility eliminates the need for battery backup. The concern for battery failure no longer exists, an important consideration for porta- ble computers and medical instruments, both requir- ing continuous operation. Series 2 Cards consume no power when the system is off, and only 60 mAi n Deep-Sleep mode (2 Megabyte card). Furthermore, Flash Memory Cards offer a considerable cost and density advantage over memory cards based on static RAM with battery backup. Besides disk emulation, the Series 2 Card’s electri- cal block-erasure, data writability, and inherent non- volatility fit well with data accumulation and record- ing needs. Electrical block-erasure provides design flexibility to selectively rewrite blocks of data, while saving other blocks for infrequently updated param- eters and lookup tables. For example, networks and systems that utilize large banks of battery-backed DRAM to store configuration and status benefit from the Series 2 Flash Card’s nonvolatility and reliability. SERIES 2 ARCHITECTURE OVERVIEW The Series 2 Flash Memory Card contains a 2 to 20 Megabyte Flash Memory array consisting of 2 to 20 28F008SA FlashFile Memory devices. Each 28F008SA contains sixteen individually-erasable, 64 Kbyte blocks; therefore, the Flash Memory Card contains from 32 to 320 device blocks. It also con- tains two Card Control Logic devices that manage the external interface, address decoding, and com- ponent management logic. (Refer to Figure 1 for a block diagram.) To support PCMCIA-compatible word-wide access, devices are paired so that each accessible memory block is 64 KWords (see Figure 2). Card logic allows the system to write or read one word at a time, or one byte at a time by referencing the high or low byte. Erasure can be performed on the entire block pair (high and low device blocks simultaneously), or on the high or low byte portion separately. Also in accordance with PCMCIA specifications this product supports byte-wide operation, in which the flash array is divided into 128K x 8 bit device blocks. In this configuration, odd bytes are multiplexed onto the low byte data bus.

Figure 2. Memory Architecture. Each Device Pair Consists of Sixteen 64 KWord Blocks. level functions and a deep-sleep mode. and completely written 100,000 times. including verifications for long-term data integrity. crements, typically in 6 ms. operating temperature range. specific device pairs (Sleep Control Register).

Release 2 of the PC Card Standard. ments as set by the PCMCIA standard. RY/BY Ý by JEDEC (component level). PCMCIA/JEIDA Type 1 mechanical specifications. See Figure 19 for mechanical dimensions. dition. Flash Memory Cards do not require batteries. and BVD 2 are driven high to maintain compatibility. and represents the user-alterable memory space. Figure 3. Component Management Registers Allow S/W Control of Components within Card

SERIES 2 FLASH MEMORY CARDS ADDRESS DECODE Address decoding provides the decoding logic for the 2 to 20 Device Chip Enables and the elements of the Attribute Memory Plane. REG Ý selects between the Common Memory Plane (REG Ý e VIH) and the Attribute Memory Plane (REG Ý e VIL). NOTE: The Series 2 Card has active address inputs A 0 to A24 implying that reading and writing to addresses beyond 32 Megabytes causes wraparound. Further- more, reads to illegal addresses (for example, be- tween 20 and 32 Meg on a 20 Megabyte card) re- turns Default data (00FFH or FFFFH). The 28F008SA devices, storing data, applications or firmware, form the Common Memory Plane ac- cessed individually or as device pairs. Memory is lin- early mapped in the Common Memory Plane. Three memory access modes are available when access- ing the Common Memory Plane: Byte-Wide, Word Wide, and Odd-Byte modes. Additional decoding selects the hardwired PCMCIA CIS and Component Management Registers mapped in the Attribute Memory Plane beginning at address 000000H. The 512 memory-mapped even-byte CMRs are lin- early mapped beginning at address 4000H in the At- tribute Memory Plane. DATA CONTROL Data Control Logic selects the path and direction for accessing the Common or Attribute Memory Plane. It controls any of the PCMCIA-defined Word-Wide, Byte-Wide or Odd-Byte modes for either reads or writes to these areas. As shown in Table 3, input pins which determine these selections are REG A0 through A 24,W E Ý,O E Ý,C E 1Ý, and CE 2Ý. PCMCIA specifications allow only even-byte access to the Attribute Memory Plane. In Byte-Wide mode, bytes contiguous in software ac- tually alternate between two device blocks of a de- vice pair. Therefore, erasure of one device block erases every other contiguous byte. In accordance with the PCMCIA standard for memory configuration, the Series 2 Card does not support confining contig- uous bytes within one flash device when in by-8 mode.

Table 3. Data Access Mode Truth Table

1. Standby mode is valid in Common Memory or Attribute Memory access.
2. To meet the low power specifications, V

PP e VPPL; however V PPH presents no reliability problems.

1. Odd-Byte data are not valid during access to the Attribute Memory Plane.

e VIH,L e VIL,X e Don’t Care.

Figure 7. CARD STATUS REGISTER (Intel) Provides a Quick Review of the Card’s Status zero indicates a busy device(s) in the card. reports the status of the WP pin. REGISTER, with 1 indicating write protected. (using the Sleep Control Register), also sets this bit. ing down any device pair sets this bit. value of the READY/BUSY MASK REGISTER. Masking any device sets this bit. writing a 1 to the CISWP Bit (bit 0). therefore not write protected. should be written as zeroes for future compatibility.

Figure 8. WRITE PROTECTION REGISTER (Intel) Eliminates Accidental Data Corruption lective power-down control of individual device pairs. into the ‘‘Deep-Sleep’’ mode.

20 Megabytes (10 device pairs), writing a one to an

cessing a data-write or block-erase operation. Register bits appear as ready. Figure 9. SLEEP CONTROL REGISTER (Intel) Allows Specific

ware polling to determine operation status. es, unused device mask bits appear as masked.

1. The standard PCMCIA READY-BUSY MODE, in
2. A High-Performance mode that generates a low-

to free up space so new file data may be written.

1. Set all bits in the READY/BUSY MASK REGIS-

an unwanted interrupt when step 3 is performed.

1. Write 01H to the READY-BUSY MODE REGIS-

TER. This sets the MODE bit.

1. Write 01H to the READY-BUSY MODE REGIS-

TER. This clears the RACK bit. an operation is initiated on the respective devices. Figure 12. High Performance Ready-Busy Mode REGISTER (Intel)

power supplies during block erasure and data writes. ware requests for status while the WSM is operating. and the address of the location to be written. Table 4. Device Command Set

1. Commands other than those shown above are reserved by Intel for future device implementations and should not be
2. DA e A device-level (or device pair) address within the card.

BA e Address within the block of a specific device (device pair) being erased. WA e Address of memory location to be written. IA e A device-level address; 00H for manufacturer code, 01 for device code.

1. Following the intelligent identifier command, two read operations access manufacturer (89H) and device codes (A2H).

e Data read from Device Status Register.

1. WD e Data to be written at location WA. Data is latched on the rising edge of WE Ý.
2. Either 40H or 10H are recognized by the WSM as the Write Setup command.

SERIES 2 FLASH MEMORY CARDS COMMAND DEFINITIONS Read Array (FFH) Ð Upon initial card power-up, after exit from the Deep- Sleep modes, and whenever illegal commands are given, individual devices default to the Read Array mode. This mode is also entered by writing FFH into the CUI. In this mode, microprocessor read cycles retrieve array data. Devices remain enabled for reads until the CUI receives an alternate command. Once the internal WSM has started a block-erase or data-write operation within a device, that device will not recognize the Read Array command until the WSM has completed its operation (or the Erase Sus- pend command is issued during erase). Intelligent Identifier (90H) Ð After executing this command, the intelligent identifi- er values can be read. Only address A 0 of each de- vice is used in this mode, all other address inputs are reserved and should be cleared to 0. [(Manufac- turer code e 89H for A 0 e 0), (Device code e A2H for A 0 e 1)]. The device will remain in this mode until the CUI receives another command. This information is useful by system software in de- termining what type of flash memory device is con- tained within the card and allows the correct match- ing of device to write and erase algorithms. System software that fully utilizes the PCMCIA specification will not use the intelligent identifier mode, as this data is available within the Card Information Struc- ture (refer to section on PCMCIA Card Information Structure). Read Status Register (70H) After writing this command, a device read outputs the contents of its Status Register, regardless of the address presented to that device. The contents of this register are latched on the falling edge of OE CE1Ý (and/or CE 2Ý), whichever occurs last in the read cycle. This prevents possible bus errors which might occur if the contents of the Status Register changed while reading its contents. CE 1Ý (and CE2Ý for odd-byte or word access) or OE Ý must be toggled with each subsequent status read, or the completion of a write or erase operation will not be evident. This command is executable while the WSM is operating, however, during a block-erase or data-write operation, reads from the device will auto- matically return status register data. Upon comple- tion of that operation, the device remains in the Status Register read mode until the CUI receives another command. The read Status Register command functions when V PP e VPPL or V PPH. Clear Status Register (50H) The Erase Status and Write Status bits may be set to ‘‘1’’s by the WSM and can only be reset by the Clear Status Register Command. These bits indicate various failure conditions. By allowing system soft- ware to control the resetting of these bits, several operations may be performed (such as cumulatively writing several bytes or erasing multiple blocks in sequence). The device’s Status Register may then be polled to determine if an error occurred during that sequence. This adds flexibility to the way the device may be used. Additionally, the V PP Status bit (SR.3) MUST be re- set by system software (Clear Status Register com- mand) before further block-erases are attempted (after an error). The Clear Status Register command functions when V PP e VPPL or V PPH. This command puts the device in the Read Array mode. Write Setup/Write A two-command sequence executes a data-write operation. After the system switches V PP to V PPH, the write setup command (40H) is written to the CUI of the appropriate device, followed by a second write specifying the address and write data (latched on the rising edge of WE Ý). The device’s WSM con- trols the data-write and write verify algorithms inter- nally. After receiving the two-command write se- quence, the device automatically outputs Status Register data when read (see Figure 13). The CPU detects the completion of the write operation by an- alyzing card-level or device-level indicators. Card- level indicators include the RDY/BSY Ý pin and the READY-BUSY STATUS REGISTER; while device- level indicators include the specific device’s Status Register. Only the Read Status Register command is valid while the write operation is active. Upon completion of the data-write sequence (see section on Status Register) the device’s Status Register re- flects the result of the write operation. The device remains in the Read Status Register mode until the CUI receives an alternate command.

SERIES 2 FLASH MEMORY CARDS Erase Setup/Erase Confirm Commands (20H) Within a device, a two-command sequence initiates an erase operation on one device block at a time. After the system switches V PP to V PPH, an Erase Setup command (20H) prepares the CUI for the Erase Confirm command (D0H). The device’s WSM controls the erase algorithms internally. After receiv- ing the two-command erase sequence, the device automatically outputs Status Register data when read (see Figure 14). If the command after erase setup is not an Erase Confirm command, the CR sets the Write Failure and Erase Failure bits of the Status Register, places the device into the Read Status Register mode, and waits for another com- mand. The Erase Confirm command enables the WSM for erase (simultaneously closing the address latches for that device’s block (A 16 –A19). The CPU detects the completion of the erase operation by an- alyzing card-level or device-level indicators. Card- level indicators include the RDY/BSY pin and the READY-BUSY STATUS REGISTER; while device- level indicators include the specific device’s Status Register. Only the Read Status Register and Erase Suspend command is valid during an active erase operation. Upon completion of the erase sequence (see section on Status Register) the device’s Status Register reflects the result of the erase operation. The device remains in the Read Status Register mode until the CUI receives an alternate command. The two-step block-erase sequence ensures that memory contents are not accidentally erased. Erase attempts while V PPL k VPPk VPPH produce spuri- ous results and are not recommended. Reliable block erasure only occurs when V PP e VPPH.I nt h e absence of this voltage, memory contents are pro- tected against erasure. If block erase is attempted while V PP e VPPL, the V PP Status bit will be set to ‘‘1’’. When erase completes, the Erase Status bit should be checked. If an erase error is detected, the de- vice’s Status Register should be cleared. The CUI remains in Read Status Register mode until receiv- ing an alternate command. Erase Suspend (B0H)/Erase Resume (D0H) Erase Suspend allows block erase interruption to read data from another block of the device or to temporarily conserve power for another system op- eration. Once the erase process starts, writing the Erase Suspend command to the CUI (see Figure 15) requests the WSM to suspend the erase sequence at a predetermined point in the erase algorithm. In the erase suspend state, the device continues to output Status Register data when read. Polling the device’s RY/BY Ý and Erase Suspend Status bits (Status Register) will determine when the erase suspend mode is valid. It is important to note that the card’s RDY/BSY Ý pin will also transition to VOH and will generate an interrupt if this pin is con- nected to a system-level interrupt. At this point, a Read Array command can be written to the device’s CUI to read data from blocks other than those which are suspended . The only other valid com- mands at this time are Read Status Register (70H) and Erase Resume (D0H). If V PP goes low during Erase Suspend, the V PP Status bit is set in the Status Register and the erase operation is aborted. The Erase Resume command clears the Erase Sus- pend state and allows the WSM to continue with the erase operation. The device’s RY/BY Ý Status and Erase Suspend Status bits and the card’s READY- BUSY Status Register are automatically updated to reflect the erase resume condition. The card’s RDY/ BSY Ý pin also returns to V OL. Invalid/Reserved These are unassigned commands having the same effect as the Read Array command. Do not issue any command other than the valid commands speci- fied above. Intel reserves the right to redefine these codes for future functions.

SERIES 2 FLASH MEMORY CARDS DEVICE STATUS REGISTER Each 28F008SA device in the Series 2 Card con- tains a Status Register which displays the condition of its Write State Machine. The Status Register is read at any time by writing the Read Status com- mand to the CUI. After writing this command, all sub- sequent Read operations output data from the Status Register, until another command is written to the CUI. Bit 7ÐWSM Status This bit reflects the Ready/Busy condition of the WSM. A ‘‘1’’ indicates that read, block-erase or data- write operations are available. A ‘‘0’’ indicates that write or erase operations are in progress. Bit 6ÐErase Suspend Status If an Erase Suspend command is issued during the erase operation, the WSM halts execution and sets the WSM Status bit and the Erase Suspend Status bit to a ‘‘1’’. This bit remains set until the device receives an Erase Resume command, at which point the CUI resets the WSM Status bit and the Erase Suspend Status bit. Bit 5ÐErase Status This bit will be cleared to 0 to indicate a successful block-erasure. When set to a ‘‘1’’, the WSM has been unsuccessful at performing an erase verifica- tion. The device’s CUI only resets this bit to a ‘‘0’’ in response to a Clear Status Register command. Bit 4ÐWrite Status This bit will be cleared to a 0 to indicate a successful data-write operation. When the WSM fails to write data after receiving a write command, the bit is set to a ‘‘1’’ and can only be reset by the CUI in re- sponse to a Clear Status Register command. Bit 3ÐV PP Status During block-erase and data-write operations, the WSM monitors the output of the device’s internal V PP detector. In the event of low V PP, the WSM sets (‘‘1’’) the V PP Status bit, the status bit for the opera- tion in progress (either write or erase). The CUI re- sets these bits in response to a Clear Status Regis- ter command. Also, the WSM RY/BY Ý bit will be set to indicate a device ready condition. This bit MUST be reset by system software (Clear Status Register command) before further data writes or block erases are attempted. Device Status Register (Read Only Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WSM Erase Erase Write V PP ReservedStatus Suspend Status Status Status Status

Figure 13. Device-Level Automated Write Algorithm

1. Repeat for subsequent data writes.
2. In addition, the card’s READY-BUSY STATUS REGISTER or the RDY/BSY
3. Full device-level status check can be done after each data write or after a sequence of data writes.
4. Write FFH (or FFFFH) after the last data write operation to reset the device(s) to Read Array Mode.
5. If a data write operation fails due to a low V

before further attempts are allowed by the Write State Machine.

1. If a data write operation fails during a multiple write sequence, SR Bit 4 (Write Status) will not be cleared until the

Command User Interface receives the Clear Status Register command.

Figure 14. Device-Level Automated Erase Algorithm

1. Repeat for subsequent data writes.
2. In addition, the card’s READY-BUSY STATUS REGISTER or the RDY/BSY
3. Full device-level status check can be done after each block erase or after a sequence of block erases.
4. Write FFH (or FFFFH) after the last block erase operation to reset the device(s) to Ready Array Mode.
5. If a block erase operation fails due to a low V

before further attempts are allowed by the Write State Machine.

1. If a block erase operation fails during a multiple block erase sequence, SR Bit 4 (Write Status) will not be cleared until the

Command User Interface receives the Clear Status Register command.

Block Address. Block Pair Address. Figure 15. Erase Suspend/Resume Algorithm. Allows Reads to Interrupt Erases. Series 2 card in standby mode is 65 mA. 28F008SA device circuitry to power back on.

and GND, as well as between V PP1/VPP2 and GND. power-up into the Read Array Mode. CC voltages above V LKO when V PP is active. Table 5. This section describes each tuple contained within the Series 2 Flash Memory Card. Table 5. Tuple Format 0 Tuple Code: CISTPL Ðxxx. The tuple code 0FFH indicates no more tuples in the list. link field contains 0FFH, this tuple is the last tuple in the list. 2bn Bytes specific to this tuple.

SERIES 2 FLASH MEMORY CARDS The Device Geometry Tuple This tuple (CISTPL ÐDEVlCEGEO e 1EH) is con- ceptually similar to a DOS disk geometry tuple (CISTPLÐGEOMETRY), except it is not a format- dependent property; this deals with the fixed archi- tecture of the memory device(s). Fields are defined as follows: DGTPL BUS ÐValue e n, where system bus width e 2(nb1) bytes. N e 2 for standard PCMClA Re- lease 1.0/2.0 cards. DGTPL EBS ÐValue e n, where the memory array’s physical memory segments have a minimum erase block size of 2 (nb1) address increments of DGTPLÐBUS-wide accesses. DGTPL RBS ÐValue e n, where the memory ar- ray’s physical memory segments have a minimum read block size of 2 (nb1) address increments of DGTPLÐBUS-wide accesses. DGTPL WBS ÐValue e n, where the memory ar- ray’s physical memory segments have a minimum write block size of 2 (nb1) address increments of DGTPLÐBUS-wide accesses. DGTPL PART ÐValue e n, where the memory ar- ray’s physical memory segments can have partitions subdividing the arrays in minimum granularity of (nb1) number of erase blocks. FL DEVICE INTERLEAVE ÐValue e n, where card architectures employ a multiple of 2 (nb1) times inter- leaving of the entire memory arrays with the above characteristics. Non-interleaved cards have values n e 1. Jedec Programming Information Tuple This tuple (CISTPL ÐJEDEC e 18H) contains the Intel manufacturing identifier (89H) and the 28F008SA device ID (A2H). Level 1 Version/Product Information Tuple This tuple (CISTPL ÐVERI e 15H) contains Level-1- version compliance and card-manufacturer informa- tion. Fields are described as follows: TPLLV1 MAJOR ÐMajor version number e 04H. TPLLV1 MINOR ÐMinor version number e 01H for release 2.0. TPLLV1 INFOÐ Name of manufacturer e intel; Name of product e SERIES2-‘‘Card size’’; Card type e 2; Speed e 150 ns or 200 ns Register Base e REGBASE 4000H Test Codes e DBBDRELP Legalities e COPYRIGHT intel Corporation 1991 The Configurable Card Tuple This tuple (ClSTPL ÐCONF e 1AH) describes the interface supported by the card and the locations of the Card Configuration Registers and the Card Con- figuration Table. Fields are described as follows: TPCC SZ ÐSize of fields byte e 01H. TPCC LAST ÐIndex number of the last entry in the Card Configuration Table e 00H. TPCC RADR ÐConfiguration Registers Base Ad- dress in Reg Space e 4000H. TPCC RMSK ÐConfiguration Registers Present Mask e 03H. The End-Of-List Tuple The end-of-list tuple (CISTPL ÐEND e FFH) marks the end of a tuple chain. Upon encountering this tu- ple, continue tuple processing as if a long-link to ad- dress 0 of common memory space were encoun- tered.

SERIES 2 FLASH MEMORY CARDS Tuple Value DescriptionAddress 00H 01H CISTPL ÐDEV 02H 03H TPL ÐLINK 04H 53H DEVICE ÐINFO e FLASH 150 ns 52H DEVICE ÐINFO e FLASH 200 ns CARD SIZE 06H 06H 2M 0EH 4M 26H 10M 4EH 20M 08H FFH END OF DEVICE 0AH 1EH CISTPL Ð DEVICEGEO 0CH 06H TPL ÐLINK 0EH 02H DGTPL ÐBUS 10H 11H DGTPL ÐEBS 12H 01H DGTPL ÐRBS 14H 01H DGPL ÐWBS 16H 03H DGTPL ÐPART 18H 01H FL ÐDEVICE INTERLEAVE 1AH 18H CISTPL ÐJEDEC 1CH 02H TPL ÐLINK 1EH 89H INTEL J-ID 20H A2H 28F008 J-ID 22H 15H CISTPL ÐVER1 24H 50H TPL ÐLINK 26H 04H TPLLV1 MAJOR 28H 01H TPLLV1 MINOR 2AH 69H TPLLV1 INFO i 2CH 6EH n 2EH 74H t 30H 65H e Tuple Value DescriptionAddress 32H 6CH l 34H 00H END TEXT 36H 53H S 38H 45H E 3AH 52H R 3CH 49H I 3EH 45H E 40H 53H S 42H 32H 2 44H 2DH Ð 46H 30H 2M e 0 30H 4M e 0 31H 10M e 1 32H 20M e 2 48H 32H 2M e 2 34H 4M e 4 30H 10M e 0 30H 20M e 0 4AH 20H SPACE 4CH 00H END TEXT 4EH 32H CARD TYPE 2 50H 41H A e 2M, 150 ns 42H B e 4M, 150 ns 45H E e 10M, 150 ns 5AH Z e 20M, 150 ns 48H H e 2M, 200 ns 49H I e 4M, 200 ns 4CH L e 10M, 200 ns 4FH O e 20M, 200 ns

SERIES 2 FLASH MEMORY CARDS Tuple Value DescriptionAddress 52H 20H SPACE 54H 52H REGBASE-R 56H 45H E 58H 47H G 5AH 42H B 5CH 41H A 5EH 53H S 60H 45H E 62H 20H SPACE 4000h 64H 34H 4 66H 30H 0 68H 30H 0 6AH 30H 0 6CH 68H h 6EH 20H SPACE 70H 44H D 72H 42H B 74H 42H B 76H 44H D 78H 52H R 7AH 45H E 7CH 4CH L 7EH 50H P 80H 00H END TEXT COPYRIGHT 82H 43H C 84H 4FH O 86H 50H P 88H 59H Y 8AH 52H R 8CH 49H I 8EH 47H G 90H 48H H 92H 54H T 94H 20H SPACE Tuple Value DescriptionAddress 96H 69H i 98H 6EH n 9AH 74H t 9CH 65H e 9EH 6CH l A0H 20H SPACE CORPORATION A2H 43H C A4H 4FH O A6H 52H R A8H 50H P AAH 4FH O ACH 52H R AEH 41H A B0H 54H T B2H 49H I B4H 4FH O B6H 4EH N B8H 20H SPACE BAH 31H 1 BCH 39H 9 BEH 39H 9 C0H 31H 1 C2H 00H END TEXT C4H FFH END OF LIST C6H 1AH CISTPL ÐCONF C8H 06H TPL ÐLINK CAH 01H TPCC ÐSZ CCH 00H TPCC ÐLAST CEH 00H TPCC ÐRADR D0H 40H TPCC ÐRADR D2H 03H TPCC ÐRMSK D4H FFH END OF LIST D6H FFH CISTPL ÐEND D8H 00H INVALID ECIS ADDRESS

SERIES 2 FLASH MEMORY CARDS OPERATING SPECIFICATlONS ABSOLUTE MAXIMUM RATINGS * Storage TemperatureÀÀÀÀÀÀÀÀÀÀÀÀ b40§Ct o a85§C Voltage on Any Pin with Respect to Ground ÀÀÀÀÀ b2.0V to V CC a 2.0V(1) VPP1/VPP2 Supply Voltage with Respect to Ground ÀÀÀÀÀÀÀ b2.0V to a14.0V(1, 2) VCC Supply Voltage with Respect to Ground ÀÀÀÀÀÀÀÀÀÀÀÀ b0.5V to a7.0V NOTICE: This data sheet contains preliminary infor- mation on new products in production. The specifica- tions are subject to change without notice. Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. NOTES: Maximum DC voltage on output pins is V CC a 0.5V. The voltage may overshoot to V CC a 2.0V for periods of less than 20 ns. 2. Maximum DC input voltage on V PP1/VPP2 may overshoot to a14.0V for periods of less than 20 ns. COMMERCIAL TEMPERATURE OPERATING CONDITIONS These operating conditions apply to commercial temperature devices. Symbol Parameter Min Max Unit TA Operating Temperature 0 70 §C VCC VCC Supply Voltage (5%) 4.75 5.25 V EXTENDED TEMPERATURE OPERATING CONDITIONS These operating conditions apply to extended temperature devices. Symbol Parameter Min Max Unit TA Operating Temperature b40 85 §C VCC VCC Supply Voltage (5%) 4.75 5.25 V CHARACTERISTICS All AC and DC characteristics apply to both commercial and extended temperature devices. COMMON DC CHARACTERISTICS, CMOS and TTL Symbol Parameter Notes Min Typ Max Unit Test Condition ILI Input Leakage Current 1, 3 g1 g20 mAV CC e VCC Max VIN e VCC or GND ILO Output Leakage Current 1 g1 g20 mAV CC e VCC Max VOUT e VCC or GND VIL Input Low Voltage 1 b0.5 0.8 V VIH Input High Voltage (TTL) 1 2.4 V CC a 0.3 V Input High Voltage (CMOS) 0.7 V CC VCC a 0.3 VOL Output Low Voltage 1 V SS 0.4 V V CC e VCC Min IOL e 3.2 mA VOH Output High Voltage 1 4.0 V CC VV CC e VCC Min IOH eb 2.0 mA VPPL VPP during Read Only Operations 1, 2 0.0 6.5 V VPPH VPP during Read/Write Operations 1 11.4 12.6 V VLKO VCC Erase/Write Lock Voltage 1 2.0 V NOTES: 1. Values are the same for byte and word wide modes and for all card densities. 2. Block Erases/Data Writes are inhibited when V PP e VPPL and not guaranteed in the range between V PPH and V PPL. 3. Exceptions: With V IN e GND, the leakage on CE 1Ý,C E 2Ý, REG Ý,O E Ý,W E Ý, will be s 500 mA due to internal pullup resistors and, with V IN e VCC, RST leakage will be s 500 mA due to internal pulldown resistor.

SERIES 2 FLASH MEMORY CARDS DC CHARACTERISTICS, CMOS Symbol Parameter Notes Byte Wide Mode Word Wide Mode Unit Test Condition Min Typ Max Min Typ Max ICCR VCC Read Current 1, 3 45 85 65 120 mA V CC e VCC Max, Control Signals e GND tCYCLE e 200 ns, IOUT e 0m A ICCW VCC Write Current 1, 3 35 80 45 110 mA Data Write in Progress ICCE VCC Erase Current 1, 2, 3 35 80 45 110 mA Block (Pair) Erase in Progress ICCS VCC Standby Current 2 Meg 1, 4, 6 110 420 110 420 mA VCC e VCC Max, Control Signals4 Meg 160 620 160 620 e VIH

10 Meg 310 1220 310 1220

20 Meg 560 2200 560 2200

ICCSL VCC Sleep Current 2 Meg 1, 4, 5 60 60 mA

4 Meg 100 100

10 Meg 260 260

20 Meg 460 460

IPPW VPP Write 1, 3 15 30 mA Data Write Current (V PP e VPPH) in Progress IPPE VPP Erase 1, 3 15 30 mA Block (Pair) Erase Current (V PP e VPPH) in Progress IPPSL VPP Sleep Current 2 Meg 1, 5 0.2 10 0.2 10 mA 4 Meg 0.4 20 0.4 20

10 Meg 1 50 1 50

20 Meg 2 100 2 100

IPPS1 VPP Standby or 2 Meg 1, 6 2.0 20 2.0 20 mA Read Current 4 Meg 2.2 30 2.2 30(VPP s VCC) 10 Meg 2.8 60 2.8 60 20 Meg 3.8 110 3.8 110 IPPS2 VPP Standby or 2 Meg 1, 6 20 400 20 400 mA Read Current 4 Meg 40 800 40 800(VPP l VCC)

10 Meg 100 2000 100 2000

20 Meg 200 4000 200 4000

NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at V CC e 5.0V, V PP e 12.0V, T e 25§C. 2. The Data Sheet specification for the 28F008SA in Erase Suspend (I CCES) is 5 mA typical and 10 mA max with the device deselected. If the device(s) are read while in Erase Suspend Mode, current draw is the sum of I CCES and I CCR. 3. Standby or Sleep currents are not included for non-accessed devices. 4. Address and data inputs to card static. Control line voltages equal to V IH or V IL. 5. All 28F008SA devices in Deep-Sleep (Reset-PowerDown) mode. 6. In Byte and Word Mode, all but two devices in Deep-Sleep.

SERIES 2 FLASH MEMORY CARDS DC CHARACTERISTICS, TTL Symbol Parameter Notes Byte Wide Mode Word Wide Mode Unit Test Condition Min Typ Max Min Typ Max ICCR VCC Read Current 1, 3 70 135 90 170 mA V CC e VCC Max, Control Signals e GND tCYCLE e 200 ns, IOUT e 0m A ICCW VCC Write Current 1, 3 60 130 70 160 mA Data Write in Progress ICCE VCC Erase Current 1, 2, 3 60 130 70 160 mA Block (Pair) Erase in Progress ICCS VCC Standby Current 2 Meg 1, 4, 6 20 100 20 100 mA VCC e VCC Max, Control Signals4 Meg e VIH

10 Meg

20 Meg

ICCSL VCC Sleep Current 2 Meg

4 Meg 1, 4, 5 20 100 20 100 mA

IPPW VPP Write 1, 3 10 30 20 60 mA Data Write Current (V PP e VPPH) in Progress IPPE VPP Erase 1, 3 10 30 20 60 mA Block (Pair) Erase Current (V PP e VPPH) in Progress IPPSL VPP Sleep Current 2 Meg 1, 5 0.2 10 0.2 10 mA 4 Meg 0.4 20 0.4 20 10 Meg 1.0 50 1.0 50 20 Meg 2.0 100 2.0 100 IPPS1 VPP Standby or 2 Meg 1, 6 2.0 20 2.0 20 mA Read Current 4 Meg 2.2 30 2.2 30(VPP s VCC) 10 Meg 2.8 60 2.8 60 20 Meg 3.8 110 3.8 110 IPPS2 VPP Standby or 2 Meg 1, 6 20 400 20 400 mA Read Current 4 Meg 40 800 40 800(VPP l VCC) NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at V CC e 5.0V, V PP e 12.0V, T e 25§C. 2. The Data Sheet specification for the 28F008SA in Erase Suspend (I CCES) is 5 mA typical and 10 mA max with the device deselected. If the device(s) are read while in Erase Suspend Mode, current draw is the sum of I CCES and I CCR. 3. Standby or Sleep currents are not included for non-accessed devices. 4. Address and data inputs to card static. Control line voltages equal to V IH or V IL. 5. All 28F008SA devices in Deep-Sleep (Reset-PowerDown) mode. 6. In Byte and Word Mode, all but two devices in Deep-Sleep. 7. The current consumption from the 28F008SA is insignificant in relation to the ASIC’s.

SERIES 2 FLASH MEMORY CARDS AC CHARACTERISTICS AC Timing Diagrams and characteristics are guaran- teed to meet or exceed PCMCIA Release 2.0 speci- fications. PCMCIA allows a 300 ns access time for Attribute Memory. Note that read and write access timings to the Series 2 Flash Memory Card’s Com- mon and Attribute Memory Planes are identical at 150 ns. Furthermore, there is no delay in switching between the Common and Attribute Memory Planes. COMMON AND ATTRIBUTE MEMORY, AC CHARACTERISTICS: Read-Only Operations Symbol Parameter Notes Min Max Unit JEDEC PCMCIA tAVAV tRC Read Cycle Time 150 ns tAVQV ta (A) Address Access Time 150 ns tELQV ta (CE) Card Enable Access Time 150 ns tGLQV ta (OE) Output Enable Access Time 75 ns tEHQX tdis (CE) Output Disable Time from CE Ý 75 ns tGHQZ tdis (CE) Output Disable Time from OE Ý 75 ns tGLQX ten (CE) Output Enable Time from CE Ý 5n s tELQX ten (OE) Output Enable Time from OE Ý 5n s tAXQX tv (A) Data Valid from Add Change 0 ns tRHQV Reset-PwrDwn Recovery to Output Delay 500 ns tsu (VCC) CE Setup Time on Power-Up 1 ms First Access after Reset 500 ns 290434–28 Transient Input/Output Reference Waveform (V CC e 5.0V) for Standard Test Configuration 290434–29 Transient Input/Output Reference Waveform (V CC e 3.3V) for Standard Test Configuration

Figure 16. AC Waveform for Read Operations

1. The hatched area may be either high or low.

SERIES 2 FLASH MEMORY CARDS COMMON AND ATTRIBUTE MEMORY, AC CHARACTERISTICS: Write Operations (1) Symbol Parameter Notes Min Max Unit JEDEC PCMCIA tAVAV tWC Write Cycle Time 150 ns tWLWH tw (WE) Write Pulse Width 80 ns tAVWL tsu (A) Address Setup Time 20 ns tAVWH tsu (A-WEH) Address Setup Time for WE Ý 100 ns tVPWH tvps VPP Setup to WE Ý Going High 100 ns tELWH tsu (CE-WEH) Card Enable Setup Time for WE Ý 100 ns tDVWH tsu (D-WEH) Data Setup Time for WE Ý 50 ns tWHDX th (D) Data Hold Time 20 ns tWHAX trec (WE) Write Recover Time 20 ns tWHRL WEÝ High to RDY/BSY Ý 120 ns tWHQV1 Duration of Data Write Operation 6 ms tWHQV2 Duration of Block Erase Operation 0.3 sec tQVVL VPP Hold from Operation Complete 2 0 ns tWHGL th (OE-WE) Write Recovery before Read 10 ns tRHWL Reset-PwrDwn Recovery to WE Ý Going Low 1 ms NOTES: 1. Read timing characteristics during erase and data write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only operations. 2. Refer to text on Data-Write and Block-Erase Operations. BLOCK ERASE AND DATA WRITE PERFORMANCE Parameter Notes Min Typ (3) Max Unit Block Pair Erase Time (1) 2, 4 1.1 10 sec Block Pair Write Time 2, 4 0.5 2.1 sec Byte/Word Write Time 4 4.8 ms6 ms3 m s NOTES: 1. Individual blocks can be erased 100,000 times. 2. Excludes System-Level Overhead. 3. 25 §C, 12.0 V PP. 4. Monitor Ready/Busy Registers for the completion of a write/erase command.

Figure 17. AC Waveform for Write Operations By writing the appropriate register, or on power-up, the card control ASIC generates the RP Ý signal to the card’s devices.

SERIES 2 FLASH MEMORY CARDS COMMON AND ATTRIBUTE MEMORY, AC CHARACTERISTICS: CE Ý-Controlled Write Operations (1) Symbol Parameter Notes Min Max Unit JEDEC PCMCIA tAVAV tWC Write Cycle Time 1 150 ns tELEH tw (WE) Chip Enable Pulse Width 1 80 ns tAVEL tsu (A) Address Setup Time 1 20 ns tAVEH tsu (A-WEH) Address Setup Time for CE Ý 1 100 ns tVPEH tvps VPP Setup to CE Ý Going High 1 100 ns tWLEH tsu (CE-WEH) Write Enable Setup Time for CE Ý 1 100 ns tDVEH tsu (D-WEH) Data Setup Time for CE Ý 15 0 n s tEHDX th (D) Data Hold Time 1 20 ns tEHAX trec (WE) Write Recover Time 1 20 ns tEHRL CEÝ High to RDY/BSY Ý 1 120 ns tEHQV1 Duration of Duration of Data Write Operation 1 6 ms Data Write tEHQV2 Duration of Duration of Block Erase Operation 1 0.3 sec Erase tQVVL VPP Hold from Operation Complete 1, 2 0 ns tEHGL th (OE-WE) Write Recovery before Read 1 10 ns tRHEL Reset-PwrDwn Recovery to CE Ý Going Low 1 ms NOTES: 1. Read timing characteristics during erase and data write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only operations. 2. Refer to text on Data-Write and Block-Erase Operations.

Figure 18. Alternate AC Waveform for Write Operations By writing the appropriate register, or on power-up, the card control ASIC generates the RP Ý signal to the card’s devices.

Figure 19. Series 2 Flash Memory Card Package Dimensions

Figure 22. Label Information

SERIES 2 FLASH MEMORY CARDS Table 5. Capacitance TA e 25§C, f e 1.0 MHz

ORDERING INFORMATION

WHERE: i e INTEL MC e MEMORY CARD 020 e DENSITY IN MEGABYTES (002,004,010,020 AVAILABLE) FL e FLASH TECHNOLOGY S e BLOCKED ARCHITECTURE A e SERIES 2 -ET e EXTENDED TEMPERATURE 15 e 150 ns M9508014,SBXXXX M e MANILA 95 e 1995 08 e WEEK 08 014 e LOT Ý SBXXXX e CUSTOMER IDENTIFIER ADDITIONAL INFORMATION ORDER NUMBER 28F008SA FlashFile TM Memory Data Sheet 290429 AP-361 ‘‘Implementing the Integrated Registers of the Series 2 Flash Memory Card’’ 292096 AP-364 ‘‘28F008SA Automation and Algorithms’’ 292099 AP-359 ‘‘28F008SA Hardware Interfacing’’ 292094 AP-360 ‘‘28F008SA Software Drivers’’ 292095 AP-606 ‘‘Interchangeability of Series 1/2/2 a Flash Memory Cards’’

REVISION HISTORY

02 Added 150 ns TUPLE, Deleted 250 ns TUPLE

Corrected Global Power Register Address to 4002H Corrected Write Protection Register Address to 4104H Corrected Ready-Busy Mode Register Address to 4140H I CC Standby Byte Wide Mode MAX/TYP Increased Added Power-On Timing Spec Added First Access after Reset Spec Changed Advanced Information to Preliminary

03 Added 2 MByte card support

Changed write timing waveforms to match PCMCIA Changed PowerDown (PWD) to Reset-PowerDown (RP)

04 Extended Operating Temperature Range

Added Maximum Byte Write Time

05 Added 150 ns Timings

Change Cover Drawing to Accommodate Label 06 Modified DC characteristics to reflect a conversion to new memory componentsÐthe 0.4 m version of the 28F008SA. The new devices also have improved program and erase performance.