8259A INTEL | Alldatasheet
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Table 1. Pin Description VCC 28 I SUPPLY: a5V Supply. status onto the data bus for the CPU. information is transferred via this bus. and inputs for a slave 8259A. SP/EN 16 I/O SLAVE PROGRAM/ENABLE BUFFER: This is a dual function pin. IR input (Level Triggered Mode). acknowledge pulses issued by the CPU. connected to the CPU A0 address line (A1 for 8086, 8088).
The 8259A is a device specifically designed for use in real time, interrupt driven microcomputer systems. It manages eight levels or requests and has built-in features for expandability to other 8259A’s (up to 64 levels). It is programmed by the system’s software as an I/O peripheral. A selection of priority modes is available to the programmer so that the manner in which the requests are processed by the 8259A can be configured to match his system requirements. The priority modes can be changed or reconfigured dynamically at any time during the main program. This means that the complete interrupt structure can be defined as required, based on the total system environment. INTERRUPT REQUEST REGISTER (IRR) AND IN-SERVICE REGISTER (ISR) The interrupts at the IR input lines are handled by two registers in cascade, the Interrupt Request Reg- ister (IRR) and the In-Service (ISR). The IRR is used to store all the interrupt levels which are requesting service; and the ISR is used to store all the interrupt levels which are being serviced. PRIORITY RESOLVER This logic block determines the priorites of the bits set in the IRR. The highest priority is selected and strobed into the corresponding bit of the ISR during INTA pulse. INTERRUPT MASK REGISTER (IMR) The IMR stores the bits which mask the interrupt lines to be masked. The IMR operates on the IRR. Masking of a higher priority input will not affect the interrupt request lines of lower quality. INT (INTERRUPT) This output goes directly to the CPU interrupt input. The V OH level on this line is designed to be fully compatible with the 8080A, 8085A and 8086 input levels. INTA (INTERRUPT ACKNOWLEDGE) INTA pulses will cause the 8259A to release vector- ing information onto the data bus. The format of this data depends on the system mode ( mPM) of the 8259A. DATA BUS BUFFER This 3-state, bidirectional 8-bit buffer is used to inter- face the 8259A to the system Data Bus. Control words and status information are transferred through the Data Bus Buffer. READ/WRITE CONTROL LOGIC The function of this block is to accept OUTput com- mands from the CPU. It contains the Initialization Command Word (ICW) registers and Operation Command Word (OCW) registers which store the various control formats for device operation. This function block also allows the status of the 8259A to be transferred onto the Data Bus. CS (CHIP SELECT) A LOW on this input enables the 8259A. No reading or writing of the chip will occur unless the device is selected. WR (WRITE) A LOW on this input enables the CPU to write con- trol words (ICWs and OCWs) to the 8259A. RD (READ) A LOW on this input enables the 8259A to send the status of the Interrupt Request Register (IRR), In Service Register (ISR), the Interrupt Mask Register (IMR), or the Interrupt level onto the Data Bus. A This input signal is used in conjunction with WR and RD signals to write commands into the various com- mand registers, as well as reading the various status registers of the chip. This line can be tied directly to one of the address lines.
231468–5 Figure 4a. 8259A Block Diagram
231468–6 Figure 4b. 8259A Block Diagram
THE CASCADE BUFFER/COMPARATOR This function block stores and compares the IDs of all 8259A’s used in the system. The associated three I/O pins (CAS0-2) are outputs when the 8259A is used as a master and are inputs when the 8259A is used as a slave. As a master, the 8259A sends the ID of the interrupting slave device onto the CAS0–2 lines. The slave thus selected will send its preprogrammed subroutine address onto the Data Bus during the next one or two consecutive INTA pulses. (See section ‘‘Cascading the 8259A’’.) INTERRUPT SEQUENCE The powerful features of the 8259A in a microcom- puter system are its programmability and the inter- rupt routine addressing capability. The latter allows direct or indirect jumping to the specific interrupt rou- tine requested without any polling of the interrupting devices. The normal sequence of events during an interrupt depends on the type of CPU being used. The events occur as follows in an MCS-80/85 sys- tem: 1. One or more of the INTERRUPT REQUEST lines (IR7–0) are raised high, setting the correspond- ing IRR bit(s). 2. The 8259A evaluates these requests, and sends an INT to the CPU, if appropriate. 3. The CPU acknowledges the INT and responds with an INTA pulse. 4. Upon receiving an INTA from the CPU group, the highest priority ISR bit is set, and the correspond- ing IRR bit is reset. The 8259A will also release a CALL instruction code (11001101) onto the 8-bit Data Bus through its D7–0 pins. 5. This CALL instruction will initiate two more INTA pulses to be sent to the 8259A from the CPU group. 6. These two INTA pulses allow the 8259A to re- lease its preprogrammed subroutine address onto the Data Bus. The lower 8-bit address is re- leased at the first INTA pulse and the higher 8-bit address is released at the second INTA pulse. 7. This completes the 3-byte CALL instruction re- leased by the 8259A. In the AEOI mode the ISR bit is reset at the end of the third INTA pulse. Otherwise, the ISR bit remains set until an appro- priate EOI command is issued at the end of the interrupt sequence. The events occuring in an 8086 system are the same until step 4. 4. Upon receiving an INTA from the CPU group, the highest priority ISR bit is set and the correspond- ing IRR bit is reset. The 8259A does not drive the Data Bus during this cycle. 5. The 8086 will initiate a second INTA pulse. Dur- ing this pulse, the 8259A releases an 8-bit pointer onto the Data Bus where it is read by the CPU. 6. This completes the interrupt cycle. In the AEOI mode the ISR bit is reset at the end of the sec- ond INTA pulse. Otherwise, the ISR bit remains set until an appropriate EOI command is issued at the end of the interrupt subroutine. If no interrupt request is present at step 4 of either sequence (i.e., the request was too short in duration) the 8259A will issue an interrupt level 7. Both the vectoring bytes and the CAS lines will look like an interrupt level 7 was requested. When the 8259A PIC receives an interrupt, INT be- comes active and an interrupt acknowledge cycle is started. If a higher priority interrupt occurs between the two INTA pulses, the INT line goes inactive im- mediately after the second INTA pulse. After an un- specified amount of time the INT line is activated again to signify the higher priority interrupt waiting for service. This inactive time is not specified and can vary between parts. The designer should be aware of this consideration when designing a sys- tem which uses the 8259A. It is recommended that proper asynchronous design techniques be fol- lowed.
Content of Second Interrupt Vector Byte IR Interval e 4 D7 D6 D5 D4 D3 D2 D1 D0
7 A 7 A 6 A 5 11100
6 A 7 A 6 A 5 11000
5 A 7 A 6 A 5 10100
4 A 7 A 6 A 5 10000
3 A 7 A 6 A 5 01100
2 A 7 A 6 A 5 01000
1 A 7 A 6 A 5 00100
0 A 7 A 6 A 5 00000
7 A 7 A 6 111000
6 A 7 A 6 110000
5 A 7 A 6 101000
4 A 7 A 6 100000
3 A 7 A 6 011000
2 A 7 A 6 010000
1 A 7 A 6 001000
0 A 7 A 6 000000
During the third INTA pulse the higher address of the appropriate service routine, which was programmed as byte 2 of the initialization sequence (A 8 –A15), is enabled onto the bus. Content of Third Interrupt Vector Byte D7 D6 D5 D4 D3 D2 D1 D0 A15 A14 A13 A12 A11 A10 A9 A8 8086, 8088 8086 mode is similar to MCS-80 mode except that only two Interrupt Acknowledge cycles are issued by the processor and no CALL opcode is sent to the processor. The first interrupt acknowledge cycle is similar to that of MCS-80, 85 systems in that the 8259A uses it to internally freeze the state of the interrupts for priority resolution and as a master it issues the interrupt code on the cascade lines at the end of the INTA pulse. On this first cycle it does not issue any data to the processor and leaves its data bus buffers disabled. On the second interrupt ac- knowledge cycle in 8086 mode the master (or slave if so programmed) will send a byte of data to the processor with the acknowledged interrupt code composed as follows (note the state of the ADI mode control is ignored and A 5 –A11 are unused in 8086 mode): Content of Interrupt Vector Byte for 8086 System Mode D7 D6 D5 D4 D3 D2 D1 D0 IR7 T7 T6 T5 T4 T3 1 1 1 IR6 T7 T6 T5 T4 T3 1 1 0 IR5 T7 T6 T5 T4 T3 1 0 1 IR4 T7 T6 T5 T4 T3 1 0 0 IR3 T7 T6 T5 T4 T3 0 1 1 IR2 T7 T6 T5 T4 T3 0 1 0 IR1 T7 T6 T5 T4 T3 0 0 1 IR0 T7 T6 T5 T4 T3 0 0 0 PROGRAMMING THE 8259A The 8259A accepts two types of command words generated by the CPU: 1. Initialization Command Words (ICWs): Before normal operation can begin, each 8259A in the system must be brought to a starting pointÐby a sequence of 2 to 4 bytes timed by WR pulses. 2. Operation Command Words (OCWs): These are the command words which command the 8259A to operate in various interrupt modes. These modes are: a. Fully nested mode b. Rotating priority mode c. Special mask mode d. Polled mode The OCWs can be written into the 8259A anytime after initialization. INITIALIZATION COMMAND WORDS (ICWS) General Whenever a command is issued with A0 e 0 and D4 e 1, this is interpreted as Initialization Command Word 1 (ICW1). ICW1 starts the intiitalization se- quence during which the following automatically oc- cur. a. The edge sense circuit is reset, which means that following initialization, an interrupt request (IR) in- put must make a low-to-high transistion to gener- ate an interrupt.
b. The Interrupt Mask Register is cleared. c. IR7 input is assigned priority 7. d. The slave mode address is set to 7. A5 –A15: Page starting address of service routines . (Address interval) has no effect. on the interrupt inputs will be disabled. val e 4; ADI e 0 then interval e 8. ICW4 is not needed, set IC4 e 0. e 0. It will load the 8-bit slave register. 2) through the cascade lines. released by it on the Data Bus. Figure 6. Initialization Sequence
slave determination is by M/S. Figure 7. Initialization Command Word Format
Slave ID is equal to the corresponding master IR input. Figure 7. Initialization Command Word Format (Continued)
1 M 7 M 6 M 5 M 4M 3M 2M 1 M 0
0 R SL EOI 0 0 L2 L1 L0
Figure 8. Operation Command Word Format
(inhibited), M e 0 indicates the channel is enabled. End of Interrupt modes and combinations of the two. Operation Command Word Format. acted upon when the SL bit is active. Figure 8. Operation Command Word Format (Continued)
Operation Control Word 3 (OCW3) ESMMÐEnable Special Mask Mode. When this bit is set to 1 it enables the SMM bit to set or reset the Special Mask Mode. When ESMM e 0 the SMM bit becomes a ‘‘don’t care’’. SMMÐSpecial Mask Mode. If ESMM e 1 and SMM e 1 the 8259A will enter Special Mask Mode. If ESMM e 1 and SMM e 0 the 8259A will revert to normal mask mode. When ESMM e 0, SMM has no effect. Fully Nested Mode This mode is entered after initialization unless anoth- er mode is programmed. The interrupt requests are ordered in priority from 0 through 7 (0 highest). When an interrupt is acknowledged the highest pri- ority request is determined and its vector placed on the bus. Additionally, a bit of the Interrupt Service register (ISO-7) is set. This bit remains set until the microprocessor issues an End of Interrupt (EOI) command immediately before returning from the service routine, or if AEOI (Automatic End of Inter- rupt) bit is set, until the trailing edge of the last INTA. While the IS bit is set, all further interrupts of the same or lower priority are inhibited, while higher lev- els will generate an interrupt (which will be acknowl- edged only if the microprocessor internal Interupt enable flip-flop has been re-enabled through soft- ware). After the initialization sequence, IR0 has the highest prioirity and IR7 the lowest. Priorities can be changed, as will be explained, in the rotating priority mode. End of Interrupt (EOI) The In Service (IS) bit can be reset either automati- cally following the trailing edge of the last in se- quence INTA pulse (when AEOI bit in ICW1 is set) or by a command word that must be issued to the 8259A before returning from a service routine (EOI command). An EOI command must be issued twice if in the Cascade mode, once for the master and once for the corresponding slave. There are two forms of EOI command: Specific and Non-Specific. When the 8259A is operated in modes which perserve the fully nested structure, it can de- termine which IS bit to reset on EOI. When a Non- Specific EOI command is issued the 8259A will auto- matically reset the highest IS bit of those that are set, since in the fully nested mode the highest IS level was necessarily the last level acknowledged and serviced. A non-specific EOI can be issued with OCW2 (EOI e 1, SL e 0, R e 0). When a mode is used which may disturb the fully nested structure, the 8259A may no longer be able to determine the last level acknowledged. In this case a Specific End of Interrupt must be issued which includes as part of the command the IS level to be reset. A specific EOI can be issued with OCW2 (EOI e 1, SL e 1, R e 0, and L0–L2 is the binary level of the IS bit to be reset). It should be noted that an IS bit that is masked by an IMR bit will not be cleared by a non-specific EOI if the 8259A is in the Special Mask Mode. Automatic End of Interrupt (AEOI) Mode If AEOI e 1 in ICW4, then the 8259A will operate in AEOI mode continuously until reprogrammed by ICW4. in this mode the 8259A will automatically per- form a non-specific EOI operation at the trailing edge of the last interrupt acknowledge pulse (third pulse in MCS-80/85, second in 8086). Note that from a system standpoint, this mode should be used only when a nested multilevel interrupt structure is not required within a single 8259A. The AEOI mode can only be used in a master 8259A and not a slave. 8259As with a copyright date of 1985 or later will operate in the AEOI mode as a master or a slave. Automatic Rotation (Equal Priority Devices) In some applications there are a number of interrupt- ing devices of equal priority. In this mode a device, after being serviced, receives the lowest priority, so a device requesting an interrupt will have to wait, in the worst case until each of 7 other devices are serviced at most once . For example, if the priority and ‘‘in service’’ status is: Before Rotate (IR4 the highest prioirity requiring service) ‘‘IS’’ Status 231468–18 Priority Status 231468–19
After Rotate (IR4 was serviced, all other priorities rotated correspondingly) ‘‘IS’’ Status 231468–20 Priority Status 231468–21 There are two ways to accomplish Automatic Rota- tion using OCW2, the Rotation on Non-Specific EOI Command (R e 1, SL e 0, EOI e 1) and the Ro- tate in Automatic EOI Mode which is set by (R e 1, SL e 0, EOI e 0) and cleared by (R e 0, SL e 0, EOI e 0). Specific Rotation (Specific Priority) The programmer can change priorities by program- ming the bottom priority and thus fixing all other pri- orities; i.e., if IR5 is programmed as the bottom prior- ity device, then IR6 will have the highest one. The Set Priority command is issued in OCW2 where: R e 1, SL e 1, L0–L2 is the binary priority level code of the bottom priority device. Observe that in this mode internal status is updated by software control during OCW2. However, it is in- dependent of the End of Interrupt (EOI) command (also executed by OCW2). Priority changes can be executed during an EOI command by using the Ro- tate on Specific EOI command in OCW2 (R e 1, SL e 1, EOI e 1 and LO–L2 e IR level to receive bottom priority). Interrupt Masks Each Interrupt Request input can bem masked indi- vidually by the Interrupt Mask Register (IMR) pro- grammed through OCW1. Each bit in the IMR masks one interrupt channel if it is set (1). Bit 0 masks IR0, Bit 1 masks IR1 and so forth. Masking an IR channel does not affect the other channels operation. Special Mask Mode Some applications may require an interrupt service routine to dynamically alter the system priority struc- ture during its execution under software control. For example, the routine may wish to inhibit lower priori- ty requests for a portion of its execution but enable some of them for another portion. The difficulty here is that if an Interrupt Request is acknowledged and an End of Interrupt command did not reset its IS bit (i.e., while executing a service routine), the 8259A would have inhibited all lower priority requests with no easy way for the routine to enable them. That is where the Special Mask Mode comes in. In the special Mask Mode, when a mask bit is set in OCW1, it inhibits further interrupts at that level and enables interrupts from all other levels (lower as well as higher) that are not masked. Thus, any interrupts may be selectively enabled by loading the mask register. The special Mask Mode is set by OWC3 where: SSMM e 1, SMM e 1, and cleared where SSMM e 1, SMM e 0. Poll Command In Poll mode the INT output functions as it normally does. The microprocessor should ignore this output. This can be accomplished either by not connecting the INT output or by masking interrupts within the microprocessor, thereby disabling its interrupt input. Service to devices is achieved by software using a Poll command. The Poll command is issued by setting P e ‘1’’ in OCW3. The 8259A treats the next RD pulse to the 8259A (i.e., RD e 0, CS e 0) as an interrupt ac- knowledge, sets the appropriate IS bit if there is a request, and reads the priority level. Interrupt is fro- zen from WR to RD . The word enabled onto the data bus during RD is: D7 D6 D5 D4 D3 D2 D1 D0 IÐ Ð Ð Ð W 2 W 1 W 0 W0–W2: Binary code of the highest priority level requesting service. I: Equal to ‘‘1’’ if there is an interrupt. This mode is useful if there is a routine command common to several levels so that the INTA se- quence is not needed (saves ROM space). Another application is to use the poll mode to expand the number of priority levels to more than 64. Reading the 8259A Status The input status of several internal registers can be read to update the user information on the system.
231468–221. Master clear active only during ICW1.
- FREEZE is active during INTA and poll sequences only.
- Truth Table for a D-Latch.
1 Di Di Follow
0 X Qn-1 Hold
Figure 9. Priority CellÐSimplified Logic Diagram tains the interrupt request lines which are masked. After initialization the 8259A is set to IRR. This mode is programmed using bit 3 in ICW1.
Figure 10. IR Triggering Timing Requirements latch is a transparent D type latch. tered. If another IR7 occurs it is a default. master too. If not, no EOI should be sent.
cascade line inactive (low). Figure 11. Cascading the 8259A
ABSOLUTE MAXIMUM RATINGS * Ambient Temperature Under Bias ÀÀÀÀÀÀ0 §Ct o7 0 §C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b65§Ct o a150§C Voltage on Any Pin with Respect to GroundÀÀÀÀÀÀÀÀÀÀ b0.5V to a7V Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1W NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. D.C. CHARACTERISTICS TA e 0§Ct o7 0 §C, V CC e 5V g 10% Symbol Parameter Min Max Units Test Conditions VIL Input Low Voltage b0.5 0.8 V VIH Input High Voltage 2.0 * VCC a 0.5V V VOL Output Low Voltage 0.45 V I OL e 2.2 mA VOH Output High Voltage 2.4 V I OH eb 400 mA VOH(INT) Interrupt Output High 3.5 V I OH eb 100 mA Voltage 2.4 V I OH eb 400 mA ILI Input Load Current b10 a10 mA0 V s VIN s VCC ILOL Output Leakage Current b10 a10 mA 0.45V s VOUT s VCC ICC VCC Supply Current 85 mA ILIR IR Input Load Current b300 mAV IN e 0 10 mAV IN e VCC *NOTE: For Extended Temperature EXPRESS V IH e 2.3V. CAPACITANCE TA e 25§C; V CC e GND e 0V Symbol Parameter Min Typ Max Unit Test Conditions CIN Input Capacitance 10 pF fc e 1 MHz CI/O I/O Capacitance 20 pF Unmeasured Pins Returned to V SS
A.C. CHARACTERISTICS TA e 0§Ct o7 0 §C, V CC e 5V g10% TIMING REQUIREMENTS Symbol Parameter 8259A 8259A-2 Units Test Conditions Min Max Min Max TAHRL AO/CS Setup to RD /INTAv 00 n s TRHAX AO/CS Hold after RD /INTAu 00 n s TRLRH RD Pulse Width 235 160 ns TAHWL AO/CS Setup to WR v 00 n s TWHAX AO/CS Hold after WR u 00 n s TWLWH WR Pulse Width 290 190 ns TDVWH Data Setup to WR u 240 160 ns TWHDX Data Hold after WR u 00 n s TJLJH Interrupt Request Width (Low) 100 100 ns See Note 1 TCVIAL Cascade Setup to Second or Third 55 40 nsINTAv(Slave Only) TRHRL End of RD to Next RD End of INTA to Next INTA within 160 100 ns an INTA Sequence Only TWHWL End of WR to Next WR 190 100 ns *TCHCL End of Command to Next Command 500 150 ns(Not Same Command Type) End of INTA Sequence to Next 500 300INTA Sequence. *Worst case timing for TCHCL in an actual microprocessor system is typically much greater than 500 ns (i.e. 8085A e 1.6 ms, 8085A-2 e 1 ms, 8086 e 1 ms, 8086-2 e 625 ns) NOTE: This is the low time required to clear the input latch in the edge triggered mode. TIMING RESPONSES Symbol Parameter 8259A 8259A-2 Units Test Conditions Min Max Min Max TRLDV Data Valid from RD /INTAv 200 120 ns C of Data Bus e 100 pF TRHDZ Data Float after RD /INTAu 10 100 10 85 ns C of Data Bus TJHIH Interrupt Output Delay 350 300 ns Max Test C e 100 pF TIALCV Cascade Valid from First INTA v 565 360 ns CINT e 100 pF Min Test C e 15 pF (Master Only) TRLEL Enable Active from RD vor INTA v 125 100 ns CCASCADE e 100 pF TRHEH Enable Inactive from RD uor INTA u 150 150 ns TAHDV Data Valid from Stable Address 200 200 ns TCVDV Cascade Valid to Valid Data 300 200 ns
A.C. TESTING INPUT/OUTPUT WAVEFORM 231468–25 A.C. Testing: Inputs are driven at 2.4V for a logic ‘‘1’’ and 0.45V for a logic ‘‘0’’. Timing measurements are made at 2.0V for a logic ‘‘1’’ and 0.8V for a logic ‘‘0’’. A.C. TESTING LOAD CIRCUIT 231468–26 CL e 100 pF CL Includes Jig Capacitance WAVEFORMS WRITE 231468–27
WAVEFORMS (Continued) READ/INTA 231468–28 OTHER TIMING 231468–29
WAVEFORMS (Continued) INTA SEQUENCE 231468–30 NOTES: Interrupt output must remain HIGH at least until leading edge of first INTA . 1. Cycle 1 in 8086, 8088 systems, the Data Bus is not active. Data Sheet Revision Review The following changes have been made since revision 2 of the 8259A data sheet. 1. The first paragraph of the Poll Command section was rewritten to clarify the status of the INT pin. 2. A paragraph was added to the Interrupt Sequence section to indicate the status of the INT pin during multiple interrupts. 3. A reference to PLCC packaging was added. 4. All references to the 8259A-8 have been deleted. INTEL CORPORATION, 2200 Mission College Blvd., Santa Clara, CA 95052; Tel. (408) 765-8080 INTEL CORPORATION (U.K.) Ltd., Swindon, United Kingdom; Tel. (0793) 696 000 INTEL JAPAN k.k., Ibaraki-ken; Tel. 029747-8511 Printed in U.S.A./xxxx/1196/B10M/xx xx