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Intel® LXT971A 3.3V Dual-Speed Fast Ethernet PHY Transceiver Datasheet The LXT971A is an IEEE compliant Fast Ethernet PHY Transceiver that directly supports both 100BASE-TX and 10BASE-T applications. It provides a Media Independent Interface (MII) for easy attachment to 10/100 Media Access Controllers (MACs). The LXT971A also provides a Low V oltage PECL (LVPECL) interface for use with 100BASE-FX fiber networks. This document also supports the LXT971 device. The LXT971A supports full-duplex operation at 10 Mbps and 100 Mbps. Its operating condition can be set using auto-negotiation, parallel detection, or manual control. The LXT971A is fabricated with an advanced CMOS process and requires only a single 3.3V power supply.
Applications
■ Combination 10BASE-T/100BASE-TX or 100BASE-FX Network Interface Cards (NICs) ■ 10/100 PCMCIA Cards ■ Cable Modems and Set-Top Boxes ■ 3.3V Operation. ■ Low power consumption (300 mW typical). ■ Low-power “Sleep” mode. ■ 10BASE-T and 100BASE-TX using a single RJ-45 connection. ■ Supports auto-negotiation and parallel detection. ■ MII interface with extended register capability. ■ Robust baseline wander correction performance. ■ 100BASE-FX fiber-optic capable. ■ Standard CSMA/CD or full-duplex operation. ■ Supports JTAG boundary scan. ■ Configurable via MDIO serial port or hardware control pins. ■ Integrated, programmable LED drivers. ■ 64-ball Plastic Ball Grid Array (PBGA). — LXT971ABC - Commercial (0 ° to 70°C ambient). —LXT971ABE - Extended (-40 ° to 85°C ambient). ■ 64-pin Low-profile Quad Flat Package (LQFP). — LXT971ALC - Commercial (0 ° to 70°C ambient). — LXT971ALE - Extended (-40 ° to 85°C ambient). Order Number: 249414-002 August 2002
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Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTELÆ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY , RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY , OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The LXT971A may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 2002 *Third-party brands and names are the property of their respective owners.
LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver Datasheet 3 Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002
Contents
LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver
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LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver
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Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002
Revision History
Revision Date: August 6, 2002 Page Description Globally replaced “pseudo-PECL” with Low-Voltage PECL”, except when identified with 5 V. 1 Front Page: Changed “pseudo-ECL (PECL)” to “Low Voltage PECL (LVPECL). Added “JTAG Boundary Scan” to Product Features on front page. 12 Modified Figure 2 “LXT971A 64-Ball PBGA Assignments” (replaced TEST1 and TEST0 with GND). 13 Modified Figure 3 “LXT971A 64-Pin LQFP Assignments” (replaced TEST1 and TEST0 with GND). 14 Modified Table 1 “LQFP Numeric Pin List” (replaced TEST1 and TEST0 with GND). 16 Added note under Section 2.0, “Signal Descriptions”: “Intel recommends that all inputs and multi- function pins be tied to the inactive states and all outputs be left floating, if unused.” 17 Modified SD/TP description in Table 3 “LXT971A Network Interface Signal Descriptions”. Added Table note 2. 18 Modified Table 4 “LXT971A Miscellaneous Signal Descriptions”. 19 Modified Table 5 “LXT971A Power Supply Signal Descriptions”. 20 Added Table 8 “LXT971A Pin Types and Modes”. 22 Replaced second paragraph under Section 3.2.1.2, “Fiber Interface”. 23 Added Section 3.2.2.1, “Increased MII Drive Strength”. 23 Changed “Far-End Fault” title to ‘100BASE-FX Far-End Fault”. Modified first sentence under this heading. 30 Modified Figure 8 “Hardware Configuration Settings”. 35 Added paragraph after bullets under Section 3.6.7.2, “Test Loopback”. 43 Modified text under Section 3.7.3.4, “Fiber PMD Sublayer”. 47 Modified Table 13 “Supported JTAG Instructions”. 47 Modified Table 14 “Device ID Register”. 52 Added a new Section 4.3, “The Fiber Interface”. 53 Replaced Figure 25 “Typical LXT971A-to-3.3 V Fiber Transceiver Interface Circuitry”. 54 Added Figure 26 “Typical LXT971A-to-5 V Fiber Transceiver Interface Circuitry”. 55 Added Figure 27 “ON Semiconductor Triple PECL-to-LVPECL Translator”. 56 Modified Table 17 “Absolute Maximum Ratings”. 56 Modified Table 18 “Operating Conditions”: Added Typ values to Vcc current. 57 Modified Table 20 “Digital I/O Characteristics - MII Pins”. 58 Modified Table 22 “I/O Characteristics - LED/CFG Pins”. 58 Added Table 23 “I/O Characteristics – SD/TP Pin”. 60 Added Table 28 “LXT971A Thermal Characteristics”.
65 Modified Table 33 “10BASE-T Receive Timing Parameters”
72 Modified Table 42 “Register Bit Map”. (Added Table 26 information). 86 Added Table 57 “Digital Config Register (Address 26)”. 87 Modified Table 58 “Transmit Control Register (Address 30)”. 90 Added Section 8.0, “Product Ordering Information”.
LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver Datasheet 9 Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 Revision 001 Revision Date: January 2001 Page Description N/A Clock Requirements: Modified language under Clock Requirements heading. Table 21 I/O Characteristics REFCLK: Changed values for Input Clock Duty Cycle under Min from 40 to 35 and under Max from 60 to 65.
LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver
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Figure 1. LXT971A Block Diagram
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1.0 Pin Assignments
Figure 2. LXT971A 64-Ball PBGA Assignments
Figure 3. LXT971A 64-Pin LQFP Assignments
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Table 1. LQFP Numeric Pin List
1 REFCLK/XI Input Table 4 on page 18
2 XO Output Table 4 on page 18
3 MDDIS Input Table 2 on page 16
4 RESET Input Table 4 on page 18
5 TxSLEW0 Input Table 4 on page 18
6 TxSLEW1 Input Table 4 on page 18
8 VCCIO – Table 5 on page 19
10 N/C – Table 4 on page 18
11 GND – Table 5 on page 19
12 ADDR0 Input Table 4 on page 18
13 ADDR1 Input Table 4 on page 18
14 ADDR2 Input Table 4 on page 18
15 ADDR3 Input Table 4 on page 18
16 ADDR4 Input Table 4 on page 18
17 RBIAS Analog Input Table 4 on page 18
18 GND – Table 5 on page 19
19 TPFOP Output Table 3 on page 17
20 TPFON Output Table 3 on page 17
21 VCCA – Table 5 on page 19
22 VCCA – Table 5 on page 19
23 TPFIP Input Table 3 on page 17
24 TPFIN Input Table 3 on page 17
25 GND – Table 5 on page 19
26 SD/TP Input Table 3 on page 17
27 TDI Input Table 6 on page 19
28 TDO Output Table 6 on page 19
29 TMS Input Table 6 on page 19
30 TCK Input Table 6 on page 19
31 TRST Input Table 6 on page 19
32 SLEEP Input Table 4 on page 18
33 PAUSE Input Table 4 on page 18
34 GND – Table 5 on page 19
35 GND – Table 5 on page 19
36 LED/CFG3 I/O Table 7 on page 19
37 LED/CFG2 I/O Table 7 on page 19
38 LED/CFG1 I/O Table 7 on page 19
39 PWRDWN Input Table 4 on page 18
40 VCCIO – Table 5 on page 19
41 GND – Table 5 on page 19
42 MDIO I/O Table 2 on page 16
43 MDC Input Table 2 on page 16
44 N/C – Table 4 on page 18
45 RXD3 Output Table 2 on page 16
46 RXD2 Output Table 2 on page 16
47 RXD1 Output Table 2 on page 16
48 RXD0 Output Table 2 on page 16
49 RX_DV Output Table 2 on page 16
50 GND – Table 5 on page 19
51 VCCD – Table 5 on page 19
52 RX_CLK Output Table 2 on page 16
53 RX_ER Output Table 2 on page 16
54 TX_ER Input Table 2 on page 16
55 TX_CLK Output Table 2 on page 16
56 TX_EN Input Table 2 on page 16
57 TXD0 Input Table 2 on page 16
58 TXD1 Input Table 2 on page 16
59 TXD2 Input Table 2 on page 16
60 TXD3 Input Table 2 on page 16
61 GND – Table 5 on page 19
62 COL Output Table 2 on page 16
63 CRS Output Table 2 on page 16
64 MDINT Open Drain Table 2 on page 16
Table 1. LQFP Numeric Pin List (Continued)
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2.0 Signal Descriptions
outputs be left floating, if unused. Table 2. LXT971A MI I Signal Descriptions respect to the TX_CLK. TXD<0> is the least significant bit. data on TXD. This signal must be synchronized to TX_CLK. 2.5 MHz for 10 Mbps operation, 25 MHz for 100 Mbps operation. valid data on RXD. This output is synchronous to RX_CLK. A5 53 RX_ER O Receive Error. Signals a receive error condition has occurred. This output is synchronous to RX_CLK. Section 3.0, “Functional Description”. of carrier, synchronous to RX_CLK.
- Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain
from read and write operations. bit control reverts to the MDIO serial channel. E7 43 MDC I Management Data Clock. Clock for the MDIO serial data channel. Table 3. LXT971A Network Interface Signal Descriptions Twisted-Pair/Fiber Outputs, Positive & Negative. 802.3 compliant pulses onto the line. LVPECL outputs for fiber transceivers. Twisted-Pair/Fiber Inputs, Positive & Negative. differential 100BASE-TX or 10BASE-T signals from the line. LVPECL inputs from fiber transceivers. Normal Operation (FX Mode): SD input from the fiber transceiver.
- Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain
- For standard digital loopback testing (Register bit 0.14) in FX mode, the SD pin should be tied to an
Table 2. LXT971A MII Signal Descriptions (Continued)
- Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain
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Table 4. LXT971A Miscellan eous Signal Descriptions Address <4:0>. Sets device address. H1 17 RBIAS AI Bias. This pin provides bias current for the internal circuitry. capabilities during auto-negotiation. overridden by Register bit 16.6 when in managed mode. Functional Description section.
- Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain.
Table 5. LXT971A Power Supply Signal Descriptions A6 51 VCCD – Digital Power. Requires a 3.3V power supply. on the other side of the MII. G3, G4 21, 22 VCCA – Analog Power. Requires a 3.3V power supply. Table 6. LXT971A JTAG Test Signal Descriptions F6 29 TMS 2 I Test Mode Select. G6 30 TCK 2 I Test Clock. Test clock input sourced by ATE. H6 31 TRST 2 I Test Reset. Test reset input sourced by ATE.
- Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain.
- If JTAG port is not used, these pins do not need to be terminated.
Table 7. LXT971A LED Signal Descriptions (refer to Table 56 on page 85 for details).
- Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain.
- Pull-up/pull-down resistors of 10 k can be implemented if LEDs are used in the design.
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Table 8. LXT971A Pin Types and Modes
- A High Z (High impedance) or three-state determines when the device is drawing a current of less than
- DL = Driven Low (Logic 0), DH = Driven High (Logic 1), IPLD = Internal Pull-Down (Weak)
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet 21 Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002
3.0 Functional Description
3.1 Introduction
The LXT971A is a single-port Fast Ethernet 10/100 transceiver that supports 10 Mbps and 100 Mbps networks and complies with all applicable requirements of IEEE 802.3. The LXT971A directly drives either a 100BASE-TX line (up to 140 meters) or a 10BASE-T line (up to 185 meters). The device also supports 100BASE-FX operation via a Low V oltage PECL (LVPECL) interface.
3.1.1 Comprehensive Functionality
The LXT971A provides a standard Media Independent Interface (MII) for 10/100 MACs. The LXT971A performs all functions of the Physical Coding Sublayer (PCS) and Physical Media Attachment (PMA) sublayer as defined in the IEEE 802.3 100BASE-X standard. This device also performs all functions of the Physical Media Dependent (PMD) sublayer for 100BASE-TX connections. The LXT971A reads its configuration pins on power-up to check for forced operation settings. If not configured for forced operation, the device uses auto-negotiation/parallel detection to automatically determine line operating conditions. If the PHY device on the other side of the link supports auto-negotiation, the LXT971A auto-negotiates with it using Fast Link Pulse (FLP) Bursts. If the PHY partner does not support auto-negotiation, the LXT971A automatically detects the presence of either link pulses (10 Mbps PHY) or Idle symbols (100 Mbps PHY) and sets its operating conditions accordingly. The LXT971A provides half-duplex and full-duplex operation at 100 Mbps and 10 Mbps.
3.1.2 OSP™ Architecture
The LXT971A incorporates high-efficiency Optimal Signal Processing™ design techniques, combining the best properties of digital and analog signal processing to produce a truly optimal device. The receiver utilizes decision feedback equalization to increase noise and cross-talk immunity by as much as 3 dB over an ideal all-analog equalizer. Using OSP mixed-signal processing techniques in the receive equalizer avoids the quantization noise and calculation truncation errors found in traditional DSP-based receivers (typically complex DSP engines with A/D converters). This results in improved receiver noise and cross-talk performance. The OSP signal processing scheme also requires substantially less computational logic than traditional DSP-based designs. This lowers power consumption and also reduces the logic switching noise generated by DSP engines. This logic switching noise can be a considerable source of EMI generated on the device’s power supplies. The OSP-based LXT971A provides improved data recovery, EMI performance and low power consumption.
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
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3.2 Network Media / Protocol Support
The LXT971A supports both 10BASE-T and 100BASE-TX Ethernet over twisted-pair, or 100 Mbps Ethernet over fiber media (100BASE-FX). 3.2.1 10/100 Netw ork Interface The network interface port consists of five external pins (two differential signal pairs and a signal detect pin). The I/O pins are shared between twisted-pair (TP) and fiber. Refer to Figure 3 on page 13 for specific pin assignments. The LXT971A output drivers generate either 100BASE-TX, 10BASE-T, or 100BASE-FX output. When not transmitting data, the LXT971A generates 802.3-compliant link pulses or idle code. Input signals are decoded either as a 100BASE-TX, 100BASE-FX, or 10BASE-T input, depending on the mode selected. Auto-negotiation/parallel detection or manual control is used to determine the speed of this interface.
3.2.1.1 Twisted-Pair Interface
The LXT971A supports either 100BASE-TX or 10BASE-T connections over 100Ω, Category 5, Unshielded Twisted Pair (UTP) cable. When operating at 100 Mbps, the LXT971A continuously transmits and receives MLT3 symbols. When not transmitting data, the LXT971A generates “IDLE” symbols. During 10 Mbps operation, Manchester-encoded data is exchanged. When no data is being exchanged, the line is left in an idle state. Link pulses are transmitted periodically to keep the link up. Only a transformer, RJ-45 connector, load resistor, and bypass capacitors are required to complete this interface. On the transmit side, the LXT971A has an active internal termination and does not require external termination resistors. Intel's patented waveshaping technology shapes the outgoing signal to help reduce the need for external EMI filters. Four slew rate settings (refer to Table 4 on page 18) allow the designer to match the output waveform to the magnetic characteristics. On the receive side, the internal impedance is high enough that it has no practical effect on the external termination circuit.
3.2.1.2 Fiber Interface
The LXT971A fiber port is designed to interface with common industry-standard fiber modules. It incorporates a Low V oltage PECL interface that complies with the ANSI X3.166 standard for seamless integration. Fiber mode is selected through Register bit 16.0 by the following two methods: 1. Drive the SD input to a valu e greater than 600 mV during power-up and reset states (all LVPECL signaling levels from a fiber transceiver are acceptable). 2. Configure Register bit 16.0 = 1 through the MDIO interface.
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet 23 Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002
3.2.1.3 Fault Detection and Reporting
The LXT971A supports two fault detection and reporting mechanisms. “Remote Fault” refers to a MAC-to-MAC communication function that is essentially transparent to PHY layer devices. It is used only during auto-negotiation, and is applicable only to twisted-pair links. “Far-End Fault” is an optional PMA-layer function that may be embedded within PHY devices. The LXT971A
3.2.1.3.1 Remote Fault
Register bit 4.13 in the Auto-Negotiation Advertisement Register is reserved for Remote Fault indications. It is typically used when re-starting the auto-negotiation sequence to indicate to the link partner that the link is down because the advertising device detected a fault. When the LXT971A receives a Remote Fault indication from its partner during auto-negotiation it does the following:
- Sets Register bit 5.13 in the Link Partner Base Page Ability Register, and
- Sets the Remote Fault Register bit 1.4 in the MII Status Register to pass this information to the local controller. 3.2.1.3.2 100BASE-FX Far-End Fault The SD/TP pin monitors signal quality during normal operation in fiber mode. If the signal quality degrades beyond the fault threshold, the fiber transceiver reports a signal quality fault condition via the SD/TP pin. Loss of signal quality blocks any fiber data from being received and causes a link loss. If the LXT971A detects a signal fault condition, it can transmit the Far-End Fault Indication (FEFI) over the fiber link. The FEFI consists of 84 consecutive ones followed by a single zero. This pattern must be repeated at least three times. The LXT971A transmits the far-end fault code a minimum of three times if all the following conditions are true:
- Fiber mode is selected.
- Fault Code transmission is enabled (Register bit 16.2 = 1).
- Either Signal Detect indicates no signal or the receive PLL cannot lock.
- Loopback is not enabled.
3.2.2 MII Data Interface
The LXT971A supports a standard Media Independent Interface (MII). The MII consists of a data interface and a management interface. The MII Data Interface passes data between the LXT971A and a Media Access Controller (MAC). Separate parallel buses are provided for transmit and receive. This interface operates at either 10 Mbps or 100 Mbps. The speed is set automatically, once the operating conditions of the network link have been determined. Refer to “MII Operation” on page 32 for additional details.
3.2.2.1 Increased MII Drive Strength
A higher Media Independent Interface (MII) drive strength may be desired in some designs to drive signals over longer PCB trace lengths, or over high-capacitive loads, through multiple vias, or through a connector. The MII drive strength in the LXT971A can be increased by setting Register
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3.2.3 Configuration Management Interface
configuration and management.
3.2.3.1 MDIO Management Interface
an “X.Y” notation, where X is the register number (0-31) and Y is the bit number (0-15). operations are disabled and the Hardware Control Interface provides primary configuration control. Hardware Control Interface is not used.
3.2.3.1.1 MDIO Addressing
ADDR<4:0> determine the chip address.
3.2.3.1.2 MDIO Frame Structure
Figure 4. Management Interface Read Frame Structure
3.2.3.1.3 MII Interrupts
- Auto-negotiation complete
- Speed status change
- Duplex status change
- Link status change
3.2.3.2 Hardware Control Interface
desired. The Hardware Control Interface uses the three LED driver pins to set device configuration. Refer to the Hardware Configuration Settings section on page 30 for additional details. Figure 5. Management Interface Write Frame Structure Figure 6. Interrupt Logic
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3.3 Operating Requirements
3.3.1 Power Requirements
The LXT971A requires three power supply inputs (VCCD, VCCA, and VCCIO). The digital and analog circuits require 3.3V supplies (VCCD and VCCA). These inputs may be supplied from a single source. Each supply input must be de-coupled to ground. An additional supply may be used for the MII (VCCIO). The supply may be either +2.5V or +3.3V . Also, the inputs on the MII interface are tolerant to 5V signals from the controller on the other side of the MII interface. Refer to Table 20 on page 57 for MII I/O characteristics. As a matter of good practice, these supplies should be as clean as possible.
3.3.2 Clock Requirements
3.3.2.1 External Crystal/Oscillator
The LXT971A requires a reference clock input that is used to generate transmit signals and recover receive signals. It may be provided by either of two methods: by connecting a crystal across the oscillator pins (XI and XO), or by connecting an external clock source to pin XI. The connection of a clock source to the XI pin requires the XO pin to be left open. A crystal-based clock is recommended over a derived clock (i.e., PLL-based) to minimize transmit jitter. Refer to the LXT971A/972A Design and Layout Guide for a list of recommended clock sources. A crystal is typically used in NIC applications. An external 25 MHz clock source, rather than a crystal, is frequently used in switch applications. Refer to Table 21 on page 57 for clock timing requirements.
3.3.2.2 MDIO Clock
The MII management channel (MDIO) also requires an external clock. The managed data clock (MDC) speed is a maximum of 8 MHz. Refer to Table 38 on page 69 for details.
3.4 Initialization
When the LXT971A is first powered on, reset, or encounters a link failure state, it checks the MDIO register configuration bits to determine the line speed and operating conditions to use for the network link. The configuration bits may be set by the Hardware Control or MDIO interface as shown in Figure 7.
3.4.1 MDIO Control Mode
In the MDIO Control mode, the LXT971A reads the Hardware Control Interface pins to set the initial (default) values of the MDIO registers. Once the initial values are set, bit control reverts to the MDIO interface.
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet 27 Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002
3.4.2 Hardware Control Mode
In the Hardware Control Mode, LXT971A disables direct write operations to the MDIO registers via the MDIO Interface. On power-up or hardware reset the LXT971A reads the Hardware Control Interface pins and sets the MDIO registers accordingly. The following modes are available using either Hardware Control or MDIO Control:
- Force network link to 100FX (Fiber).
- Force network link operation to: — 100BASE-TX, Full-Duplex. — 100BASE-TX, Half-Duplex. — 10BASE-T, Full-Duplex. — 10BASE-T, Half-Duplex.
- Allow auto-negotiation/parallel-detection. When the network link is forced to a specific configuration, the LXT971A immediately begins operating the network interface as commanded. When auto-negotiation is enabled, the LXT971A begins the auto-negotiation/parallel-detection operation.
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3.4.3 Reduced Power Modes
The LXT971A offers two power-down modes and a sleep mode.
3.4.3.1 Hardware Power Down
- The LXT971A network port and clock are shut down.
- All outputs are three-stated.
- All weak pad pull-up and pull-down resistors are disabled.
- The MDIO registers are not accessible.
Figure 7. Initialization Sequence
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet 29 Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002
3.4.3.2 Software Power Down
Software power-down control is provided by Register bit 0.11 in the Control Register (refer to Table 43 on page 74). During soft power-down, the following conditions are true:
- The network port is shut down.
- The MDIO registers remain accessible.
3.4.3.3 Sleep Mode
The LXT971A supports a power-saving sleep mode. Sleep mode is enabled when SLEEP is asserted via pin 32(LQFP)/H7(PBGA). The value of pin 32/H7 can be overridden by Register bit 16.6 when in managed mode as shown in Table 4 on page 18. The LXT971A enters into sleep mode when SLEEP is enabled and no energy is detected on the twisted-pair input for 1-3 seconds (the time is controlled by Register bits 16.4:3 in the Configuration Register, with a default of 3.04 seconds). During this mode, the LXT971A still responds to management transactions (MDC/MDIO). In this mode the power consumption is minimized, and the supply current is reduced below the maximum value given in Table 18 on page 56. If the LXT971A detects activity on the twisted-pair inputs, it comes out of the sleep state and check for link. If no link is detected in 1-3 seconds (programmable) it reverts back to the low power sleep state. Note: Sleep Mode is not functional in fiber network applications.
3.4.4 Reset
The LXT971A provides both hardware and software resets. Configuration control of auto- negotiation, speed, and duplex mode selection is handled differently for each. During a hardware reset, auto-negotiation and speed configuration settings are read in from pins (refer to Table 9 on page 30 for pin settings and to Table 43 on page 74 for register bit definitions). During a software reset (0.15 = 1), these bit settings are not re-read from the pins. They revert back to the values that were read in during the last hardware reset. Therefore, any changes to pin values made since the last hardware reset is not detected during a software reset. During a hardware reset, register information is unavailable for 1 ms after de-assertion of the reset. During a software reset (0.15 = 1) the registers are available for reading. The reset bit should be polled to see when the part has completed reset (0.15 = 0).
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3.4.5 Hardware Configuration Settings
LED drivers can operate as either open-drain or open-source circuits as shown in Figure 8. Figure 8. Hardware Configuration Settings Table 9. Hardware Configuration Settings
- Refer to Table 7 on page 19 for LED/CFG pin assignments.
- The LED/CFG pins auto matically adjust their
polarity upon power-up or reset.
- Unused LEDs may be implemented with pull-up/
pull-down resistors of 10 K.
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet 31 Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002
3.5 Establishing Link
See Figure 9 for an overview of link establishment.
3.5.1 Auto-Negotiation
If not configured for forced operation, the LXT971A attempts to auto-negotiate with its link partner by sending Fast Link Pulse (FLP) bursts. Each burst consists of up to 33 link pulses spaced 62.5 µs apart. Odd link pulses (clock pulses) are always present. Even link pulses (data pulses) may be present or absent to indicate a “1” or a “0”. Each FLP burst exchanges 16 bits of data, which are referred to as a “link code word”. All devices that support auto-negotiation must implement the “Base Page” defined by IEEE 802.3 (registers 4 and 5). LXT971A also supports the optional “Next Page” function as described in Tables 50 and 51 on page 80 (registers 7 and 8).
3.5.1.1 Base Page Exchange
By exchanging Base Pages, the LXT971A and its link partner communicate their capabilities to each other. Both sides must receive at least three identical base pages for negotiation to continue. Each side identifies the highest common capabilities that both sides support and configures itself accordingly.
3.5.1.2 Next Page Exchange
Additional information, above that required by base page exchange is also sent via “Next Pages”. The LXT971A fully supports the IEEE 802.3ab method of negotiation via Next Page exchange.
3.5.1.3 Controlling Auto-Negotiation
When auto-negotiation is controlled by software, the following steps are recommended:
- After power-up, power-down, or reset, the power-down recovery time, as specified in Table 40 on page 70, must be exhausted before proceeding.
- Set the Auto-Negotiation Advertisement Register bits.
- Enable auto-negotiation (set MDIO Register bit 0.12 = 1).
3.5.2 Parallel Detection
For the parallel detection feature of auto-negotiation, the LXT971A also monitors for 10BASE-T Normal Link Pulses (NLP) and 100BASE-TX Idle symbols. If either is detected, the device automatically reverts to the corresponding operating mode. Parallel detection allows the LXT971A to communicate with devices that do not support auto-negotiation.
32 Datasheet
3.6 MII Operation
data from the MAC: TXD<3:0>, TX_CLK, TX_EN, and TX_ER. collision. Data transmission across the MII is normally implemented in 4-bit-wide nibbles.
3.6.1 MII Clocks
Mbps, the clocks are set to 2.5 MHz. Figures 10 through 12 show the clock cycles for each mode. LXT971A samples these signals on the rising edge of TX_CLK. Figure 9. Link Establishment Overview
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet 33 Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002
3.6.2 Transmit Enable
The MAC must assert TX_EN the same time as the first nibble of preamble, and de-assert TX_EN after the last bit of the packet.
3.6.3 Receive Data Valid
The LXT971A asserts RX_DV when it receives a valid packet. Timing changes depend on line operating speed:
- For 100BASE-TX links, RX_DV is asserted from the first nibble of preamble to the last nibble of the data packet.
- For 10BT links, the entire preamble is truncated. RX_DV is asserted with the first nibble of the Start of Frame Delimiter (SFD) “5D” and remains asserted until the end of the packet.
3.6.4 Carrier Sense
Carrier Sense (CRS) is an asynchronous output. It is always generated when a packet is received from the line and in half-duplex mode when a packet is transmitted. Table 10 summarizes the conditions for assertion of carrier sense, collision, and data loopback signals. Carrier sense is not generated when a packet is transmitted and in full-duplex mode.
3.6.5 Error Signals
When LXT971A is in 100 Mbps mode and receives an invalid symbol from the network, it asserts RX_ER and drives “1110” on the RXD pins. When the MAC asserts TX_ER, the LXT971A drives “H” symbols out on the TPFOP/N pins.
3.6.6 Collision
The LXT971A asserts its collision signal, asynchronously to any clock, whenever the line state is half-duplex and the transmitter and receiver are active at the same time. Table 10 summarizes the conditions for assertion of carrier sense, collision, and data loopback signals.
34 Datasheet
3.6.7 Loopback
paths are shown in Figure 13. Figure 10. 10BASE-T Clocking Figure 11. 100BASE-X Clocking Figure 12. Link Down Clock Transition
2.5 MHz during auto-negotiation and 10BASE-T Data & Idle
2.5 MHz during auto-negotiation
25 MHz once 100BASE-X
2.5 MHz during auto-negotiation 25 MHz once 100BASE-X
100 Mbps = 25 MHz
3.6.7.1 Operational Loopback
transmitted by the MAC (TXData) is looped back on the receive side of the MII (RXData). Operational loopback is not provided for 100 Mbps links, full-duplex links, or when 16.8 = 1.
3.6.7.2 Test Loopback
back by the LXT971A and returned to the MAC.
- Register bit 0.14 = 1
- Register bit 0.8 = 1 (full-duplex)
- Register bit 0.12 = 0 (disable auto-negotiation). Test loopback is also available for 100BASE-FX operation. Test loopback in this mode is enabled by setting Register bit 0.14 = 1 and tying the SD input to an LVPECL logic High value (2.4 V).
Figure 13. Loopback Paths
36 Datasheet
actively transmitting data, the LXT971A sends out Idle symbols on the line. decoded, and sent across the MII to the MAC. enable 100BASE-FX operation, auto-negotiation must be disabled and FX selected. Table 10. Carrier Sense, Loopback, and Collision Conditions
100 Mbps
10 Mbps
- Test Loopback is enabled when 0.14 = 1
Figure 14. 100BASE-X Frame Format
38 Datasheet
3.7.2 Collision Indication
and remains asserted for the duration of the collision as shown in Figure 19. the reference model point of view.
3.7.3.1 PCS Sublayer
line driver as long as TX_EN is de-asserted.
3.7.3.1.1 Preamble Handling
then returns to supplying IDLE symbols to the line driver. Figure 18. 100BASE-TX Transmission with No Errors Figure 19. 100BASE-TX Transmission with Collision
3.7.3.1.2 Dribble Bits
received, the second nibble is not sent to the MII bus. Figure 20. Protocol Sublayers
40 Datasheet
Table 11. 4B/5B Coding
- The /I/ (Idle) code group is sent continuously between frames.
- The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/.
- The /T/ and /R/ (ESD) code groups are always sent in pairs; /R/ follows /T/.
- An /H/ (Error) code group is used to signal an error condition.
3.7.3.2 PMA Sublayer
3.7.3.2.1 Link
robust link, essentially filtering out any small noise hits that may otherwise disrupt the link. Furthermore, 100 Mbps idle patterns will not bring up a 10 Mbps link. functions. Link failure causes the LXT971A to re-negotiate if auto-negotiation is enabled.
3.7.3.2.2 Link Failure Override
LXT971A automatically transmits FLP bursts if the link is down.
3.7.3.2.3 Carrier Sense
however, in this case RX_ER is asserted for one clock cycle when CRS is de-asserted. Table 11. 4B/5B Coding (Continued)
- The /I/ (Idle) code group is sent continuously between frames.
- The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/.
- The /T/ and /R/ (ESD) code groups are always sent in pairs; /R/ follows /T/.
- An /H/ (Error) code group is used to signal an error condition.
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
42 Datasheet
Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002
- De-assertion time for CRS is slightly longer than assertion time. This causes IFG intervals to appear somewhat shorter to the MAC than it actually is on the wire.
- CRS de-assertion is not aligned with TX_EN de-assertion on transmit loopbacks in half- duplex mode.
3.7.3.2.4 Receive Data Valid
The LXT971A asserts RX_DV to indicate that the received data maps to valid symbols. However, RXD outputs zeros until the received data is decoded and available for transfer to the controller.
3.7.3.3 Twisted-Pair PMD Sublayer
The twisted-pair Physical Medium Dependent (PMD) layer provides the signal scrambling and de- scrambling, line coding and decoding (MLT-3 for 100BASE-TX, Manchester for 10BASE-T), as well as receiving, polarity correction, and baseline wander correction functions. Scrambler/De-scrambler The purpose of the scrambler is to spread the signal power spectrum and further reduce EMI using an 11-bit, data-independent polynomial. The receiver automatically decodes the polynomial whenever IDLE symbols are received. Scrambler Seeding Once the transmit data (or Idle symbols) are properly encoded, they are scrambled to further reduce EMI and to spread the power spectrum using an 11-bit scrambler seed. Five seed bits are determined by the PHY address, and the remaining bits are hard coded in the design. Scrambler Bypass The scrambler/de-scrambler can be bypassed by setting Register bit 16.12 = 1. The scrambler is automatically bypassed when the fiber port is enabled. Scrambler bypass is provided for diagnostic and test support.
3.7.3.3.1 Baseline Wander Correction
The LXT971A provides a baseline wander correction function which makes the device robust under all network operating conditions. The MLT3 coding scheme used in 100BASE-TX is by definition “unbalanced”. This means that the average value of the signal voltage can “wander” significantly over short time intervals (tenths of seconds). This wander can cause receiver errors at long-line lengths (100 meters) in less robust designs. Exact characteristics of the wander are completely data dependent. The LXT971A baseline wander correction characteristics allow the device to recover error-free data while receiving worst-case “killer” packets over all cable lengths.
3.7.3.3.2 Polarity Correction
The 100BASE-TX de-scrambler automatically detects and corrects for the condition where the receive signal at TPFIP and TPFIN is inverted.
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet 43 Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002
3.7.3.3.3 Programmable Slew Rate Control
The LXT971A device supports a slew rate mechanism whereby one of four pre-selected slew rates can be used. This allows the designer to optimize the output waveform to match the characteristics of the magnetics. The slew rate is determined by the TxSLEW pins as shown in Table 4 on page 18.
3.7.3.4 Fiber PMD Sublayer
The LXT971A provides a Low V oltage PECL interface for connection to an external 3.3 V or 5.0 V fiber-optic transceiver. (The external transceiver provides the PMD function for fiber media.) The LXT971A uses an NRZI format for the fiber interface. The fiber interface operates at 100 Mbps and does not support 10FL applications. 3.8 10 Mbps Operation The LXT971A operates as a standard 10BASE-T transceiver. The LXT971A supports all the standard 10 Mbps functions. During 10BASE-T operation, the LXT971A transmits and receives Manchester-encoded data across the network link. When the MAC is not actively transmitting data, the LXT971A drives link pulses onto the line. In 10BASE-T mode, the polynomial scrambler/de-scrambler is inactive. Manchester-encoded signals received from the network are decoded by the LXT971A and sent across the MII to the MAC. The LXT971A does not support fiber connections at 10 Mbps. 3.8.1 10BASE-T Preamble Handling The LXT971A offers two options for preamble handling, selected by Register bit 16.5. In 10BASE-T Mode when 16.5 = 0, the LXT971A strips the entire preamble off of received packets. CRS is asserted coincident with SFD. RX_DV is held Low for the duration of the preamble. When RX_DV is asserted, the very first two nibbles driven by the LXT971A are the SFD “5D” hex followed by the body of the packet. In 10BASE-T mode with 16.5 = 1, the LXT971A passes the preamble through the MII and asserts RX_DV and CRS simultaneously. In 10BASE-T loopback, the LXT971A loops back whatever the MAC transmits to it, including the preamble. 3.8.2 10BASE-T Carrier Sense For 10BASE-T links, CRS assertion is based on reception of valid preamble, and de-assertion on reception of an end-of-frame (EOF) marker. Register bit 16.7 allows CRS de-assertion to be synchronized with RX_DV de-assertion. Refer to Table 52 on page 81. 3.8.3 10BASE-T Dribble Bits The LXT971A device handles dribbles bits in all modes. If one to four dribble bits are received, the nibble is passed across the MII, padded with ones if necessary. If five to seven dribble bits are received, the second nibble is not sent to the MII bus.
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
44 Datasheet
Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 3.8.4 10BASE-T Link Integrity Test In 10BASE-T mode, the LXT971A always transmits link pulses. When the Link Integrity Test function is enabled (the normal configuration), it monitors the connection for link pulses. Once link pulses are detected, data transmission is enabled and remains enabled as long as either the link pulses or data transmission continue. If the link pulses stop, the data transmission is disabled. If the Link Integrity Test function is disabled, the LXT971A transmits to the connection regardless of detected link pulses. The Link Integrity Test function can be disabled by setting Register bit 16.14 = 1.
3.8.4.1 Link Failure
Link failure occurs if the Link Integrity Test is enabled and link pulses or packets stop being received. If this condition occurs, the LXT971A returns to the auto-negotiation phase if auto- negotiation is enabled. If the Link Integrity Test function is disabled by setting Register bit 16.14 = 1 in the Configuration Register, the LXT971A transmits packets, regardless of link status. 3.8.5 10BASE-T SQE (Heartbeat) By default, the Signal Quality Error (SQE) or heartbeat function is disabled on the LXT971A. To enable this function, set Register bit 16.9 = 1. When this function is enabled, the LXT971A asserts its COL output for 5-15 BT after each packet. See Figure 35 on page 67 for SQE timing parameters. 3.8.6 10BASE-T Jabber If a transmission exceeds the jabber timer, the LXT971A disables the transmit and loopback functions. See Figure 34 on page 67 for jabber timing parameters. The LXT971A automatically exits jabber mode after the unjabber time has expired. This function can be disabled by setting Register bit 16.10 = 1. 3.8.7 10BASE-T Polarity Correction The LXT971A automatically detects and corrects for the condition where the receive signal (TPFIP/N) is inverted. Reversed polarity is detected if eight inverted link pulses, or four inverted end-of-frame (EOF) markers, are received consecutively. If link pulses or data are not received by the maximum receive time-out period (96-128 ms), the polarity state is reset to a non-inverted state.
3.9 Monitoring Operations
3.9.1 Monitoring Auto-Negotiation
Auto-negotiation can be monitored as follows:
- Register bit 17.7 is set to 1 once the auto-negotiation process is completed.
- Register bits 1.2 and 17.10 are set to 1 once the link is established.
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet 45 Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002
- Register bits 17.14 and 17.9 can be used to determine the link operating conditions (speed and duplex).
3.9.1.1 Monitoring Next Page Exchange
The LXT971A offers an Alternate Next Page mode to simplify the next page exchange process. Normally, Register bit 6.1 (Page Received) remains set until read. When Alternate Next Page mode is enabled Register bit 6.1 is automatically cleared whenever a new negotiation process takes place. This prevents the user from reading an old value in 6.1 and assuming that Registers 5 and 8 (Partner Ability) contain valid information. Additionally, the LXT971A uses Register bit 6.5 to indicate when the current received page is the base page. This information is useful for recognizing when next pages must be resent due to a new negotiation process starting. Register bits 6.1 and 6.5 are cleared when read.
3.9.2 LED Functions
The LXT971A incorporates three direct LED drivers. On power up all the drivers are asserted for approximately 1 second after reset de-asserts. Each LED driver can be programmed using the LED Configuration Register (refer to Table 56 on page 85) to indicate one of the following conditions:
- Operating Speed
- Transmit Activity
- Receive Activity
- Collision Condition
- Link Status
- Duplex Mode The LED drivers can also be programmed to display various combined status conditions. For example, setting Register bits 20.15:12 = 1101 produces the following combination of Link and Activity indications:
- If Link is down LED is off.
- If Link is up LED is on.
- If Link is up and activity is detected, the LED blinks at the stretch interval selected by Register bits 20.3:2 and continues to blink as long as activity is present. The LED driver pins also provide initial configuration settings. The LED pins are sensitive to polarity and automatically pull up or pull down to configure for either open drain or open collector circuits (10 mA Max current rating) as required by the hardware configuration. Refer to the discussion of “Hardware Configuration Settings” on page 30 for details.
3.9.2.1 LED Pulse Stretching
The LED Configuration Register also provides optional LED pulse stretching to 30, 60, or 100 ms. The pulse stretch time is further extended if the event occurs again during this pulse stretch period. When an event such as receiving a packet occurs it is edge detected and it starts the stretch timer. The LED driver remains asserted until the stretch timer expires. If another event occurs before the stretch timer expires then the stretch timer is reset and the stretch time is extended.
46 Datasheet
When a long event (such as duplex status) occurs it is edge detected and it starts the stretch timer. remain asserted. Figure 21 shows how the stretch operation functions. sales office or by accessing the Intel website (www.intel.com).
3.10.1 Boundary Scan Interface
internally pulled down. TDO does not have an internal pull-up or pull-down.
3.10.2 State Machine
3.10.3 Instruction Register
instructions are listed in Table 13.
3.10.4 Boundary Scan Register (BSR)
Figure 21. LED Pulse Stretching Note: The direct drive LED outputs in this diagram are shown as active Low.
Table 12. BSR Mode of Operation
3 Update
4 System Function
Table 13. Supported JTAG Instructions Table 14. Device ID Register
- The JEDEC IS is an 8-bit identifier. The MSB is for parity and is ignored. Intel’s JEDEC ID is FE
- See the LXT971A/972A Specification Update (document number 249354) for the current version of the
Jedec continuation characters.
48 Datasheet
4.0 Application Information
4.1 Magnetics Information
connectors and cables. Refer to Table 15 for transformer requirements.
4.2 Typical Twisted-Pair Interface
typical twisted-pair interface setting. the RJ-45 connections configured for a NIC application. Table 15. Magnetics Requirements Table 16. I/O Pin Comparison of NIC and Switch RJ-45 Setups
Figure 22. Typical Twisted-Pair Interface - Switch
- Center-tap current may be supplied from 3.3 V VCCA as shown. Additional power savings
bead (rated at 50 mA) should be used to supply center-tap current.
- The 100 Ω transmit load termination resistor typically required is integrated in the
- Magnetics without a receive pair center-tap do not require a 2 kV termination.
- RJ-45 connections shown are for a standard switch application. For a standard NIC RJ-45
setup, see Figure 23 on page 50.
50 Datasheet
Figure 23. Typical Twisted-Pair Interface - NIC
- Center-tap current may be supplied from 3.3 V VCCA as shown. Additional power savings may
(rated at 50 mA) should be used to supply center-tap current.
- The 100 Ω transmit load termination resistor typically required is integrated in the LXT971A.
- Magnetics without a receive pair center-tap do not require a 2 kV termination.
- RJ-45 connections shown for standard NIC. TX/RX crossover may be required for repeater and
Figure 24. Typical MII Interface
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
52 Datasheet
Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002
4.3 The Fiber Interface
The fiber interface consists of an LVPECL transmit and receive pair to an external fiber-optic transceiver. Both 3.3 V fiber-optic transceivers and 5 V fiber-optic transceivers can be used with the LXT971A. The following should occur in 3.3 V fiber transceiver applications as shown in Figure 25:
- The transmit pair should be DC-coupled with the 50 Ω/16 Ω pull-up combination
- The receive pair should be DC-coupled with an emitter current path for the fiber transceiver
- The signal detect pin should be DC-coupled with an emitter current path for the fiber transceiver Refer to the fiber transceiver manufacturer’s recommendations for termination circuitry. Figure 25 shows a typical example of an LXT971A-to-3.3 V fiber transceiver interface. The following occurs in 5 V fiber transceiver applications as shown in Figure 26:
- The transmit pair should be AC-coupled and re-biased to 5 V PECL input levels
- The receive pair should be AC-coupled with an emitter current path for the fiber transceiver and re-biased to 3.3 V LVPECL input levels. The signal detect pin on a 5 V fiber transceiver interface should use the logic translator circuitry as shown in Figure 27. Refer to the fiber transceiver manufacturer’s recommendations for termination circuitry. Figure 26 shows a typical example of an LXT971A-to-5 V fiber transceiver interface, while Figure 27 shows the interface circuitry for the logic translator.
Figure 25. Typical LXT971A-to-3.3 V Fiber Transceiver Interface Circuitry
- Refer to the transceiver manufacturer’s recommendations for termination circuitry.
54 Datasheet
Figure 26. Typical LXT971A-to-5 V Fiber Transceiver Interface Circuitry
- Refer to the transceiver manufacturer’s recommendations for termination circuitry.
- See Figure 27 for recommended logic translator interface circuitry.
Figure 27. ON Semiconductor Triple PECL-to-LVPECL Translator
56 Datasheet
5.0 Test Specifications
recommended operating conditions specified in Table 18.
5.1 Electrical Parameters
Table 17. Absolute Maximum Ratings Caution: Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Table 18. Operating Conditions
- Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
- Voltages with respect to ground unless otherwise specified.
Table 19. Digital I/O Characteristics 2
- Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
- Applies to all pins except MII, LED, XI/XO, and SD/TP pins. Refer to Table 20 for MII I/O Characteristics,
Table 21 for XI/XO and Table 22 for LED Characteristics. Table 20. Digital I/O Characteristics - MII Pins
- Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
- Parameter is guaranteed by design; not subject to production testing.
Table 21. I/O Characteristics - REFCLK/XI and XO Pins
- Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
- Parameter is guaranteed by design; not subject to production testing.
58 Datasheet
Table 22. I/O Characteristics - LED/CFG Pins Table 23. I/O Characteristics – SD/TP Pin
- Typical values are for design aid only; not guaranteed and not subject to production testing.
Table 24. 100BASE-TX Transceiver Characteristics
- Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
- Measured at the line side of the transformer, line replaced by 100Ω(+/-1%) resistor.
Table 25. 100BASE-FX Transceiver Characteristics
- Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
Table 26. 10BASE-T Transceiver Characteristics Table 27. 10BASE-T Link Integrity Timing Characteristics
- Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
60 Datasheet
Table 28. LXT971A Thermal Characteristics
5.2 Timing Diagrams
Figure 28. 100BASE-TX Receive Timing - 4B Mode Table 29. 100BASE-TX Receive Timing Parameters - 4B Mode
- Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
- BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate.
62 Datasheet
Figure 29. 100BASE-TX Transmit Timing - 4B Mode Table 30. 100BASE-TX Transmit Timing Parameters - 4B Mode
- Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
- BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate.
Figure 30. 100BASE-FX Receive Timing Table 31. 100BASE-FX Receive Timing Parameters
- Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
- BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate.
64 Datasheet
Figure 31. 100BASE-FX Transmit Timing Table 32. 100BASE-FX Transmit Timing Parameters
- Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
- BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate.
Figure 32. 10BASE-T Receive Timing Table 33. 10BASE-T Receive Timing Parameters
- Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
- BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate.
66 Datasheet
Figure 33. 10BASE-T Transmit Timing Table 34. 10BASE-T Transmit Timing Parameters
- Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
- BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate.
68 Datasheet
Figure 36. Auto-Negotiation and Fast Link Pulse Timing Figure 37. Fast Link Pulse Timing Table 37. Auto-Negotiation and Fast Link Pulse Timing Parameters
- Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
70 Datasheet
Figure 40. Power-Up Timing Table 39. Power-Up Timing Parameters
- Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production
- Power-up delay is specified as a maximum value because it refers to the PHY guaranteed performance -
Figure 41. RESET Pulse Width and Recovery Timing Table 40. RESET Pulse Width and Recovery Timing Parameters
- Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production
- Reset Recovery Delay is specified as a maximum value because it refers to the PHY guaranteed
Than 300 µs before accessing the MDIO port.
6.0 Register Definitions
individual register definitions. Negotiation” sections of the IEEE 802.3 standard. Table 41. Register Set
0 Control Register Refer to Table 43 on page 74
1 Status Register #1 Refer to Table 44 on page 75
2 PHY Identification Register 1 Refer to Table 45 on page 76
3 PHY Identification Register 2 Refer to Table 46 on page 76
4 Auto-Negotiation Advertisement Register Refer to Table 47 on page 77
5 Auto-Negotiation Link Partner Base Page Ability Register Refer to Table 48 on page 78
6 Auto-Negotiation Expansion Register Refer to Table 49 on page 79
7 Auto-Negotiation Next Page Transmit Register Refer to Table 50 on page 79
8 Auto-Negotiation Link Partner Received Next Page Register Refer to Table 51 on page 80
15 Extended Status Register Not Implemented
16 Port Configuration Register Refer to Table 52 on page 81
17 Status Register #2 Refer to Table 53 on page 82
18 Interrupt Enable Register Refer to Table 54 on page 83
19 Interrupt Status Register Refer to Table 55 on page 84
20 LED Configuration Register Refer to Table 56 on page 85
26 Digital Config Register Refer to Table 57 on page 86
30 Transmit Control Register Refer to Table 58 on page 87
72 Datasheet
Table 42. Register Bit Map
Table 42. Register Bit Map (Continued)
74 Datasheet
Table 43. Control Register (Address 0)
0.15 Reset 1 = PHY reset
0.14 Loopback 1 = Enable loopback mode
0.13 Speed Selection
1000 Mbps (not supported)
0.12 Auto-Negotiation
0.11 Power-Down 1 = Power-down
0.10 Isolate 1 = Electrically isolate PHY from MII
0.9 Restart
0.8 Duplex Mode 1 = Full-duplex
0.7 Collision Test 1 = Enable COL signal test
0.6 Speed Selection
- Default value of Register bits 0.12, 0.13 and 0.8 are determined by the LED/CFG
Table 44. MII Status Register #1 (Address 1)
1.8 Extended Status 1 = Extended status information in register 15
1.7 Reserved 1 = ignore when read RO 0
1.6 MF Preamble
1.5 Auto-Negotiation
1.4 Remote Fault 1 = Remote fault condition detected
1.3 Auto-Negotiation Ability 1 = PHY is able to perform auto-negotiation
1.2 Link Status 1 = Link is up
1.1 Jabber Detect 1 = Jabber condition detected
1.0 Extended Capability 1 = Extended register capabilities
76 Datasheet
Table 45. PHY Identification Register 1 (Address 2) Table 46. PHY Identification Register 2 (Address 3) Figure 42. PHY Identifier Bit Mapping
Table 47. Auto-Negotiation Advertisement Register (Address 4) 4.15 Next Page 1 = Port has ability to send multiple pages. 4.13 Remote Fault 1 = Remote fault.
4.11 Asymmetric
4.10 Pause 1 = Pause operation enabled for full-duplex links. 1 = 100BASE-T4 capability is available. 0 = 100BASE-T4 capability is not available. 1 = Port is 100BASE-TX full-duplex capable. 4.7 100BASE-TX 1 = Port is 100BASE-TX capable. 1 = Port is 10BASE-T full-duplex capable. 4.5 10BASE-T 1 = Port is 10BASE-T capable.
- The default setting of Register bit 4.10 (PAUSE) is determined by pin 33/H8 at reset.
78 Datasheet
Table 48. Auto-Negotiation Link Partner Base Page Ability Register (Address 5) 5.15 Next Page 1 = Link Partner has ability to send multiple pages.
5.14 Acknowledge
5.13 Remote Fault 1 = Remote fault.
5.11 Asymmetric
Pause operation defined in Clause 40 and 27. 1 = Link Partner is Pause capable. 0 = Link Partner is not Pause capable. 5.10 Pause 1 = Link Partner is Pause capable. 5.9 100BASE-T4 1 = Link Partner is 100BASE-T4 capable. 1 = Link Partner is 100BASE-TX full-duplex capable. 5.7 100BASE-TX 1 = Link Partner is 100BASE-TX capable. 1 = Link Partner is 10BASE-T full-duplex capable. 5.5 10BASE-T 1 = Link Partner is 10BASE-T capable.
Table 49. Auto-Negotiation Expansion (Address 6)
6.5 Base Page
16.1 (Alternate NP feature) is set.
6.4 Parallel
1 = Parallel detection fault has occurred. 0 = Parallel detection fault has not occurred.
6.3 Link Partner
1 = Link partner is next page able. 6.2 Next Page Able 1 = Local device is next page able.
6.1 Page Received
in Clause 28 of IEEE 802.3. This bit is cleared on Read.
6.0 Link Partner A/N
1 = Link partner is auto-negotiation able.
- RO = Read Only LH = Latching High
Table 50. Auto-Negotiation Next Page Transmit Register (Address 7)
7.15 Next Page
7.14 Reserved Write as 0, ignore on read RO 0
7.13 Message Page
7.12 Acknowledge 2
7.11 Toggle
- RO = Read Only. R/W = Read/Write
80 Datasheet
Table 51. Auto-Negotiation Link Partner Next Page Receive Register (Address 8)
8.15 Next Page
8.14 Acknowledge
8.13 Message Page
8.12 Acknowledge 2
8.11 Toggle
Table 52. Configuration Register (Address 16, Hex 10)
16.14 Force Link Pass 1 = Force Link pass
16.13 Transmit Disable 1 = Disable Twisted Pair transmitter
16.12 Bypass Scrambler
16.11 Reserved Ignore R/W 0
16.10 Jabber
16.9 SQE
16.8 TP Loopback
16.7 CRS Select
16.6 Sleep Mode 1 = Enable Sleep Mode
16.5 PRE_EN
0 = Set RX_DV high coincident with SFD.
16.2 Fault Code
16.1 Alternate NP
16.0 Fiber Select 1 = Select fiber mode.
- The default value of Register bit 16.6 is determined by the state of the SLEEP pin 32/H7.
- The default value of Register bit 16.0 is determined by pin 26/G2 (SD/TP
82 Datasheet
Table 53. Status Register #2 (Address 17) 17.14 10/100 Mode 1 = LXT971A is operating in 100BASE-TX mode. 17.13 Transmit Status 1 = LXT971A is transmitting a packet. 17.12 Receive Status 1 = LXT971A is receiving a packet. 17.11 Collision Status 1 = Collision is occurring. 17.9 Duplex Mode 1 = Full-duplex. 17.8 Auto-Negotiation 1 = LXT971A is in auto-negotiation mode.
17.7 Auto-Negotiation
1 = Auto-negotiation process completed. 0 = Auto-negotiation process not completed. enabled, and is equivalent to Register bit 1.5. 17.5 Polarity 1 = Polarity is reversed. 17.4 Pause 1 = Device Pause capable. 17:3 Error 1 = Error Occurred (Remote Fault, X,Y, Z).
- RO = Read Only. R/W = Read/Write
Table 54. Interrupt Enable Register (Address 18)
18.7 ANMSK
1 = Enable event to cause interrupt. 0 = Do not allow event to cause interrupt.
18.6 SPEEDMSK
1 = Enable event to cause interrupt. 0 = Do not allow event to cause interrupt.
18.5 DUPLEXMSK
1 = Enable event to cause interrupt. 0 = Do not allow event to cause interrupt.
18.4 LINKMSK
1 = Enable event to cause interrupt. 0 = Do not allow event to cause interrupt. 18.1 INTEN 1 = Enable interrupts. 18.0 TINT 1 = Force interrupt on MDINT.
84 Datasheet
Table 55. Interrupt Status Register (Address 19, Hex 13)
19.8 Reserved Ignore RO 0
19.7 ANDONE
1= Auto-negotiation has completed. 0= Auto-negotiation has not completed.
19.6 SPEEDCHG
19.5 DUPLEXCHG
19.4 LINKCHG
19.2 MDINT 1 = MII interrupt pending.
19.0 Reserved Ignore RO 0
- R/W = Read/Write, RO = Read Only, SC = Self Clearing.
Table 56. LED Configuration Re gister (Address 20, Hex 14)
- Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up.
The secondary LED driver (Receive or Activity) causes the LED to change state (blink).
- Combined event LED settings are not affected by Pulse Stretch Register bit 20.1. These display settings
are stretched regardless of the value of 20.1.
- Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full-duplex.
Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs.
- Values are relative approximations. Not guaranteed or production tested.
86 Datasheet
00 = Stretch LED events to 30 ms. 01 = Stretch LED events to 60 ms. 10 = Stretch LED events to 100 ms.
20.1 PULSE-
0 = Disable pulse stretching of all LEDs.
26.11 MII Drive Strength 1 = Increased MII drive strength
26.10 Reserved Reserved RO 0
26.9 Show Symbol Error 1 = Map Symbol Error Signal To RXER
- R/W = Read /Write, RO = Read Only, LH = Latching High
Table 56. LED Configuration Register (Address 20, Hex 14) (Continued)
- Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up.
The secondary LED driver (Receive or Activity) causes the LED to change state (blink).
- Combined event LED settings are not affected by Pulse Stretch Register bit 20.1. These display settings
are stretched regardless of the value of 20.1.
- Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full-duplex.
Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs.
- Values are relative approximations. Not guaranteed or production tested.
Table 58. Transmit Control Register (Address 30)
30.12 Transmit Low Power
1 = Forces the transmitter into low power mode. Also forces a zero-differential transmission.
- Values are relative approximations. Not guaranteed or production tested.
88 Datasheet
7.0 Package Specifications
Figure 43. PBGA Package Specification
- All dimensions and tolerances conform to ASME Y 14.5 M - 1994.
- Dimension is measured at the maximum solder ball diameter, parallel to primary datum C.
- Primary datum C and seating plane are defined by the spherical crowns of the solder balls.
- Maximum mold to substrate offset shall be 0.127.
- The surface finish of the package shall be EDM Charmille #18 - #21.
- Unless otherwise specified tolerance: Decimal ± 0.05 Angular ±2°.
- Part Number - LXT971ABC Commercial Temperature Range (0ºC to +70ºC)
- Part Number - LXT971ABE Extended Temperature Range (-40ºC to +85ºC)
Figure 44. LXT971A LQFP Package Specifications
- Part Number - LXT971ALC Commercial Temperature Range (0ºC to +70ºC)
- Part Number - LXT971ALE Extended Temperature Range (-40ºC to +85ºC) Dim Millimeters Min Max A – 1.60 A1 0.05 0.15 A2 1.35 1.45 B 0.17 0.27 D 11.85 12.15 D1 9.9 10.1 E 11.85 12.15 E1 9.9 10.1 e 0.50 BSC 1 L 0.45 0.75 L1 1.00 REF θ3 11o 13o θ 0o 7o 1. Basic Spacing between Centers
90 Datasheet
8.0 Product Ordering Information
Table 59. Product Information Figure 45. Ordering Information - Sample