LXT972M INTEL | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1.0 Introduction to This Document
- 1.1 Document Overview
- 1.2 Related Documents
- 2.0 Block Diagram for Intel ® LXT972M Transceiver
- 3.0 Pin Assignments for Intel ® LXT972M Transceiver
- 4.0 Signal Descriptions for Intel ® LXT972M Transceiver
- 5.0 Functional Description
- 5.1 Device Overview
- 5.1.1 Comprehensive Functionality
- 5.1.2 Optimal Signal Processing Architecture
- 5.2 Network Media / Protocol Support
- 5.2.2 MII Data Interface
- 5.2.3 Configuration Management Interface
- 5.3 Operating Requirements
- 5.3.1 Power Requirements
- 5.3.2 Clock Requirements
- 5.4 Initialization
- 5.4.1 MDIO Control Mode and Hardware Control Mode
- 5.4.2 Reduced-Power Modes
- 5.4.3 Reset for Intel
- 5.4.4 Hardware Configuration Settings
- 5.5 Establishing Link
- 5.5.1 Auto-Negotiation
- 5.5.2 Parallel Detection
- 5.6 MII Operation
- 5.6.1 MII Clocks
- 5.6.2 Transmit Enable
- 5.6.3 Receive Data Valid
- 5.6.4 Carrier Sense
- 5.6.5 Error Signals
- 5.6.6 Collision
- 5.6.7 Loopback
- 5.7.2 Collision Indication
- 5.8.5 Link Failure
Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver Datasheet The Intel® LXT972M Single-Port 10/100 Mbps PHY Tr ansceiver is an IEEE compliant Fast Ethernet PHY Transceiver that directly supports both 100BASE-TX and 10BASE-T applications. It provides a Media Independent Interface (MII) for easy attachment to 10/100 Media Access Controllers (MACs). Both full and half-duplex operation at 10 Mbps and 100 Mbps is supported. Operation mode can be set to auto-negotiation, para llel detection, or manual control. The device is powered from a single 3.3V power supply.
Applications
■ Combination 10BASE-T/100BASE-TX Network Interface Cards (NICs) ■ Wireless access points ■ Network printers ■ 10/100 Personal Computer Memory Card International Association (PCMCIA) cards ■ Cable Modems and Set-Top Boxes ■ 3.3V Operation ■ IEEE 802.3-compliant 10BASE-T or 100BASE-TX with integrated filters ■ Auto-negotiation and parallel detection ■ MII interface with extended register capability ■ Robust baseline wander correction ■ Carrier Sense Multiple Access / Collision Detection (CSMA/CD) or full-duplex operation ■ JTAG boundary scan ■ MDIO serial port or hardware pin configurable ■ Integrated, programmable LED drivers ■ 48-pin Low-profile Quad Flat Package Document Number: 302875-005 Revision Date: 27-Oct-2005 TX_EN RX_ER CRS Power SupplyManagement / Mode Select Logic ADDR[1:0] MDIO MDC RX_DV TPON TPOP TPIN TPIP REFCLK/XI VCC GND COL RX_CLK TX_CLK TXD[3:0] Decoder & Descrambler Serial-to- Parallel Converter Scrambler & Encoder Parallel/Serial Converter Carrier Sense Data Valid Error Detect Auto Negotiation Manchester Decoder Manchester Encoder 10 100 100 Media Select TP Driver TP Out Register Set Register Set Clock Generator 10BT Collision Detect Clock Generator OSP Adaptive EQ with Baseline Wander Cancellation OSP Slicer OSP Pulse Shaper RXD[3:0] 100TX TP In RX PCS JTAG 5 TDO TMS TCK TRST_L RESET_L B3387-13 LED/CFG[3:1] TDI TX PCS XO
Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver
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Document Number: 302875-005 Revision Date: 27-Oct-2005 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice. The Intel ® LXT972M Single-Port 10/100 Mbps PHY Transceiver may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtaine d by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2005, Intel Corporation.
Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver
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Document Number: 302875-005 Revision Date: 27-Oct-2005
10.0 Intel
5 Initialization Sequence for Intel
10 Intel
Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver Datasheet 5 Document Number: 302875-005 Revision Date: 27-Oct-2005
19 Intel
35 Intel
37 Sample Pb-Free (RoHS-Compliant) LQFP Package - Intel ® LX972M Transceiver
2 Intel
7 Intel ® LXT972M Transceiver Standard Bus and Interface Signal Descriptions...17
8 Intel ® LXT972M Transceiver Configuration and LED Driver Signal Descriptions18
9 Intel ® LXT972M Transceiver Power, Ground, No-Connect Signal Descriptions .19
18 Device ID Register for Intel
Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver
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Document Number: 302875-005 Revision Date: 27-Oct-2005
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46 Auto-Negotiation Link Partner Base P age Ability Register - Address 5, Hex 5... 80
49 Auto-Negotiation Link Partner Next Page Receive Register - Address 8, Hex 8 82
Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver Datasheet 7 Document Number: 302875-005 Revision Date: 27-Oct-2005
Revision History
Intel® LXT972M Transceiver Datasheet Revision 005 Revision Date: 27-Oct-2005 Page Description Added Figure 36 “Sample LQFP Package - Intel® LXT972M Transceiver” and Figure 37 “Sample Pb-Free (RoHS-Compliant) LQFP Package - Intel® LX972M Transceiver” under Section 10.1, “Top Label Markings”.
92 Modified Table 57 “Product Ordering Information”: added RoHS information
92 Modified Figure 38 “Order Matrix for Intel® LXT972M Transceiver”. Intel® LXT972M Transceiver Datasheet Revision 004 Revision Date: February 18, 2005 Page Description - Removed “Preliminary” label from document.
10 Added Table 1 “Related Documents from Intel”
92 Change to product ordering information in Chapter 11.0, “Product Ordering Information”. Intel® LXT972M Transceiver Datasheet Revision 003 Revision Date: October 21, 2004 Page Description 1 Block diagram changed. 11 Chapter 2.0, “Block Diagram for Intel® LXT972M Transceiver” . Block diagram changed. Chapter 3.0, “Pin Assignments for Intel® LXT972M Transceiver”. - Figure 2 “Pin Assignments for Intel® LXT972M Transceiver 48-Pin LQFP Package” changed. - Figure 11 “Pin Assignments for Intel® LXT972M Transceiver Pb-Free 48-Pin LQFP”. Added new figure for lead-free package. - Table 2 “Intel® LXT972M Transceiver Signal Types”. Changed old Table 2 to Table 1 and table text changed. - T able 3 “Intel® LXT972M Transceiver LQFP Numeric Pin List” changed. Chapter 4.0, “Signal Descriptions for Intel® LXT972M Transceiver”. - T able 6 “Intel® LXT972M Transceiver Network Interface Signal Descriptions” changed. - T able 8 “Intel® LXT972M Transceiver Configuration and LED Driver Signal Descriptions” changed. Section 5.4.4, “Hardware Configuration Settings”. - T ext changed. - Table 13 “Hardware Configuration Settings for Intel® LXT972M Transceiver” changed. 53 Section 5.9.3, “LED Functions” . Text changed. Chapter 7.0, “Electrical Specifications”. - T able 20 “Absolute Maximum Ratings for Intel ® LXT972M Transceiver” changed. - Table 23 “Digital I/O Characteristics (Except for MII, XI/XO, and LED/CFG Pins)” changed. - Table 27 “100BASE-TX Transceiver Characteristics” changed. 66 Section 7.2, “Timing Diagrams” . Added timing diagrams.
Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver
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Document Number: 302875-005 Revision Date: 27-Oct-2005 Chapter 8.0, “Register Definitions - IEEE Base Registers” - Table 40 “Register Set for IEEE Base Registers” changed. - Table 41 “Control Register - Address 0, Hex 0” changed. Chapter 9.0, “Register Definitions - Product-Specific Registers”. - Table 50 “Register Set for Product-Specific Registers” changed. - Table 54 “LED Configuration Register - Address 20, Hex 14” changed. - Table 56 “Transmit Control Register - Address 30, Hex 1E” 90 Chapter 10.0, “Intel® LXT972M Transceiver Package Specifications”. - Figure 35 “Intel® LXT972M Transceiver LQFP Package Specifications” changed. Intel® LXT972M Transceiver Datasheet Revision 002 Revision Date: July 14, 2004 Page Description 1 Text changed. 10 Figure 1 “Intel ® LXT972M Transceiver Block Diagram” - Deleted ECL Driver from figure. 21 Section 5.1, “Introduction” - Text changed. 22 Section 5.2.1.1, “Twisted-Pair Interface” - Added text on MDI crossover. 23 Section 5.2.1.2, “Fault Detection and Reporting” - Text changed. 26 Section 5.3.2.1, “External Crystal/Oscillator” - Text changed. 30 Table 12 “Hardware Configuration Settings for Intel® LXT972M Transceiver” - Bit value for 0.8 changed. 33 Section 5.5.2, “Parallel Detection” - T ext changed. 36 Section 5.6.2, “Transmit Enable” - Text changed. 37 Section 5.6.4, “Carrier Sense” - Text changed. 53 Section 5.9.4, “LED Pulse Stretching” - T ext changed. 80 Table 46 “Auto-Negotiation Next Page Transmit Register - Address 7, Hex 7” - Bits 7.10:0 and 7.13 changed.
80 Table 47 “Auto-Negotiation Link Partner Next Page Receive Register - Address 8, Hex 8” - Bits
8.18 and 8.10:0 changed. 85 Table 52 “LED Configuration Register - Address 20, Hex 14” - Bit 20.0 changed. Intel® LXT972M Transceiver Datasheet Revision 001 Revision Date: July 2, 2004 Page Description - Initial release of this document. Intel® LXT972M Transceiver Datasheet Revision 003 Revision Date: October 21, 2004 Page Description
Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver Datasheet 9 Document Number: 302875-005 Revision Date: 27-Oct-2005
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1.0 Introduction to This Document
1.1 Document Overview
1.2 Related Documents
Table 1. Related Documents from Intel
2.0 Block Diagram for Intel ® LXT972M Transceiver
Figure 1. Intel ® LXT972M Transceiver Block Diagram
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3.0 Pin Assignments for Intel ® LXT972M Transceiver
Figure 2 shows the pin assignments for the LXT972M Transceiver LQFP package. Figure 2. Pin Assignments for Intel ® LXT972M Transceiver 48-Pin LQFP Package
Table 3 lists the LXT972M Transceiver LQFP pin numbers, symbols, and pin types. Table 2. Intel ® LXT972M Transceiver Signal Types Table 3. Intel ® LXT972M Transceiver LQFP Numeric Pin List (Sheet 1 of 2)
1 CRS O
2 REFCLK/XI AI
4 RESET_L I
6 VCCIO –
10 ADDR0 I
11 ADDR1 I
12 RBIAS AI
13 GNDA –
14 TPOP AO
15 TPON AO
16 VCCA –
17 TPIP AI
18 TPIN AI
19 TDI I
20 TDO O
21 TMS I
22 TCK I
23 TRST_L I
24 GND –
25 GND –
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26 LED/CFG3 I/O
27 LED/CFG2 I/O
28 LED/CFG1 I/O
29 VCCIO –
30 GND –
31 MDIO I/O
32 MDC I
33 RXD3 O
34 RXD2 O
35 RXD1 O
36 RXD0 O
37 RX_DV O
38 GND –
39 VCCD –
40 RX_CLK O
41 RX_ER O
42 TX_CLK O
43 TX_EN I
44 TXD0 I
45 TXD1 I
46 TXD2 I
47 TXD3 I
48 COL O
Table 3. Intel ® LXT972M Transceiver LQFP Numeric Pin List (Sheet 2 of 2)
Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver Datasheet 15 Document Number: 302875-005 Revision Date: 27-Oct-2005
4.0 Signal Descriptions for Intel ® LXT972M Transceiver
Intel recommends the following configurations for unused pins: Unused inputs. Configure all unused inputs and unused multi-function pins for inactive states. Unused outputs. Leave all unused outputs floating. No connects. Do not use pins designated as NC (no connect), and do not terminate them. Note: For the tables in this section, the abbreviations listed in Table 2, “Intel® LXT972M Transceiver Signal Types” on page 13 are used for the “Type” column. Tables in this section include the following Table 4, “Intel® LXT972M Transceiver MII Data Interface Signal Descriptions” Table 5, “Intel® LXT972M Transceiver MII Controller Interface Signal Descriptions” Table 6, “Intel® LXT972M Transceiver Network Interface Signal Descriptions” Table 7, “Intel® LXT972M Transceiver Standard Bus and Interface Signal Descriptions” Table 8, “Intel® LXT972M Transceiver Configuration and LED Driver Signal Descriptions” Table 9, “Intel® LXT972M Transceiver Power, Ground, No-Connect Signal Descriptions” Table 10, “Intel® LXT972M Transceiver JTAG Test Signal Descriptions” Table 11, “Intel® LXT972M Transceiver Pin Types and Modes”
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Table 4 lists signal descriptions of the LXT972M Transceiver MII data interface pins. Table 4. Intel ® LXT972M Transceiver MII Data Interface Signal Descriptions TXD is a group of parallel data signals that are driven by the MAC. TXD[3:0] transition synchronously with respect to TX_CLK. TXD[0] is the least-significant bit. The MAC asserts this signal when it drives valid data on TXD. This signal must be synchronized to TX_CLK.
2.5 MHz for 10 Mbps operation
25 MHz for 100 Mbps operation. RXD[0] is the least-significant bit. This output is synchronous to RX_CLK. Signals a receive error condition has occurred. This output is synchronous to RX_CLK. 25 MHz for 100 Mbps operation. 2.5 MHz for 10 Mbps operation. This output remains High for the duration of the collision. de-asserted on loss of carrier, synchronous to RX_CLK.
Table 5 lists signal descriptions of the LXT972M Transceiver MII controller interface pins. Table 6 lists signal descriptions of the LXT972M Transceiver network interface pins. Table 7 lists signal descriptions of the LXT972M Transceiver standard bus and interface signals. Table 5. Intel ® LXT972M Transceiver MII Controller Interface Signal Descriptions Clock for the MDIO serial data channel. 31 MDIO I/O Management Data Input/Output. Bidirectional serial data channel for PHY/STA communication. Table 6. Intel ® LXT972M Transceiver Network Interface Signal Descriptions Twisted-Pair Outputs, Positive and Negative. IEEE 802.3 compliant pulses onto the line. Twisted-Pair Inputs, Positive and Negative. differential 100BASE-TX or 10BASE-T signals from the line. Table 7. Intel ® LXT972M Transceiver Standard Bus and Interface Signal Descriptions
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Table 8 lists signal descriptions of the LXT972M Transceiver configuration and LED driver pins. Note: Pull-up/pull-down resistors of 10k Ohms can be implemented if LEDs are not used in the design. Table 8. Intel ® LXT972M Transceiver Configuration and LED Driver Signal Descriptions is extended to 258 μs (nominal) after reset is de-asserted. be tied to ground through a 22.1 k Ω, 1% resistor. Reference Clock Input / Crystal Input and Crystal Output.
Table 9 lists signal descriptions of the LXT972M Transceiver power, ground, and no-connect pins. Table 10 lists signal descriptions of LXT972M Transceiver Joint Test Action Group (JTAG) pins. Note: If a JTAG port is not used, these pins do not need to be terminated. Table 9. Intel ® LXT972M Transceiver Power, Ground, No-Connect Signal Descriptions Ground return for digital I/O circuits (VCCIO). For the LXT972M Transceiver, VCCIO is 3.3 V. Requires a 3.3 V power supply. Requires a 3.3 V power supply. These pins are not used and must not be terminated. Table 10. Intel ® LXT972M Transceiver JTAG Test Signal Descriptions Test data sampled with respect to the rising edge of TCK. Test data driven with respect to the falling edge of TCK. Clock input for boundary scan. This active-low test reset input is sourced by ATE.
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Table 11 lists pin types and modes of the LXT972M Transceiver. Table 11. Intel ® LXT972M Transceiver Pin Types and Modes
Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver Datasheet 21 Document Number: 302875-005 Revision Date: 27-Oct-2005
5.0 Functional Description
This chapter has the following sections: Section 5.1, “Device Overview” Section 5.2, “Network Media / Protocol Support” Section 5.3, “Operating Requirements” Section 5.4, “Initialization” Section 5.5, “Establishing Link” Section 5.6, “MII Operation” Section 5.7, “100 Mbps Operation” Section 5.8, “10 Mbps Operation” Section 5.9, “Monitoring Operations” Section 5.10, “Boundary Scan (JTAG 1149.1) Functions”
Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver
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Document Number: 302875-005 Revision Date: 27-Oct-2005
5.1 Device Overview
The LXT972M Transceiver is a single-port Fast Ethernet 10/100 transceiver that supports 10 Mbps and 100 Mbps networks. It complies with applicable requirements of IEEE 802.3. It directly drives either a 100BASE-TX line or a 10BASE-T line.
5.1.1 Comprehensive Functionality
The LXT972M Transceiver provides a standard Media Independent Interface (MII) for 10/100 MACs. The LXT972M Transceiver performs all functions of the Physical Coding Sublayer (PCS) and Physical Media Attachment (PMA) sublayer as defined in the IEEE 802.3 100BASE-X standard. It also performs all functions of the Physical Media Dependent (PMD) sublayer for 100BASE-TX connections. If the LXT972M Transceiver is not set for forced operation, it uses auto-negotiation/parallel detection to automatically determine line operating conditions. If the PHY device on the other side of the link supports auto-negotiation, the LXT972M Transceiver auto-negotiates with it using Fast Link Pulse (FLP) Bursts. If the PHY partner does not support auto-negotiation, the LXT972M Transceiver automatically detects the presence of either link pulses (10 Mbps PHY) or Idle symbols (100 Mbps PHY) and sets its operating conditions accordingly. The LXT972M Transceiver provides half-duplex and full-duplex operation at 100 Mbps and 10 Mbps.
5.1.2 Optimal Signal Processing Architecture
The LXT972M Transceiver incorporates high-efficiency Optimal Signal Processing (OSP) design techniques, which combine optimal properties of digital and analog signal processing. The receiver utilizes decision feedback equalization to increase noise and cross-talk immunity by as much as 3 dB over an ideal all-analog equalizer. Using OSP mixed-signal processing techniques in the receive equalizer avoids the quantization noise and calculation truncation errors found in traditional DSP-based receivers (typically complex DSP engines with A/D converters). This results in improved receiver noise and cross-talk performance. The OSP signal processing scheme also requires substantially less computational logic than traditional DSP-based designs. This lowers power consumption and also reduces the logic switching noise generated by DSP engines. This logic switching noise can be a considerable source of EMI generated on the device’s power supplies. The OSP-based LXT972M Transceiver provides improved data recovery, EMI performance, and low power consumption.
Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver Datasheet 23 Document Number: 302875-005 Revision Date: 27-Oct-2005
5.2 Network Media / Protocol Support
This section includes the following: Section 5.2.1, “10/100 Network Interface” Section 5.2.2, “MII Data Interface” Section 5.2.3, “Configuration Management Interface” The LXT972M Transceiver supports both 10BASE-T and 100BASE-TX Ethernet over twisted- pair. 5.2.1 10/100 Network Interface The network interface port consists of two differential signal pairs. For specific pin assignments, see Chapter 4.0, “Signal Descriptions for Intel® LXT972M Transceiver” . The LXT972M Transceiver output drivers can generate one of the following outputs: 100BASE-TX 10BASE-T When not transmitting data, the LXT972M Transceiver generates IEEE 802.3-compliant link pulses or idle code. Depending on the mode selected, input signals are decoded as one of the following: When not transmitting data, the LXT972M Transceiver generates IEEE 802.3-compliant link pulses or idle code. Depending on the mode selected, input signals are decoded as one of the following: 100BASE-TX 10BASE-T Auto-negotiation/parallel detection or manual control is used to determine the speed of this interface.
Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver
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Document Number: 302875-005 Revision Date: 27-Oct-2005
5.2.1.1 Twisted-Pair Interface
The LXT972M Transceiver supports either 100BASE-TX or 10BASE-T connections over 100 Ω, Category 5, Unshielded Twisted Pair (UTP) cable. When operating at 100 Mbps, the LXT972M Transceiver continuously transmits and receives MLT3 symbols. When not transmitting data, the LXT972M Transceiver generates “IDLE” symbols. During 10 Mbps operation, Manchester-encoded data is exchanged. When no data is being exchanged, the line is left in an idle state. Link pulses are transmitted periodically to keep the link up. Only a transformer, RJ-45 connector, load resistor, and bypass capacitors are required to complete this interface. On the transmit side, the LXT972M Transceiver has an active internal termination and does not require external termination resistors. Intel's patented waveshaping technology shapes the outgoing signal to help reduce the need for external EMI filters. Four slew rate settings allow the designer to match the output waveform to the magnetic characteristics. On the receive side, the internal impedance is high enough that it has no practical effect on the external termination circuit. (For the slew rate settings, see Table 56, “Transmit Control Register - Address 30, Hex 1E” on page 89.) Note: On the LXT972M Transceiver, MDIX crossover (MDIX) is supported by board design.
5.2.1.2 Remote Fault Detection and Reporting
The LXT972M Transceiver supports the remote fault detection and reporting mechanisms. “Remote Fault” refers to a MAC-to-MAC communication function that is transparent to PHY layer devices. It is used only during auto-negotiation, and is applicable only to twisted-pair links. Remote Fault Detection. Register bit 4.13 in the Auto-Negotiation Advertisement Register is reserved for Remote Fault indications. It is typically used when re-starting the auto-negotiation sequence to indicate to the link partner that the link is down because the advertising device detected a local fault. When the LXT972M Transceiver receives a Remote Fault indication from its partner during auto- negotiation, the following occurs: Register bit 5.13 in the Link Partner Base Page Ability Register is set. Remote Fault Register bit 1.4 in the MII Status Register is set to pass this information to the local controller.
Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver Datasheet 25 Document Number: 302875-005 Revision Date: 27-Oct-2005
5.2.2 MII Data Interface
The LXT972M Transceiver supports a standard Media Independent Interface (MII). The MII consists of a data interface and a management interface. The MII Data Interface passes data between the LXT972M Transceiver and a Media Access Controller (MAC). Separate parallel buses are provided for transmit and receive. This interface operates at either 10 Mbps or 100 Mbps. The speed is set automatically, once the operating conditions of the network link have been determined. For details, see Section 5.6, “MII Operation” on page 36 . Increased MII Drive Strength. A higher Media Independent Interface (MII) drive strength may be desired in some designs to drive signals over longer PCB trace lengths, or over high-capacitive loads, through multiple vias, or through a connector. The MII drive strength in the LXT972M Transceiver can be increased by setting Register bit 26.11 through software control. Setting Register bit 26.11 = 1 through the MDC/MDIO interface sets the MII pins (RXD[3:0], RX_DV , RX_CLK, RX_ER, COL, CRS, and TX_CLK) to a higher drive strength.
5.2.3 Configuration Management Interface
The LXT972M Transceiver provides both an MDIO interface and a reduced hardware control interface for device configuration and management.
5.2.3.1 MDIO Management Interface
MDIO management interface topics include the following: Section 5.2.3.1.1, “MDIO Addressing for Intel® LXT972M Transceiver” Section 5.2.3.1.2, “MDIO Frame Structure” The LXT972M Transceiver supports the IEEE 802.3 MII Management Interface also known as the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the LXT972M Transceiver. The MDIO interface consists of a physical connection, a specific protocol that runs across the connection, and an internal set of addressable registers. Some registers are required and their functions are defined by the IEEE 802.3 standard. The LXT972M Transceiver also supports additional registers for expanded functionality. The LXT972M Transceiver supports multiple internal registers, each of which is 16 bits wide. Specific register bits are referenced using an “X.Y” notation, where X is the register number (0-31) and Y is the bit number (0-15).
5.2.3.1.1 MDIO Addressing for Intel ® LXT972M Transceiver
The MDIO addressing protocol allows a controller to communicate with multiple LXT972M Transceivers.As listed in Table 12, pins ADDR[1:0] determine the PHY device address that is selected.
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Table 12. Intel ® LXT972M Transceiver - PHY Device Address Selections
5.2.3.1.2 MDIO Frame Structure
shown in Figure 3 and Figure 4 (Read and Write). MDIO Interface timing is given in Chapter 7.0, “Electrical Specifications”.
5.2.3.2 Hardware Control Interface
Figure 3. Management Interface Read Frame Structure Figure 4. Management Interface Write Frame Structure
Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver
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Document Number: 302875-005 Revision Date: 27-Oct-2005
5.3 Operating Requirements
5.3.1 Power Requirements
The LXT972M Transceiver requires three power supply inputs: VCCA VCCD VCCIO The digital and analog circuits require 3.3 V supplies (VCCA and VCCD). These inputs may be supplied from a single source. Each supply input must be de-coupled to ground. An additional supply may be used for the MII (VCCIO). The supply may be either +2.5 V or +3.3 V . Also, the inputs on the MII interface are tolerant to 5 V signals from the controller on the other side of the MII interface. For MII I/O characteristics, see Table 24, “Digital I/O Characteristics1 - MII Pins” on page 62 . Note: Bring up power supplies as close to the same time as possible. Note: As a matter of good practice, keep power supplies as clean as possible.
5.3.2 Clock Requirements
5.3.2.1 External Crystal/Oscillator
The LXT972M Transceiver requires a reference clock input that is used to generate transmit signals and recover receive signals. It may be provided by either of two methods: by connecting a crystal across the oscillator pins (XI and XO) with load capacitors, or by connecting an external clock source to pin XI. The connection of a clock source to the XI pin requires the XO pin to be left open. To minimize transmit jitter, Intel recommends a crystal-based clock instead of a derived clock (that is, a PLL- based clock). A crystal is typically used in NIC applications. An external 25 MHz clock source, rather than a crystal, is frequently used in switch applications. For clock timing requirements, see Table 25, “I/O Characteristics - REFCLK/XI and XO Pins” on page 63 .
5.3.2.2 MDIO Clock
The MII management channel (MDIO) also requires an external clock. The managed data clock (MDC) speed is a maximum of 8 MHz. For details, see Table 37, “Intel® LXT972M Transceiver MDIO Timing” on page 72.
Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver Datasheet 29 Document Number: 302875-005 Revision Date: 27-Oct-2005
5.4 Initialization
This section includes the following topics: Section 5.4.1, “MDIO Control Mode and Hardware Control Mode” Section 5.4.2, “Reduced-Power Modes” Section 5.4.3, “Reset for Intel® LXT972M Transceiver” Section 5.4.4, “Hardware Configuration Settings” When the LXT972M Transceiver is first powered on, reset, or encounters a link failure state, it checks the MDIO register configuration bits to determine the line speed and operating conditions to use for the network link.
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may be set by the Hardware Control or MDIO interface. Figure 5. Initialization Sequence for Intel ® LXT972M Transceiver
Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver Datasheet 31 Document Number: 302875-005 Revision Date: 27-Oct-2005
5.4.1 MDIO Control Mode and Hardware Control Mode
In the MDIO Control mode, the LXT972M Transceiver reads the Hardware Control Interface pins to set the initial (default) values of the MDIO regi sters. Once the initial values are set, bit control reverts to the MDIO interface. The following modes are available using MDIO Control. Force network link operation to: — 100BASE-TX, Full-Duplex — 100BASE-TX, Half-Duplex — 10BASE-T, Full-Duplex — 10BASE-T, Half-Duplex Allow auto-negotiation/parallel-detection On power-up or hardware reset, the LXT972M Transceiver reads the Hardware Control Interface pins and sets the MDIO registers accordingly. The following modes are available using the Hardware Control: Auto-negotiation-enabled advertising, either: — 10/100 BASE-T Full/Half Duplex — 10/100 BASE-T Half Duplex LXT972M Transceiver device ID enable Link Hold-off When the network link is forced to a specific configuration, the LXT972M Transceiver immediately begins operating the network interface as commanded. When auto-negotiation is enabled, the LXT972MTransceiver begins the auto-negotiation/parallel-detection operation.
5.4.2 Reduced-Power Modes
This section discusses the LXT972M Transceiver reduced-power modes.
5.4.2.1 Software Power Down
Software power-down control is provided by Register bit 0.11 in the Control Register. (See Table 41 on page 76.) During soft power-down, the following conditions are true: The network port is shut down. The MDIO registers remain accessible.
5.4.3 Reset for Intel ® LXT972M Transceiver
The LXT972M Transceiver provides both hardware and software resets, each of which manage differently the configuration control of auto-negotiation, speed, and duplex-mode selection. For a software reset, Register bit 0.15 = 1. For register bit definitions used for software reset, see Table 41, “Control Register - Address 0, Hex 0” on page 76 .
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Document Number: 302875-005 Revision Date: 27-Oct-2005 During a software reset, bit settings in Table 45, “Auto-Negotiation Advertisement Register - Address 4, Hex 4” on page 79 are not re-read from the LXT972M Transceiver configuration pins. Instead, the bit settings revert to the values that were read in during the last hardware reset. Therefore, any changes to pin values made since the last hardware reset are not detected during a software reset. During a software reset, registers are available for reading. To see when the LXT972M Transceiver has completed reset, the reset bit can be polled (that is, Register bit 0.15 = 0). For pin settings used during a hardware reset, see Section 5.4.4, “Hardware Configuration Settings”. During a hardware reset, configuration settings for auto-negotiation and speed are read in from pins, and register information is unavailable for 1 ms after de-assertion of the reset.
5.4.4 Hardware Configuration Settings
Table 13. Hardware Configuration Settings for Intel ® LXT972M Transceiver
- L = Low, and H = High. For LED/CFG pin assignments, see Chapter 3.0, “Pin Assignments for Intel® LXT972M
34 Datasheet
5.5 Establishing Link
Figure 6 shows an overview of link establishment for the LXT972M Transceiver. half-duplex, as defined by the IEEE 802.3 standard.
5.5.1 Auto-Negotiation
implement the “Base Page” defined by the IEEE 802.3 standard (Registers 4 and 5). “Auto-Negotiation Link Partner Next Page Receive Register - Address 8, Hex 8” on page 82 .
5.5.1.1 Base Page Exchange
support, and each side configures itself accordingly. Figure 6. Link Establishment Overview)
Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver Datasheet 35 Document Number: 302875-005 Revision Date: 27-Oct-2005
5.5.1.2 Manual Next Page Exchange
“Next Page Exchange” information is additional information that exceeds the information required by Base Page exchange and that is sent by “Next Pages”. The LXT972M Transceiver fully supports the IEEE 802.3 standard method of negotiation through the Next Page exchange. The Next Page exchange uses Register 7 to send information and Register 8 to receive it. Next Page exchange occurs only if both ends of the link partners advertise their ability to exchange Next Pages. Register bit 6.1 is used to make manual next page exchange easier for software. This register bit is cleared when a new negotiation occurs, preventing the user from reading an old value in Register 6 and assuming there is valid information in Registers 5 and 8.
5.5.1.3 Controlling Auto-Negotiation
When auto-negotiation is controlled by software, Intel recommends the following steps: 1. After power-up, power-down, or reset, the power-down recovery time (specified in Table 39, “Intel® LXT972M Transceiver RESET_L Pulse Width and Recovery Timing” on page 74 ) must be exhausted before proceeding. 2. Set the Auto-Negotiation Advertisement Register bits in Register 4 as desired. 3. Enable auto-negotiation. (Set MDIO Register bit 0.12 = 1.) 4. To ensure proper operation, enable or restart auto-negotiation as soon as possible after writing to Register 4.
5.5.2 Parallel Detection
In parallel with auto-negotiation, the LXT972M Transceiver also monitors for 10 Mbps Normal Link Pulses (NLP) or 100 Mbps Idle symbols. If either symbol is detected, the device automatically reverts to the corresponding speed in half-duplex mode. Parallel detection allows the LXT972M Transceiver to communicate with devices that do not support auto-negotiation. When parallel detection resolves a link, the link must be established in half-duplex mode. According to IEEE standards, the forced link partner cannot be configured to full-duplex. If the auto-negotiation link partner does not advertise half-duplex capability at the speed of the forced link partner, link is not established. The IEEE Standard prevents full-duplex-to-half-duplex link connections.
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5.6 MII Operation
This section includes the following topics: Section 5.6.1, “MII Clocks” Section 5.6.2, “Transmit Enable” Section 5.6.3, “Receive Data Valid” Section 5.6.4, “Carrier Sense” Section 5.6.5, “Error Signals” Section 5.6.6, “Collision” Section 5.6.7, “Loopback” The LXT972M Transceiver implements the Media Independent Interface (MII) as defined by the IEEE 802.3 standard. Separate channels are provided for transmitting data from the MAC to the LXT972M Transceiver (TXD), and for passing data received from the line (RXD) to the MAC. Each channel has its own clock, data bus, and control signals. The following signals are used to pass received data to the MAC: COL CRS RX_CLK RX_DV RX_ER RXD[3:0] The following signals are used to transmit data from the MAC: TX_CLK TX_EN TXD[3:0] The LXT972M Transceiver supplies both clock signals as well as separate outputs for carrier sense and collision. Data transmission across the MII is normally implemented in 4-bit-wide nibbles.
5.6.1 MII Clocks
When the link is operating at 100 Mbps, the clocks are set to 25 MHz. When the link is operating at 10 Mbps, the clocks are set to 2.5 MHz. Figure 7 through Figure 9 show the clock cycles for each mode. LXT972M Transceiver samples these signals on the rising edge of TX_CLK. Figure 7. Clocking for 10BASE-T Figure 8. Clocking for 100BASE-X
2.5 MHz during auto-negotiation and 10BASE-T Data & Idle
2.5 MHz during auto-negotiation
25 MHz once 100BASE-X
2.5 MHz during auto-negotiation 25 MHz once 100BASE-X
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5.6.2 Transmit Enable
after the last nibble of the packet.
5.6.3 Receive Data Valid
of the Start of Frame Delimiter (SFD) “5D” and remains asserted until the end of the packet. Figure 9. Clocking for Link Down Clock Transition
2.5 MHz
100 Mbps = 25 MHz
5.6.4 Carrier Sense
Carrier Sense (CRS) is an asynchronous output. CRS is always generated when the LXT972M Transceiver receives a packet from the line. signals. Carrier sense is not generated when a packet is transmitted and in full-duplex mode.
5.6.5 Error Signals
network, it asserts RX_ER and drives “0101” on the RXD pins. implemented in the LXT972M Transceiver.
5.6.6 Collision
summarizes the conditions for assertion of carrier sense, data loopback, and collision signals. Table 14. Carrier Sense, Loopback, and Collision Conditions
- T est Loopback is enabled when Register bit 0.14 = 1.
- For descriptions of Test Loopback and Operational Loopback, see Section 5.6.7, “Loopback” on page 40.
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5.6.7 Loopback
Figure 10 shows LXT972M Transceiver loopback paths.
5.6.7.1 Operational Loopback
Operational loopback is provided for 10 Mbps half-duplex links when Register bit 16.8 = 0. Data that the MAC (TXData) transmits loops back on the receive side of the MII (RXData). Figure 10. Intel® LXT972M Transceiver Loopback Paths
5.6.7.2 Internal Digital Loopback (Test Loopback)
internally looped back by the LXT972M Transceiver and returned to the MAC. not actively transmitting data, the LXT972M Transceiver sends out Idle symbols on the line. balance of the preamble, the SFD, packet data, and CRC. symbols T and R) and then returns to transmitting Idle symbols. For details on the symbols used, see 4B/5B coding listed in Table 15, “4B/5B Coding” on page 46. Figure 11. 100BASE-X Frame Format
42 Datasheet
are de-scrambled, decoded, and sent across the MII to the MAC. Figure 12. 100BASE-TX Data Path
44 Datasheet
5.7.2 Collision Indication
Figure 15 shows normal transmission. the collision as shown in Figure 16. Figure 15. 100BASE-TX Transmission with No Errors Figure 16. 100BASE-TX Transmission with Collision
46 Datasheet
5.7.3.1 Physical Coding Sublayer
as long as TX_EN is de-asserted.
5.7.3.1.1 Preamble Handling
asserted. It then returns to supplying IDLE symbols to the line driver. Table 15. 4B/5B Coding (Sheet 1 of 2)
- The /I/ (Idle) code group is sent continuously between frames.
- The /J/ and /K/ (SSD) code groups are always sent in pairs, and /K/ follows /J/.
- The /T/ and /R/ (ESD) code groups are always sent in pairs, and /R/ follows /T/.
- An /H/ (Error) code group is used to signal an error condition.
Table 15. 4B/5B Coding (Sheet 2 of 2)
- The /I/ (Idle) code group is sent continuously between frames.
- The /J/ and /K/ (SSD) code groups are always sent in pairs, and /K/ follows /J/.
- The /T/ and /R/ (ESD) code groups are always sent in pairs, and /R/ follows /T/.
- An /H/ (Error) code group is used to signal an error condition.
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5.7.3.2 Physical Medium Attachment Sublayer
5.7.3.2.1 Link
In 100 Mbps mode, link is established when the descrambler becomes locked and remains locked for approximately 50 ms. Link remains up unless the descrambler receives less than 16 consecutive idle symbols in any 2 ms period. This operation filters out small noise hits that may disrupt the link. In 100 Mbps mode, link is established when the descrambler becomes locked and remains locked for approximately 50 ms. Link remains up unless the descrambler receives less than 16 consecutive idle symbols in any 2 ms period. This operation filters out small noise hits that may disrupt the link. For short periods, MLT-3 idle waveforms meet all criteria for 10BASE-T start delimiters. A working 10BASE-T receive may temporarily indicate link to 100BASE-TX waveforms. However, the PHY does not bring up a permanent 10 Mbps link. The LXT972M Transceiver reports link failure through the MII status bits (Register bits 1.2 and 17.10). Link failure causes the LXT972M Transceiver to re-negotiate if auto-negotiation is enabled.
5.7.3.2.2 Link Failure Override
The LXT972M Transceiver normally transmits data packets only if it detects the link is up. Setting Register bit 16.14 = 1 overrides this function, allowing the LXT972M Transceiver to transmit data packets even when the link is down. This feature is provided as a transmit diagnostic tool. Note: Auto-negotiation must be disabled to transmit data packets in the absence of link. If auto- negotiation is enabled, the LXT972M Transceiver automatically transmits FLP bursts if the link is down. Caution: During normal operation, Intel does not recommend setting Register bit 16.14 for 100 Mbps receive functions because receive errors may be generated.
5.7.3.2.3 Carrier Sense
For 100BASE-TX links, a start-of-stream delimiter ( SSD) or /J/K symbol pair causes assertion of carrier sense (CRS). An end-of-stream delimiter (ESD) or /T/R symbol pair causes de-assertion of CRS. The PMA layer also de-asserts CRS if IDLE symbols are received without /T/R. However, in this case RX_ER is asserted for one clock cycle when CRS is de-asserted. Intel does not recommend using CRS for Interframe Gap (IFG) timing for the following reasons: CRS de-assertion time is slightly longer than CRS assertion time. As a result, an IFG interval appears somewhat shorter to the MAC than it actually is on the wire. CRS de-assertion is not aligned with TX_EN de-assertion on transmit loopbacks in half- duplex mode.
5.7.3.2.4 Receive Data Valid
The LXT972M Transceiver asserts RX_DV to indicate that the received data maps to valid symbols. In 100 Mbps operation, RX_DV is active with the first nibble of preamble.
Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver Datasheet 49 Document Number: 302875-005 Revision Date: 27-Oct-2005
5.7.3.3 Twisted-Pair Physical Medium Dependent Sublayer
The twisted-pair Physical Medium Dependent (PMD) layer provides signal scrambling and de- scrambling functions, line coding and decoding functions (MLT-3 for 100BASE-TX, Manchester for 10BASE-T), as well as receiving, polarity correction, and baseline wander correction functions.
5.7.3.3.1 Scrambler/Descrambler
The purpose of the scrambler/descrambler is to spread the signal power spectrum and further reduce EMI using an 11-bit, data-independent polynomial. The receiver automatically decodes the polynomial whenever IDLE symbols are received. Scrambler Seeding. Once the transmit data (or Idle symbols) are properly encoded, they are scrambled to further reduce EMI and to spread the power spectrum using an 11-bit scrambler seed. Five seed bits are determined by the PHY address, and the remaining bits are hard coded in the design. Scrambler Bypass. The scrambler/de-scrambler can be bypassed by setting Register bit 16.12 = 1. Scrambler bypass is provided for diagnostic and test support.
5.7.3.3.2 Polarity Correction
The 100 Mbps twisted pair signaling is not polarity sensitive. As a result, the polarity status is not a valid status indicator.
5.7.3.3.3 Baseline Wander Correction
The LXT972M Transceiver provides a baseline wander correction function for when the LXT972M Transceiver is under network operating conditions. The MLT3 coding scheme used in 100BASE-TX is by definition “unbalanced”. As a result, the average value of the signal voltage can “wander” significantly over short time intervals (tenths of seconds). This wander can cause receiver errors at long-line lengths (100 meters) in less robust designs. Exact characteristics of the wander are completely data dependent. The LXT972M Transceiver baseline wander correction characteristics allow the device to recover error-free data while receiving worst-case packets over all cable lengths.
5.7.3.3.4 Programmable Slew Rate Control
The LXT972M Transceiver device supports a programmable slew-rate mechanism whereby one of four pre-selected slew rates can be used. (For details, see Table 56, “Transmit Control Register - Address 30, Hex 1E” on page 89 .) The slew-rate mechanism allows the designer to optimize the output waveform to match the characteristics of the magnetics.
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Document Number: 302875-005 Revision Date: 27-Oct-2005 5.8 10 Mbps Operation The LXT972M Transceiver operates as a standard 10BASE-T transceiver and supports standard 10 Mbps functions. During 10BASE-T operation, the LXT972M Transceiver transmits and receives Manchester-encoded data across the network link. When the MAC is not actively transmitting data, the LXT972M Transceiver drives link pulses onto the line. In 10BASE-T mode, the polynomial scrambler/de-scrambler is inactive. Manchester-encoded signals received from the network are decoded by the LXT972M Transceiver and sent across the MII to the MAC. Note: 5.8.1 10BASE-T Preamble Handling The LXT972M Transceiver offers two options for preamble handling, selected by Register bit 16.5. In 10BASE-T mode when Register bit 16.5 = 0, the LXT972M Transceiver strips the entire preamble off of received packets. CRS is asserted coincident with the start of the preamble. RX_DV is held Low for the duration of the preamble. When RX_DV is asserted, the very first two nibbles driven by the LXT972M Transceiver are the SFD “5D” hex followed by the body of the packet. In 10BASE-T mode when Register bit 16.5 = 1, the LXT972M Transceiver passes the preamble through the MII and asserts RX_DV and CRS simultaneously. (In 10BASE-T loopback, the LXT972M Transceiver loops back whatever the MAC transmits to it, including the preamble.) 5.8.2 10BASE-T Carrier Sense For 10BASE-T links, CRS assertion is based on reception of valid preamble, and CRS de-assertion is based on reception of an end-of-frame (EOF) marker. Register bit 16.7 allows CRS de-assertion to be synchronized with RX_DV de-assertion. For details, see Table 51, “Configuration Register - Address 16, Hex 10” on page 84 . 5.8.3 10BASE-T Dribble Bits The LXT972M Transceiver handles dribble bits in all modes. If one to four dribble bits are received, the nibble is passed across the MII, padded with ones if necessary. If five to seven dribble bits are received, the second nibble is not sent to the MII bus.
Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver Datasheet 51 Document Number: 302875-005 Revision Date: 27-Oct-2005 5.8.4 10BASE-T Link Integrity Test In 10BASE-T mode, the LXT972M Transceiver always transmits link pulses. If the Link Integrity Test function is enabled (the normal configuration), the LXT972M Transceiver monitors the connection for link pulses. Once link pulses are detected, data transmission is enabled and remains enabled as long as either the link pulses or data transmission continue. If the link pulses stop, the data transmission is disabled. If the Link Integrity Test function is disabled (which can be done by setting Configuration Register bit 16.14 to ‘1’), the LXT972M Transceiver transmits to the connection regardless of detected link pulses.
5.8.5 Link Failure
Link failure occurs if the Link Integrity Test is enabled and link pulses or packets stop being received. If this condition occurs, the LXT972M Transceiver returns to the auto-negotiation phase if auto-negotiation is enabled. If the Link Integrity Test function is disabled by setting Configuration Register bit 16.14 to ‘1’, the LXT972M Transceiver transmits packets, regardless of link status. 5.8.6 10BASE-T SQE (Heartbeat) By default, the Signal Quality Error (SQE) or heartbeat function is disabled on the LXT972M Transceiver. To enable this function, set Register bit 16.9 = 1. When this function is enabled, the LXT972M Transceiver asserts its COL output for 5 to 15 bit times (BT) after each packet. 5.8.7 10BASE-T Jabber If a transmission exceeds the jabber timer, the LXT972M Transceiver disables the transmit and loopback functions. For jabber timing parameters, see Figure 26, “Intel® LXT972M Transceiver 10BASE-T Jabber and Unjabber Timing” on page 69 . The LXT972M Transceiver automatically exits jabber mode after the unjabber time has expired. This function can be disabled by setting Register bit 16.10 = 1. 5.8.8 10BASE-T Polarity Correction The LXT972M Transceiver automatically detects and corrects for the condition in which the receive signal (TPIP/N) is inverted. Reversed polarity is detected if eight inverted link pulses - or four inverted end-of-frame (EOF) markers - are received consecutively. If link pulses or data are not received by the maximum receive time-out period (96 to 128 ms), the polarity state is reset to a non-inverted state. When polarity reversal is detected in 10BASE-T operation, register 17.5 is set to 1. (For details, see bit 17.5 in Table 52, “Status Register #2 - Address 17, Hex 11” on page 85 .)
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5.9 Monitoring Operations
5.9.1 Monitoring Auto-Negotiation
Auto-negotiation can be monitored as follows: Register bit 17.7 is set to ‘1’ once the auto-negotiation process is completed. Register bits 1.2 and 17.10 are set to ‘1’ once the link is established. Register bits 17.14 and 17.9 can be used to determine the link operating conditions (speed and duplex). Note: When the LXT972M Transceiver detects incorrect polarity for a 10BASE-T operation, Register bit 17.5 is set to ‘1’.
5.9.2 Monitoring Next Page Exchange
The LXT972M Transceiver offers an Alternate Next Page mode to simplify the next page exchange process. Normally, Register bit 6.1 (Page Received) remains set until read. When Alternate Next Page mode is enabled, Register bit 6.1 is automatically cleared whenever a new negotiation process takes place. This action prevents the user from reading an old value in bit 6.1 and assuming that Registers 5 and 8 (Partner Ability) contain valid information. Additionally, the LXT972M Transceiver uses Register bit 6.5 to indicate when the current received page is the base page. This information is useful for recognizing when next pages must be resent due to a new negotiation process starting. Register bits 6.1 and 6.5 are cleared when read.
Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver Datasheet 53 Document Number: 302875-005 Revision Date: 27-Oct-2005
5.9.3 LED Functions
The LXT972M Transceiver has these direct LED driver pins: LED/CFG1, LED/CFG2, and LED/ CFG3. On power-up, all the drivers are asserted for approximately 1 second after reset de-asserts. Each LED driver can be programmed using the LED Configuration Register ( Table 54, “LED Configuration Register - Address 20, Hex 14” on page 87 ) to indicate one of the following conditions: Collision Condition Duplex Mode Link Status Operating Speed Receive Activity Transmit Activity The LED drivers can also be programmed to display various combined status conditions. For example, setting Register bits 20.15:12 to ‘1101’ produces the following combination of Link and Activity indications: If Link is down, LED is off. If activity is detected from the MAC, the LED still blinks even if the link is down. If Link is up, LED is on. If Link is up and activity is detected, the LED blinks at the stretch interval selected by Register bits 20.3:2 and continues to blink as long as activity is present. For the LXT972M Transceiver, the LED driver pins also provide initial configuration settings. The LED pins are sensitive to polarity and automatically pull up or pull down to configure for either open drain or open collector circuits (10 mA Max current rating) as required by the hardware configuration. For details, see the discussion of “Hardware Configuration Settings” on page 33 .
54 Datasheet
5.9.4 LED Pulse Stretching
The LED Configuration Register also provides optional LED pulse stretching to 30, 60, or 100 ms. The pulse stretch time is extended further if the event occurs again during this pulse stretch period. before the stretch timer expires, then the stretch timer is reset and the stretch time is extended. Figure 18 shows how the stretch operation functions. Figure 18. LED Pulse Stretching Note: The direct drive LED out puts in this diagram are shown as active Low.
The LXT972M Transceiver includes a IEEE 1149.1 boundary scan test port for board level testing. All digital input, output, and input/output pins are accessible.
5.10.1 Boundary Scan Interface
5.10.2 State Machine
5.10.3 Instruction Register
ensures the correct data flow to the Data registers according to the current instruction. Table 16 lists valid JTAG instructions for the LXT972M Transceiver. Table 16. Valid JTAG Instructions
56 Datasheet
5.10.4 Boundary Scan Register
serial shift stage and the parallel output stage. Table 17 lists the four BSR modes of operation.
5.10.5 Device ID Register
characters, see the specification update for the LXT972M Transceiver. Table 17. BSR Mode of Operation
3 Update
4 System Function
Table 18. Device ID Register for Intel ® LXT972M Transceiver
- The JEDEC ID is an 8-bit identifier. The MSB is for parity and is ignored. The Intel JEDEC ID is FE
6.0 Application Information
6.1 Magnetics Information
across the connectors and cables. For transformer/magnetics requirements, see Table 19. specifications and validate the magnetics for the specific application.
6.2 Typical Twisted-Pair Interface
typical twisted-pair interface setting. Table 19. Magnetics Requirements Table 20. I/O Pin Comparison of NIC and Switch RJ-45 Setups
58 Datasheet
connections crossed over for a Switch configuration. Figure 19. Intel® LXT972M Transceiver Typical Twisted-Pair Interface - Switch
- Center tap current may be supplied from 3.3 V VCCA as shown. Additional power savings may be
mA) should be used to supply center tap current.
- The 100 Ω transmit load termination resistor typically required is integrated in the LXT972M
- Magnetics without a receive pair center-tap do not require a 2 kV termination.
- RJ-45 connections shown are for a standard switch application. For a standard NIC RJ-45 setup,
60 Datasheet
Figure 21 shows a typical media independent interface (MII) for the LXT972M Transceiver. Figure 21. Intel® LXT972M Transceiver Typical Media Independent Interface
7.0 Electrical Specifications
guaranteed by test except where noted “by design”. Table 21 lists the absolute maximum ratings. Table 22 lists the recommended operating conditions. recommended operating conditions specified.
7.1 Electrical Parameters
Table 21 lists absolute maximum ratings for the LXT972M Transceiver. Exceeding the absolute maximum rating values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 22 lists the recommended operating conditions for the LXT972M Transceiver. Table 21. Absolute Maximum Ratings for Intel® LXT972M Transceiver Table 22. Recommended Operating Conditions for Intel® LXT972M Transceiver
- Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production
- Voltages are with respect to ground unless otherwise specified.
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Table 23 lists digital I/O characteristics for all pins except the MII, XI/XO, and LED/CFG pins. Table 24 lists digital I/O characteristics for the MII pins. Table 23. Digital I/O Characteristics (Except for MII, XI/XO, and LED/CFG Pins)
- Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production
Table 24. Digital I/O Characteristics1 - MII Pins
- MII digital I/O pins are tolerant to 5 V inputs.
- Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production
- Parameter is guaranteed by design and not subject to production testing.
Table 25 lists the I/O characteristics for the REFCLK/XI and XO pins. Table 26 lists the I/O characteristics for the LXT972M Transceiver LED/CFG pins. Table 25. I/O Characteristics - REFCLK/XI and XO Pins
- Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production
- Parameter is guaranteed by design and not subject to production testing.
Table 26. I/O Characteristics - LED/CFG Pins
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Table 27 lists the 100BASE-TX characteristics. Table 28 lists the 10BASE-T characteristics. Table 29 lists the 10BASE-T link integrity timing characteristics. Table 27. 100BASE-TX Transceiver Characteristics
- Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production
- Measured at the line side of the transformer, line replaced by 100 Ω(+/-1%) resistor.
Table 28. 10BASE-T Transceiver Characteristics Table 29. 10BASE-T Link Integrity Timing Characteristics
- Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production
7.2 Timing Diagrams
Figure 22. Intel® LXT972M Transceiver 100BASE-TX Receive Timing Table 30. Intel® LXT972M Transceiver 100BASE-TX Receive Timing Parameters
- Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production
- BT (Bit Time) is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit
rate. 100BASE-T bit time = 10-8 s or 10 ns.
- RX_ER is not shown in the figure.
B3492-03Note: Timing diagram depicts 4B mode.
66 Datasheet
Figure 23 does not show the TX_ER signal. Figure 23. Intel® LXT972M Transceiver 100BASE-TX Transmit Timing B3454-03Note: Timing diagram depicts 4B mode. Table 31. Intel® LXT972M Transceiver 100BASE-TX Transmit Timing Parameters
- Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production
- BT (Bit Time) is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit
rate. 100BASE-T bit time = 10-8 s or 10 ns.
Figure 24. Intel® LXT972M Transceiver 10BASE-T Receive Timing Table 32. Intel® LXT972M Transceiver 10BASE-T Receive Timing
- Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production
- BT (Bit Time) is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit
rate. 10BASE-T bit time = 10-7 s or 100 ns.
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Figure 25. Intel® LXT972M Transceiver 10BASE-T Transmit Timing Table 33. Intel® LXT972M Transceiver 10BASE-T Transmit Timing
- Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production
- BT (Bit Time) is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit
rate. 10BASE-T bit time = 10-7 s or 100 ns.
Figure 26. Intel® LXT972M Transceiver 10BASE-T Jabber and Unjabber Timing Table 34. Intel® LXT972M Transceiver 10BASE-T Jabber and Unjabber Timing
- Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production
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Figure 27. Intel® LXT972M Transceiver 10BASE-T SQE (Heartbeat) Timing Table 35. Intel® LXT972M Transceiver 10BASE-T SQE (Heartbeat) Timing
- Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production
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Figure 30. Intel® LXT972M Transceiver MDIO Input Timing Figure 31. Intel® LXT972M Transceiver MDIO Output Timing Table 37. Intel® LXT972M Transceiver MDIO Timing
- Typical values are at 25° C and are for design aid only, not guaranteed, and not subject to production
Figure 32. Intel® LXT972M Transceiver Power-Up Timing Table 38. Intel® LXT972M Transceiver Power-Up Timing
- Typical values are at 25° C and are for design aid only, not guaranteed, and not subject to production
- Power-up delay is specified as a maximum value because it refers to the PHY guaranteed performance.
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Figure 33. Intel® LXT972M Transceiver RESET_L Pulse Width and Recovery Timing Table 39. Intel® LXT972M Transceiver RESET_L Pulse Width and Recovery Timing
- Typical values are at 25° C and are for design aid only, not guaranteed, and not subject to production
- Reset Recovery Delay is specified as a maximum value because it refers to the PHY guaranteed
300 μs before accessing the MDIO port.
8.0 Register Definitions - IEEE Base Registers
This chapter includes definitions for the IEEE base registers used by the LXT972M Transceiver. 802.3 standard for adding unique device functions. The LXT972M Transceiver register set has multiple 16-bit registers. Table 40 is a register set listing of the IEEE base registers. Table 40. Register Set for IEEE Base Registers
0 Control Register See Table 41
1 Status Register #1 See Table 42. 2 PHY Identification Register 1 See Table 43. 3 PHY Identification Register 2 See Table 44.
4 Auto-Negotiation Advertisement Register See Table 45
5 Auto-Negotiation Link Partner Base Page Ability Register See Table 46. 6 Auto-Negotiation Expansion Register See Table 47. 7 Auto-Negotiation Next Page Transmit Register See Table 48. 8 Auto-Negotiation Link Partner Next Page Receive Register See Table 49.
15 Extended Status Register Not Implemented
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Table 41 lists control register bits. Table 41. Control Register - Address 0, Hex 0
0.15 Reset 0 = Normal operation
0.14 Loopback 0 = Disable loopback mode
0.13 Speed Selection
10 Mbps
100 Mbps
1000 Mbps (not supported)
0.12 Auto-Negotiation
0.11 Power-Down 0 = Normal operation
0.10 Isolate 0 = Normal operation
0.9 Restart Auto-
0.8 Duplex Mode 0 = Half-duplex
0.7 Collision T est 0 = Disable COL signal test
0.6 Speed Selection
- Some bits have their default values determined at reset by hardware configuration pins. For default details
for these bits, see Section 5.4.4, “Hardware Configuration Settings”.
Table 42 lists MII status register bits. Table 42. MII Status Register #1 - Address 1, Hex 1
1.8 Extended Status 0 = No extended status information in register 15
1.6 MF Preamble
1.5 Auto-Negotiation
1.4 Remote Fault 0 = No remote fault condition detected
1.3 Auto-Negotiation Ability 0 = PHY is not able to perform auto-negotiation
1.2 Link Status 0 = Link is down
1.1 Jabber Detect 0 = Jabber condition not detected
1.0 Extended Capability 0 = Basic register capabilities
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For Table 43 and Table 44, see Figure 34. Table 43. PHY Identification Register 1 - Address 2, Hex 2 Table 44. PHY Identification Register 2 - Address 3, Hex 3 Figure 34. PHY Identifier Bit Mapping
Table 45 lists auto-negotiation advertisement bits. Table 45. Auto-Negotiation Advertisement Register - Address 4, Hex 4 4.15 Next Page 0 = Port has no ability to send multiple pages. 4.13 Remote Fault 0 = No remote fault.
4.11 Asymmetric
4.10 Pause 0 = Pause operation disabled. 0 = 100BASE-T4 capability is not available. 1 = 100BASE-T4 capability is available. switched in if this capability is desired. 0 = Port is not 100BASE-TX full-duplex capable. 4.7 100BASE-TX 0 = Port is not 100BASE-TX capable. 0 = Port is not 10BASE-T full-duplex capable. 4.5 10BASE-T 0 = Port is not 10BASE-T capable.
- Some bits have their default values determined at reset by hardware configuration pins. For default details
for these bits, see Section 5.4.4, “Hardware Configuration Settings”.
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Table 46 lists auto-negotiation link partner base page ability bits. Table 46. Auto-Negotiation Link Partner Base Page Ability Register - Address 5, Hex 5 5.15 Next Page 0 = Link Partner has no ability to send multiple pages.
5.14 Acknowledge
from the LXT972M Transceiver. 5.13 Remote Fault 0 = No remote fault.
5.11 Asymmetric
0 = Link Partner is not Pause capable. 1 = Link Partner is Pause capable. 5.10 Pause 0 = Link Partner is not Pause capable. 5.9 100BASE-T4 0 = Link Partner is not 100BASE-T4 capable. 1 = Link Partner is 100BASE-TX full-duplex capable. 5.7 100BASE-TX 0 = Link Partner is not 100BASE-TX capable. 0 = Link Partner is not 10BASE-T full-duplex capable. 5.5 10BASE-T 0 = Link Partner is not 10BASE-T capable.
Table 47 lists auto-negotiation expansion bits. Table 47. Auto-Negotiation Expansion - Address 6, Hex 6
6.5 Base Page
16.1 (that is, Alternate NP feature) is set.
6.4 Parallel
0 = Parallel detection fault has not occurred.
6.3 Link Partner
0 = Link partner is not next page able. 6.2 Next Page Able 0 = Local device is not next page able.
6.1 Page Received
mr_page_rx = false or transmit_disable = true.
6.0 Link Partner A/N
0 = Link partner is not auto-negotiation able.
- RO = Read Only LH = Latching High
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Table 48 lists auto-negotiation next page transmit bits. Table 49 lists auto-negotiation link partner next page receive bits. Table 48. Auto-Negotiation Next Page Transmit Register - Address 7, Hex 7
7.15 Next Page (NP) 0 = Last page
7.13 Message Page
0 = Register bits 7.10:0 are user defined.
7.12 Acknowledge 2
7.11 Toggle (T)
- RO = Read Only. R/W = Read/Write
Table 49. Auto-Negotiation Link Partner Next Page Receive Register - Address 8, Hex 8
8.15 Next Page (NP)
8.14 Acknowledge (ACK)
8.13 Message Page (MP)
0 = Register bits 8.10:0 are user defined.
8.12 Acknowledge 2
8.11 T oggle (T)
9.0 Register Definitions - Product-Specific Registers
Table 50 lists the register set of the product-specific registers. Table 50. Register Set for Product-Specific Registers
16 Port Configuration Register See Table 51
17 Status Register #2 See Table 52
18 Reserved
19 Status Change Register See Table 53
20 LED Configuration Register See Table 54
21 Reserved
26 Digital Configuration Register See Table 55
27 Reserved
28 Reserved
29 Reserved
30 Transmit Control Register See Table 56
31 Reserved
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Table 51 lists configuration bits. Table 51. Configuration Register - Address 16, Hex 10
16.14 Force Link Pass 0 = Normal operation
16.13 Transmit Disable 0 = Normal operation
16.12 Bypass Scrambler
16.10 Jabber
16.9 SQE
16.8 TP Loopback
16.7 CRS Select
16.5 PRE_EN
0 = Set RX_DV high coincident with SFD.
16.1 Alternate NP
Table 52 lists register #2 status bits. Table 52. Status Register #2 - Address 17, Hex 11
17.13 Transmit Status
17.12 Receive Status
1 = LXT972M Transceiver is receiving a packet. 17.11 Collision Status 0 = No collision. 17.10 Link 0 = Link is down. 17.9 Duplex Mode 0 = Half-duplex.
17.8 Auto-Negotiation
0 = LXT972M Transceiver is in manual mode.
17.7 Auto-Negotiation
0 = Auto-negotiation process not completed. 1 = Auto-negotiation process completed.
17.5 Polarity
0 = Polarity is not reversed.
17.4 Pause
1 = The LXT972M Transceiver is Pause capable.
- RO = Read Only. R/W = Read/Write
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Table 53 lists status change bits. Table 53. Status Change Register - Address 19, Hex 13
19.7 ANDONE
0 = Auto-negotiation has not completed. 1 = Auto-negotiation has completed.
19.6 SPEEDCHG
19.5 DUPLEXCHG
19.4 LINKCHG
- R/W = Read/Write, RO = Read Only, SC = Self Clearing.
Table 54 lists LED configuration bits. Table 54. LED Configuration Register - Address 20, Hex 14 (Sheet 1 of 2)
- R/W = Read /Write. RO = Read Only. LH = Latching High
- Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up.
The secondary LED driver (Receive or Activity) causes the LED to change state (blink). Activity causes the LED to blink, regardless of the link status.
- Combined event LED settings are not affected by Pulse Stretch Register bit 20.1. These display settings
are stretched regardless of the value of 20.1.
- Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full-duplex.
Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs.
- Values are approximations. Not guaranteed or production tested.
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Table 55 lists digital configuration bits for the LXT972M Transceiver. 00 = Stretch LED events to 30 ms. 01 = Stretch LED events to 60 ms. 10 = Stretch LED events to 100 ms.
20.1 PULSE-
0 = Disable pulse stretching of all LEDs. Table 54. LED Configuration Register - Address 20, Hex 14 (Sheet 2 of 2)
- R/W = Read /Write. RO = Read Only. LH = Latching High
- Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up.
The secondary LED driver (Receive or Activity) causes the LED to change state (blink). Activity causes the LED to blink, regardless of the link status.
- Combined event LED settings are not affected by Pulse Stretch Register bit 20.1. These display settings
are stretched regardless of the value of 20.1.
- Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full-duplex.
Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs.
- Values are approximations. Not guaranteed or production tested.
Table 55. Digital Configuration Register - Address 26, Hex 1A
26.11 MII Drive Strength
26.9 Show Symbol Error
- R/W = Read /Write, RO = Read Only
Table 56 lists transmit control bits. Table 56. Transmit Control Register - Address 30, Hex 1E
30.12 Transmit Low Power
1 = Forces the transmitter into low power mode. Also forces a zero-differential transmission.
- Values are approximations and may vary outside indicated values based upon implementation loading
- Latch State during Reset is based on the state of hardware configuration pins at RESET_L.
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10.0 Intel ® LXT972M Transceiver Package Specifications
Figure 35. Intel® LXT972M Transceiver LQFP Package Specifications NOTE: The package figure is generic and used only to demonstrate package dimensions.
5.500 REF
- Basic Spacing between Centers
10.1 Top Label Markings
Figure 36 shows a sample LQFP package for the LXT972M Transceiver. does not have the “e3” symbol in the last line of the package label. Figure 36. Sample LQFP Package - Intel® LXT972M Transceiver Figure 37. Sample Pb-Free (RoHS-Compliant) LQFP Package - Intel ® LX972M Transceiver
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11.0 Product Ordering Information
Table 57 lists product ordering information for the LXT972M Transceiver. Figure 38 shows an order matrix with sample information for ordering an LXT972M Transceiver. Table 57. Product Ordering Information Figure 38. Order Matrix for Intel® LXT972M Transceiver