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FAIXEPCD0SE000

Intel Corporation

Advanced 8-Port 10/100 Mbps PHY Transceivers

Manufacturer: Intel Corporation

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LXT9785 INTEL | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 226

Technical content

Datasheet sections

1.0 Introduction
1.1 What You Will Find in This Document
1.2 Related Documents
2.0 Block Diagram
3.0 Pin/Ball Assignments and Signal Descriptions
3.1 PQFP Pin Assignments
3.1.1 PQFP Pin Assignments – RMII Configuration
3.1.2 PQFP Pin Assignments – SMII Configuration
3.1.3 PQFP Pin Assignments – SS-SMII Configuration
3.2 PQFP Signal Descriptions
3.2.1 Signal Name Conventions
3.2.2 PQFP Signal Description s – RMII, SMII, and SS-SMII Configurations
3.3 BGA23 Ball Assignments
3.3.1 RMII BGA23 Ball List
3.3.2 SMII BGA23 Ball List
3.3.3 SS-SMII BGA23 Ball List
3.4 BGA23 Signal Descriptions
3.4.1 Signal Name Conventions
3.4.2 Signal Descriptions – RMII, SMII, and SS-SMII Configurations
3.5 BGA15 Ball Assignments
3.5.1 BGA15 Ball List
3.6 BGA15 Signal Descriptions
3.6.1 Signal Name Conventions
3.6.2 Signal Descriptions – SMII and SS-SMII Configurations
4.0 Functional Description
4.1 Introduction
4.1.1 OSP™ Architecture
4.1.2 Comprehensive Functiona lity
4.1.2.1 Sectionalization
4.2 Interface Descriptions
4.2.1.1 Twisted-Pair Interface
4.2.1.2 MDI Crossover (MDIX)
4.2.1.3 Fiber Interface
4.3 Media Independent Interface (MII) Interfaces
4.3.1 Global MII Mode Select
4.3.2 Internal Loopback
4.3.3 RMII Data Interface
4.3.4 Serial Media Independent Interf ace (SMII) and Source Synchronous-
4.3.4.1 SMII Interface
4.3.4.2 Source Synchronous-Serial Medi a Independent Interface
4.3.5 Configuration Management Interface
4.3.6 MII Isolate

Datasheet sections

4 Datasheet
4.3.7 MDIO Management Interface
4.3.8 MII Sectionalization
4.3.9 MII Interrupts
4.3.10 Global Hardware Control Interface
4.3.11 FIFO Initial Fill Values
4.4 Operating Requirements
4.4.1 Power Requirements
4.4.2 Clock/SYNC Requirements
4.4.2.1 Reference Clock
4.4.2.2 TxCLK Signal (SS-SMII only)
4.4.2.3 TxSYNC Signal (SMII/SS-SMII)
4.4.2.4 RxSYNC Signal (SS-SMII only)
4.4.2.5 RxCLK Signal (SS-SMII only)
4.5 Initialization
4.5.1 MDIO Control Mode
4.5.2 Hardware Control Mode
4.5.3 Power-Down Mode
4.5.3.1 Global (Hardware) Power Down
4.5.3.2 Port (Software) Power Down
4.5.5 Hardware Configuration Settings
4.6 Link Establishment
4.6.1 Auto-Negotiation
4.6.1.1 Base Page Exchange
4.6.1.2 Manual Next Page Exchange
4.6.1.3 Controlling Auto-Negotiation
4.6.1.4 Link Criteria
4.6.1.5 Parallel Detection
4.6.1.6 Reliable Link Establishm ent While Auto MDI/MDIX is
4.7 Serial MII Operation
4.7.1 SMII Reference Clock
4.7.2 TxSYNC Pulse (SMII/SS-SMII)
4.7.3 Transmit Data Stream
4.7.3.1 Transmit Enable
4.7.3.2 Transmit Error
4.7.4 Receive Data Stream
4.7.4.1 Carrier Sense
4.7.4.2 Receive Data Valid
4.7.4.3 Receive Error
4.7.4.4 Receive Status Encoding
4.7.6 Source Synchronous-Serial Media Inde pendent Interface
4.8 RMII Operation
4.8.1 RMII Reference Clock
4.8.2 Transmit Enable
4.8.3 Carrier Sense & Data Valid
4.8.4 Receive Error
4.8.5 Out-of-Band Signaling

Datasheet sections

4.9.2.1 PCS Sublayer
4.9.3 PMA Sublayer
4.9.3.1 Link
4.9.3.2 Link Failure Override
4.9.3.3 Carrier Sense/Data Valid (RMII)
4.9.3.4 Carrier Sense (SMII)
4.9.3.5 Receive Data Valid (SMII)
4.9.3.6 Twisted-Pair PMD Sublayer
4.9.3.7 Fiber PMD Sublayer
4.10.1 Preamble Handling
4.10.2 Dribble Bits
4.10.3.1 Link Failure
4.11.2 Interaction between Processor, MAC, and PHY
4.11.3 Management Interface and Control
4.11.4 DTE Discovery Process Flow
4.11.5 DTE Discovery Behavior
4.12 Monitoring Operations
4.12.1 Monitoring Auto-Negotiation
4.12.2 Per-Port LED Driver Functions
4.12.3 Out-of-Band Signaling
4.12.4 Boundary Scan Interface
4.12.5 State Machine
4.12.6 Instruction Register
4.12.7 Boundary Scan Register
4.13 Cable Diagnostics Overview
4.13.2 Operation
4.13.2.1 Short and Long Cable Testing Requirements
4.13.2.2 Precision
4.13.3 Implementation Considerations
4.13.4 Basic Implementation
4.14 Link Hold-Off Overview
4.14.2 Operation
5.0 Application Information
5.1 Design Recommendations
5.2 General Design Guidelines
5.2.1 Power Supply Filtering
5.2.2 Power and Ground Plane Layout Considerations
5.2.2.1 Chassis Ground
5.2.3 MII Terminations
5.2.4 Twisted-Pair Interface
5.2.4.1 Magnetic Requirements

Datasheet sections

6 Datasheet
5.2.5 The Fiber Interface
5.2.6 LED Circuit
6.0 Test Specifications
7.0 Register Definitions
8.0 Package Specifications
9.0 Ordering Information
1 Intel ® LXT9785/LXT9785E Block Diagram
2 Intel ® LXT9785 and Intel® LXT9785E RMII 208-Pin PQFP Assignments
3 Intel ® LXT9785/LXT9785E SMII 208-Pin PQFP Assignments
4 Intel ® LXT9785/LXT9785E SS-SMII 208-Pin PQFP Assignments
5 Intel® LXT9785/LXT9785E 241-Ball BGA23 Assignments (Top View)
6 Intel ® LXT9785MBC 196-Ball BGA15 Assignments (Top View)
7 Intel ® LXT9785/LXT9785E Interfaces
8 Intel ® LXT9785/LXT9785E Internal Loopback
9 Intel ® LXT9785/LXT9785E Management Interface Read Frame Structure
10 Intel ® LXT9785/LXT9785E Management Interface Write Frame Structure
11 Intel ® LXT9785/LXT9785E Port Address Scheme
12 Intel ® LXT9785/LXT9785E Interrupt Logic
13 Intel ® LXT9785/LXT9785E Initialization Sequence
14 Intel ® LXT9785/LXT9785E Auto-Negotiation Operation
15 Intel ® LXT9785/LXT9785E Typical SMII Interface Diagram
16 Intel ® LXT9785/LXT9785E Typical SMII Quad Sectionalization Diagram
17 Intel ® LXT9785/LXT9785E 100 Mbps Serial MII Data Flow
18 Intel ® LXT9785/LXT9785E Serial MII Transmit Synchronization
19 Intel ® LXT9785/LXT9785E Serial MII Receive Synchronization
20 Intel ® LXT9785/LXT9785E Typical SS-SMII Interface Diagram
21 Intel ® LXT9785/LXT9785E Typical SS-SMII Quad Sectionalization Diagram
22 Intel ® LXT9785/LXT9785E SS-SMII Transmit Timing
23 Intel ® LXT9785/LXT9785E SS-SMII Receive Timing
24 Intel ® LXT9785/LXT9785E RMII Data Flow
25 Intel ® LXT9785/LXT9785E Typical RMII Interface Diagram
26 Intel ® LXT9785/LXT9785E Typical RMII Quad Sectionalization Diagram
27 Intel ® LXT9785/LXT9785E 100BASE-X Frame Format
28 Intel ® LXT9785/LXT9785E Protocol Sublayers
29 Typical IP Telephone System Connection
30 Intel
31 Intel ® LXT9785/LXT9785E LED Pulse Stretching
32 Intel ® LXT9785/LXT9785E RMII Programmable Out-of-Band Signaling
33 LED Circuit
34 Intel ® LXT9785/LXT9785E Power and Ground Supply Connections
35 Intel ® LXT9785/LXT9785E Typical Twisted-Pair Interface
37 Recommended Intel ® LXT9785/LXT9785E-to-5 V Fiber Transceiver Interface Circuitry
38 ON Semiconductor Triple PECL-to-LVPECL Transla tor

Datasheet sections

39 Intel ® LXT9785/LXT9785E SMII - 100BASE-TX Receive Timing
40 Intel ® LXT9785/LXT9785E SMII - 100BASE-TX Transmit Timing
41 Intel ® LXT9785/LXT9785E SMII - 100BASE-FX Receive Timing
42 Intel ® LXT9785/LXT9785E SMII - 100BASE-FX Transmit Timing
43 Intel ® LXT9785/LXT9785E SMII - 10BASE-T Receive Timing
44 Intel ® LXT9785/LXT9785E SMII - 10BASE-T Transmit Timing
45 Intel ® LXT9785/LXT9785E SS-SMII - 100BASE-TX Receive Timing
46 Intel ® LXT9785/LXT9785E SS-SMII - 100BASE-TX Transmit Timing
47 Intel ® LXT9785/LXT9785E SS-SMII - 100BASE-FX Receive Timing
48 Intel ® LXT9785/LXT9785E SS-SMII - 100BASE-FX Transmit Timing
49 Intel ® LXT9785/LXT9785E SS-SMII - 10BASE-T Receive Timing
50 Intel ® LXT9785/LXT9785E SS-SMII - 10BASE-T Transmit Timing
51 Intel ® LXT9785/LXT9785E RMII - 100BASE-TX Receive Timing
52 Intel ® LXT9785/LXT9785E RMII - 100BASE-TX Transmit Timing
53 Intel ® LXT9785/LXT9785E RMII - 100BASE-FX Receive Timing
54 Intel ® LXT9785/LXT9785E RMII - 100BASE-FX Transmit Timing
55 Intel ® LXT9785/LXT9785E RMII - 10BASE-T Receive Timing
56 Intel ® LXT9785/LXT9785E RMII - 10BASE-T Transmit Timing
57 Intel ® LXT9785/LXT9785E Auto-Negotiation and Fast Link Pulse Timing
58 Intel ® LXT9785/LXT9785E Fast Link Pulse Timing
59 Intel ® LXT9785/LXT9785E MDIO Write Timing (MDIO Sourced by MAC)
60 Intel ® LXT9785/LXT9785E MDIO Read Timing (MDIO Sourced by PHY)
61 Intel ® LXT9785/LXT9785E Power-Up Timing
62 Intel ® LXT9785/LXT9785E Reset Recovery Timing
63 PHY Identifier Bit Mapping
64 Intel ® LXT9785/LXT9785E 208-Pin PQFP Plastic Package Specification
66 Intel ® LXT9785/LXT9785E 241-Ball BGA23 Package Specs - Bottom View (LXT9785BC)
67 Intel ® LXT9785MBC 196-Ball BGA15 Package Specs - Top/Side View (LXT9785MBC)
68 Ordering Information - Sample
1 Intel ® LXT9785/LXT9785E Signal Type Descriptions
2 Intel ® LXT9785/LXT9785E RMII PQFP Pin List
3 Intel ® LXT9785/LXT9785E SMII PQFP Pin List
4 Intel ® LXT9785/LXT9785 SS-SMII PQFP Pin List
5 Intel ® LXT9785/LXT9785E RMII Signal Descriptions – PQFP
6 Intel ® LXT9785/LXT9785E SMII / SS-SMII Common Signal Descriptions – PQFP
7 Intel ® LXT9785/LXT9785E SMII Specific Signal Descriptions – PQFP
8 Intel ® LXT9785/LXT9785E SS-SMII Specific Signal Descriptions – PQFP
9 Intel ® LXT9785/LXT9785E MDIO Control Interface Signals – PQFP
10 Intel ® LXT9785/LXT9785E Signal Detect – PQFP
11 Intel ® LXT9785/LXT9785E Network Interface Signal Descriptions – PQFP
12 Intel ® LXT9785/LXT9785E JTAG Test Signal Descriptions – PQFP
13 Intel ® LXT9785/LXT9785E Miscellaneous Signal Descriptions – PQFP
14 Intel ® LXT9785/LXT9785E LED Signal Descriptions – PQFP
15 Intel ® LXT9785/LXT9785E Power Supply Signal Descriptions – PQFP
16 Intel ® LXT9785/LXT9785E Unused/Reserved Pins – PQFP
17 Intel ® LXT9785/LXT9785E Receive FIFO Depth Considerations

Datasheet sections

8 Datasheet
18 Intel® LXT9785/LXT9785E RMII BGA23 Ball Li st in Alphanumeric Order by Signal Name
19 Intel® LXT9785/LXT9785E RMII BGA23 Ball Li st in Alphanumeric Order by Ball Location
20 Intel® LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by Signal Name
21 Intel® LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by Ball Location
24 Intel
25 Intel ® LXT9785/LXT9785E SMII / SS-SMII Common Signal Descriptions – BGA23
26 Intel ® LXT9785/LXT9785E SMII Specific Signal Descriptions – BGA23
27 Intel ® LXT9785/LXT9785E SS-SMII Specific Signal Descriptions – BGA23
28 Intel ® LXT9785/LXT9785E MDIO Control Interface Signals – BGA23
29 Intel ® LXT9785/LXT9785E Signal Detect – BGA23
30 Intel ® LXT9785/LXT9785E Network Interface Signal Descriptions – BGA23
31 Intel ® LXT9785/LXT9785E JTAG Test Signal Descriptions – BGA23
32 Intel ® LXT9785/LXT9785E Miscellaneous Signal Descriptions – BGA23
33 Intel ® LXT9785/LXT9785E LED Signal Descriptions – BGA23
34 Intel ® LXT9785/LXT9785E Power Supply Signal Descriptions – BGA23
35 Intel ® LXT9785/LXT9785E Unused/Reserved Pins – BGA23
36 Intel ® LXT9785/LXT9785E Receive FIFO Depth Configurations
37 Intel® LXT9785MBC BGA15 Ball List in Alphanu meric Order by Signal Name
38 Intel® LXT9785MBC BGA15 Ball List in Alphanumeric Order by Ball Location
39 Intel ® LXT9785 BGA15 Signal Descriptions
40 Intel ® LXT9785/LXT9785E MDIX Selection
41 Intel ® LXT9785/LXT9785E MII Mode Select
42 Intel ® LXT9785/9785E Global Hardware Configuration Settings
43 Intel ® LXT9785/LXT9785E SMII Signal Summary
44 Intel ® LXT9785/LXT9785E RX Status Encoding Bit Definitions
45 Intel ® LXT9785/LXT9785E SS-SMII
47 Next Page Message #5 Code Word Definitions
48 BSR Mode of Operation
50 Intel
51 Intel ® LXT9785/LXT9785E Absolute Maximum Ratings
52 Intel ® LXT9785/LXT9785E Operating Conditions
55 Intel ® LXT9785/LXT9785E Digital I/O DC Electrical Characteristics – SD Pins
56 Intel ® LXT9785/LXT9785E Required Clock Characteristics
57 Intel ® LXT9785/LXT9785E 100BASE-TX Transceiver Characteristics
58 Intel ® LXT9785/LXT9785E 100BASE-FX Transceiver Characteristics
59 Intel ® LXT9785/LXT9785E 10BASE-T Transceiver Characteristics
60 Intel ® LXT9785/LXT9785E SMII - 100BASE-TX Receive Timing Parameters
61 Intel ® LXT9785/LXT9785E SMII - 100BASE-TX Transmit Timing Parameters
62 Intel ® LXT9785/LXT9785E SMII - 100BASE-FX Receive Timing Parameters
63 Intel ® LXT9785/LXT9785E SMII - 100BASE-FX Transmit Timing Parameters
64 Intel ® LXT9785/LXT9785E SMII - 10BASE-T Receive Timing Parameters
65 Intel ® LXT9785/LXT9785E SMII-10BASE-T Transmit Timing Parameters
66 Intel ® LXT9785/LXT9785E SS-SMII - 100BASE-TX Receive Timing Parameters

Datasheet sections

67 Intel ® LXT9785/LXT9785E SS-SMII - 100BASE-TX Transmit Timing
68 Intel ® LXT9785/LXT9785E SS-SMII - 100BASE-FX Receive Timing Parameters
69 Intel ® LXT9785/LXT9785E SS-SMII - 100BASE-FX Transmit Timing Parameters
70 Intel ® LXT9785/LXT9785E SS-SMII - 10BASE-T Receive Timing Parameters
71 Intel ® LXT9785/LXT9785E SS-SMII - 10BASE-T Transmit Timing Parameters
72 Intel ® LXT9785/LXT9785E RMII - 100BASE-TX Receive Timing Parameters
73 Intel ® LXT9785/LXT9785E RMII - 100BASE-TX Transmit Timing Parameters
74 Intel ® LXT9785/LXT9785E RMII - 100BASE-FX Receive Timing Parameters
75 Intel ® LXT9785/LXT9785E RMII - 100BASE-FX Transmit Timing Parameters
76 Intel ® LXT9785/LXT9785E RMII - 10BASE-T Receive Timing Parameters
77 Intel ® LXT9785/LXT9785E RMII - 10BASE-T Transmit Timing Parameters
78 Intel ® LXT9785/LXT9785E Auto-Negotiation and Fast Link Pulse Timing Parameters
79 Intel ® LXT9785/LXT9785E MDIO Timing Parameters
80 Intel ® LXT9785/LXT9785E Power-Up Timing Parameters
81 Intel ® LXT9785/LXT9785E Reset Recovery Timing Parameters
82 Intel ® LXT9785/LXT9785E Register Set
83 Control Register (Address 0)
84 Status Register (Address 1)
85 PHY Identification Register 1 (Address 2)
86 PHY Identification Register 2 (Address 3)
87 Auto-Negotiation Adve rtisement Register (Address 4)
88 Auto-Negotiation Link Partner Base Page Ability Register (Address 5)
89 Auto-Negotiation Expansion Register (Address 6)
90 Auto-Negotiation Next Page Transmit Register (Address 7)
91 Auto-Negotiation Link Partner Next Page Receive Register (Address 8)
92 Port Configuration Register (A ddress 16, Hex 10)
93 Quick Status Register (Address 17, Hex 11)
94 Interrupt Enable Regist er (Address 18, Hex 12)
95 Interrupt Status Register (Addr ess 19, Hex 13)
96 LED Configuration Register (Address 20, Hex 14 )
97 Receive Error Count Register (Address 21, Hex 15)
98 RMII Out-of-Band Signaling Register (Address 25, Hex 19)
99 Trim Enable Register (Address 27, Hex 1B)
100 Cable Diagnostics Register (Address 29, Hex 1D)
101 Intel
102 Intel® LXT9785MBC 196-Ball BGA15 Package Dim ensions
103 Product Information

Datasheet sections

10 Datasheet
51 Replaced old Figures 5, 6, and 7 with Figure 5 “Intel® LXT9785/LXT9785E 241-Ball BGA23
52 Modified Table 18 “Intel® LXT9785/LXT9785E RMII BGA23 Ball List in Alphanumeric Order by
57 Modified Table 19 “Intel® LXT9785/LXT9785E RMII BGA23 Ball List in Alphanumeric Order by Ball
62 Modified Table 20 “Intel® LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by
67 Modified Table 21 “Intel® LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by Ball
72 Modified Table 22 “Intel® LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by
77 Modified Table 23 “Intel® LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by
82 Modified Table 23 “Intel® LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by

Datasheet sections

12 Datasheet
173 Modified Table 52 “Intel® LXT9785/LXT9785E Operating Conditions”
176 Modified Table 58 “Intel® LXT9785/LXT9785E 100BASE-FX Transceiver Characteristics”
178 Added table note to Table 60 “Intel® LXT9785/LXT9785E SMII - 100BASE-TX Receive Timing
184 Added table note to Table 66 “Intel® LXT9785/LXT9785E SS-SMII - 100BASE-TX Receive Timing
190 Added table note to Table 72 “Intel® LXT9785/LXT9785E RMII - 100BASE-TX Receive Timing
198 Added software power-down and note to Table 80 “Intel® LXT9785/LXT9785E Power-Up Timing
203 Modified Table 86 “PHY Identification Register 2 (Address 3)”
204 Modified Table 87 “Auto-Negotiation Advertisement Register (Address 4)”
211 Modified Table 94 “Interrupt Enable Register (Address 18, Hex 12)”
212 Modified Table 95 “Interrupt Status Register (Address 19, Hex 13)”
213 Modified Table 96 “LED Configuration Register (Address 20, Hex 14)”
226 Added Figure 102 “Intel® LXT9785MBC 196-Ball BGA15 Package Dimensions”

Datasheet sections

1 Changed "pseudo-ECL (PECL)" to "Low Voltage Positive Emitter Coupled Logic (LVPECL)" in the
42 Modified Table 11 “Intel® LXT9785/LXT9785E Network Interface Signal Descriptions – PQFP”,
171 Replaced Figure 37 “Recommended Intel® LXT9785/LXT9785E-to-5 V Fiber Transceiver Interface
174 Modified Table 53 “Intel® LXT9785/LXT9785E Digital I/O DC Electrical Characteristics (VCCIO =
175 Modified Table 54 “Intel® LXT9785/LXT9785E Digital I/O DC Electrical Characteristics (VCCIO =

Datasheet sections

14 Datasheet
211 Modified Table 94 “Interrupt Enable Register (Address 18, Hex 12)”
1 Added bullet to Product Features
49 Modified Table 12 “Intel® LXT9785/LXT9785E Miscellaneous Signal Descriptions” (Added
110 Added Figure 39 “Recommended Intel® LXT9785/LXT9785E-to-5 V Fiber Transceiver Interface
111 Added Figure 40 “ON Semiconductor Triple PECL-to-LVPECL Translator”
112 Modified Table 28 “Absolute Maximum Ratings”
112 Modified Table 29 “Operating Conditions”
129 Modified Figure 53 “RMII - 100BASE-TX Receive Timing” and Table 49 “RMII - 100BASE-TX
131 Modified Figure 55 “RMII - 100BASE-FX Receive Timing” and Table 51 “RMII - 100BASE-FX
133 Modified Figure 57 “RMII - 10BASE-T Receive Timing” and Table 53 “RMII - 10BASE-T Receive

Datasheet sections

148 Modified Table 71 “Interrupt Enable Register (Address 18, Hex 12)”
102 Required Clock Characteristics table: Replaced SMII Input frequency and RMII Input frequency

Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Datasheet The Intel® LXT9785 and Intel® LXT9785E are 8-port Fast Ethernet PHY Transceivers supporting IEEE 802.3 physical layer applications at 10 Mbps and 100 Mbps. These devices provide Serial/Source Synchronous Serial Media Independent Interfaces (SMII/SS-SMII) and Reduced Media Independent Interface (RMII) for switching and other independent port applications. The LXT9785 and LXT9785E are identical except for the IP telephony features included in the LXT9785E transceiver. The LXT9785E is an enhanced version of the LXT9785 that detects Data Terminal Equipment (DTE) requiring power from the switch over a CAT5 cable. The system uses the information collected by the LXT97985E to apply power if the DTE at the far end requires power over the cable, such as an IP telephone. Each network port can provide a twisted-pair (TP) or Low-V oltage Positive Emitter Coupled Logic (LVPECL) interface. The twisted-pair interface supports 10 Mbps and 100 Mbps (10BASE-T and 100BASE-TX) Ethernet over twisted-pair. The LVPECL interface supports 100 Mbps (100BASE-FX) Ethernet over fiber-optic media. The LXT9785/LXT9785E provides three discrete LED driver outputs for each port. The devices support both half-duplex and full-duplex operation at 10 Mbps and 100 Mbps and require only a single 2.5 V power supply.

Applications

Enterprise switches IP telephony switches Storage Area Networks Multi-port Network Interface Cards (NICs) Eight IEEE 802.3-compliant 10BASE-T or 100BASE-TX ports with integrated filters. 100BASE-FX fiber-optic capability on all ports. 2.5 V operation. Low power consumption; 250 mW per port typical. Multiple RMII or SMII/SS-SMII ports for independent PHY port operation. Auto MDI/MDIX crossover capability. Proprietary Optimal Signal Processing™ architecture improves SNR by 3 dB over ideal analog filters. Optimized for dual-high stacked RJ-45 applications. MDIO sectionalization into 2x4 or 1x8 configurations. Supports both auto-negotiation systems and legacy systems without auto-negotiation capability. Robust baseline wander correction. Configurable through the MDIO port or external control pins. JTAG boundary scan. 208-pin PQFP: LXT9785HC, LXT9785EHC, LXT9785HE. 241-ball BGA: LXT9785BC, LXT9785EBC. 196-ball BGA: LXT9785MBC DTE detection for remote powering applications (LXT9785E only). Extended temperature operation of -40oC to +85oC (LXT9785HE). Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003

2 Datasheet

Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY , OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® LXT9785 and Intel® LXT9785E may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, i386, i486, i960, iCOMP, InstantIP, Intel, Intel Centrino, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel Create & Share, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetMerge, Intel NetStructure, Intel Play, Intel Play logo, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel Xeon, Intel XScale, IPLink, Itanium, MCS, MMX, MMX logo, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, PDCharm, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, RemoteExpress, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside., The Journey Inside, TokenExpress, VoiceBrick, VTune, and Xircom are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2003, Intel Corporation

LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers

18 Datasheet

Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003

1.0 Introduction

This document contains information on the Intel® LXT9785/LXT9785E Advanced 8-port 10/100 Mbps Fast Ethernet transceivers.

1.1 What You Will Find in This Document

This document contains the following sections:

Section 3.0, “Pin/Ball Assignments and Signal Descriptions” on page 20 This section contains pin/ball assignments and signal descriptions for the following: — Section 3.1, “PQFP Pin Assignments” on page 20 — Section 3.2, “PQFP Signal Descriptions” on page 36 — Section 3.3, “BGA23 Ball Assignments” on page 51 — Section 3.4, “BGA23 Signal Descriptions” on page 82 — Section 3.5, “BGA15 Ball Assignments” on page 98 — Section 3.6, “BGA15 Signal Descriptions” on page 109
Section 4.0, “Functional Description” on page 116
Section 5.0, “Application Information” on page 164
Section 6.0, “Test Specifications” on page 173
Section 7.0, “Register Definitions” on page 199
Section 8.0, “Package Specifications” on page 221
Section 9.0, “Ordering Information” on page 227

1.2 Related Documents

Intel® LXT9785/LXT9785E Design and Layout Guide 249509 Intel® LXT9785/LXT9785E Specification Update 249357 Intel® LXT9785/LXT9785E 100BASE-FX Fiber Optic Transceivers: Connecting a PECL/ LVPECL Interface 250781 IP Telephony and DTE Discovery Using Intel Ethernet® PHYs 249611

2.0 Block Diagram

Figure 1 provides the LXT9785/LXT9785E block diagram. Figure 1. Intel ® LXT9785/LXT9785E Block Diagram

20 Datasheet

3.0 Pin/Ball Assignments and Signal Descriptions

3.1 PQFP Pin Assignments

Section 3.1.1, “PQFP Pin Assignments – RMII Configuration” on page 21
Section 3.1.2, “PQFP Pin Assignments – SMII Configuration” on page 26
Section 3.1.3, “PQFP Pin Assignments – SS-SMII Configuration” on page 31 Table 1 lists the acronyms and descriptions for signal types.

Table 1. Intel ® LXT9785/LXT9785E Signal Type Descriptions

3.1.1 PQFP Pin Assignments – RMII Configuration

LXT9785/LXT9785 RMII PQFP pin assignments. Figure 2. Intel ® LXT9785 and Intel® LXT9785E RMII 208-Pin PQFP Assignments

Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers

22 Datasheet

Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 Table 2. Intel ® LXT9785/LXT9785E RMII PQFP Pin List

Description

1 CRS_DV6 O, TS,

SL Table 5 (page 36)

2 RxER6/

O, TS, SL, ID, I, ST Table 5 (page 36)

3 TxEN6 I, ID Table 5 (page 36)

4 TxData6_0 I, ID Table 5 (page 36)

5 TxData6_1 I, ID Table 5 (page 36)

6 REFCLK1 I Table 5 (page 36)

7 RxData5_1 O, TS,

ID Table 5 (page 36)

8 RxData5_0 O, TS Table 5 (page 36)

9G N D I O – Table 15 (page 48)

10 CRS_DV5 O, TS,

SL Table 5 (page 36)

11 RxER5 /

O, TS, SL, ID, I, ST Table 5 (page 36)

12 TxEN5 I, ID Table 5 (page 36)

13 TxData5_0 I, ID Table 5 (page 36)

14 TxData5_1 I, ID Table 5 (page 36)

15 RxData4_1 O,

TS,ID Table 5 (page 36)

16 RxData4_0 O, TS Table 5 (page 36)

17 CRS_DV4 O, TS,

SL Table 5 (page 36)

18 VCCIO – Table 15 (page 48)

19 GNDIO – Table 15 (page 48)

20 RxER4 /

O, TS, SL, ID, I, ST Table 5 (page 36)

21 TxEN4 I, ID Table 5 (page 36)

22 TxData4_0 I, ID Table 5 (page 36)

23 TxData4_1 I, ID Table 5 (page 36)

24 MDC1 I, ST, ID Table 8 (page 40)

25 MDIO1 I/O, TS,

SL, IP Table 8 (page 40)

26 MDINT1

OD, TS, SL, IP Table 8 (page 40)

27 RxData3_1 O, TS,

ID Table 5 (page 36)

28 RxData3_0 O, TS Table 5 (page 36)

29 VCCIO – Table 15 (page 48)

30 GNDIO – Table 15 (page 48)

31 CRS_DV3 O, TS,

SL Table 5 (page 36)

32 RxER3 O, TS,

SL, ID Table 5 (page 36)

33 TxEN3 I, ID Table 5 (page 36)

34 TxData3_0 I, ID Table 5 (page 36)

35 TxData3_1 I, ID Table 5 (page 36)

36 RxData2_1 O, TS,

ID Table 5 (page 36)

37 RxData2_0 O, TS Table 5 (page 36)

38 GNDIO – Table 15 (page 48)

39 CRS_DV2 O, TS,

SL Table 5 (page 36)

40 RxER2

(PREASEL) O, TS, SL, ID, I, ST Table 5 (page 36)

41 TxEN2 I, ID Table 5 (page 36)

42 TxData2_0 I, ID Table 5 (page 36)

43 TxData2_1 I, ID Table 5 (page 36)

44 REFCLK0 I Table 5 (page 36)

45 RxData1_1 O, TS,

ID Table 5 (page 36)

46 RxData1_0 O, TS Table 5 (page 36)

47 VCCIO – Table 15 (page 48)

48 GNDIO – Table 15 (page 48)

49 CRS_DV1 O, TS,

SL Table 5 (page 36)

50 RxER1/

O, TS, SL, ID, I, ST Table 5 (page 36)

51 TxEN1 I, ID Table 5 (page 36)

52 TxData1_0 I, ID Table 5 (page 36)

53 TxData1_1 I, ID Table 5 (page 36)

54 RxData0_1 O, TS,

ID Table 5 (page 36)

55 RxData0_0 O, TS Table 5 (page 36)

56 VCCIO – Table 15 (page 48)

57 GNDIO – Table 15 (page 48)

58 CRS_DV0 O, TS,

SL Table 5 (page 36) Pin Symbol Type Reference for Full

Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Datasheet 23 Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003

59 RxER0/

O, TS, SL, ID, I, ST Table 5 (page 36)

60 TxEN0 I, ID Table 5 (page 36)

61 TxData0_0 I, ID Table 5 (page 36)

62 TxData0_1 I, ID Table 5 (page 36)

63 MDC0 I, ST, ID Table 8 (page 40)

64 MDIO0 I/O, TS,

SL, IP Table 8 (page 40)

65 VCCD – Table 15 (page 48)

66 GNDD – Table 15 (page 48)

67 MDINT0

OD, TS, SL, IP Table 8 (page 40)

68 LED3_3 OD, TS,

SO, IP Table 14 (page 47)

69 LED3_2 OD, TS,

SL, IP Table 14 (page 47)

70 LED3_1 OD, TS,

SL, IP Table 14 (page 47)

71 LED2_3 OD, TS,

SL, IP Table 14 (page 47)

72 LED2_2 OD, TS,

SL, IP Table 14 (page 47)

73 LED2_1 OD, TS,

SL, IP Table 14 (page 47)

74 GNDIO – Table 15 (page 48)

75 LED1_3 OD, TS,

SL, IP Table 14 (page 47)

76 LED1_2 OD, TS,

SL, IP Table 14 (page 47)

77 LED1_1 OD, TS,

SL, IP Table 14 (page 47)

78 VCCD – Table 15 (page 48)

79 GNDD – Table 15 (page 48)

80 LED0_3 OD, TS,

SL, IP Table 14 (page 47)

81 LED0_2 OD, TS,

SL, IP Table 14 (page 47)

82 LED0_1 OD, TS,

SL, IP Table 14 (page 47)

83 AMDIX_EN I, ST, IP Table 13 (page 43)

84 MDDIS I, ST, ID Table 9 (page 41)

85 CFG_3 I, ST, ID Table 13 (page 43)

86 CFG_2 I, ST, ID Table 13 (page 43)

Pin Symbol Type Reference for Full

87 CFG_1 I, ST, ID Table 13 (page 43)

88 ADD_4 I, ST, ID Table 13 (page 43)

89 ADD_3 I, ST, ID Table 13 (page 43)

90 ADD_2 I, ST, ID Table 13 (page 43)

91 ADD_1 I, ST, ID Table 13 (page 43)

92 ADD_0 I, ST, ID Table 13 (page 43)

93 TxSLEW_1 I, ST, ID Table 13 (page 43)

94 TxSLEW_0 I, ST, ID Table 13 (page 43)

95 SD_2P5V I, ST, ID Table 10 (page 42)

96 SD0 I Table 10 (page 42)

97 SD1 I Table 10 (page 42)

98 VCCPECL – Table 15 (page 48)

99 GNDPECL – Table 15 (page 48)

100 SD2 I Table 10 (page 42)

101 SD3 I Table 10 (page 42)

102 N/C – Table 17 (page 50)

103 VCCR0 – Table 15 (page 48)

104 TPFIP0 AO/AI Table 11 (page 42)

105 TPFIN0 AO/AI Table 11 (page 42)

106 GNDR0 – Table 15 (page 48)

107 TPFOP0 AO/AI Table 11 (page 42)

108 TPFON0 AO/AI Table 11 (page 42)

109 VCCT0/1 – Table 15 (page 48)

110 TPFON1 AO/AI Table 11 (page 42)

111 TPFOP1 AO/AI Table 11 (page 42)

112 GNDR1 – Table 15 (page 48)

113 GNDT0/1 – Table 15 (page 48)

114 TPFIN1 AO/AI Table 11 (page 42)

115 TPFIP1 AO/AI Table 11 (page 42)

116 VCCR1 – Table 15 (page 48)

117 VCCR2 – Table 15 (page 48)

118 TPFIP2 AO/AI Table 11 (page 42)

119 TPFIN2 AO/AI Table 11 (page 42)

120 GNDR2 – Table 15 (page 48)

121 TPFOP2 AO/AI Table 11 (page 42)

122 TPFON2 AO/AI Table 11 (page 42)

123 VCCT2/3 – Table 15 (page 48)

124 TPFON3 AO/AI Table 11 (page 42)

Pin Symbol Type Reference for Full

Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers

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Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003

125 TPFOP3 AO/AI Table 11 (page 42)

126 GNDR3 – Table 15 (page 48)

127 GNDT2/3 – Table 15 (page 48)

128 TPFIN3 AO/AI Table 11 (page 42)

129 TPFIP3 AO/AI Table 11 (page 42)

130 VCCR3 – Table 15 (page 48)

131 VCCR4 – Table 15 (page 48)

132 TPFIP4 AO/AI Table 11 (page 42)

133 TPFIN4 AO/AI Table 11 (page 42)

134 GNDT4/5 – Table 15 (page 48)

135 GNDR4 – Table 15 (page 48)

136 TPFOP4 AO/AI Table 11 (page 42)

137 TPFON4 AO/AI Table 11 (page 42)

138 VCCT4/5 – Table 15 (page 48)

139 TPFON5 AO/AI Table 11 (page 42)

140 TPFOP5 AO/AI Table 11 (page 42)

141 GNDR5 – Table 15 (page 48)

142 TPFIN5 AO/AI Table 11 (page 42)

143 TPFIP5 AO/AI Table 11 (page 42)

144 VCCR5 – Table 15 (page 48)

145 VCCR6 – Table 15 (page 48)

146 TPFIP6 AO/AI Table 11 (page 42)

147 TPFIN6 AO/AI Table 11 (page 42)

148 GNDT6/7 – Table 15 (page 48)

149 GNDR6 – Table 15 (page 48)

150 TPFOP6 AO/AI Table 11 (page 42)

151 TPFON6 AO/AI Table 11 (page 42)

152 VCCT6/7 – Table 15 (page 48)

153 TPFON7 AO/AI Table 11 (page 42)

154 TPFOP7 AO/AI Table 11 (page 42)

155 GNDR7 – Table 15 (page 48)

156 TPFIN7 AO/AI Table 11 (page 42)

157 TPFIP7 AO/AI Table 11 (page 42)

158 VCCR7 – Table 15 (page 48)

159 N/C – Table 17 (page 50)

160 N/C – Table 17 (page 50)

161 SD4 I Table 10 (page 42)

162 SD5 I Table 10 (page 42)

Pin Symbol Type Reference for Full

163 GNDPECL – Table 15 (page 48)

164 VCCPECL – Table 15 (page 48)

165 SD6 I Table 10 (page 42)

166 SD7 I Table 10 (page 42)

167 TDI I, ST, IP Table 12 (page 43)

168 TDO O, TS Table 12 (page 43)

169 TMS I, ST, IP Table 12 (page 43)

170 TCK I, ST, ID Table 12 (page 43)

171 TRST I, ST, IP Table 12 (page 43)

172 N/C – Table 17 (page 50)

173 G_FX/TP I, ST, ID Table 13 (page 43)

174 PWRDWN I, ST, ID Table 13 (page 43)

175 RESET I, ST, IP Table 13 (page 43)

176 SECTION I, ST, ID Table 13 (page 43)

177 ModeSel0 I, ST, ID Table 13 (page 43)

178 ModeSel1 I, ST, ID Table 13 (page 43)

179 SGND – Table 15 (page 48)

180 LED4_1 OD, TS,

SL, IP Table 14 (page 47)

181 LED4_2 OD, TS,

SL, IP Table 14 (page 47)

182 LED4_3 OD, TS,

SL, IP Table 14 (page 47)

183 GNDD – Table 15 (page 48)

184 VCCD – Table 15 (page 48)

185 LED5_1 OD, TS,

SL, IP Table 14 (page 47)

186 LED5_2 OD, TS,

SL, IP Table 14 (page 47)

187 LED5_3 OD, TS,

SL, IP Table 14 (page 47)

188 GNDIO – Table 15 (page 48)

189 LED6_1 OD, TS,

SL, IP Table 14 (page 47)

190 LED6_2 OD, TS,

SL, IP Table 14 (page 47)

191 LED6_3 OD, TS,

SL, IP Table 14 (page 47)

192 LED7_1 OD, TS,

SL, IP Table 14 (page 47)

193 LED7_2 OD, TS,

SL, IP Table 14 (page 47) Pin Symbol Type Reference for Full

Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Datasheet 25 Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003

194 LED7_3 OD, TS,

SL, IP Table 5 (page 36)

195 GNDD – Table 15 (page 48)

196 VCCD – Table 15 (page 48)

197 RxData7_1 O, TS,

ID Table 5 (page 36)

198 RxData7_0 O, TS Table 5 (page 36)

199 GNDIO – Table 15 (page 48)

200 CRS_DV7 O, TS,

SL Table 5 (page 36)

201 RxER7 O, TS,

SL, ID Table 5 (page 36)

202 TxEN7 I, ID Table 5 (page 36)

203 TxData7_0 I, ID Table 5 (page 36)

204 TxData7_1 I, ID Table 5 (page 36)

205 RxData6_1 O, TS,

ID Table 5 (page 36)

206 RxData6_0 O, TS Table 5 (page 36)

207 GNDIO – Table 15 (page 48)

208 VCCIO – Table 15 (page 48)

Pin Symbol Type Reference for Full

26 Datasheet

3.1.2 PQFP Pin Assignments – SMII Configuration

LXT9785/LXT9785E SMII PQFP pin assignments. Figure 3. Intel ® LXT9785/LXT9785E SMII 208-Pin PQFP Assignments

Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Datasheet 27 Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 Table 3. Intel ® LXT9785/LXT9785E SMII PQFP Pin List 1N / C – Table 16 (page 50)

2 N/C

(LINKHOLD) I, ID, Table 16 (page 50) 3N / C – Table 16 (page 50)

4 TxData6 I, ID Table 6 (page 39)

5N / C – Table 16 (page 50) 7N / C – Table 16 (page 50)

8 RxData5 O, TS Table 6 (page 39)

9 GNDIO – Table 15 (page 48)

10 N/C – Table 16 (page 50)

11 FIFOSEL1 I, ID,

ST Table 16 (page 50)

12 N/C – Table 16 (page 50)

13 TxData5 I, ID Table 6 (page 39)

14 N/C – Table 16 (page 50)

15 N/C – Table 16 (page 50)

16 RxData4 O, TS Table 6 (page 39)

17 N/C – Table 16 (page 50)

20 FIFOSEL0 I, ID,

ST Table 16 (page 50)

21 N/C I, ID Table 16 (page 50)

22 TxData4 I, ID Table 6 (page 39)

23 N/C – Table 16 (page 50)

24 MDC1 I, ST, ID Table 9 (page 41)

SL, IP Table 9 (page 41) OD, TS, SL, IP Table 9 (page 41)

27 N/C – Table 16 (page 50)

28 RxData3 O, TS Table 6 (page 39)

31 N/C – Table 16 (page 50)

32 N/C – Table 16 (page 50)

33 N/C – Table 16 (page 50)

34 TxData3 I, ID Table 6 (page 39)

35 SYNC0 I, ID Table 7 (page 39)

36 N/C – Table 16 (page 50)

37 RxData2 O, TS Table 6 (page 39)

39 N/C – Table 16 (page 50)

40 PREASEL I, ID,

ST Table 16 (page 50)

41 N/C – Table 16 (page 50)

42 TxData2 I, ID Table 6 (page 39)

43 N/C – Table 16 (page 50)

45 N/C – Table 16 (page 50)

46 RxData1 O, TS Table 6 (page 39)

49 N/C – Table 16 (page 50)

50 PAUSE I, ID,

ST Table 13 (page 43)

51 N/C – Table 16 (page 50)

52 TxData1 I, ID Table 6 (page 39)

53 N/C – Table 16 (page 50)

54 N/C – Table 16 (page 50)

55 RxData0 O, TS Table 6 (page 39)

58 N/C – Table 16 (page 50)

59 MDIX I, ID,

ST Table 13 (page 43)

60 N/C – Table 16 (page 50)

61 TxData0 I, ID Table 6 (page 39)

62 N/C – Table 16 (page 50)

63 MDC0 I, ST, ID Table 9 (page 41)

SL, IP Table 9 (page 41) OD, TS, SL, IP Table 9 (page 41) Pin Symbol Type 1 Reference for Full

Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers

28 Datasheet

Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003

68 LED3_3

OD, TS, SO, IP Table 14 (page 47)

69 LED3_2

OD, TS, SL, IP Table 14 (page 47)

70 LED3_1

OD, TS, SL, IP Table 14 (page 47)

71 LED2_3

OD, TS, SL, IP Table 14 (page 47)

72 LED2_2

OD, TS, SL, IP Table 14 (page 47)

73 LED2_1

OD, TS, SL, IP Table 14 (page 47)

75 LED1_3

OD, TS, SL, IP Table 14 (page 47)

76 LED1_2

OD, TS, SL, IP Table 14 (page 47)

77 LED1_1

OD, TS, SL, IP Table 14 (page 47)

80 LED0_3

OD, TS, SL, IP Table 14 (page 47)

81 LED0_2

OD, TS, SL, IP Table 14 (page 47)

82 LED0_1

OD, TS, SL, IP Table 14 (page 47)

84 MDDIS I, ST, ID Table 8 (page 40)

Pin Symbol Type 1 Reference for Full

104 TPFIP0 AI/AO Table 11 (page 42)

105 TPFIN0 AI/AO Table 11 (page 42)

114 TPFIN1 AI/AO Table 11 (page 42)

115 TPFIP1 AI/AO Table 11 (page 42)

118 TPFIP2 AI/AO Table 11 (page 42)

119 TPFIN2 AI/AO Table 11 (page 42)

128 TPFIN3 AI/AO Table 11 (page 42)

129 TPFIP3 AI/AO Table 11 (page 42)

Pin Symbol Type 1 Reference for Full

Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Datasheet 29 Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003

132 TPFIP4 AI/AO Table 11 (page 42)

133 TPFIN4 AI/AO Table 11 (page 42)

142 TPFIN5 AI/AO Table 11 (page 42)

143 TPFIP5 AI/AO Table 11 (page 42)

146 TPFIP6 AI/AO Table 11 (page 42)

147 TPFIN6 AI/AO Table 11 (page 42)

156 TPFIN7 AI/AO Table 11 (page 42)

157 TPFIP7 AI/AO Table 11 (page 42)

Pin Symbol Type 1 Reference for Full

180 LED4_1

OD, TS, SL, IP Table 14 (page 47)

181 LED4_2

OD, TS, SL, IP Table 14 (page 47)

182 LED4_3

OD, TS, SL, IP Table 14 (page 47)

185 LED5_1

OD, TS, SL, IP Table 14 (page 47)

186 LED5_2

OD, TS, SL, IP Table 14 (page 47)

187 LED5_3

OD, TS, SL, IP Table 14 (page 47)

189 LED6_1

OD, TS, SL, IP Table 14 (page 47)

190 LED6_2

OD, TS, SL, IP Table 14 (page 47)

191 LED6_3

OD, TS, SL, IP Table 14 (page 47)

192 LED7_1

OD, TS, SL, IP Table 14 (page 47) Pin Symbol Type 1 Reference for Full

Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers

30 Datasheet

Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003

193 LED7_2

OD, TS, SL, IP Table 14 (page 47)

194 LED7_3

OD, TS, SL, IP Table 5 (page 36)

197 N/C O, TS,

ID Table 16 (page 50)

198 RxData7 O, TS Table 6 (page 39)

200 N/C – Table 16 (page 50)

201 N/C – Table 16 (page 50)

202 N/C – Table 16 (page 50)

203 TxData7 I, ID Table 6 (page 39)

204 SYNC1 I, ID Table 5 (page 36)

205 N/C – Table 16 (page 50)

206 RxData6 O, TS Table 6 (page 39)

Pin Symbol Type 1 Reference for Full

3.1.3 PQFP Pin Assignments – SS-SMII Configuration

the LXT9785/LXT9785E SS-SMII PQFP pin assignments. Figure 4. Intel ® LXT9785/LXT9785E SS-SMII 208-Pin PQFP Assignments

Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers

32 Datasheet

Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 Table 4. Intel ® LXT9785/LXT9785 SS-SMII PQFP Pin List 1N / C – Table 16 (page 50) LINKHOLD Table 13 (page 43) 3N / C – Table 16 (page 50) 5N / C I Table 16 (page 50)

6 REFCLK1 I Table 6 (page 39)

7 RxData5 O, TS,

ID Table 8 (page 40) 8N / C – Table 16 (page 50)

11 FIFOSEL1 I, ID, ST Table 13 (page 43)

15 RxData4 O, TS,

ID Table 8 (page 40)

16 N/C – Table 16 (page 50)

17 RxSYNC1 O, TS,

ID Table 8 (page 40)

20 FIFOSEL0 I, ID, ST Table 13 (page 43)

21 RxCLK1 O, TS,

ID Table 8 (page 40) SL, IP Table 9 (page 41)

26 MDINT1 OD, TS,

SL, IP Table 9 (page 41)

27 RxData3 O, TS,

ID Table 8 (page 40)

28 N/C – Table 16 (page 50)

32 TxCLK0 I, ID Table 8 (page 40)

35 TxSYNC0 I, ID Table 8 (page 40)

36 RxData2 O, TS,

ID Table 8 (page 40)

37 N/C – Table 16 (page 50)

40 PREASEL I, ST Table 13 (page 43)

44 REFCLK0 I Table 6 (page 39)

45 RxData1 O, TS,

ID Table 8 (page 40)

46 N/C – Table 16 (page 50)

50 PAUSE I, ID, ST Table 13 (page 43)

54 RxData0 O, TS,

ID Table 8 (page 40)

55 N/C – Table 16 (page 50)

58 RxSYNC0 O, TS,

ID Table 8 (page 40)

59 MDIX I, ID, ST Table 13 (page 43)

60 RxCLK0 – Table 8 (page 40)

SL, IP Table 9 (page 41) Pin Symbol Type 1 Reference for Full

Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Datasheet 33 Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003

67 MDINT0 OD, TS,

SL, IP Table 9 (page 41) SO, IP Table 14 (page 47) SL, IP Table 14 (page 47) SL, IP Table 14 (page 47) SL, IP Table 14 (page 47) SL, IP Table 14 (page 47) SL, IP Table 14 (page 47) SL, IP Table 14 (page 47) SL, IP Table 14 (page 47) SL, IP Table 14 (page 47) SL, IP Table 14 (page 47) SL, IP Table 14 (page 47) SL, IP Table 14 (page 47) Pin Symbol Type 1 Reference for Full

102 N/C – Table 16 (page 50)

Pin Symbol Type 1 Reference for Full

Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers

34 Datasheet

Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003

159 N/C – Table 16 (page 50)

160 N/C – Table 16 (page 50)

172 N/C – Table 16 (page 50)

Pin Symbol Type 1 Reference for Full SL, IP Table 14 (page 47) SL, IP Table 14 (page 47) SL, IP Table 14 (page 47) SL, IP Table 14 (page 47) SL, IP Table 14 (page 47) SL, IP Table 14 (page 47) SL, IP Table 14 (page 47) SL, IP Table 14 (page 47) SL, IP Table 14 (page 47) SL, IP Table 14 (page 47) SL, IP Table 14 (page 47) SL, IP Table 14 (page 47)

197 RxData7 O, TS,

ID Table 8 (page 40)

198 N/C – Table 16 (page 50)

201 TxCLK1 I, ID Table 8 (page 40)

Pin Symbol Type 1 Reference for Full

Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Datasheet 35 Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003

204 TxSYNC1 I, ID Table 8 (page 40)

205 RxData6 O, TS,

ID Table 8 (page 40)

206 N/C – Table 16 (page 50)

Pin Symbol Type 1 Reference for Full

36 Datasheet

3.2 PQFP Signal Descriptions

3.2.1 Signal Name Conventions

Port Number Only. Individual signals that apply to a particular port are designated by the Signal Mnemonic, immediately followed by the Port Designation. For example, Transmit Enable signals would be identified as TxEN0, TxEN1, and TxEN2.
Serial Number Only. A set of signals which are not tied to any specific port are designated by the Signal Mnemonic, followed by an underscore and a serial designation. For example, a set of three Global Configuration signals would be identified as CFG_1, CFG_2, and CFG_3.
Port and Serial Number. In cases where each port is assigned a set of multiple signals, each signal is designated in the following order: Signal Mnemonic, Port Designation, an underscore, and the serial designation. For example, a set of three Port Configuration signals would be identified as RxData0_0 and RxData0_1, RxData1_0 and RxData1_1, and RxData2_0 and RxData2_1.

3.2.2 PQFP Signal Descriptions – RMII, SMII, and SS-SMII Configurations

page 50 provide PQFP signal descriptions. Ball designations are included for cross-reference. Table 5. Intel ® LXT9785/LXT9785E RMII Signal Descriptions – PQFP (Sheet 1 of 3) from port 0 are clocked in synchronously to REFCLK. from port 2 are clocked in synchronously to REFCLK.

Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID

resistors are also disabled when the output is enabled.

RxData[0:7]_0, RxData[0:7]_1, CRS_DV[0:7] and RxER[0:7] outputs are three-stated in Isolation and H/W

Power-Down modes and during H/W reset.

from port 3 are clocked in synchronously to REFCLK. from port 4 are clocked in synchronously to REFCLK. from port 5 are clocked in synchronously to REFCLK. from port 6 are clocked in synchronously to REFCLK. from port 7 are clocked in synchronously to REFCLK. Transmit Enable - Ports 0-7. Active High input enables respective port transmitter. This signal must be synchronous to the REFCLK. Table 5. Intel ® LXT9785/LXT9785E RMII Signal Descriptions – PQFP (Sheet 2 of 3)

Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID

resistors are also disabled when the output is enabled.

RxData[0:7]_0, RxData[0:7]_1, CRS_DV[0:7] and RxER[0:7] outputs are three-stated in Isolation and H/W

Power-Down modes and during H/W reset.

38 Datasheet

Carrier Sense/Receive Data Valid - Ports 0-7. asserted asynchronously with respect to REFCLK. group is invalid, or that PLL is not locked. Table 5. Intel ® LXT9785/LXT9785E RMII Signal Descriptions – PQFP (Sheet 3 of 3)

Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID

resistors are also disabled when the output is enabled.

RxData[0:7]_0, RxData[0:7]_1, CRS_DV[0:7] and RxER[0:7] outputs are three-stated in Isolation and H/W

Power-Down modes and during H/W reset.

Table 6. Intel ® LXT9785/LXT9785E SMII / SS-SMII Common Signal Descriptions – PQFP connected regardless of sectionalization mode.

Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
The IP/ID resistors are disabled during H/W Power-Down mode.

Table 7. Intel ® LXT9785/LXT9785E SMII Specific Signal Descriptions – PQFP to be used when 2x4 port sectionalization is chosen.

Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
The IP/ID resistors are disabled during H/W Power-Down mode.
RxData[0:7] outputs are three-stated in Isolation and hardware power-down modes and during hardware

40 Datasheet

Table 8. Intel ® LXT9785/LXT9785E SS-SMII Specific Signal Descriptions – PQFP SS-SMII Transmit Synchronization. used when 1x8 port sectionalization is selected. SS-SMII Receive Synchronization. only enabled when SS-SMII mode is enabled.

Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID

resistors are also disabled when the output is enabled.

RxData[0:7], RxSYNC[0:1], and RxCLK[0:1] outputs are three-stated in Isolation and H/W Power-Down

Table 9. Intel ® LXT9785/LXT9785E MDIO Control Interface Signals – PQFP Management Data Input/Output. accesses ports 0-3 and MDIO1 accesses ports 4-7. Refer to Figure 21 on page 140. accesses and MDC1 clocks ports 4-7 register accesses. Refer to Figure 21 on page 140.

84 L1 MDDIS I, ST, ID

their respective bits at power up and reset.

Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID

resistors are also disabled when the output is enabled. [0:1] outputs are three-stated in H/W Power-Down mode and during H/W reset.

Supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation,

where X is the register number (0-32) and Y is the bit number (0-15).

42 Datasheet

Table 10. Intel ® LXT9785/LXT9785E Signal Detect – PQFP

95 P1 SD_2P5V I, ST, ID

Signal Detect 2.5 Volt Interface. SD input threshold voltage select. are only active for ports operating in fiber mode).

Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
The IP/ID resistors are disabled during H/W Power-Down mode.
Tie SD[0:7] inputs to GNDPECL if unused.

Table 11. Intel ® LXT9785/LXT9785E Network Interface Signal Descriptions – PQFP 10BASE-T signals from the line.

Type Column Coding: AI = Analog Input, AO = Analog Output.
Switched to Inputs (see TPFIP/N description) when not in fiber mode and MDIX is not active [that is,

twisted-pair, non-crossover MDI mode].

Switched to Outputs (see TPFOP/N description) when not in fiber mode and MDIX is not active [that is,

twisted-pair, non-crossover MDI mode].

Table 12. Intel ® LXT9785/LXT9785E JTAG Test Signal Descriptions – PQFP 167 N14 TDI I, ST, IP Test Data Input. Test data sampled with respect to the rising edge of TCK. 168 N15 TDO O, TS Test Data Output. Test data driven with respect to the falling edge of TCK. 169 N16 TMS I, ST, IP Test Mode Select. 170 M16 TCK I, ST, ID Test Clock. 171 M17 TRST I, ST, IP Test Reset.

Type Column Coding: I = Input, O = Output, OD = Open Drain, TS = Three-State-able output, SMT =
The IP/ID resistors are disabled during H/W Power-Down mode. If a pin is an output or an I/O, the IP/ID

resistors are also disabled when the output is enabled.

TDO output is three-stated in H/W Power-Down mode and during H/W reset.

Table 13. Intel ® LXT9785/LXT9785E Miscellaneous Signal Descriptions – PQFP (Sheet 1 of 4) Tx Output Slew Controls 0 and 1 Defaults. and overwritten after startup / reset.

Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS =
The IP/ID resistors are disabled during hardware power-down mode.

44 Datasheet

50 D5 PAUSE I, ID, ST

capabilities on all ports during auto-negotiation.

174 L14 PWRDWN I, ST, ID

175 M15 RESET

mixed and must be all RMII, SMII, or SS-SMII.

176 L15 SECTION I, ST, ID

This pin selects sectionalization into separate ports. Table 13. Intel ® LXT9785/LXT9785E Miscellaneous Signal Descriptions – PQFP (Sheet 2 of 4)

Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS =
The IP/ID resistors are disabled during hardware power-down mode.

83 K1 AMDIX_EN I, ST, IP

(regardless of segmentation) is selected for all ports.

59 D2 MDIX I, ID, ST

When AMDIX_EN is active this pin is ignored. MDI or the MDIX function regardless of segmentation. a pull-up) in non-RMII modes. Global Port Configuration Defaults 1-3. (refer to page 129 for details).

173 M14 G_FX/TP

Global FX/TP Enable Default. Configuration Register (Address 16, Hex 10)” on page 207. Table 13. Intel ® LXT9785/LXT9785E Miscellaneous Signal Descriptions – PQFP (Sheet 3 of 4)

Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS =
The IP/ID resistors are disabled during hardware power-down mode.

46 Datasheet

and overwritten after startup/reset. state is set via the internal pull-down resistors. FIFO Depth Considerations” on page 50.

40 D7 PREASEL I, ID, ST

internal pull-down resistors.

2 A17 LINKHOLD ID

High, the LXT9785/9785E powers down all ports. Table 13. Intel ® LXT9785/LXT9785E Miscellaneous Signal Descriptions – PQFP (Sheet 4 of 4)

Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS =
The IP/ID resistors are disabled during hardware power-down mode.

Table 14. Intel ® LXT9785/LXT9785E LED Signal Descriptions – PQFP (Sheet 1 of 2) 20, Hex 14)” on page 213 for details). 20, Hex 14)” on page 213 for details). 20, Hex 14)” on page 213 for details). 20, Hex 14)” on page 213 for details). 20, Hex 14)” on page 213 for details).

Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
The IP/ID resistors are disabled during H/W Power-Down mode. If a pin is an output or an I/O, the IP/ID

resistors are also disabled when the output is enabled.

The LED outputs are three-stated in H/W Power-Down mode and during H/W reset.

48 Datasheet

20, Hex 14)” on page 213 for details). 20, Hex 14)” on page 213 for details). 20, Hex 14)” on page 213 for details). Table 15. Intel ® LXT9785/LXT9785E Power Supply Signal Descriptions – PQFP (Sheet 1 of 2) F5, J5 VCCD - Digital Power Supply - Core. +2.5 V supply for core digital circuits. Digital Power Supply - I/O Ring. Digital Power Supply - PECL Signal Detect Inputs. VCCR - Analog Power Supply - Receive. +2.5 V supply for all analog receive circuits.

Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =

Table 14. Intel ® LXT9785/LXT9785E LED Signal Descriptions – PQFP (Sheet 2 of 2)

Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
The IP/ID resistors are disabled during H/W Power-Down mode. If a pin is an output or an I/O, the IP/ID

resistors are also disabled when the output is enabled.

The LED outputs are three-stated in H/W Power-Down mode and during H/W reset.

VCCT - Analog Power Supply - Transmit. +2.5 V supply for all analog transmit circuits. GNDIO - Digital GND - I/O Ring. Ground return for digital I/O circuits (VCCIO). 99, 163 M5, M13 GNDPECL - Digital GND - PECL Signal Detect Inputs. Ground return for PECL Signal Detect input circuits. pins can be tied together using a single ground plane. pins can be tied together using a single ground plane.

179 K14 SGND -

together using a single ground plane. Table 15. Intel ® LXT9785/LXT9785E Power Supply Signal Descriptions – PQFP (Sheet 2 of 2)

Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =

50 Datasheet

Table 16. Intel ® LXT9785/LXT9785E Unused/Reserved Pins – PQFP

Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =

Table 17. Intel ® LXT9785/LXT9785E Receive FIFO Depth Considerations

3.3 BGA23 Ball Assignments

Table 3.3.1 “RMII BGA23 Ball List” on page 52
Table 3.3.2 “SMII BGA23 Ball List” on page 62
Table 3.3.3 “SS-SMII BGA23 Ball List” on page 72
Table 3.4 “BGA23 Signal Descriptions” on page 82 Figure 5 illustrates the LXT9785/LXT9785E 241-ball BGA23 ball locations for RMII, SMII, and SS-SMII.

Figure 5. Intel® LXT9785/LXT9785E 241-Ball BGA23 Assignments (Top View)

52 Datasheet

3.3.1 RMII BGA23 Ball List

Table 18 “Intel® LXT9785/LXT9785E RMII BGA23 Ball List in Alphanumeric Order by Signal Name”
Table 19 “Intel® LXT9785/LXT9785E RMII BGA23 Ball List in Alphanumeric Order by Ball Location” on page 57

Table 18. Intel® LXT9785/LXT9785E RMII BGA23 Ball List in Alphanumeric Order by Signal

LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Datasheet 53 Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 GNDT P14 – Table 34 (page 95) GNDT R1 – Table 34 (page 95) GNDT R3 – Table 34 (page 95) GNDT R5 – Table 34 (page 95) GNDT R15 – Table 34 (page 95) GNDT R17 – Table 34 (page 95) GNDT T17 – Table 34 (page 95) GNDT U2 – Table 34 (page 95) GNDT U4 – Table 34 (page 95) GNDT U6 – Table 34 (page 95) GNDT U10 – Table 34 (page 95) GNDT U12 – Table 34 (page 95) GNDT U14 – Table 34 (page 95) GNDT U16 – Table 34 (page 95) GNDT U17 – Table 34 (page 95) LED0_1 K3 OD, TS, SL, IP Table 33 (page 94) LED0_2 K2 OD, TS, SL, IP Table 33 (page 94) LED0_3 J1 OD, TS, SL, IP Table 33 (page 94) LED1_1 J4 OD, TS, SL, IP Table 33 (page 94) LED1_2 J3 OD, TS, SL, IP Table 33 (page 94) LED1_3 H1 OD, TS, SL, IP Table 33 (page 94) LED2_1 H2 OD, TS, SL, IP Table 33 (page 94) LED2_2 H3 OD, TS, SL, IP Table 33 (page 94) LED2_3 G1 OD, TS, SL, IP Table 33 (page 94) LED3_1 F2 OD, TS, SL, IP Table 33 (page 94) LED3_2 G3 OD, TS, SL, IP Table 33 (page 94) LED3_3 G4 OD, TS, SO, IP Table 33 (page 94) LED4_1 K16 OD, TS, SL, IP Table 33 (page 94) LED4_2 K17 OD, TS, SL, IP Table 33 (page 94) Signal Ball Type 1 Reference for Full Description LED4_3 J17 OD, TS, SL, IP Table 33 (page 94) LED5_1 J15 OD, TS, SL, IP Table 33 (page 94) LED5_2 J16 OD, TS, SL, IP Table 33 (page 94) LED5_3 H17 OD, TS, SL, IP Table 33 (page 94) LED6_1 H15 OD, TS, SL, IP Table 33 (page 94) LED6_2 H16 OD, TS, SL, IP Table 33 (page 94) LED6_3 G17 OD, TS, SL, IP Table 33 (page 94) LED7_1 G15 OD, TS, SL, IP Table 33 (page 94) LED7_2 F17 OD, TS, SL, IP Table 33 (page 94) LED7_3 F16 OD, TS, SL, IP Table 33 (page 94) MDC0 E1 I, ST, ID Table 28 (page 87) MDC1 B10 I, ST, ID Table 28 (page 87) MDDIS L1 I, ST, ID Table 28 (page 87) MDINT0 F1 OD, TS, SL, IP Table 28 (page 87) MDINT1 C9 OD, TS, SL, IP Table 28 (page 87) MDIO0 F3 I/O, TS, SL, IP Table 28 (page 87) MDIO1 A10 I/O, TS, SL, IP Table 28 (page 87) ModeSel0 L16 I, ST, ID Table 32 (page 90) ModeSel1 L17 I, ST, ID Table 32 (page 90) N/C F15 – Table 35 (page 97) N/C G2 – Table 35 (page 97) N/C G5 – Table 35 (page 97) N/C G14 – Table 35 (page 97) N/C G16 – Table 35 (page 97) N/C H4 – Table 35 (page 97) N/C H14 – Table 35 (page 97) N/C J2 – Table 35 (page 97) N/C J13 – Table 35 (page 97) N/C K4 – Table 35 (page 97) N/C K15 – Table 35 (page 97) Signal Ball Type 1 Reference for Full Description

LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers

54 Datasheet

Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 No ball F6 – – No ball F7 – – No ball F8 – – No Ball E8 – – No Ball E10 No Ball F9 – – No Ball F10 – – No Ball F11 – – No Ball F12 – – No Ball G6 – – No Ball G7 – – No Ball G8 – – No Ball G9 – – No Ball G10 – – No Ball G11 – – No Ball G12 – – No Ball H5 – – No Ball H6 – – No Ball H7 – – No Ball H11 – – No Ball H12 – – No Ball H13 – – No Ball J6 – – No Ball J7 – – No Ball J11 – – No Ball J12 – – No Ball K5 – – No Ball K6 – – No Ball K7 – – No Ball K11 – – No Ball K12 – – No Ball K13 – – No Ball L6 – – No Ball L7 – – No Ball L8 – – No Ball L9 – – No Ball L10 – – No Ball L11 – – Signal Ball Type

1 Reference for

No Ball L11 – – No Ball M6 – – No Ball M7 – – No Ball M8 – – No Ball M9 – – No Ball M10 – – No Ball M11 – – No Ball M12 – – No Ball N8 – – No Ball N10 – – PWRDWN L14 I, ST, ID Table 32 (page 90) REFCLK0 E6 I Table 24 (page 82) REFCLK1 E12 I Table 24 (page 82) RESET M15 I, ST, IP Table 32 (page 90) RxData0_0 C2 O, TS Table 24 (page 82) RxData0_1 B1 O, TS, ID Table 24 (page 82) RxData1_0 A3 O, TS Table 24 (page 82) RxData1_1 B4 O, TS, ID Table 24 (page 82) RxData2_0 B6 O, TS Table 24 (page 82) RxData2_1 C7 O, TS, ID Table 24 (page 82) RxData3_0 D9 O, TS Table 24 (page 82) RxData3_1 B9 O, TS, ID Table 24 (page 82) RxData4_0 A13 O, TS Table 24 (page 82) RxData4_1 C12 O, TS,ID Table 24 (page 82) RxData5_0 B14 O, TS Table 24 (page 82) RxData5_1 B15 O, TS, ID Table 24 (page 82) RxData6_0 C15 O, TS Table 24 (page 82) RxData6_1 B17 O, TS, ID Table 24 (page 82) RxData7_0 E16 O, TS Table 24 (page 82) RxData7_1 F14 O, TS, ID Table 24 (page 82) RxER0 (MDIX) D2 O, TS, SL, ID, I, ST Table 32 (page 90) RxER1 (PAUSE) D5 O, TS, SL, ID, I, ST Table 32 (page 90) RxER2 (PREASEL) D7 O, TS, SL, ID, I, ST Table 24 (page 82) RxER3 C8 O, TS, SL, ID Table 24 (page 82) RxER4 (FIFOSEL0) A12 O, TS, SL, ID, I, ST Table 24 (page 82) Signal Ball Type 1 Reference for Full Description

LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Datasheet 55 Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 RxER5 (FIFOSEL1) A15 O, TS, SL, ID, I, ST Table 24 (page 82) RxER6LINK HOLD A17 O, TS, SL, ID Table 24 (page 82) RxER7 D17 O, TS, SL, ID Table 24 (page 82) SD_2P5V P1 I, ST, ID Table 29 (page 88) SD0 P2 I Table 29 (page 88) SD1 N4 I Table 29 (page 88) SD2 P3 I Table 29 (page 88) SD3 N5 I Table 29 (page 88) SD4 P15 I Table 29 (page 88) SD5 P16 I Table 29 (page 88) SD6 P17 I Table 29 (page 88) SD7 N17 I Table 29 (page 88) SECTION L15 I, ST, ID Table 32 (page 90) SGND K14 – Table 34 (page 95) TCK M16 I, ST, ID Table 31 (page 89) TDI N14 I, ST, IP Table 31 (page 89) TDO N15 O, TS Table 31 (page 89) TMS N16 I, ST, IP Table 31 (page 89) TPFIN0 T1 AO/AI Table 30 (page 88) TPFIN1 T4 AO/AI Table 30 (page 88) TPFIN2 T5 AO/AI Table 30 (page 88) TPFIN3 R8 AO/AI Table 30 (page 88) TPFIN4 U9 AO/AI Table 30 (page 88) TPFIN5 T12 AO/AI Table 30 (page 88) TPFIN6 T13 AO/AI Table 30 (page 88) TPFIN7 T16 AO/AI Table 30 (page 88) TPFIP0 R2 AO/AI Table 30 (page 88) TPFIP1 U3 AO/AI Table 30 (page 88) TPFIP2 R6 AO/AI Table 30 (page 88) TPFIP3 T8 AO/AI Table 30 (page 88) TPFIP4 T9 AO/AI Table 30 (page 88) TPFIP5 U13 AO/AI Table 30 (page 88) TPFIP6 R12 AO/AI Table 30 (page 88) TPFIP7 R16 AO/AI Table 30 (page 88) TPFON0 U1 AO/AI Table 30 (page 88) TPFON1 R4 AO/AI Table 30 (page 88) Signal Ball Type 1 Reference for Full Description TPFON2 U5 AO/AI Table 30 (page 88) TPFON3 T7 AO/AI Table 30 (page 88) TPFON4 R10 AO/AI Table 30 (page 88) TPFON5 U11 AO/AI Table 30 (page 88) TPFON6 U15 AO/AI Table 30 (page 88) TPFON7 T15 AO/AI Table 30 (page 88) TPFOP0 T2 AO/AI Table 30 (page 88) TPFOP1 T3 AO/AI Table 30 (page 88) TPFOP2 T6 AO/AI Table 30 (page 88) TPFOP3 U7 AO/AI Table 30 (page 88) TPFOP4 T10 AO/AI Table 30 (page 88) TPFOP5 T11 AO/AI Table 30 (page 88) TPFOP6 T14 AO/AI Table 30 (page 88) TPFOP7 R14 AO/AI Table 30 (page 88) TRST M17 I, ST, IP Table 31 (page 89) TxData0_0 E2 I, ID Table 24 (page 82) TxData0_1 F4 I, ID Table 24 (page 82) TxData1_0 C3 I, ID Table 24 (page 82) TxData1_1 D4 I, ID Table 24 (page 82) TxData2_0 B5 I, ID Table 24 (page 82) TxData2_1 A4 I, ID Table 24 (page 82) TxData3_0 D8 I, ID Table 24 (page 82) TxData3_1 A6 I, ID Table 24 (page 82) TxData4_0 A11 I, ID Table 24 (page 82) TxData4_1 C10 I, ID Table 24 (page 82) TxData5_0 B13 I, ID Table 24 (page 82) TxData5_1 D11 I, ID Table 24 (page 82) TxData6_0 D13 I, ID Table 24 (page 82) TxData6_1 A16 I, ID Table 24 (page 82) TxData7_0 E14 I, ID Table 24 (page 82) TxData7_1 C16 I, ID Table 24 (page 82) TxEN0 E3 I, ID Table 24 (page 82) TxEN1 B2 I, ID Table 24 (page 82) TxEN2 C6 I, ID Table 24 (page 82) TxEN3 A7 I, ID Table 24 (page 82) TxEN4 B11 I, ID Table 24 (page 82) TxEN5 A14 I, ID Table 24 (page 82) TxEN6 C14 I, ID Table 24 (page 82) Signal Ball Type 1 Reference for Full Description

LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers

56 Datasheet

Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 TxEN7 D16 I, ID Table 24 (page 82) TxSLEW_0 N3 I, ST, ID Table 32 (page 90) TxSLEW_1 M4 I, ST, ID Table 32 (page 90) VCCD F5 – Table 34 (page 95) VCCD G13 – Table 34 (page 95) VCCD J5 – Table 34 (page 95) VCCD J14 – Table 34 (page 95) VCCIO A2 – Table 34 (page 95) VCCIO A8 – Table 34 (page 95) VCCIO C1 – Table 34 (page 95) VCCIO C11 – Table 34 (page 95) VCCIO D14 – Table 34 (page 95) VCCPECL L5 – Table 34 (page 95) VCCPECL L13 – Table 34 (page 95) VCCR N13 – Table 34 (page 95) VCCR P4 – Table 34 (page 95) VCCR P7 – Table 34 (page 95) VCCR P8 – Table 34 (page 95) VCCR P9 – Table 34 (page 95) VCCR P10 – Table 34 (page 95) VCCR P11 – Table 34 (page 95) VCCR P12 – Table 34 (page 95) VCCT N6 – Table 34 (page 95) VCCT N7 – Table 34 (page 95) VCCT N9 – Table 34 (page 95) VCCT N11 – Table 34 (page 95) VCCT N12 – Table 34 (page 95) Signal Ball Type 1 Reference for Full Description

Table 19. Intel® LXT9785/LXT9785E RMII BGA2 3 Ball List in Alphanumeric Order by Ball

LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers

58 Datasheet

Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 D16 TxEN7 I, ID Table 24 (page 82) D17 RxER7 O, TS, SL, ID Table 24 (page 82) E1 MDC0 I, ST, ID Table 28 (page 87) E2 TxData0_0 I, ID Table 24 (page 82) E3 TxEN0 I, ID Table 24 (page 82) E4 CRS_DV0 O, TS, SL Table 24 (page 82) E5 GNDD – Table 34 (page 95) E6 REFCLK0 I Table 24 (page 82) E7 GNDD – Table 34 (page 95) E8 No Ball – – E9 GNDD – Table 34 (page 95) E10 No Ball E11 GNDD – Table 34 (page 95) E12 REFCLK1 I Table 24 (page 82) E13 GNDD – Table 34 (page 95) E14 TxData7_0 I, ID Table 24 (page 82) E15 CRS_DV7 O, TS, SL Table 24 (page 82) E16 RxData7_0 O, TS Table 24 (page 82) E17 GNDD – Table 34 (page 95) F1 MDINT0 OD, TS, SL, IP Table 28 (page 87) F2 LED3_1 OD, TS, SL, IP Table 33 (page 94) F3 MDIO0 I/O, TS, SL, IP Table 28 (page 87) F4 TxData0_1 I, ID Table 24 (page 82) F5 VCCD – Table 34 (page 95) F6 No ball – – F7 No ball – – F8 No ball – – F9 No Ball – – F10 No Ball – – F11 No Ball – – F12 No Ball – – F13 GNDD – Table 34 (page 95) F14 RxData7_1 O, TS, ID Table 24 (page 82) F15 N/C – Table 35 (page 97) F16 LED7_3 OD, TS, SL, IP Table 33 (page 94) Ball Signal Type 1 Reference for Full Description F17 LED7_2 OD, TS, SL, IP Table 33 (page 94) G1 LED2_3 OD, TS, SL, IP Table 33 (page 94) G2 N/C – Table 35 (page 97) G3 LED3_2 OD, TS, SL, IP Table 33 (page 94) G4 LED3_3 OD, TS, SO, IP Table 33 (page 94) G5 N/C – Table 35 (page 97) G6 No Ball – – G7 No Ball – – G8 No Ball – – G9 No Ball – – G10 No Ball – – G11 No Ball – – G12 No Ball – – G13 VCCD – Table 34 (page 95) G14 N/C – Table 35 (page 97) G15 LED7_1 OD, TS, SL, IP Table 33 (page 94) G16 N/C – Table 35 (page 97) G17 LED6_3 OD, TS, SL, IP Table 33 (page 94) H1 LED1_3 OD, TS, SL, IP Table 33 (page 94) H2 LED2_1 OD, TS, SL, IP Table 33 (page 94) H3 LED2_2 OD, TS, SL, IP Table 33 (page 94) H4 N/C – Table 35 (page 97) H5 No Ball – – H6 No Ball – – H7 No Ball – – H8 GNDD – Table 34 (page 95) H9 GNDD – Table 34 (page 95) H10 GNDD – Table 34 (page 95) H11 No Ball – – H12 No Ball – – H13 No Ball – – H14 N/C – Table 35 (page 97) Ball Signal Type 1 Reference for Full Description

LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Datasheet 59 Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 H15 LED6_1 OD, TS, SL, IP Table 33 (page 94) H16 LED6_2 OD, TS, SL, IP Table 33 (page 94) H17 LED5_3 OD, TS, SL, IP Table 33 (page 94) J1 LED0_3 OD, TS, SL, IP Table 33 (page 94) J2 N/C – Table 35 (page 97) J3 LED1_2 OD, TS, SL, IP Table 33 (page 94) J4 LED1_1 OD, TS, SL, IP Table 33 (page 94) J5 VCCD – Table 34 (page 95) J6 No Ball – – J7 No Ball – – J8 GNDD – Table 34 (page 95) J9 GNDD – Table 34 (page 95) J10 GNDD – Table 34 (page 95) J11 No Ball – – J12 No Ball – – J13 N/C – Table 35 (page 97) J14 VCCD – Table 34 (page 95) J15 LED5_1 OD, TS, SL, IP Table 33 (page 94) J16 LED5_2 OD, TS, SL, IP Table 33 (page 94) J17 LED4_3 OD, TS, SL, IP Table 33 (page 94) K1 AMDIX_EN I, ST, IP Table 32 (page 90) K2 LED0_2 OD, TS, SL, IP Table 33 (page 94) K3 LED0_1 OD, TS, SL, IP Table 33 (page 94) K4 N/C – Table 35 (page 97) K5 No Ball – – K6 No Ball – – K7 No Ball – – K8 GNDD – Table 34 (page 95) K9 GNDD – Table 34 (page 95) K10 GNDD – Table 34 (page 95) K11 No Ball – – Ball Signal Type 1 Reference for Full Description K12 No Ball – – K13 No Ball – – K14 SGND – Table 34 (page 95) K15 N/C – Table 35 (page 97) K16 LED4_1 OD, TS, SL, IP Table 33 (page 94) K17 LED4_2 OD, TS, SL, IP Table 33 (page 94) L1 MDDIS I, ST, ID Table 28 (page 87) L2 CFG_3 I, ST, ID Table 32 (page 90) L3 CFG_2 I, ST, ID Table 32 (page 90) L4 ADD_4 I, ST, ID Table 32 (page 90) L5 VCCPECL – Table 34 (page 95) L6 No Ball – – L7 No Ball – – L8 No Ball – – L9 No Ball – – L10 No Ball – – L11 No Ball – – L11 No Ball – – L13 VCCPECL – Table 34 (page 95) L14 PWRDWN I, ST, ID Table 32 (page 90) L15 SECTION I, ST, ID Table 32 (page 90) L16 ModeSel0 I, ST, ID Table 32 (page 90) L17 ModeSel1 I, ST, ID Table 32 (page 90) M1 CFG_1 I, ST, ID Table 32 (page 90) M2 ADD_3 I, ST, ID Table 32 (page 90) M3 ADD_2 I, ST, ID Table 32 (page 90) M4 TxSLEW_1 I, ST, ID Table 32 (page 90) M5 GNDPECL – Table 34 (page 95) M6 No Ball – – M7 No Ball – – M8 No Ball – – M9 No Ball – – M10 No Ball – – M11 No Ball – – M12 No Ball – – M13 GNDPECL – Table 34 (page 95) M14 G_FX/TP I, ST, ID Table 32 (page 90) Ball Signal Type 1 Reference for Full Description

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60 Datasheet

Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 M15 RESET I, ST, IP Table 32 (page 90) M16 TCK I, ST, ID Table 31 (page 89) M17 TRST I, ST, IP Table 31 (page 89) N1 ADD_1 I, ST, ID Table 32 (page 90) N2 ADD_0 I, ST, ID Table 32 (page 90) N3 TxSLEW_0 I, ST, ID Table 32 (page 90) N4 SD1 I Table 29 (page 88) N5 SD3 I Table 29 (page 88) N6 VCCT – Table 34 (page 95) N7 VCCT – Table 34 (page 95) N8 No Ball – – N9 VCCT – Table 34 (page 95) N10 No Ball – – N11 VCCT – Table 34 (page 95) N12 VCCT – Table 34 (page 95) N13 VCCR – Table 34 (page 95) N14 TDI I, ST, IP Table 31 (page 89) N15 TDO O, TS Table 31 (page 89) N16 TMS I, ST, IP Table 31 (page 89) N17 SD7 I Table 29 (page 88) P1 SD_2P5V I, ST, ID Table 29 (page 88) P2 SD0 I Table 29 (page 88) P3 SD2 I Table 29 (page 88) P4 VCCR – Table 34 (page 95) P5 GNDR – Table 34 (page 95) P6 GNDR – Table 34 (page 95) P7 VCCR – Table 34 (page 95) P8 VCCR – Table 34 (page 95) P9 VCCR – Table 34 (page 95) P10 VCCR – Table 34 (page 95) P11 VCCR – Table 34 (page 95) P12 VCCR – Table 34 (page 95) P13 GNDR – Table 34 (page 95) P14 GNDT – Table 34 (page 95) P15 SD4 I Table 29 (page 88) P16 SD5 I Table 29 (page 88) P17 SD6 I Table 29 (page 88) R1 GNDT – Table 34 (page 95) Ball Signal Type 1 Reference for Full Description R2 TPFIP0 AO/AI Table 30 (page 88) R3 GNDT – Table 34 (page 95) R4 TPFON1 AO/AI Table 30 (page 88) R5 GNDT – Table 34 (page 95) R6 TPFIP2 AO/AI Table 30 (page 88) R7 GNDR – Table 34 (page 95) R8 TPFIN3 AO/AI Table 30 (page 88) R9 GNDR – Table 34 (page 95) R10 TPFON4 AO/AI Table 30 (page 88) R11 GNDR – Table 34 (page 95) R12 TPFIP6 AO/AI Table 30 (page 88) R13 GNDR – Table 34 (page 95) R14 TPFOP7 AO/AI Table 30 (page 88) R15 GNDT – Table 34 (page 95) R16 TPFIP7 AO/AI Table 30 (page 88) R17 GNDT – Table 34 (page 95) T1 TPFIN0 AO/AI Table 30 (page 88) T2 TPFOP0 AO/AI Table 30 (page 88) T3 TPFOP1 AO/AI Table 30 (page 88) T4 TPFIN1 AO/AI Table 30 (page 88) T5 TPFIN2 AO/AI Table 30 (page 88) T6 TPFOP2 AO/AI Table 30 (page 88) T7 TPFON3 AO/AI Table 30 (page 88) T8 TPFIP3 AO/AI Table 30 (page 88) T9 TPFIP4 AO/AI Table 30 (page 88) T10 TPFOP4 AO/AI Table 30 (page 88) T11 TPFOP5 AO/AI Table 30 (page 88) T12 TPFIN5 AO/AI Table 30 (page 88) T13 TPFIN6 AO/AI Table 30 (page 88) T14 TPFOP6 AO/AI Table 30 (page 88) T15 TPFON7 AO/AI Table 30 (page 88) T16 TPFIN7 AO/AI Table 30 (page 88) T17 GNDT – Table 34 (page 95) U1 TPFON0 AO/AI Table 30 (page 88) U2 GNDT – Table 34 (page 95) U3 TPFIP1 AO/AI Table 30 (page 88) U4 GNDT – Table 34 (page 95) U5 TPFON2 AO/AI Table 30 (page 88) Ball Signal Type 1 Reference for Full Description

LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Datasheet 61 Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 U6 GNDT – Table 34 (page 95) U7 TPFOP3 AO/AI Table 30 (page 88) U8 GNDR – Table 34 (page 95) U9 TPFIN4 AO/AI Table 30 (page 88) U10 GNDT – Table 34 (page 95) U11 TPFON5 AO/AI Table 30 (page 88) U12 GNDT – Table 34 (page 95) U13 TPFIP5 AO/AI Table 30 (page 88) U14 GNDT – Table 34 (page 95) U15 TPFON6 AO/AI Table 30 (page 88) U16 GNDT – Table 34 (page 95) U17 GNDT – Table 34 (page 95) Ball Signal Type 1 Reference for Full Description

62 Datasheet

3.3.2 SMII BGA23 Ball List

Table 20 “Intel® LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by Signal Name”
Table 21 “Intel® LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by Ball Location” on page 67

Table 20. Intel® LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by Signal

LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Datasheet 63 Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 GNDR R11 – Table 34 (page 95) GNDR R13 – Table 34 (page 95) GNDR U8 – Table 34 (page 95) GNDT P14 – Table 34 (page 95) GNDT R1 – Table 34 (page 95) GNDT R3 – Table 34 (page 95) GNDT R5 – Table 34 (page 95) GNDT R15 – Table 34 (page 95) GNDT R17 – Table 34 (page 95) GNDT T17 – Table 34 (page 95) GNDT U2 – Table 34 (page 95) GNDT U4 – Table 34 (page 95) GNDT U6 – Table 34 (page 95) GNDT U10 – Table 34 (page 95) GNDT U12 – Table 34 (page 95) GNDT U14 – Table 34 (page 95) GNDT U16 – Table 34 (page 95) GNDT U17 – Table 34 (page 95) LED0_1 K3 OD, TS, SL, IP Table 33 (page 94) LED0_2 K2 OD, TS, SL, IP Table 33 (page 94) LED0_3 J1 OD, TS, SL, IP Table 33 (page 94) LED1_1 J4 OD, TS, SL, IP Table 33 (page 94) LED1_2 J3 OD, TS, SL, IP Table 33 (page 94) LED1_3 H1 OD, TS, SL, IP Table 33 (page 94) LED2_1 H2 OD, TS, SL, IP Table 33 (page 94) LED2_2 H3 OD, TS, SL, IP Table 33 (page 94) LED2_3 G1 OD, TS, SL, IP Table 33 (page 94) LED3_1 F2 OD, TS, SL, IP Table 33 (page 94) LED3_2 G3 OD, TS, SL, IP Table 33 (page 94) LED3_3 G4 OD, TS, SO, IP Table 33 (page 94) Signal Ball Type 1 Reference for Full Description LED4_1 K16 OD, TS, SL, IP Table 33 (page 94) LED4_2 K17 OD, TS, SL, IP Table 33 (page 94) LED4_3 J17 OD, TS, SL, IP Table 33 (page 94) LED5_1 J15 OD, TS, SL, IP Table 33 (page 94) LED5_2 J16 OD, TS, SL, IP Table 33 (page 94) LED5_3 H17 OD, TS, SL, IP Table 33 (page 94) LED6_1 H15 OD, TS, SL, IP Table 33 (page 94) LED6_2 H16 OD, TS, SL, IP Table 33 (page 94) LED6_3 G17 OD, TS, SL, IP Table 33 (page 94) LED7_1 G15 OD, TS, SL, IP Table 33 (page 94) LED7_2 F17 OD, TS, SL, IP Table 33 (page 94) LED7_3 F16 OD, TS, SL, IP Table 33 (page 94) LINKHOLD A17 O, TS, SL, ID, I, ST Table 24 (page 82) MDC0 E1 I, ST, ID Table 28 (page 87) MDC1 B10 I, ST, ID Table 28 (page 87) MDDIS L1 I, ST, ID Table 28 (page 87) MDINT0 F1 OD, TS, SL, IP Table 28 (page 87) MDINT1 C9 OD, TS, SL, IP Table 28 (page 87) MDIO0 F3 I/O, TS, SL, IP Table 28 (page 87) MDIO1 A10 I/O, TS, SL, IP Table 28 (page 87) MDIX D2 O, TS, SL, ID, I, ST Table 32 (page 90) ModeSel0 L16 I, ST, ID Table 32 (page 90) ModeSel1 L17 I, ST, ID Table 32 (page 90) N/C A4 I, ID Table 24 (page 82) N/C A7 I, ID Table 24 (page 82) N/C A14 I, ID Table 24 (page 82) N/C A16 I, ID Table 24 (page 82) Signal Ball Type 1 Reference for Full Description

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Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 N/C B1 O, TS, ID Table 24 (page 82) N/C B2 I, ID Table 24 (page 82) N/C B4 O, TS, ID Table 24 (page 82) N/C B9 O, TS, ID Table 24 (page 82) N/C B11 I, ID Table 24 (page 82) N/C B15 O, TS, ID Table 24 (page 82) N/C B17 O, TS, ID Table 24 (page 82) N/C C6 I, ID Table 24 (page 82) N/C C7 O, TS, ID Table 24 (page 82) N/C C8 O, TS, SL, ID Table 24 (page 82) N/C C10 I, ID Table 24 (page 82) N/C C12 O, TS,ID Table 24 (page 82) N/C C14 I, ID Table 24 (page 82) N/C D4 I, ID Table 24 (page 82) N/C D11 I, ID Table 24 (page 82) N/C D16 I, ID Table 24 (page 82) N/C D17 O, TS, SL, ID Table 24 (page 82) N/C E3 I, ID Table 24 (page 82) N/C F4 I, ID Table 24 (page 82) N/C F14 O, TS, ID Table 24 (page 82) N/C F15 – Table 35 (page 97) N/C G2 – Table 35 (page 97) N/C G5 – Table 35 (page 97) N/C G14 – Table 35 (page 97) N/C G16 – Table 35 (page 97) N/C H4 – Table 35 (page 97) N/C H14 – Table 35 (page 97) N/C J2 – Table 35 (page 97) N/C J13 – Table 35 (page 97) N/C K4 – Table 35 (page 97) N/C K15 – Table 35 (page 97) No ball F6 – – No ball F7 – – No ball F8 – – No Ball E8 – – No Ball E10 No Ball F9 – – Signal Ball Type No Ball F10 – – No Ball F11 – – No Ball F12 – – No Ball G6 – – No Ball G7 – – No Ball G8 – – No Ball G9 – – No Ball G10 – – No Ball G11 – – No Ball G12 – – No Ball H5 – – No Ball H6 – – No Ball H7 – – No Ball H11 – – No Ball H12 – – No Ball H13 – – No Ball J6 – – No Ball J7 – – No Ball J11 – – No Ball J12 – – No Ball K5 – – No Ball K6 – – No Ball K7 – – No Ball K11 – – No Ball K12 – – No Ball K13 – – No Ball L6 – – No Ball L7 – – No Ball L8 – – No Ball L9 – – No Ball L10 – – No Ball L11 – – No Ball L11 – – No Ball M6 – – No Ball M7 – – No Ball M8 – – No Ball M9 – – No Ball M10 – – Signal Ball Type

LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Datasheet 65 Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 No Ball M11 – – No Ball M12 – – No Ball N8 – – No Ball N10 – – PAUSE D5 O, TS, SL, ID, I, ST Table 32 (page 90) PREASEL D7 O, TS, SL, ID, I, ST Table 24 (page 82) PWRDWN L14 I, ST, ID Table 32 (page 90) REFCLK0 E6 I Table 24 (page 82) REFCLK1 E12 I Table 24 (page 82) RESET M15 I, ST, IP Table 32 (page 90) RxData0 C2 O, TS Table 24 (page 82) RxData1 A3 O, TS Table 24 (page 82) RxData2 B6 O, TS Table 24 (page 82) RxData3 D9 O, TS Table 24 (page 82) RxData4 A13 O, TS Table 24 (page 82) RxData5 B14 O, TS Table 24 (page 82) RxData6 C15 O, TS Table 24 (page 82) RxData7 E16 O, TS Table 24 (page 82) SD_2P5V P1 I, ST, ID Table 29 (page 88) SD0 P2 I Table 29 (page 88) SD1 N4 I Table 29 (page 88) SD2 P3 I Table 29 (page 88) SD3 N5 I Table 29 (page 88) SD4 P15 I Table 29 (page 88) SD5 P16 I Table 29 (page 88) SD6 P17 I Table 29 (page 88) SD7 N17 I Table 29 (page 88) SECTION L15 I, ST, ID Table 32 (page 90) SGND K14 – Table 34 (page 95) SYNC0 A6 I, ID Table 24 (page 82) SYNC1 C16 I, ID Table 24 (page 82) TCK M16 I, ST, ID Table 31 (page 89) TDI N14 I, ST, IP Table 31 (page 89) TDO N15 O, TS Table 31 (page 89) TMS N16 I, ST, IP Table 31 (page 89) TPFIN0 T1 AO/AI Table 30 (page 88) TPFIN1 T4 AO/AI Table 30 (page 88) Signal Ball Type 1 Reference for Full Description TPFIN2 T5 AO/AI Table 30 (page 88) TPFIN3 R8 AO/AI Table 30 (page 88) TPFIN4 U9 AO/AI Table 30 (page 88) TPFIN5 T12 AO/AI Table 30 (page 88) TPFIN6 T13 AO/AI Table 30 (page 88) TPFIN7 T16 AO/AI Table 30 (page 88) TPFIP0 R2 AO/AI Table 30 (page 88) TPFIP1 U3 AO/AI Table 30 (page 88) TPFIP2 R6 AO/AI Table 30 (page 88) TPFIP3 T8 AO/AI Table 30 (page 88) TPFIP4 T9 AO/AI Table 30 (page 88) TPFIP5 U13 AO/AI Table 30 (page 88) TPFIP6 R12 AO/AI Table 30 (page 88) TPFIP7 R16 AO/AI Table 30 (page 88) TPFON0 U1 AO/AI Table 30 (page 88) TPFON1 R4 AO/AI Table 30 (page 88) TPFON2 U5 AO/AI Table 30 (page 88) TPFON3 T7 AO/AI Table 30 (page 88) TPFON4 R10 AO/AI Table 30 (page 88) TPFON5 U11 AO/AI Table 30 (page 88) TPFON6 U15 AO/AI Table 30 (page 88) TPFON7 T15 AO/AI Table 30 (page 88) TPFOP0 T2 AO/AI Table 30 (page 88) TPFOP1 T3 AO/AI Table 30 (page 88) TPFOP2 T6 AO/AI Table 30 (page 88) TPFOP3 U7 AO/AI Table 30 (page 88) TPFOP4 T10 AO/AI Table 30 (page 88) TPFOP5 T11 AO/AI Table 30 (page 88) TPFOP6 T14 AO/AI Table 30 (page 88) TPFOP7 R14 AO/AI Table 30 (page 88) TRST M17 I, ST, IP Table 31 (page 89) TxData0 E2 I, ID Table 24 (page 82) TxData1 C3 I, ID Table 24 (page 82) TxData2 B5 I, ID Table 24 (page 82) TxData3 D8 I, ID Table 24 (page 82) TxData4 A11 I, ID Table 24 (page 82) TxData5 B13 I, ID Table 24 (page 82) TxData6 D13 I, ID Table 24 (page 82) Signal Ball Type 1 Reference for Full Description

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66 Datasheet

Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 TxData7 E14 I, ID Table 24 (page 82) TxSLEW_0 N3 I, ST, ID Table 32 (page 90) TxSLEW_1 M4 I, ST, ID Table 32 (page 90) VCCD F5 – Table 34 (page 95) VCCD G13 – Table 34 (page 95) VCCD J5 – Table 34 (page 95) VCCD J14 – Table 34 (page 95) VCCIO A2 – Table 34 (page 95) VCCIO A8 – Table 34 (page 95) VCCIO C1 – Table 34 (page 95) VCCIO C11 – Table 34 (page 95) VCCIO D14 – Table 34 (page 95) VCCPECL L5 – Table 34 (page 95) VCCPECL L13 – Table 34 (page 95) VCCR N13 – Table 34 (page 95) VCCR P4 – Table 34 (page 95) VCCR P7 – Table 34 (page 95) VCCR P8 – Table 34 (page 95) VCCR P9 – Table 34 (page 95) VCCR P10 – Table 34 (page 95) VCCR P11 – Table 34 (page 95) VCCR P12 – Table 34 (page 95) VCCT N6 – Table 34 (page 95) VCCT N7 – Table 34 (page 95) VCCT N9 – Table 34 (page 95) VCCT N11 – Table 34 (page 95) VCCT N12 – Table 34 (page 95) Signal Ball Type 1 Reference for Full Description

Table 21. Intel® LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by Ball

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Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 D16 N/C I, ID Table 24 (page 82) D17 N/C O, TS, SL, ID Table 24 (page 82) E1 MDC0 I, ST, ID Table 28 (page 87) E2 TxData0 I, ID Table 24 (page 82) E3 N/C I, ID Table 24 (page 82) E4 CRS_DV0 O, TS, SL Table 24 (page 82) E5 GNDD – Table 34 (page 95) E6 REFCLK0 I Table 24 (page 82) E7 GNDD – Table 34 (page 95) E8 No Ball – – E9 GNDD – Table 34 (page 95) E10 No Ball E11 GNDD – Table 34 (page 95) E12 REFCLK1 I Table 24 (page 82) E13 GNDD – Table 34 (page 95) E14 TxData7 I, ID Table 24 (page 82) E15 CRS_DV7 O, TS, SL Table 24 (page 82) E16 RxData7 O, TS Table 24 (page 82) E17 GNDD – Table 34 (page 95) F1 MDINT0 OD, TS, SL, IP Table 28 (page 87) F2 LED3_1 OD, TS, SL, IP Table 33 (page 94) F3 MDIO0 I/O, TS, SL, IP Table 28 (page 87) F4 N/C I, ID Table 24 (page 82) F5 VCCD – Table 34 (page 95) F6 No ball – – F7 No ball – – F8 No ball – – F9 No Ball – – F10 No Ball – – F11 No Ball – – F12 No Ball – – F13 GNDD – Table 34 (page 95) F14 N/C O, TS, ID Table 24 (page 82) F15 N/C – Table 35 (page 97) F16 LED7_3 OD, TS, SL, IP Table 33 (page 94) Ball Signal Type 1 Reference for Full Description F17 LED7_2 OD, TS, SL, IP Table 33 (page 94) G1 LED2_3 OD, TS, SL, IP Table 33 (page 94) G2 N/C – Table 35 (page 97) G3 LED3_2 OD, TS, SL, IP Table 33 (page 94) G4 LED3_3 OD, TS, SO, IP Table 33 (page 94) G5 N/C – Table 35 (page 97) G6 No Ball – – G7 No Ball – – G8 No Ball – – G9 No Ball – – G10 No Ball – – G11 No Ball – – G12 No Ball – – G13 VCCD – Table 34 (page 95) G14 N/C – Table 35 (page 97) G15 LED7_1 OD, TS, SL, IP Table 33 (page 94) G16 N/C – Table 35 (page 97) G17 LED6_3 OD, TS, SL, IP Table 33 (page 94) H1 LED1_3 OD, TS, SL, IP Table 33 (page 94) H2 LED2_1 OD, TS, SL, IP Table 33 (page 94) H3 LED2_2 OD, TS, SL, IP Table 33 (page 94) H4 N/C – Table 35 (page 97) H5 No Ball – – H6 No Ball – – H7 No Ball – – H8 GNDD – Table 34 (page 95) H9 GNDD – Table 34 (page 95) H10 GNDD – Table 34 (page 95) H11 No Ball – – H12 No Ball – – H13 No Ball – – H14 N/C – Table 35 (page 97) Ball Signal Type 1 Reference for Full Description

LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Datasheet 69 Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 H15 LED6_1 OD, TS, SL, IP Table 33 (page 94) H16 LED6_2 OD, TS, SL, IP Table 33 (page 94) H17 LED5_3 OD, TS, SL, IP Table 33 (page 94) J1 LED0_3 OD, TS, SL, IP Table 33 (page 94) J2 N/C – Table 35 (page 97) J3 LED1_2 OD, TS, SL, IP Table 33 (page 94) J4 LED1_1 OD, TS, SL, IP Table 33 (page 94) J5 VCCD – Table 34 (page 95) J6 No Ball – – J7 No Ball – – J8 GNDD – Table 34 (page 95) J9 GNDD – Table 34 (page 95) J10 GNDD – Table 34 (page 95) J11 No Ball – – J12 No Ball – – J13 N/C – Table 35 (page 97) J14 VCCD – Table 34 (page 95) J15 LED5_1 OD, TS, SL, IP Table 33 (page 94) J16 LED5_2 OD, TS, SL, IP Table 33 (page 94) J17 LED4_3 OD, TS, SL, IP Table 33 (page 94) K1 AMDIX_EN I, ST, IP Table 32 (page 90) K2 LED0_2 OD, TS, SL, IP Table 33 (page 94) K3 LED0_1 OD, TS, SL, IP Table 33 (page 94) K4 N/C – Table 35 (page 97) K5 No Ball – – K6 No Ball – – K7 No Ball – – K8 GNDD – Table 34 (page 95) K9 GNDD – Table 34 (page 95) K10 GNDD – Table 34 (page 95) K11 No Ball – – Ball Signal Type 1 Reference for Full Description K12 No Ball – – K13 No Ball – – K14 SGND – Table 34 (page 95) K15 N/C – Table 35 (page 97) K16 LED4_1 OD, TS, SL, IP Table 33 (page 94) K17 LED4_2 OD, TS, SL, IP Table 33 (page 94) L1 MDDIS I, ST, ID Table 28 (page 87) L2 CFG_3 I, ST, ID Table 32 (page 90) L3 CFG_2 I, ST, ID Table 32 (page 90) L4 ADD_4 I, ST, ID Table 32 (page 90) L5 VCCPECL – Table 34 (page 95) L6 No Ball – – L7 No Ball – – L8 No Ball – – L9 No Ball – – L10 No Ball – – L11 No Ball – – L11 No Ball – – L13 VCCPECL – Table 34 (page 95) L14 PWRDWN I, ST, ID Table 32 (page 90) L15 SECTION I, ST, ID Table 32 (page 90) L16 ModeSel0 I, ST, ID Table 32 (page 90) L17 ModeSel1 I, ST, ID Table 32 (page 90) M1 CFG_1 I, ST, ID Table 32 (page 90) M2 ADD_3 I, ST, ID Table 32 (page 90) M3 ADD_2 I, ST, ID Table 32 (page 90) M4 TxSLEW_1 I, ST, ID Table 32 (page 90) M5 GNDPECL – Table 34 (page 95) M6 No Ball – – M7 No Ball – – M8 No Ball – – M9 No Ball – – M10 No Ball – – M11 No Ball – – M12 No Ball – – M13 GNDPECL – Table 34 (page 95) M14 G_FX/TP I, ST, ID Table 32 (page 90) Ball Signal Type 1 Reference for Full Description

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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Datasheet 71 Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 U6 GNDT – Table 34 (page 95) U7 TPFOP3 AO/AI Table 30 (page 88) U8 GNDR – Table 34 (page 95) U9 TPFIN4 AO/AI Table 30 (page 88) U10 GNDT – Table 34 (page 95) U11 TPFON5 AO/AI Table 30 (page 88) U12 GNDT – Table 34 (page 95) U13 TPFIP5 AO/AI Table 30 (page 88) U14 GNDT – Table 34 (page 95) U15 TPFON6 AO/AI Table 30 (page 88) U16 GNDT – Table 34 (page 95) U17 GNDT – Table 34 (page 95) Ball Signal Type 1 Reference for Full Description

72 Datasheet

3.3.3 SS-SMII BGA23 Ball List

Table 22 “Intel® LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by Signal Name”
Table 23 “Intel® LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by Ball Location” on page 77

Table 22. Intel® LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by

LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Datasheet 73 Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 GNDR P6 AO/AI Table 30 (page 88) GNDR P13 AO/AI Table 30 (page 88) GNDR R7 AO/AI Table 30 (page 88) GNDR R9 AO/AI Table 30 (page 88) GNDR R11 AO/AI Table 30 (page 88) GNDR R13 AO/AI Table 30 (page 88) GNDR U8 – Table 34 (page 95) GNDT P14 AO/AI Table 30 (page 88) GNDT R1 AO/AI Table 30 (page 88) GNDT R3 AO/AI Table 30 (page 88) GNDT R5 AO/AI Table 30 (page 88) GNDT R15 O, TS, SL, ID Table 24 (page 82) GNDT R17 I, ID Table 24 (page 82) GNDT T17 – Table 34 (page 95) GNDT U2 – Table 34 (page 95) GNDT U4 – Table 34 (page 95) GNDT U6 – Table 34 (page 95) GNDT U10 – Table 34 (page 95) GNDT U12 – Table 34 (page 95) GNDT U14 – Table 34 (page 95) GNDT U16 – Table 34 (page 95) GNDT U17 – Table 34 (page 95) LED0_1 K3 – – LED0_2 K2 – – LED0_3 J1 – Table 35 (page 97) LED1_1 J4 – Table 35 (page 97) LED1_2 J3 – Table 35 (page 97) LED1_3 H1 I, ID Table 24 (page 82) LED2_1 H2 O, TS, SL, ID Table 24 (page 82) LED2_2 H3 I, ID Table 24 (page 82) LED2_3 G1 O, TS, SL, ID Table 32 (page 90) LED3_1 F2 OD, TS, SL, IP Table 33 (page 94) LED3_2 G3 I, ST, ID Table 32 (page 90) LED3_3 G4 – Table 24 (page 82) LED4_1 K16 – – LED4_2 K17 – – Signal Ball Type 1 Reference for Full Description LED4_3 J17 – – LED5_1 J15 – – LED5_2 J16 – – LED5_3 H17 – Table 35 (page 97) LED6_1 H15 – Table 35 (page 97) LED6_2 H16 – Table 35 (page 97) LED6_3 G17 – Table 24 (page 82) LED7_1 G15 I, ID Table 24 (page 82) LED7_2 F17 I/O, TS, SL, IP Table 28 (page 87) LED7_3 F16 I/O, TS, SL, IP Table 28 (page 87) LINKHOLD A17 O, TS, SL Table 24 (page 82) MDC0 E1 – Table 34 (page 95) MDC1 B10 – Table 34 (page 95) MDDIS L1 – – MDINT0 F1 OD, TS, SL, IP Table 33 (page 94) MDINT1 C9 – Table 34 (page 95) MDIO0 F3 OD, TS, SL, IP Table 33 (page 94) MDIO1 A10 O, TS, SL Table 24 (page 82) MDIX D2 I, ST Table 34 (page 95) ModeSel0 L16 – – ModeSel1 L17 – – N/C A3 I, ST, ID Table 32 (page 90) N/C A4 I, ST, ID Table 32 (page 90) N/C A7 I, ST, ID Table 32 (page 90) N/C A13 O, TS, SL Table 24 (page 82) N/C A14 O, TS, SL Table 24 (page 82) N/C A16 O, TS, SL Table 24 (page 82) N/C B2 – Table 34 (page 95) N/C B6 – Table 34 (page 95) N/C B11 – Table 34 (page 95) N/C B14 – Table 34 (page 95) N/C C2 – Table 34 (page 95) N/C C6 – Table 34 (page 95) N/C C8 – Table 34 (page 95) N/C C10 – Table 34 (page 95) N/C C14 – Table 34 (page 95) Signal Ball Type 1 Reference for Full Description

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Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 N/C C15 – Table 34 (page 95) N/C D4 – Table 34 (page 95) N/C D9 – Table 34 (page 95) N/C D11 – Table 34 (page 95) N/C D16 – Table 34 (page 95) N/C E16 OD, TS, SL, IP Table 33 (page 94) N/C F4 OD, TS, SL, IP Table 33 (page 94) N/C F15 OD, TS, SL, IP Table 28 (page 87) N/C G2 I, ST, ID Table 32 (page 90) N/C G5 I, ID Table 24 (page 82) N/C G14 – Table 24 (page 82) N/C G16 – Table 24 (page 82) N/C H4 I, ID Table 24 (page 82) N/C H14 – Table 35 (page 97) N/C J2 – Table 35 (page 97) N/C J13 – – N/C K4 – – N/C K15 – – No ball F6 OD, TS, SL, IP Table 33 (page 94) No ball F7 OD, TS, SL, IP Table 33 (page 94) No ball F8 OD, TS, SL, IP Table 33 (page 94) No Ball E8 OD, TS, SL, IP Table 33 (page 94) No Ball E10 OD, TS, SL, IP Table 33 (page 94) No Ball F9 OD, TS, SL, IP Table 33 (page 94) No Ball F10 OD, TS, SL, IP Table 33 (page 94) No Ball F11 I, ST, ID Table 28 (page 87) No Ball F12 I, ST, ID Table 28 (page 87) No Ball G6 I, ID Table 24 (page 82) No Ball G7 O, TS, SL, ID Table 24 (page 82) No Ball G8 – Table 24 (page 82) No Ball G9 I, ID Table 24 (page 82) Signal Ball Type No Ball G10 O, TS, SL, ID Table 24 (page 82) No Ball G11 I, ID Table 24 (page 82) No Ball G12 O, TS, SL, ID Table 24 (page 82) No Ball H5 – Table 24 (page 82) No Ball H6 I, ID Table 24 (page 82) No Ball H7 O, TS, SL, ID Table 24 (page 82) No Ball H11 – Table 24 (page 82) No Ball H12 I, ID Table 24 (page 82) No Ball H13 – Table 35 (page 97) No Ball J6 – Table 35 (page 97) No Ball J7 – – No Ball J11 No Ball J12 – – No Ball K5 – – No Ball K6 – – No Ball K7 – – No Ball K11 – – No Ball K12 – – No Ball K13 – – No Ball L6 – – No Ball L7 – – No Ball L8 – – No Ball L9 – – No Ball L10 – – No Ball L11 – – No Ball L11 – – No Ball M6 I Table 24 (page 82) No Ball M7 I Table 24 (page 82) No Ball M8 I, ST, IP Table 32 (page 90) No Ball M9 I, ID Table 24 (page 82) No Ball M10 O, TS Table 24 (page 82) No Ball M11 O, TS Table 24 (page 82) No Ball M12 O, TS Table 24 (page 82) No Ball N8 I Table 29 (page 88) No Ball N10 I, ST, ID Table 32 (page 90) PAUSE D5 I, ST Table 34 (page 95) Signal Ball Type

LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Datasheet 75 Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 PREASEL D7 I, ST Table 34 (page 95) PWRDWN L14 – – REFCLK0 E6 OD, TS, SL, IP Table 33 (page 94) REFCLK1 E12 OD, TS, SL, IP Table 33 (page 94) RESET M15 O, TS, ID Table 24 (page 82) RxCLK0 E3 – Table 34 (page 95) RxData0 B1 I, ST, ID Table 32 (page 90) RxData1 B4 – Table 34 (page 95) RxData2 C7 – Table 34 (page 95) RxData3 B9 – Table 34 (page 95) RxData4 C12 – Table 34 (page 95) RxData5 B15 – Table 34 (page 95) RxData6 B17 – Table 34 (page 95) RxData7 F14 OD, TS, SL, IP Table 28 (page 87) SD_2P5V P1 AO/AI Table 30 (page 88) SD0 P2 AO/AI Table 30 (page 88) SD1 N4 I Table 29 (page 88) SD2 P3 AO/AI Table 30 (page 88) SD3 N5 I Table 29 (page 88) SD4 P15 AO/AI Table 30 (page 88) SD5 P16 AO/AI Table 30 (page 88) SD6 P17 AO/AI Table 30 (page 88) SD7 N17 AO/AI Table 30 (page 88) SECTION L15 – – SGND K14 – – TCK M16 O, TS, ID Table 24 (page 82) TDI N14 O, TS Table 31 (page 89) TDO N15 I, ST, IP Table 31 (page 89) TMS N16 AO/AI Table 30 (page 88) TPFIN0 T1 I, ID Table 24 (page 82) TPFIN1 T4 I, ID Table 24 (page 82) TPFIN2 T5 I, ID Table 24 (page 82) TPFIN3 R8 AO/AI Table 30 (page 88) TPFIN4 U9 – Table 34 (page 95) TPFIN5 T12 – Table 34 (page 95) TPFIN6 T13 – Table 34 (page 95) Signal Ball Type 1 Reference for Full Description TPFIN7 T16 – Table 34 (page 95) TPFIP0 R2 AO/AI Table 30 (page 88) TPFIP1 U3 – Table 34 (page 95) TPFIP2 R6 AO/AI Table 30 (page 88) TPFIP3 T8 I, ST, ID Table 32 (page 90) TPFIP4 T9 I, ID Table 24 (page 82) TPFIP5 U13 – Table 34 (page 95) TPFIP6 R12 AO/AI Table 30 (page 88) TPFIP7 R16 I, ID Table 24 (page 82) TPFON0 U1 – Table 34 (page 95) TPFON1 R4 AO/AI Table 30 (page 88) TPFON2 U5 – Table 34 (page 95) TPFON3 T7 I, ST, ID Table 32 (page 90) TPFON4 R10 AO/AI Table 30 (page 88) TPFON5 U11 – Table 34 (page 95) TPFON6 U15 – Table 34 (page 95) TPFON7 T15 – Table 34 (page 95) TPFOP0 T2 I, ID Table 24 (page 82) TPFOP1 T3 I, ID Table 24 (page 82) TPFOP2 T6 I, ID Table 24 (page 82) TPFOP3 U7 – Table 34 (page 95) TPFOP4 T10 I, ID Table 24 (page 82) TPFOP5 T11 – Table 34 (page 95) TPFOP6 T14 – Table 34 (page 95) TPFOP7 R14 I, ST, IP Table 31 (page 89) TRST M17 O, TS, ID Table 24 (page 82) TxCLK1 D17 – Table 34 (page 95) TxData0 E2 – Table 34 (page 95) TxData1 C3 – Table 34 (page 95) TxData2 B5 – Table 34 (page 95) TxData3 D8 – Table 34 (page 95) TxData4 A11 O, TS, SL Table 24 (page 82) TxData5 B13 – Table 34 (page 95) TxData6 D13 – Table 34 (page 95) TxData7 E14 OD, TS, SL, IP Table 33 (page 94) TxSLEW_0 N3 I Table 29 (page 88) TxSLEW_1 M4 O, TS, SL, ID Table 32 (page 90) Signal Ball Type 1 Reference for Full Description

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Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 TxSYNC0 A6 I, ST, IP Table 32 (page 90) TxSYNC1 C16 – Table 34 (page 95) VCCD F5 OD, TS, SL, IP Table 33 (page 94) VCCD G13 I, ID Table 24 (page 82) VCCD J5 – Table 35 (page 97) VCCD J14 – – VCCIO A2 I, ST, ID Table 32 (page 90) VCCIO A8 I, ST, ID Table 32 (page 90) VCCIO C1 – Table 34 (page 95) VCCIO C11 – Table 34 (page 95) VCCIO D14 – Table 34 (page 95) VCCPECL L5 – – VCCPECL L13 – – VCCR N13 I, ST, IP Table 31 (page 89) VCCR P4 AO/AI Table 30 (page 88) VCCR P7 AO/AI Table 30 (page 88) VCCR P8 AO/AI Table 30 (page 88) VCCR P9 AO/AI Table 30 (page 88) VCCR P10 AO/AI Table 30 (page 88) VCCR P11 AO/AI Table 30 (page 88) VCCR P12 AO/AI Table 30 (page 88) VCCT N6 I Table 29 (page 88) VCCT N7 I Table 29 (page 88) VCCT N9 I Table 29 (page 88) VCCT N11 – Table 34 (page 95) VCCT N12 I, ST, ID Table 31 (page 89) Signal Ball Type

Table 23. Intel® LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by Ball

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Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 D16 N/C I, ID Table 24 (page 82) D17 TxCLK1 O, TS, SL, ID Table 24 (page 82) E1 MDC0 I, ST, ID Table 28 (page 87) E2 TxData0 I, ID Table 24 (page 82) E3 RxCLK0 I, ID Table 24 (page 82) E4 CRS_DV0 O, TS, SL Table 24 (page 82) E5 GNDD – Table 34 (page 95) E6 REFCLK0 I Table 24 (page 82) E7 GNDD – Table 34 (page 95) E8 No Ball – – E9 GNDD – Table 34 (page 95) E10 No Ball E11 GNDD – Table 34 (page 95) E12 REFCLK1 I Table 24 (page 82) E13 GNDD – Table 34 (page 95) E14 TxData7 I, ID Table 24 (page 82) E15 CRS_DV7 O, TS, SL Table 24 (page 82) E16 N/C O, TS Table 24 (page 82) E17 GNDD – Table 34 (page 95) F1 MDINT0 OD, TS, SL, IP Table 28 (page 87) F2 LED3_1 OD, TS, SL, IP Table 33 (page 94) F3 MDIO0 I/O, TS, SL, IP Table 28 (page 87) F4 N/C I, ID Table 24 (page 82) F5 VCCD – Table 34 (page 95) F6 No ball – – F7 No ball – – F8 No ball – – F9 No Ball – – F10 No Ball – – F11 No Ball – – F12 No Ball – – F13 GNDD – Table 34 (page 95) F14 RxData7 O, TS, ID Table 24 (page 82) F15 N/C – Table 35 (page 97) F16 LED7_3 OD, TS, SL, IP Table 33 (page 94) Ball Symbol Type 1 Reference for Full Description F17 LED7_2 OD, TS, SL, IP Table 33 (page 94) G1 LED2_3 OD, TS, SL, IP Table 33 (page 94) G2 N/C – Table 35 (page 97) G3 LED3_2 OD, TS, SL, IP Table 33 (page 94) G4 LED3_3 OD, TS, SO, IP Table 33 (page 94) G5 N/C – Table 35 (page 97) G6 No Ball – – G7 No Ball – – G8 No Ball – – G9 No Ball – – G10 No Ball – – G11 No Ball – – G12 No Ball – – G13 VCCD – Table 34 (page 95) G14 N/C – Table 35 (page 97) G15 LED7_1 OD, TS, SL, IP Table 33 (page 94) G16 N/C – Table 35 (page 97) G17 LED6_3 OD, TS, SL, IP Table 33 (page 94) H1 LED1_3 OD, TS, SL, IP Table 33 (page 94) H2 LED2_1 OD, TS, SL, IP Table 33 (page 94) H3 LED2_2 OD, TS, SL, IP Table 33 (page 94) H4 N/C – Table 35 (page 97) H5 No Ball – – H6 No Ball – – H7 No Ball – – H8 GNDD – Table 34 (page 95) H9 GNDD – Table 34 (page 95) H10 GNDD – Table 34 (page 95) H11 No Ball – – H12 No Ball – – H13 No Ball – – H14 N/C – Table 35 (page 97) Ball Symbol Type 1 Reference for Full Description

LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Datasheet 79 Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 H15 LED6_1 OD, TS, SL, IP Table 33 (page 94) H16 LED6_2 OD, TS, SL, IP Table 33 (page 94) H17 LED5_3 OD, TS, SL, IP Table 33 (page 94) J1 LED0_3 OD, TS, SL, IP Table 33 (page 94) J2 N/C – Table 35 (page 97) J3 LED1_2 OD, TS, SL, IP Table 33 (page 94) J4 LED1_1 OD, TS, SL, IP Table 33 (page 94) J5 VCCD – Table 34 (page 95) J6 No Ball – – J7 No Ball – – J8 GNDD – Table 34 (page 95) J9 GNDD – Table 34 (page 95) J10 GNDD – Table 34 (page 95) J11 No Ball – – J12 No Ball – – J13 N/C – Table 35 (page 97) J14 VCCD – Table 34 (page 95) J15 LED5_1 OD, TS, SL, IP Table 33 (page 94) J16 LED5_2 OD, TS, SL, IP Table 33 (page 94) J17 LED4_3 OD, TS, SL, IP Table 33 (page 94) K1 AMDIX_EN I, ST, IP Table 32 (page 90) K2 LED0_2 OD, TS, SL, IP Table 33 (page 94) K3 LED0_1 OD, TS, SL, IP Table 33 (page 94) K4 N/C – Table 35 (page 97) K5 No Ball – – K6 No Ball – – K7 No Ball – – K8 GNDD – Table 34 (page 95) K9 GNDD – Table 34 (page 95) K10 GNDD – Table 34 (page 95) K11 No Ball – – Ball Symbol Type 1 Reference for Full Description K12 No Ball – – K13 No Ball – – K14 SGND – Table 34 (page 95) K15 N/C – Table 35 (page 97) K16 LED4_1 OD, TS, SL, IP Table 33 (page 94) K17 LED4_2 OD, TS, SL, IP Table 33 (page 94) L1 MDDIS I, ST, ID Table 28 (page 87) L2 CFG_3 I, ST, ID Table 32 (page 90) L3 CFG_2 I, ST, ID Table 32 (page 90) L4 ADD_4 I, ST, ID Table 32 (page 90) L5 VCCPECL – Table 34 (page 95) L6 No Ball – – L7 No Ball – – L8 No Ball – – L9 No Ball – – L10 No Ball – – L11 No Ball – – L11 No Ball – – L13 VCCPECL – Table 34 (page 95) L14 PWRDWN I, ST, ID Table 32 (page 90) L15 SECTION I, ST, ID Table 32 (page 90) L16 ModeSel0 I, ST, ID Table 32 (page 90) L17 ModeSel1 I, ST, ID Table 32 (page 90) M1 CFG_1 I, ST, ID Table 32 (page 90) M2 ADD_3 I, ST, ID Table 32 (page 90) M3 ADD_2 I, ST, ID Table 32 (page 90) M4 TxSLEW_1 I, ST, ID Table 32 (page 90) M5 GNDPECL – Table 34 (page 95) M6 No Ball – – M7 No Ball – – M8 No Ball – – M9 No Ball – – M10 No Ball – – M11 No Ball – – M12 No Ball – – M13 GNDPECL – Table 34 (page 95) M14 G_FX/TP I, ST, ID Table 32 (page 90) Ball Symbol Type 1 Reference for Full Description

LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers

80 Datasheet

Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 M15 RESET I, ST, IP Table 32 (page 90) M16 TCK I, ST, ID Table 31 (page 89) M17 TRST I, ST, IP Table 31 (page 89) N1 ADD_1 I, ST, ID Table 32 (page 90) N2 ADD_0 I, ST, ID Table 32 (page 90) N3 TxSLEW_0 I, ST, ID Table 32 (page 90) N4 SD1 I Table 29 (page 88) N5 SD3 I Table 29 (page 88) N6 VCCT – Table 34 (page 95) N7 VCCT – Table 34 (page 95) N8 No Ball – – N9 VCCT – Table 34 (page 95) N10 No Ball – – N11 VCCT – Table 34 (page 95) N12 VCCT – Table 34 (page 95) N13 VCCR – Table 34 (page 95) N14 TDI I, ST, IP Table 31 (page 89) N15 TDO O, TS Table 31 (page 89) N16 TMS I, ST, IP Table 31 (page 89) N17 SD7 I Table 29 (page 88) P1 SD_2P5V I, ST, ID Table 29 (page 88) P2 SD0 I Table 29 (page 88) P3 SD2 I Table 29 (page 88) P4 VCCR – Table 34 (page 95) P5 GNDR – Table 34 (page 95) P6 GNDR – Table 34 (page 95) P7 VCCR – Table 34 (page 95) P8 VCCR – Table 34 (page 95) P9 VCCR – Table 34 (page 95) P10 VCCR – Table 34 (page 95) P11 VCCR – Table 34 (page 95) P12 VCCR – Table 34 (page 95) P13 GNDR – Table 34 (page 95) P14 GNDT – Table 34 (page 95) P15 SD4 I Table 29 (page 88) P16 SD5 I Table 29 (page 88) P17 SD6 I Table 29 (page 88) R1 GNDT – Table 34 (page 95) Ball Symbol Type 1 Reference for Full Description R2 TPFIP0 AO/AI Table 30 (page 88) R3 GNDT – Table 34 (page 95) R4 TPFON1 AO/AI Table 30 (page 88) R5 GNDT – Table 34 (page 95) R6 TPFIP2 AO/AI Table 30 (page 88) R7 GNDR – Table 34 (page 95) R8 TPFIN3 AO/AI Table 30 (page 88) R9 GNDR – Table 34 (page 95) R10 TPFON4 AO/AI Table 30 (page 88) R11 GNDR – Table 34 (page 95) R12 TPFIP6 AO/AI Table 30 (page 88) R13 GNDR – Table 34 (page 95) R14 TPFOP7 AO/AI Table 30 (page 88) R15 GNDT – Table 34 (page 95) R16 TPFIP7 AO/AI Table 30 (page 88) R17 GNDT – Table 34 (page 95) T1 TPFIN0 AO/AI Table 30 (page 88) T2 TPFOP0 AO/AI Table 30 (page 88) T3 TPFOP1 AO/AI Table 30 (page 88) T4 TPFIN1 AO/AI Table 30 (page 88) T5 TPFIN2 AO/AI Table 30 (page 88) T6 TPFOP2 AO/AI Table 30 (page 88) T7 TPFON3 AO/AI Table 30 (page 88) T8 TPFIP3 AO/AI Table 30 (page 88) T9 TPFIP4 AO/AI Table 30 (page 88) T10 TPFOP4 AO/AI Table 30 (page 88) T11 TPFOP5 AO/AI Table 30 (page 88) T12 TPFIN5 AO/AI Table 30 (page 88) T13 TPFIN6 AO/AI Table 30 (page 88) T14 TPFOP6 AO/AI Table 30 (page 88) T15 TPFON7 AO/AI Table 30 (page 88) T16 TPFIN7 AO/AI Table 30 (page 88) T17 GNDT – Table 34 (page 95) U1 TPFON0 AO/AI Table 30 (page 88) U2 GNDT – Table 34 (page 95) U3 TPFIP1 AO/AI Table 30 (page 88) U4 GNDT – Table 34 (page 95) U5 TPFON2 AO/AI Table 30 (page 88) Ball Symbol Type 1 Reference for Full Description

LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Datasheet 81 Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 U6 GNDT – Table 34 (page 95) U7 TPFOP3 AO/AI Table 30 (page 88) U8 GNDR – Table 34 (page 95) U9 TPFIN4 AO/AI Table 30 (page 88) U10 GNDT – Table 34 (page 95) U11 TPFON5 AO/AI Table 30 (page 88) U12 GNDT – Table 34 (page 95) U13 TPFIP5 AO/AI Table 30 (page 88) U14 GNDT – Table 34 (page 95) U15 TPFON6 AO/AI Table 30 (page 88) U16 GNDT – Table 34 (page 95) U17 GNDT – Table 34 (page 95) Ball Symbol Type 1 Reference for Full Description

82 Datasheet

3.4 BGA23 Signal Descriptions

3.4.1 Signal Name Conventions

Port Number Only. Individual signals that apply to a particular port are designated by the Signal Mnemonic, immediately followed by the Port Designation. For example, Transmit Enable signals would be identified as TxEN0, TxEN1, and TxEN2.
Serial Number Only. A set of signals which are not tied to any specific port are designated by the Signal Mnemonic, followed by an underscore and a serial designation. For example, a set of three Global Configuration signals would be identified as CFG_1, CFG_2, and CFG_3.
Port and Serial Number. In cases where each port is assigned a set of multiple signals, each signal is designated in the following order: Signal Mnemonic, Port Designation, an underscore, and the serial designation. For example, a set of three Port Configuration signals would be identified as RxData0_0 and RxData0_1, RxData1_0 and RxData1_1, and RxData2_0 and RxData2_1.

3.4.2 Signal Descriptions – RMII, SMII, and SS-SMII Configurations

Table 24. Intel ® LXT9785/LXT9785E RMII Signal Descriptions – BGA23 (Sheet 1 of 3) from port 0 are clocked in synchronously to REFCLK. from port 2 are clocked in synchronously to REFCLK.

Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID

resistors are also disabled when the output is enabled.

RxData[0:7]_0, RxData[0:7]_1, CRS_DV[0:7] and RxER[0:7] outputs are three-stated in Isolation and H/W

Power-Down modes and during H/W reset.

from port 3 are clocked in synchronously to REFCLK. from port 4 are clocked in synchronously to REFCLK. from port 5 are clocked in synchronously to REFCLK. from port 6 are clocked in synchronously to REFCLK. from port 7 are clocked in synchronously to REFCLK. Transmit Enable - Ports 0-7. Active High input enables respective port transmitter. This signal must be synchronous to the REFCLK. Table 24. Intel ® LXT9785/LXT9785E RMII Signal Descriptions – BGA23 (Sheet 2 of 3)

Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID

resistors are also disabled when the output is enabled.

RxData[0:7]_0, RxData[0:7]_1, CRS_DV[0:7] and RxER[0:7] outputs are three-stated in Isolation and H/W

Power-Down modes and during H/W reset.

84 Datasheet

Carrier Sense/Receive Data Valid - Ports 0-7. asserted asynchronously with respect to REFCLK. group is invalid, or that PLL is not locked. Table 24. Intel ® LXT9785/LXT9785E RMII Signal Descriptions – BGA23 (Sheet 3 of 3)

Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID

resistors are also disabled when the output is enabled.

RxData[0:7]_0, RxData[0:7]_1, CRS_DV[0:7] and RxER[0:7] outputs are three-stated in Isolation and H/W

Power-Down modes and during H/W reset.

Table 25. Intel ® LXT9785/LXT9785E SMII / SS-SMII Common Signal Descriptions – BGA23 connected regardless of sectionalization mode.

Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
The IP/ID resistors are disabled during H/W Power-Down mode.

Table 26. Intel ® LXT9785/LXT9785E SMII Specific Signal Descriptions – BGA23 to be used when 2x4 port sectionalization is chosen.

Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
The IP/ID resistors are disabled during H/W Power-Down mode.
RxData[0:7] outputs are three-stated in Isolation and hardware power-down modes and during hardware

86 Datasheet

Table 27. Intel ® LXT9785/LXT9785E SS-SMII Specific Signal Descriptions – BGA23 SS-SMII Transmit Synchronization. used when 1x8 port sectionalization is selected. SS-SMII Receive Synchronization. only enabled when SS-SMII mode is enabled.

Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID

resistors are also disabled when the output is enabled.

RxData[0:7], RxSYNC[0:1], and RxCLK[0:1] outputs are three-stated in Isolation and H/W Power-Down

Table 28. Intel ® LXT9785/LXT9785E MDIO Control Interface Signals – BGA23 Management Data Input/Output. accesses ports 0-3 and MDIO1 accesses ports 4-7. SS-SMII Quad Sectionalization Diagram” on page 140. Quad Sectionalization Diagram” on page 140. accesses and MDC1 clocks ports 4-7 register accesses. SS-SMII Quad Sectionalization Diagram” on page 140. their respective bits at power up and reset.

Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID

resistors are also disabled when the output is enabled. [0:1] outputs are three-stated in H/W Power-Down mode and during H/W reset.

Supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation,

where X is the register number (0-32) and Y is the bit number (0-15).

88 Datasheet

Table 29. Intel ® LXT9785/LXT9785E Signal Detect – BGA23 Signal Detect 2.5 Volt Interface. SD input threshold voltage select. are only active for ports operating in fiber mode).

Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
The IP/ID resistors are disabled during H/W Power-Down mode.
Tie SD[0:7] inputs to GNDPECL if unused.

Table 30. Intel ® LXT9785/LXT9785E Network Interface Signal Descriptions – BGA23 10BASE-T signals from the line.

Type Column Coding: AI = Analog Input, AO = Analog Output.
Switched to Inputs (see TPFIP/N description) when not in fiber mode and MDIX is not active [that is,

twisted-pair, non-crossover MDI mode].

Switched to Outputs (see TPFOP/N description) when not in fiber mode and MDIX is not active [that is,

twisted-pair, non-crossover MDI mode].

Table 31. Intel ® LXT9785/LXT9785E JTAG Test Signal Descriptions – BGA23 N14 167 TDI I, ST, IP Test Data Input. Test data sampled with respect to the rising edge of TCK. N15 168 TDO O, TS Test Data Output. Test data driven with respect to the falling edge of TCK. N16 169 TMS I, ST, IP Test Mode Select. M16 170 TCK I, ST, ID Test Clock. M17 171 TRST I, ST, IP Test Reset.

Type Column Coding: I = Input, O = Output, OD = Open Drain, TS = Three-State-able output, SMT =
The IP/ID resistors are disabled during H/W Power-Down mode. If a pin is an output or an I/O, the IP/ID

resistors are also disabled when the output is enabled.

TDO output is three-stated in H/W Power-Down mode and during H/W reset.

90 Datasheet

Table 32. Intel ® LXT9785/LXT9785E Miscellaneous Signal Descriptions – BGA23 (Sheet 1 of 4) Tx Output Slew Controls 0 and 1 Defaults. and overwritten after startup / reset. capabilities on all ports during auto-negotiation.

Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS =
The IP/ID resistors are disabled during hardware power-down mode.

mixed and must be all RMII, SMII, or SS-SMII. This pin selects sectionalization into separate ports. Auto MDI/MDIX Enable Default. (regardless of segmentation) is selected for all ports. Table 32. Intel ® LXT9785/LXT9785E Miscellaneous Signal Descriptions – BGA23 (Sheet 2 of 4)

Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS =
The IP/ID resistors are disabled during hardware power-down mode.

92 Datasheet

When AMDIX_EN is active this pin is ignored. MDI or the MDIX function regardless of segmentation. a pull-up) in non-RMII modes. Global Port Configuration Defaults 1-3. Global FX/TP Enable Default. Configuration Register (Address 16, Hex 10)” on page 207. Table 32. Intel ® LXT9785/LXT9785E Miscellaneous Signal Descriptions – BGA23 (Sheet 3 of 4)

Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS =
The IP/ID resistors are disabled during hardware power-down mode.

and overwritten after startup/reset. state is set via the internal pull-down resistors. FIFO Depth Configurations” on page 97. internal pull-down resistors. High, the LXT9785/9785E powers down all ports. Table 32. Intel ® LXT9785/LXT9785E Miscellaneous Signal Descriptions – BGA23 (Sheet 4 of 4)

Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS =
The IP/ID resistors are disabled during hardware power-down mode.

94 Datasheet

Table 33. Intel ® LXT9785/LXT9785E LED Signal Descriptions – BGA23 (Sheet 1 of 2) Hex 14)” on page 213 for details). Hex 14)” on page 213 for details). Hex 14)” on page 213 for details). Hex 14)” on page 213 for details). Hex 14)” on page 213 for details).

Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
The IP/ID resistors are disabled during H/W Power-Down mode. If a pin is an output or an I/O, the IP/ID

resistors are also disabled when the output is enabled.

The LED outputs are three-stated in H/W Power-Down mode and during H/W reset.

Hex 14)” on page 213 for details). Hex 14)” on page 213 for details). Hex 14)” on page 213 for details). Table 34. Intel ® LXT9785/LXT9785E Power Supply Signal Descriptions – BGA23 (Sheet 1 of 2) 196 VCCD - Digital Power Supply - Core. +2.5 V supply for core digital circuits. Digital Power Supply - I/O Ring. Digital Power Supply - PECL Signal Detect Inputs. VCCR - Analog Power Supply - Receive. +2.5 V supply for all analog receive circuits.

Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =

Table 33. Intel ® LXT9785/LXT9785E LED Signal Descriptions – BGA23 (Sheet 2 of 2)

Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
The IP/ID resistors are disabled during H/W Power-Down mode. If a pin is an output or an I/O, the IP/ID

resistors are also disabled when the output is enabled.

The LED outputs are three-stated in H/W Power-Down mode and during H/W reset.

96 Datasheet

138, 152 VCCT - Analog Power Supply - Transmit. +2.5 V supply for all analog transmit circuits. GNDIO - Digital GND - I/O Ring. Ground return for digital I/O circuits (VCCIO). M5, M13 99, 163 GNDPECL - Digital GND - PECL Signal Detect Inputs. Ground return for PECL Signal Detect input circuits. pins can be tied together using a single ground plane. pins can be tied together using a single ground plane. together using a single ground plane. Table 34. Intel ® LXT9785/LXT9785E Power Supply Signal Descriptions – BGA23 (Sheet 2 of 2)

Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =

Table 35. Intel ® LXT9785/LXT9785E Unused/Reserved Pins – BGA23

Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =

Table 36. Intel ® LXT9785/LXT9785E Receive FIFO Depth Configurations

98 Datasheet

3.5 BGA15 Ball Assignments

Figure 6 “Intel® LXT9785MBC 196-Ball BGA15 Assignments (Top View)”
Table 37, “Intel® LXT9785MBC BGA15 Ball List in Alphanumeric Order by Signal Name” on page 99
Table 38, “Intel® LXT9785MBC BGA15 Ball List in Alphanumeric Order by Ball Location (SMII/SS-SMII)” on page 103

Figure 6. Intel ® LXT9785MBC 196-Ball BGA15 Assignments (Top View)

Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Datasheet 99 Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003

3.5.1 BGA15 Ball List

The following tables provide the RMII BGA23 ball locations and signal names arranged in alphanumeric order as follows: Table 37 “Intel® LXT9785MBC BGA15 Ball List in Alphanumeric Order by Signal Name” Table 38 “Intel® LXT9785MBC BGA15 Ball List in Alphanumeric Order by Ball Location (SMII/ SS-SMII)” Table 37. Intel® LXT9785MBC BGA15 Ball List in Alphanumeric Order by Signal Name ADD_3 P10 I, ST, ID Table 39 on page 109 ADD_4 N10 I, ST, ID Table 39 on page 109 AMDIX_EN K8 I, ST, IP Table 39 on page 109 AVCC D12 – Table 39 on page 109 AVCC E12 – Table 39 on page 109 AVCC F12 – Table 39 on page 109 AVCC G12 – Table 39 on page 109 AVCC H12 – Table 39 on page 109 AVCC J12 – Table 39 on page 109 AVCC K12 – Table 39 on page 109 AVCC L12 – Table 39 on page 109 AVSS E11 – Table 39 on page 109 AVSS F9 – Table 39 on page 109 AVSS F10 – Table 39 on page 109 AVSS F11 – Table 39 on page 109 AVSS G9 – Table 39 on page 109 AVSS G10 – Table 39 on page 109 AVSS G11 – Table 39 on page 109 AVSS H9 – Table 39 on page 109 AVSS H10 – Table 39 on page 109 AVSS H11 – Table 39 on page 109 AVSS J9 – Table 39 on page 109 AVSS J10 – Table 39 on page 109 AVSS J11 – Table 39 on page 109 AVSS K11 – Table 39 on page 109 AVSS L11 – Table 39 on page 109 CFG_1 M10 I, ST, ID Table 39 on page 109 CFG_2 L9 I, ST, ID Table 39 on page 109 CFG_3 M9 I, ST, ID Table 39 on page 109 FIFOSEL0 F1 I, ID Table 39 on page 109 FIFOSEL1 C1 I, ID Table 39 on page 109 GNDD A1 – Table 39 on page 109 GNDD A2 – Table 39 on page 109 GNDD A3 – Table 39 on page 109 GNDD B1 – Table 39 on page 109 GNDD B2 – Table 39 on page 109 GNDD B5 – Table 39 on page 109 GNDD B10 – Table 39 on page 109 GNDD D9 – Table 39 on page 109 GNDD D11 – Table 39 on page 109 GNDD E5 – Table 39 on page 109 GNDD E6 – Table 39 on page 109 GNDD E9 – Table 39 on page 109 GNDD E10 – Table 39 on page 109 GNDD F5 – Table 39 on page 109 GNDD F6 – Table 39 on page 109 GNDD F7 – Table 39 on page 109 GNDD F8 – Table 39 on page 109 GNDD G4 – Table 39 on page 109 GNDD G6 – Table 39 on page 109 GNDD G7 – Table 39 on page 109 GNDD G8 – Table 39 on page 109 GNDD H6 – Table 39 on page 109 GNDD H7 – Table 39 on page 109 GNDD H8 – Table 39 on page 109 GNDD J5 – Table 39 on page 109 Signal Name Ball Type Reference for Full

100 Datasheet

Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers GNDD J6 – Table 39 on page 109 GNDD J7 – Table 39 on page 109 GNDD J8 – Table 39 on page 109 GNDD K5 – Table 39 on page 109 GNDD K6 – Table 39 on page 109 GNDD K9 – Table 39 on page 109 GNDD K10 – Table 39 on page 109 GNDD L2 – Table 39 on page 109 GNDD N1 – Table 39 on page 109 GNDD N11 – Table 39 on page 109 GNDD P1 – Table 39 on page 109 GNDD P11 – Table 39 on page 109 LED0_1 N9 OD, TS, SL, IP Table 39 on page 109 LED0_2 P9 OD, TS, SL, IP Table 39 on page 109 LED1_1 N8 OD, TS, SL, IP Table 39 on page 109 LED1_2 P8 OD, TS, SL, IP Table 39 on page 109 LED2_1 P7 OD, TS, SL, IP Table 39 on page 109 LED2_2 N7 OD, TS, SL, IP Table 39 on page 109 LED3_1 P6 OD, TS, SL, IP Table 39 on page 109 LED3_2 N6 OD, TS, SL, IP Table 39 on page 109 LED4_1 B9 OD, TS, SL, IP Table 39 on page 109 LED4_2 A9 OD, TS, SL, IP Table 39 on page 109 LED5_1 B8 OD, TS, SL, IP Table 39 on page 109 LED5_2 A8 OD, TS, SL, IP Table 39 on page 109 Signal Name Ball Type Reference for Full LED6_1 A7 OD, TS, SL, IP Table 39 on page 109 LED6_2 B7 OD, TS, SL, IP Table 39 on page 109 LED7_1 B6 OD, TS, SL, IP Table 39 on page 109 LED7_2 A6 OD, TS, SL, IP Table 39 on page 109 LINKHOLD B3 ID Table 39 on page 109 MDC P4 I, ST, ID Table 39 on page 109 MDINT P5 OD, TS, SL, IP Table 39 on page 109 MDIO N5 IO, TS, SL, IP Table 39 on page 109 ModeSel_0 C9 I, ST, ID Table 39 on page 109 ModeSel_1 E8 I, ST, ID Table 39 on page 109 N/C C4 – Table 39 on page 109 N/C C7 – Table 39 on page 109 N/C D1 – Table 39 on page 109 N/C D2 – Table 39 on page 109 N/C D5 – Table 39 on page 109 N/C D6 – Table 39 on page 109 N/C D8 – Table 39 on page 109 N/C D10 – Table 39 on page 109 N/C E4 – Table 39 on page 109 N/C E7 – Table 39 on page 109 N/C G2 – Table 39 on page 109 N/C G5 – Table 39 on page 109 N/C H1 – Table 39 on page 109 N/C H5 – Table 39 on page 109 N/C J4 – Table 39 on page 109 N/C K4 – Table 39 on page 109 N/C K7 – Table 39 on page 109 N/C L1 – Table 39 on page 109 N/C L6 – Table 39 on page 109 N/C L8 – Table 39 on page 109 Signal Name Ball Type Reference for Full

Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Datasheet 101 Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 N/C L10 – Table 39 on page 109 N/C M4 – Table 39 on page 109 N/C M5 – Table 39 on page 109 N/C M6 – Table 39 on page 109 N/C M7 – Table 39 on page 109 N/C M8 – Table 39 on page 109 N/C P2 – Table 39 on page 109 N/C P3 – Table 39 on page 109 REFCLK0 L4 I Table 39 on page 109 REFCLK1 C3 I Table 39 on page 109 RESET C10 I, ST, IP Table 39 on page 109 RXCLK G1 O, TS, ID Table 39 on page 109 RxData0_S N3 O, TS Table 39 on page 109 RxData0_SS M3 O, TS, ID Table 39 on page 109 RxData1_S M2 O, TS Table 39 on page 109 RxData1_SS M1 O, TS, ID Table 39 on page 109 RxData2_S K2 O, TS Table 39 on page 109 RxData2_SS J2 O, TS, ID Table 39 on page 109 RxData3_S H3 O, TS Table 39 on page 109 RxData3_SS H2 O, TS, ID Table 39 on page 109 RxData4_S F2 O, TS Table 39 on page 109 RxData4_SS F3 O, TS, ID Table 39 on page 109 RxData5_S E3 O, TS Table 39 on page 109 RxData5_SS C2 O, TS Table 39 on page 109 RxData6_S B4 O, TS Table 39 on page 109 RxData6_SS A4 O, TS, ID Table 39 on page 109 RxData7_S C5 O, TS Table 39 on page 109 RxData7_SS C6 O, TS, ID Table 39 on page 109 RxSYNC E1 O, TS, ID Table 39 on page 109 SGND C8 – Table 39 on page 109 SYNC/ TXSYNC K1 I, ID Table 39 on page 109 Signal Name Ball Type Reference for Full TCK A11 I, ST, ID Table 39 on page 109 TDI C12 I, ST, IP Table 39 on page 109 TDO C11 O, TS Table 39 on page 109 TMS B11 I, ST, IP Table 39 on page 109 TPIN0 N12 AI/AO Table 39 on page 109 TPIN1 M13 AI/AO Table 39 on page 109 TPIN2 L14 AI/AO Table 39 on page 109 TPIN3 H13 AI/AO Table 39 on page 109 TPIN4 G13 AI/AO Table 39 on page 109 TPIN5 D14 AI/AO Table 39 on page 109 TPIN6 C13 AI/AO Table 39 on page 109 TPIN7 B12 AI/AO Table 39 on page 109 TPIP0 P12 AI/AO Table 39 on page 109 TPIP1 M14 AI/AO Table 39 on page 109 TPIP2 L13 AI/AO Table 39 on page 109 TPIP3 H14 AI/AO Table 39 on page 109 TPIP4 G14 AI/AO Table 39 on page 109 TPIP5 D13 AI/AO Table 39 on page 109 TPIP6 C14 AI/AO Table 39 on page 109 TPIP7 A12 AI/AO Table 39 on page 109 TPON0 N13 AO/AI Table 39 on page 109 TPON1 P14 AO/AI Table 39 on page 109 TPON2 K14 AO/AI Table 39 on page 109 TPON3 J13 AO/AI Table 39 on page 109 TPON4 F13 AO/AI Table 39 on page 109 TPON5 E14 AO/AI Table 39 on page 109 TPON6 A14 AO/AI Table 39 on page 109 TPON7 B13 AO/AI Table 39 on page 109 TPOP0 P13 AO/AI Table 39 on page 109 TPOP1 N14 AO/AI Table 39 on page 109 TPOP2 K13 AO/AI Table 39 on page 109 TPOP3 J14 AO/AI Table 39 on page 109 TPOP4 F14 AO, AI Table 39 on page 109 TPOP5 E13 AO/AI Table 39 on page 109 TPOP6 B14 AO/AI Table 39 on page 109 TPOP7 A13 AO/AI Table 39 on page 109 Signal Name Ball Type Reference for Full

102 Datasheet

Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers TRST A10 I, ST, IP Table 39 on page 109 TXCLK J3 I, ID Table 39 on page 109 TxData0 N4 I, ID Table 39 on page 109 TxData1 N2 I, ID Table 39 on page 109 TxData2 K3 I, ID Table 39 on page 109 TxData3 J1 I, ID Table 39 on page 109 TxData4 G3 I, ID Table 39 on page 109 TxData5 E2 I, ID Table 39 on page 109 TxData6 D3 I, ID Table 39 on page 109 TxData7 A5 I, ID Table 39 on page 109 TXSLEW_0 M11 I, ST, ID Table 39 on page 109 TXSLEW_1 M12 I,ST, ID Table 39 on page 109 VCCD D7 – Table 39 on page 109 VCCD L7 – Table 39 on page 109 VCCIO D4 – Table 39 on page 109 VCCIO F4 – Table 39 on page 109 VCCIO H4 – Table 39 on page 109 VCCIO L3 – Table 39 on page 109 VCCIO L5 – Table 39 on page 109 Signal Name Ball Type Reference for Full

Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Datasheet 103 Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 Table 38 shows the ball locations and signal names arranged in order by ball location. Table 38. Intel® LXT9785MBC BGA15 Ball List in Alphanumeric Order by Ball Location (SMII/ A1 GNDD – Table 39 on page 109 A2 GNDD – Table 39 on page 109 A3 GNDD – Table 39 on page 109 A4 RxData6_SS O, TS, ID Table 39 on page 109 A5 TxData7 I, ID Table 39 on page 109 A6 LED7_2 OD, TS, SL, IP Table 39 on page 109 A7 LED6_1 OD, TS, SL, IP Table 39 on page 109 A8 LED5_2 OD, TS, SL, IP Table 39 on page 109 A9 LED4_2 OD, TS, SL, IP Table 39 on page 109 A10 TRST I, ST, IP Table 39 on page 109 A11 TCK I, ST, ID Table 39 on page 109 A12 TPIP7 AI/AO Table 39 on page 109 A13 TPOP7 AO/AI Table 39 on page 109 A14 TPON6 AO/AI Table 39 on page 109 B1 GNDD – Table 39 on page 109 B2 GNDD – Table 39 on page 109 B3 LINKHOLD ID Table 39 on page 109 B4 RxData6_S O, TS Table 39 on page 109 B5 GNDD – Table 39 on page 109 B6 LED7_1 OD, TS, SL, IP Table 39 on page 109 B7 LED6_2 OD, TS, SL, IP Table 39 on page 109 B8 LED5_1 OD, TS, SL, IP Table 39 on page 109 B9 LED4_1 OD, TS, SL, IP Table 39 on page 109 B10 GNDD – Table 39 on page 109 B11 TMS I, ST, IP Table 39 on page 109 B12 TPIN7 AI/AO Table 39 on page 109 B13 TPON7 AO/AI Table 39 on page 109 B14 TPOP6 AO/AI Table 39 on page 109 C1 FIFOSEL1 I, ID Table 39 on page 109 C2 RxData5_SS O, TS, ID Table 39 on page 109 C3 REFCLK1 I Table 39 on page 109 C4 N/C – Table 39 on page 109 C5 RxData7_S O, TS Table 39 on page 109 C6 RxData7_SS O, TS, ID Table 39 on page 109 C7 N/C – Table 39 on page 109 C8 SGND – Table 39 on page 109 C9 ModeSel_0 I, ST, ID Table 39 on page 109 C10 RESET I, ST, IP Table 39 on page 109 C11 TDO O, TS Table 39 on page 109 C12 TDI I, ST, IP Table 39 on page 109 C13 TPIN6 AI/AO Table 39 on page 109 Ball Signal Name Type Reference for Full

104 Datasheet

Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers C14 TPIP6 AI/AO Table 39 on page 109 D1 N/C – Table 39 on page 109 D2 N/C – Table 39 on page 109 D3 TxData6 I, ID Table 39 on page 109 D4 VCCIO – Table 39 on page 109 D5 N/C – Table 39 on page 109 D6 N/C – Table 39 on page 109 D7 VCCD – Table 39 on page 109 D8 N/C – Table 39 on page 109 D9 GNDD – Table 39 on page 109 D10 N/C – Table 39 on page 109 D11 GNDD – Table 39 on page 109 D12 AVCC – Table 39 on page 109 D13 TPIP5 AI/AO Table 39 on page 109 D14 TPIN5 AI/AO Table 39 on page 109 E1 RxSYNC O, TS, ID Table 39 on page 109 E2 TxData5 I, ID Table 39 on page 109 E3 RxData5_S O, TS Table 39 on page 109 E4 N/C – Table 39 on page 109 E5 GNDD – Table 39 on page 109 E6 GNDD – Table 39 on page 109 E7 N/C – Table 39 on page 109 E8 ModeSel_1 I, ST, ID Table 39 on page 109 E9 GNDD – Table 39 on page 109 Ball Signal Name Type Reference for Full E10 GNDD – Table 39 on page 109 E11 AVSS – Table 39 on page 109 E12 AVCC – Table 39 on page 109 E13 TPOP5 AO/AI Table 39 on page 109 E14 TPON5 AO/AI Table 39 on page 109 F1 FIFOSEL0 I, ID Table 39 on page 109 F2 RxData4_S O, TS Table 39 on page 109 F3 RxData4_SS O, TS, ID Table 39 on page 109 F4 VCCIO – Table 39 on page 109 F5 GNDD – Table 39 on page 109 F6 GNDD – Table 39 on page 109 F7 GNDD – Table 39 on page 109 F8 GNDD – Table 39 on page 109 F9 AVSS – Table 39 on page 109 F10 AVSS – Table 39 on page 109 F11 AVSS – Table 39 on page 109 F12 AVCC – Table 39 on page 109 F13 TPON4 AO/AI Table 39 on page 109 F14 TPOP4 AO, AI Table 39 on page 109 G1 RXCLK O, TS, ID Table 39 on page 109 G2 N/C – Table 39 on page 109 G3 TxData4 I, ID Table 39 on page 109 G4 GNDD – Table 39 on page 109 G5 N/C – Table 39 on page 109 Ball Signal Name Type Reference for Full

Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Datasheet 105 Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 G6 GNDD – Table 39 on page 109 G7 GNDD – Table 39 on page 109 G8 GNDD – Table 39 on page 109 G9 AVSS – Table 39 on page 109 G10 AVSS – Table 39 on page 109 G11 AVSS – Table 39 on page 109 G12 AVCC – Table 39 on page 109 G13 TPIN4 AI/AO Table 39 on page 109 G14 TPIP4 AI/AO Table 39 on page 109 H1 N/C – Table 39 on page 109 H2 RxData3_SS O, TS, ID Table 39 on page 109 H3 RxData3_S O, TS Table 39 on page 109 H4 VCCIO – Table 39 on page 109 H5 N/C – Table 39 on page 109 H6 GNDD – Table 39 on page 109 H7 GNDD – Table 39 on page 109 H8 GNDD – Table 39 on page 109 H9 AVSS – Table 39 on page 109 H10 AVSS – Table 39 on page 109 H11 AVSS – Table 39 on page 109 H12 AVCC – Table 39 on page 109 H13 TPIN3 AI/AO Table 39 on page 109 H14 TPIP3 AI/AO Table 39 on page 109 J1 TxData3 I, ID Table 39 on page 109 Ball Signal Name Type Reference for Full J2 RxData2_SS O, TS, ID Table 39 on page 109 J3 TXCLK I, ID Table 39 on page 109 J4 N/C – Table 39 on page 109 J5 GNDD – Table 39 on page 109 J6 GNDD – Table 39 on page 109 J7 GNDD – Table 39 on page 109 J8 GNDD – Table 39 on page 109 J9 AVSS – Table 39 on page 109 J10 AVSS – Table 39 on page 109 J11 AVSS – Table 39 on page 109 J12 AVCC – Table 39 on page 109 J13 TPON3 AO/AI Table 39 on page 109 J14 TPOP3 AO/AI Table 39 on page 109 K1 SYNC/ TXSYNC I, ID Table 39 on page 109 K2 RxData2_S O, TS Table 39 on page 109 K3 TxData2 I, ID Table 39 on page 109 K4 N/C – Table 39 on page 109 K5 GNDD – Table 39 on page 109 K6 GNDD – Table 39 on page 109 K7 N/C – Table 39 on page 109 K8 AMDIX_EN I, ST, IP Table 39 on page 109 K9 GNDD – Table 39 on page 109 K10 GNDD – Table 39 on page 109 K11 AVSS – Table 39 on page 109 Ball Signal Name Type Reference for Full

106 Datasheet

Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers K12 AVCC – Table 39 on page 109 K13 TPOP2 AO/AI Table 39 on page 109 K14 TPON2 AO/AI Table 39 on page 109 L1 N/C – Table 39 on page 109 L2 GNDD – Table 39 on page 109 L3 VCCIO – Table 39 on page 109 L4 REFCLK0 I Table 39 on page 109 L5 VCCIO – Table 39 on page 109 L6 N/C – Table 39 on page 109 L7 VCCD – Table 39 on page 109 L8 N/C – Table 39 on page 109 L9 CFG_2 I, ST, ID Table 39 on page 109 L10 N/C – Table 39 on page 109 L11 AVSS – Table 39 on page 109 L12 AVCC – Table 39 on page 109 L13 TPIP2 AI/AO Table 39 on page 109 L14 TPIN2 AI/AO Table 39 on page 109 M1 RxData1_SS O, TS, ID Table 39 on page 109 M2 RxData1_S O, TS Table 39 on page 109 M3 RxData0_SS O, TS, ID Table 39 on page 109 M4 N/C – Table 39 on page 109 M5 N/C – Table 39 on page 109 M6 N/C – Table 39 on page 109 M7 N/C – Table 39 on page 109 Ball Signal Name Type Reference for Full M8 N/C – Table 39 on page 109 M9 CFG_3 I, ST, ID Table 39 on page 109 M10 CFG_1 I, ST, ID Table 39 on page 109 M11 TXSLEW_0 I, ST, ID Table 39 on page 109 M12 TXSLEW_1 I,ST, ID Table 39 on page 109 M13 TPIN1 AI/AO Table 39 on page 109 M14 TPIP1 AI/AO Table 39 on page 109 N1 GNDD – Table 39 on page 109 N2 TxData1 I, ID Table 39 on page 109 N3 RxData0_S O, TS Table 39 on page 109 N4 TxData0 I, ID Table 39 on page 109 N5 MDIO IO, TS, SL, IP Table 39 on page 109 N6 LED3_2 OD, TS, SL, IP Table 39 on page 109 N7 LED2_2 OD, TS, SL, IP Table 39 on page 109 N8 LED1_1 OD, TS, SL, IP Table 39 on page 109 N9 LED0_1 OD, TS, SL, IP Table 39 on page 109 N10 ADD_4 I, ST, ID Table 39 on page 109 N11 GNDD – Table 39 on page 109 N12 TPIN0 AI/AO Table 39 on page 109 N13 TPON0 AO/AI Table 39 on page 109 N14 TPOP1 AO/AI Table 39 on page 109 P1 GNDD – Table 39 on page 109 Ball Signal Name Type Reference for Full

Intel® LXT9785 and Intel® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Datasheet 107 Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 P2 N/C – Table 39 on page 109 P3 N/C – Table 39 on page 109 P4 MDC I, ST, ID Table 39 on page 109 P5 MDINT OD, TS, SL, IP Table 39 on page 109 P6 LED3_1 OD, TS, SL, IP Table 39 on page 109 P7 LED2_1 OD, TS, SL, IP Table 39 on page 109 P8 LED1_2 OD, TS, SL, IP Table 39 on page 109 P9 LED0_2 OD, TS, SL, IP Table 39 on page 109 P10 ADD_3 I, ST, ID Table 39 on page 109 P11 GNDD – Table 39 on page 109 P12 TPIP0 AI/AO Table 39 on page 109 P13 TPOP0 AO/AI Table 39 on page 109 P14 TPON1 AO/AI Table 39 on page 109 Ball Signal Name Type Reference for Full

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3.6 BGA15 Signal Descriptions

3.6.1 Signal Name Conventions

Port Number Only. Individual signals that apply to a particular port are designated by the Signal Mnemonic, immediately followed by the Port Designation. For example, Transmit Enable signals would be identified as TxEN0, TxEN1, and TxEN2.
Serial Number Only. A set of signals which are not tied to any specific port are designated by the Signal Mnemonic, followed by an underscore and a serial designation. For example, a set of three Global Configuration signals would be identified as CFG_1, CFG_2, and CFG_3.
Port and Serial Number. In cases where each port is assigned a set of multiple signals, each signal is designated in the following order: Signal Mnemonic, Port Designation, an underscore, and the serial designation. For example, a set of three Port Configuration signals would be identified as RxData0_0 and RxData0_1, RxData1_0 and RxData1_1, and RxData2_0 and RxData2_1.

3.6.2 Signal Descriptions – SM II and SS-SMII Configurations

Table 39 provides the BGA15 signal descriptions. Table 39. Intel ® LXT9785 BGA15 Signal Descriptions (Sheet 1 of 7) cycles to synchronize the SMII.

Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =

110 Datasheet

SS-SMII Transmit Synchronization. cycles to mark the start of TxData segments. SS-SMII Receive Synchronization. Requirements” on page 125 for detailed clock requirements. only enabled when SS-SMII mode is enabled. Management Data Input/Output. Pin indicates status change. Refer to Figure 21 on page 140. Table 39. Intel ® LXT9785 BGA15 Signal Descriptions (Sheet 2 of 7)

Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =

2, Positive & Negative, Ports 0-7. drive 802.3 compliant pulses onto the line. 3, Positive & Negative, Ports 0-7. C12 TDI I, ST, IP Test Data Input. Test data sampled with respect to the rising edge of TCK. C11 TDO O, TS Test Data Output. Test data driven with respect to the falling edge of TCK. B11 TMS I, ST, IP Test Mode Select. A11 TCK I, ST, ID Test Clock. A10 TRST I, ST, IP Test Reset. Table 39. Intel ® LXT9785 BGA15 Signal Descriptions (Sheet 3 of 7)

Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =

112 Datasheet

Tx Output Slew Controls 0 and 1 Defaults. overwritten after startup / reset.

00000
01000
10000
11000 Each port adds its port number (starting with 0) to this address to determine its PHY address. Port 0 Address = Base Port 1 Address = Base + 1 Port 2 Address = Base + 2 Port 3 Address = Base + 3 Port 4 Address = Base + 4 Port 5 Address = Base + 5 Port 6 Address = Base + 6 Port 7 Address = Base + 7 C9, MODESEL_1 MODESEL_0 I, ST, ID Mode Select[1:0]. 00 = Reserved 01 = SMII 10 = SS-SMII 11 = Reserved All ports are configured the same. Interfaces cannot be mixed and must be all SMII or SS-SMII.

Table 39. Intel ® LXT9785 BGA15 Signal Descriptions (Sheet 4 of 7)

Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =

Auto MDI/MDIX Enable Default. used to set the default state of Register bit 27.9 for all ports. startup / reset. Refer to Table 40 on page 119. inactive (Low) MDIX is selected according to the MDIX pin. Global Port Configuration Defaults 1-3. overwritten after startup/reset. Depth Configurations” on page 97. 9785E powers down all ports. state is set inactive via the internal pull-down resistor. 14)” on page 213 for details). Table 39. Intel ® LXT9785 BGA15 Signal Descriptions (Sheet 5 of 7)

Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =

114 Datasheet

14)” on page 213 for details). 14)” on page 213 for details). 14)” on page 213 for details). 14)” on page 213 for details). 14)” on page 213 for details). 14)” on page 213 for details). 14)” on page 213 for details). +2.5 V supply for analog circuits. Table 39. Intel ® LXT9785 BGA15 Signal Descriptions (Sheet 6 of 7)

Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =

be tied together using a single ground plane. D7, L7 VCCD – Digital Power Supply - Core. +2.5 V supply for core digital circuits. Digital Power Supply - I/O Ring. pins can be tied together using a single ground plane. together using a single ground plane. Table 39. Intel ® LXT9785 BGA15 Signal Descriptions (Sheet 7 of 7)

Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =

LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers

116 Datasheet

Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003

4.0 Functional Description

4.1 Introduction

The Intel® LXT9785/LXT9785E is an 8-port Fast Ethernet 10/100 PHY transceiver that supports 10 Mbps and 100 Mbps networks, complying with all applicable requirements of IEEE 802.3 standards. The device incorporates a Serial Media Independent Interface (SMII), Source Synchronous-Serial Media Independent Interface (SS-SMII), and a Reduced Serial Independent Interface (RMII) to enable each individual network port to interface with multiple 10/100 MACs. Each port directly drives either a 100BASE-TX line or a 10BASE-T line. The LXT9785/9785E also supports 100BASE-FX operation via an LVPECL interface. The device has a 241-ball BGA, a 208-pin QFP, or a 196-ball BGA package. The 196-ball BGA package (BGA15) is a reduced feature-set product. The BGA15 package does not support the following features:

RMII
Fiber
Sectionalization
Third LED port (only two LEDs per port)
Hardware control pins: —P A U S E —M D I X —M D D I S —P W R D W N — Lower three PHY address (out of five PHY address bits)
Extended temperature Note: Unless otherwise noted, all information in this document applies to the LXT9785 and LXT9785E.

4.1.1 OSP™ Architecture

The Intel LXT9785/LXT9785E incorporates high-efficiency Optimal Signal Processing™ design techniques, combining the best properties of digital and analog signal processing to produce a truly optimal device. The receiver utilizes decision feedback equalization to increase noise and cross-talk immunity by as much as 3 dB over an ideal all-analog equalizer. Using OSP mixed-signal processing techniques in the receive equalizer avoids the quantization noise and calculation truncation errors found in traditional DSP-based receivers (typically complex DSP engines with A/D converters). The result is improved receiver noise and cross-talk performance. The OSP architecture also requires substantially less computational logic than traditional DSP- based designs. The result is lower power consumption and reduced logic switching noise generated by DSP engines clocked at speeds up to 125 MHz. The logic switching noise can be a considerable source of EMI when generated from the device’s power supplies.

LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Datasheet 117 Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 The OSP-based LXT9785/LXT9785E provides improved data recovery, EMI performance and power consumption.

4.1.2 Comprehensive Functionality

The LXT9785/LXT9785E performs all functions of the Physical Coding Sublayer (PCS) and Physical Media Attachment (PMA) sublayer as defined in the IEEE 802.3 100BASE-X specification. This device also performs all functions of the Physical Media Dependent (PMD) sublayer for 100BASE-TX connections. On power-up, the LXT9785/LXT9785E reads its configuration inputs to check for forced operation settings. If not configured for forced operation, each port uses auto-negotiation/parallel detection to automatically determine line operating conditions. If the PHY device on the other side of the link supports auto-negotiation, the LXT9785/LXT9785E auto-negotiates with it using Fast Link Pulse (FLP) Bursts. If the PHY partner does not support auto-negotiation, the LXT9785/LXT9785E automatically detects the presence of either link pulses (10 Mbps PHY) or Idle symbols (100 Mbps PHY) and set its operating conditions accordingly. The LXT9785/LXT9785E provides half-duplex and full-duplex operation at 100 Mbps and 10 Mbps.

4.1.2.1 Sectionalization

The LXT9785/LXT9785E’s sectional design allows flexibility with large multiport MACs and ASICs. With the use of the Section pin, the LXT9785/LXT9785E can be configured into a single 8- port or two separate 4-port sections, each with its own MDIO (with separate MDC clock) and MII data (with separate REFCLK/TxCLK/RxCLK clocks) interfaces. See Figure 16, “Intel® LXT9785/LXT9785E Typical SMII Quad Sectionalization Diagram” on page 134, Figure 21, “Intel® LXT9785/LXT9785E Typical SS-SMII Quad Sectionalization Diagram” on page 140, and Figure 26, “Intel® LXT9785/LXT9785E Typical RMII Quad Sectionalization Diagram” on page 144. Note: The BGA15 package does not support sectionalization.

4.2 Interface Descriptions

4.2.1 10/100 Network Interface The LXT9785/LXT9785E supports 10 Mbps and 100 Mbps (10BASE-T and 100BASE-TX) Ethernet over twisted-pair, or 100 Mbps (100BASE-FX) Ethernet over fiber media. Each network interface port consists of four external pins (two differential signal pairs). The pins are shared between twisted-pair (TP) and fiber. The LXT9785/LXT9785E pinout is designed to interface seamlessly with dual-high stacked RJ-45 connectors. Refer to Table 11, “Intel® LXT9785/ LXT9785E Network Interface Signal Descriptions – PQFP” on page 42 for specific pin assignments. The LXT9785/LXT9785E output drivers generate either 100BASE-TX, 10BASE-T, or 100BASE- FX output. When not transmitting data, the device generates IEEE 802.3-compliant link pulses or idle code. Input signals are decoded either as a 100BASE-TX, 100BASE-FX, or 10BASE-T input, depending on the mode selected. Auto-negotiation/parallel detection or manual control is used to determine the speed of this interface.

118 Datasheet

4.2.1.1 Twisted-Pair Interface

transmitter uses a transformer with a center tap to help reduce power consumption. transmitting data, the LXT9785/LXT9785E generates “IDLE” symbols. Figure 7. Intel ® LXT9785/LXT9785E Interfaces

being exchanged, the line is left in an idle state with NLPs transmitted to maintain link.

4.2.1.2 MDI Crossover (MDIX)

function can be disabled via Register bits 27.9:8 or by using the hardware configuration pins. control the function after power-up.

4.2.1.3 Fiber Interface

that complies with the ANSI X3.166 standard for seamless integration. Note: The BGA15 package does not support the fiber interface.

Configure Register bit 16.0 = 1 on a global ba sis (all 8 ports) by driving the Hardware Control

pin G_FX/TP to a logic High value on power-up and/or reset.

Configure Register bit 16.0 = 1 on a pe r-port basis through the MDIO interface.

4.3 Media Independent In terface (MII) Interfaces

mode selection pins configures the device for either RMII or SMII/SS-SMII on all eight ports. Refer to Table 41 for the mode select settings. Note: The BGA15 package does not support the RMII interface.

4.3.1 Global MII Mode Select

The mode select pins are used for MII interface configuration settings upon power-up sequencing. All ports are configured the same and cannot be intermixed. Table 40. Intel ® LXT9785/LXT9785E MDIX Selection

1 X Auto MDI/MDIX

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4.3.2 Internal Loopback

Write Register 0 with 0x2100h (forced 100 Mbps), and
Write Register 0 with 0x6100h (enable internal loopback with forced 100 Mbps)

to eliminate the auto-negotiation BLT timer requirement.

4.3.3 RMII Data Interface

and up to eight Media Access Controllers (MACs). Table 41. Intel ® LXT9785/LXT9785E MII Mode Select

Invalid for the BGA15 package.

Figure 8. Intel ® LXT9785/LXT9785E Internal Loopback

LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Datasheet 121 Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003

4.3.4 Serial Media Independent Interf ace (SMII) and Source Synchronous-

Serial Media Independent Interface (SS-SMII)

4.3.4.1 SMII Interface

The LXT9785/LXT9785E provides an independent serial interface for each network port, complying with the Serial-MII Specification, Revision 1.2. All SMII ports use a common reference clock and SYNC signal. The SMII Data Interface exchanges data between the LXT9785/ LXT9785E and multiple Media Access Controllers (MACs). All signals are synchronous to the reference clock. One SYNC control stream is sourced by the MAC to the PHY . Both the transmit and receive data streams are segmented into boundaries delimited by the SYNC pulses. This interface is expected to drive up to 6 inches of trace lengths.

4.3.4.2 Source Synchronous- Serial Media Independent Interface

The new revision to the SMII interface, SS-SMII, allows for a longer trace length and helps to relieve timing constraints, requiring the addition of four new signals, TxCLK, TxSYNC, RxCLK, and RxSYNC. The transmit TxCLK and TxSYNC are sourced from the MAC to the PHY and referenced to the REFCLK input. The receive RxCLK and RxSYNC are sourced by the PHY to the MAC and in reference to the REFCLK.

4.3.5 Configuration Management Interface

The LXT9785/LXT9785E provides an MDIO Management Interface and a Hardware Control Interface (via the CFG pins) for device configuration and management. Mode control selection is provided via the MDDIS pin as shown in Table 9, “Intel® LXT9785/LXT9785E MDIO Control Interface Signals – PQFP” on page 41. When sectionalization (2x4) is selected, separate MDIO interfaces are enabled (see Figure 13 on page 127).

4.3.6 MII Isolate

In applications where the MII must be isolated from the bus, the RMII and the SMII/SS-SMII configurations can be three-stated using Register 0.10. On each individual port, Register bit 0.10 controls the isolation of the transmit and receive data signals for that port. Register bit 0.10 on ports 0 and 4 isolate the RxCLKn/TxCLKn and SYNC signals. When 1x8 sectionalization is selected, TxCLK0, TxSYNC0, RxCLK1, and RxSYNC1 are used for the clocking and synchronization interface. Port 4 controls the isolation of RxCLK0, RxCLK1, RxSYNC0, and RxSYNC1, and must be used to isolate the receive clock and synchronization interface. When 2x4 sectionalization is selected, TxCLK0, TxSNC0, RxCLK0, and TxCLK0 are used for Port 0 through Port 3 and TxCLK1, TxSYNC1, RxCLK1, and RxSYNC1 are used for Port 4 through Port 7. Port 0 must be isolated to isolate the receive clock and synchronization interface for Port 0 through Port 3. Port 4 must be isolated to isolate Port 4 through Port 7.

4.3.7 MDIO Management Interface

The LXT9785/LXT9785E supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the LXT9785/LXT9785E. The MDIO interface consists of a

122 Datasheet

completely disabled. The Hardware Control Interface provides primary configuration control. Hardware Control Interface is not used. Note: The BGA15 package does not support the MDDIS pin. “Intel® LXT9785/LXT9785E Management Interface Write Frame Structure” on page 122. obtain its port address as shown in Figure 11. Figure 9. Intel Figure 10. Intel® LXT9785/LXT9785E Management Interface Write Frame Structure

4.3.8 MII Sectionalization

Note: The BGA15 package does not support the MII sectionalization feature.

4.3.9 MII Interrupts

The LXT9785/LXT9785E provides a single per-section interrupt pin that is available to all ports. interrupt via the MDINT pin. An active Low on this pin indicates a status change on the device. Figure 11. Intel® LXT9785/LXT9785E Port Address Scheme

124 Datasheet

Auto-negotiation complete.
Speed status change.
Duplex status change.
Link status change.
Isolate status change.

4.3.10 Global Hardware Control Interface

MDIO is not desired. Refer to “Initialization” on page 126 for additional details.

4.3.11 FIFO Initial Fill Values

one nibble less than the selected size.

The frequency difference between the link partner and the local LXT9895 device exceed 200 ppm (the IEEE standard requirement).
Jumbo packets (8192 byte packets or longer) are used.
Packets on the wire occur with minimum Inter-Packet Gap (IPG) of 96 bit times. The concatenation of the packets is flagged by the MAC as a CRC error and possibly an oversized packet depending upon the length indication capabilities of the MAC. The possibility of packet concatenation can be minimized on the RMII interface by setting the initial fill FIFO Register bits 18.15:14 to 01. The FIFO setting bits should be set to 10 for the SMII interfaces.

Figure 12. Intel® LXT9785/LXT9785E Interrupt Logic I nterrupt ( Event) Status Register is cleared on read.

LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Datasheet 125 Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003

4.4 Operating Requirements

4.4.1 Power Requirements

The LXT9785/LXT9785E requires four power supply inputs: VCCD, VCCA, VCCPECL and VCCIO. The digital and analog circuits require 2.5 V supplies (VCCD, VCCR, and VCCT). These inputs may be supplied from a single source although decoupling is required to each respective ground. The fiber VCCPECL supply can be connected to either 2.5 V or 3.3 V . A separate power supply may be used for the MII, JTAG and MDIO (VCCIO) interfaces. The power supply may be either +2.5 V or +3.3 V . VCCIO should be supplied from the same power source used to supply the controller on the other side of the interface. Refer to Table 53, “Intel® LXT9785/LXT9785E Digital I/O DC Electrical Characteristics (VCCIO = 2.5 V +/- 5%)” on page 174, Table 54, “Intel® LXT9785/LXT9785E Digital I/O DC Electrical Characteristics (VCCIO = 3.3 V +/- 5%)” on page 175, and Table 55, “Intel® LXT9785/LXT9785E Digital I/O As a matter of good practice, these supplies should be as clean as possible. Typical filtering and decoupling are shown in Figure 34 on page 168. The power supplies should be brought up as close to the same time as possible. However, there are no specific timing requirements.

4.4.2 Clock/SYNC Requirements

4.4.2.1 Reference Clock

The LXT9785/LXT9785E requires a constant enabled reference clock (REFCLK). REFCLK’s frequency must be 50 MHz for RMII or 125 MHz for SMII/SS-SMII. The reference clock is used to generate transmit signals and recover receive signals. A crystal-based clock is recommended over a derived clock (that is, PLL-based) to minimize transmit jitter. Refer to Table 56, “Intel® LXT9785/LXT9785E Required Clock Characteristics” on page 175 for clock timing requirements. For applications that use a single 8-port sectionalization, REFCLK0 and REFCLK1 must always be tied together and to the source. In 2x4 applications, REFCLK0 and REFCLK1 are not tied together.

4.4.2.2 TxCLK Signal (SS-SMII only)

The LXT9785/LXT9785E requires a 125 MHz input transmit clock synchronous with TxData n and frequency locked to REFCLK. See Figure 22 on page 141.

4.4.2.3 TxSYNC Signal (SMII/SS-SMII)

The LXT9785/LXT9785E requires a 12.5 MHz input pulse for SMII synchronization. See Figure 22 on page 141.

4.4.2.4 RxSYNC Signal (SS-SMII only)

The LXT9785/LXT9785E provides a 12.5 MHz output pulse synchronous with the RxDatan outputs. See Figure 23 on page 141.

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4.4.2.5 RxCLK Signal (SS-SMII only)

In SS-SMII mode, the LXT9785/LXT9785E provides a 125 MHz clock output in reference to the output RxDatan. RxCLK is referenced and synchronized to the REFCLK. See Figure 23 on page 141.

4.5 Initialization

When the LXT9785/LXT9785E is first powered on, reset, or encounters a link failure state, it checks the MDIO register configuration bits to determine the line speed and operating conditions to use for the network link. The configuration bits may be set by the Hardware Control or MDIO interface as shown in Figure 13 on page 127.

4.5.1 MDIO Control Mode

In the MDIO Control mode, the LXT9785/LXT9785E reads the Hardware Control Interface pins to set the initial (default) values of the MDIO registers. Once the initial values are set, bit control reverts to the MDIO interface.

4.5.2 Hardware Control Mode

In the Hardware Control Mode, the LXT9785/LXT9785E disables direct write operations to the MDIO registers via the MDIO Interface. On power-up or hardware reset, the LXT9785/LXT9785E reads the Hardware Control Interface pins and sets the MDIO registers accordingly. The following modes are available using either Hardware Control or MDIO Control:

Force network link to 100BASE-FX (Fiber).
Force network link operation to: — 100BASE-TX, Full-Duplex — 100BASE-TX, Half-Duplex — 10BASE-T, Full-Duplex — 10BASE-T, Half-Duplex
Allow auto-negotiation/parallel-detection.
Auto/Manual MDIX enable/disable.
Pause for full-duplex links operation.
Global Output Slew Rate Control. When the network link is forced to a specific configuration, the LXT9785/LXT9785E immediately begins operating the network interface as commanded. When auto-negotiation is enabled, the LXT9785/LXT9785E begins the auto-negotiation/ parallel-detection operation.

4.5.3 Power-Down Mode

The LXT9785/LXT9785E incorporates numerous features to maintain the lowest power possible. The lowest power operation is achieved using the Global power-down pin, which is active High. and maintained when the Global PWRDWN pin is released. Note: The BGA15 package does not support the PWRDWN pin feature. Figure 13. Intel® LXT9785/LXT9785E Initialization Sequence

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Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 Note: Intel recommends that a minimum recovery time be allowed after bringing up a port from software or hardware power-down or link hold-off modes. The recovery times are specified in Table 80, “Intel® LXT9785/LXT9785E Power-Up Timing Parameters” on page 198

4.5.3.1 Global (Hardware) Power Down

The global power-down mode is controlled by the PWRDWN pin. When PWRDWN is High, the following conditions are true:

All LXT9785/LXT9785E ports and the clock are shut down.
All outputs are three-stated.
All weak pad pull-up and pull-down resistors are disabled.
The MDIO registers are not accessible.
Configuration pins are read upon release of the PWRDWN pin, and registers are loaded with the current values of the hardware configuration pins.

4.5.3.2 Port (Software) Power Down

Individual port power-down control is provided by Register bit 0.11 in the respective port Control Registers (refer to Table 83, “Control Register (Address 0)” on page 200). During individual port power-down, the following conditions are true:

The individual port is shut down.
The MDIO registers remain accessible.
Pull-up and pull-down resisters are not affected and the outputs are not three-stated.
The register remains unchanged.

4.5.4 Reset

The LXT9785/LXT9785E provides both hardware and software resets. Configuration control of Auto-Negotiation, speed, and duplex mode selection is handled differently for each. During a hardware reset, settings for bits 0.13, 0.12, 0.8, and 4.8:5 are read in from the pins (refer to Table 42, “Intel® LXT9785/9785E Global Hardware Configuration Settings” on page 129 for pin settings, and Table 83, “Control Register (Address 0)” on page 200 and Table 87, “Auto- Negotiation Advertisement Register (Address 4)” on page 204 for register bit definitions). During a software reset (Register bit 0.15 = 1), the bit settings are not re-read from the pins and revert back to the values that were read in during the last hardware reset. Any changes to pin values from the last hardware reset are not detected during a software reset. During a hardware reset, register information is unavailable for 1 ms after de-assertion of the reset. All MII interface pins are disabled during a hardware reset and released to the bus on de-assertion of reset. During a software reset (0.15 = 1) the registers are available for reading. The reset bit should be polled to see when the part has completed reset (0.15 = 0). Pull up and pull down resisters are not affected.

4.5.5 Hardware Configuration Settings

hardware option uses three Global CFG pins that provide control for all ports (see Table 42).

4.6 Link Establishment

4.6.1 Auto-Negotiation

4.6.1.1 Base Page Exchange

the operating state of the line. Table 42. Intel ® LXT9785/9785E Global Hardware Configuration Settings

Refer to Table 5, “Intel® LXT9785/LXT9785E RMII Signal Descriptions – PQFP” on page 36 through

Descriptions” on page 109 for CFG pin assignments.

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4.6.1.2 Manual Next Page Exchange

Additional information, exceeding that required by base page exchange, is also sent via “Next Pages.” The LXT9785/LXT9785E fully supports the IEEE 802.3 method of negotiation via Next Page exchange. The Next Page exchange uses Register 7 to send information and Register 8 to receive it. Next Page exchange occurs only if both ends of the link partners advertise their ability to exchange Next Pages. A special mode has been added to make manual next page exchange easier for software. When Register 6 “page” is received, it stays set until read. This bit is cleared when a new negotiation occurs, preventing the user from reading an old value in Register 6 and assuming there is valid information in Registers 5 and 8. The page received bit is cleared upon reading the “Auto-Negotiation Expansion Register (Address 6)” on page 206.

4.6.1.3 Controlling Auto-Negotiation

The following steps are recommended when auto-negotiation is controlled by software:

After power-up, power-down, or reset, the power-down recovery time, as specified in Table 80, “Intel® LXT9785/LXT9785E Power-Up Timing Parameters” on page 198, must be exhausted before proceeding.
Set the auto-negotiation advertisement register bits in Register 4 as desired.
Enable auto-negotiation (set MDIO Register bit 0.12 = 1).
Enable or restart auto-negotiation as soon as possible after writing to Register 4 to ensure proper operation.

4.6.1.4 Link Criteria

In 100 Mbps mode, link is established when the descrambler becomes locked and remains locked for approximately 50 ms. Link remains up unless the descrambler receives less than 12 consecutive idle symbols in any 2 ms period. This provides a robust operation, filtering out any small noise hits that may disrupt the link. MLT-3 idle waveforms, for short periods, meet all the criteria for 10BASE-T start delimiters. A working 10BASE-T receive may temporarily indicate link to 100BASE-TX waveforms. However, the PHY will not bring up a permanent 10 Mbps link. According to the IEEE standard 10 Mbps link state machine, the last condition that must be met before 10 Mbps link can come up is a period of transmit and receive idle time. TXEN and RXDV are inactive at the same time. This ensures that link is not brought up in the middle of transmitting or receiving a packet. To ensure link establishment, Intel recommends no packet transmission into the MII interface until link is established. The IEEE Standard references this requirement in Section 14.2.3 State Diagrams, Figure 14-6-Link Integrity Test Function State Diagram and in Section 28.3.4 State Diagrams, Figure 28-17-NLP Receive Link Integrity Test State Diagram. These diagrams illustrate that while the PHY is in the Link Test Fail Extend state, the last state before Link Pass state) Packet receive activity (RD) and Transmit Activity (DO) must be idle (RD = idle * D0 = idle) for link to establish.

4.6.1.5 Parallel Detection

When parallel detection resolves a link, the link must be established in half-duplex mode.

4.6.1.6 Reliable Link Establishment While Auto MDI/MDIX is Enabled in Forced

and Parallel Detect specifications. Link may not occur according to the IEEE specification. Figure 14. Intel

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4.7 Serial MII Operation

Conveys complete MII information between a 10/100 PHY and MAC with two pins per port.
Allows a multi-port MAC/PHY communication with one system clock.
Operates in both half and full-duplex.
Supports per-packet switching between 10 Mbps and 100 Mbps data rates. The Serial MII operates at 125 MHz using a global reference clock and frame synchronization signal (REFCLK and SYNC). Each port has an individual two-line data interface (TxDatan and RxDatan). All signals are synchronous to REFCLK. Table 43 summarizes the SMII signals. Data is exchanged in 10-bit serial words. Each word contains one data byte (two nibbles of 4B coded data) and two status bits. When the port is operating at 100 Mbps, each word contains a new data byte. When the port is operating at 10 Mbps, each data byte is repeated 10 times.

Table 43. Intel ® LXT9785/LXT9785E SMII Signal Summary

Refer to Table 7, “Intel® LXT9785/LXT9785E SMII Specific

Figure 15. Intel® LXT9785/LXT9785E Typical SMII Interface Diagram

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Figure 16. Intel® LXT9785/LXT9785E Typical SMII Quad Sectionalization Diagram

125 MHz Sourced

4.7.1 SMII Reference Clock

signals on the rising edge of the REFCLK.

4.7.2 TxSYNC Pul se (SMII/SS-SMII)

signals the start of each new segment (see Figure 21 on page 140).

4.7.3 Transmit Data Stream

ten times on TxData. The LXT9785/LXT9785E may sample that serial word at any point. The TxSYNC pulse signals the start of a new segment as shown in Figure 18.

4.7.3.1 Transmit Enable

4.7.3.2 Transmit Error

symbols onto the network interface. TxER does not have any function in 10M operation. Figure 17. Intel® LXT9785/LXT9785E 100 Mbps Serial MII Data Flow

2 Nibbles Tx/Rx Data

2 Symbols Tx/Rx Data

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4.7.4 Receive Data Stream

for the CRS bit), and the MAC can sample any of the ten segments.

4.7.4.1 Carrier Sense

bit is set in real time, even in 10 Mbps mode (all other bits are repeated in 10 sequential segments).

4.7.4.2 Receive Data Valid

For 100BASE-TX and 100BASE-FX links, the RX_DV bit is asserted from the first nibble of preamble to the last nibble of the data packet.
For 10BASE-T links, the entire preamble is truncated. The RX_DV bit is asserted with the first nibble of the Start-of-Frame Delimiter (SFD) “5D” and remains asserted until the end of the packet.

4.7.4.3 Receive Error

mode, it drives “0101” on the associated RxData signals.

4.7.4.4 Receive Status Encoding

4.7.5 Collision

conditions using CRS and TxEN. CRS is unaffected by the transmit path. Figure 18. Intel® LXT9785/LXT9785E Serial MII Transmit Synchronization

4.7.6 Source Synchronous-Serial Media Independent Interface

RxCLK. See Figure 23 on page 141. Figure 19. Intel Table 44. Intel ® LXT9785/LXT9785E RX Status Encoding Bit Definitions CRS Carrier Sense - identical to MII, except that it is not an asynchronous signal. received data is transmitted to the MAC. PHY detected an error somewhere in the previous frame. PHY has detected a false carrier event.

Both RxData0 and RxData5 bits are valid in the segment immediately following a frame, and remain valid

until the first data segment of the next frame begins.

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Table 45. Intel ® LXT9785/LXT9785E SS-SMII

Figure 20. Intel® LXT9785/LXT9785E Typical SS-SMII Interface Diagram

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Figure 21. Intel® LXT9785/LXT9785E Typical SS-SMII Quad Sectionalization Diagram

4 TxData n

4.8 RMII Operation

transmission across the RMII is implemented in di-bit pairs which equal a 4-bit wide nibble. Note: The BGA15 package does not support the RMII interface.

4.8.1 RMII Reference Clock

Figure 22. Intel® LXT9785/LXT9785E SS-SMII Transmit Timing Figure 23. Intel® LXT9785/LXT9785E SS-SMII Receive Timing

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4.8.2 Transmit Enable

4.8.3 Carrier Sense & Data Valid

RxDatan outputs zeros until the received data is decoded and available for transfer to the controller.

4.8.4 Receive Error

Whenever the LXT9785/LXT9785E receives an error symbol from the network, it asserts RxERn. pins to indicate a false carrier event.

4.8.5 Out-of-Band Signaling

during IPG . See “Monitoring Operations” on page 157 for details. symbols. Table 46 on page 147 shows 4B/5B symbol coding (not all symbols are valid). Figure 24. Intel® LXT9785/LXT9785E RMII Data Flow

Figure 25. Intel® LXT9785/LXT9785E Typical RMII Interface Diagram

50 Mhz Sourced

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Figure 26. Intel® LXT9785/LXT9785E Typical RMII Quad Sectionalization Diagram

is not actively transmitting data, the LXT9785/LXT9785E sends out Idle symbols on the line. and then returns to transmitting Idle symbols. In a 7-layer communications model, the LXT9785/LXT9785E is a Physical Layer 1 (PHY) device. LXT9785E operation from the reference model point of view.

4.9.2.1 PCS Sublayer

does not use the 4B/5B encoder. Figure 27. Intel® LXT9785/LXT9785E 100BASE-X Frame Format

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4.9.2.1.1 Preamble Handling

continues to encode the remaining RMII data until TxEN is de-asserted (see Table 46 on page 147). It then returns to supplying IDLE symbols to the line driver. Figure 28. Intel® LXT9785/LXT9785E Protocol Sublayers

4.9.3 PMA Sublayer

streams. The coding scheme is shown in Table 46. Table 46. 4B/5B Coding 1 1 1 1 11 Idle. Used as inter stream fill code.

The /I/ (Idle) code group is sent continuously between frames.
The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/.
The /T/ and /R/ (ESD) code groups are always sent in pairs; /R/ follows /T/.
An /H/ (Error) code group is used to signal an error condition.

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4.9.3.1 Link

In 100 Mbps mode, the LXT9785/LXT9785E establishes a link whenever the descrambler becomes locked and remains locked for approximately 50 ms. Whenever the descrambler loses lock (<12 consecutive idle symbols during a 2 ms window), the link is taken down. This provides a robust link, filtering out any small noise hits that may otherwise disrupt the link. Furthermore, 100 Mbps idle patterns will not bring up a 10 Mbps link. The LXT9785/LXT9785E reports link failure via the Register status bits (1.2, 17.10, and 19.4) and interrupt functions. If auto-negotiate is enabled, link failure causes the device to re-negotiate.

4.9.3.2 Link Failure Override

The LXT9785/LXT9785E normally transmits 100 Mbps data packets or Idle symbols only if it detects the link is up, and transmits only FLP bursts if the link is not up. Setting bit 16.14 = 1 overrides this function, allowing the LXT9785/LXT9785E to transmit data packets even when the link is down. This feature is provided as a diagnostic tool. Note: Auto-negotiation must be disabled to transmit data packets in the absence of link. If auto- negotiation is enabled, the LXT9785/LXT9785E automatically begins transmitting FLP bursts if the link goes down.

4.9.3.3 Carrier Sense/Data Valid (RMII)

The LXT9785/LXT9785E asserts CRS_DV whenever the respective port receiver is in a non-idle state (as defined by the RMII Specification Revision 1.2), including false carrier events. Assertion of CRS_DV is asynchronous with respect to REFCLK. In the event that signal decoding is not complete when CRS_DV is asserted, the LXT9785/LXT9785E outputs 00 on the RxData1:0 lines until the decoded data are available. When the line returns to an idle state, CRS_DV is de-asserted synchronously with respect to REFCLK. If the FIFO still contains data to be passed to the MAC via the RMII when CRS is de- asserted, CRS_DV toggles on nibble boundaries until the FIFO is empty. For 100BASE-X signals, CRS_DV toggles at 25 MHz. For 10BASE-T signals, CRS_DV toggles at 2.5 MHz.

4.9.3.4 Carrier Sense (SMII)

For 100BASE-TX and 100BASE-FX links, a Start-of-Stream Delimiter (SSD) or /J/K/ symbol pair causes assertion of carrier sense (CRS). An End-of-Stream Delimiter (ESD), or /T/R/ symbol pair causes de-assertion of CRS. The PMA layer also de-asserts CRS if IDLE symbols are received without /T/R/. In this event, receive error is indicated during the IPG until the next packet is received. For 10T links, CRS assertion is based on receipt of valid preamble, and de-assertion on receipt of an End-of-Frame (EOF) marker.

4.9.3.5 Receive Data Valid (SMII)

The LXT9785/LXT9785E asserts the RX_DV bit when it receives a valid packet. However, RxData outputs zeros until the received data are decoded and available for transfer to the controller.

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4.9.3.6 Twisted-Pair PMD Sublayer

The twisted-pair Physical Medium Dependent (PMD) layer provides the signal scrambling and descrambling, line coding and decoding (MLT-3 for 100BASE-TX, Manchester for 10T), as well as receiving, polarity correction, and baseline wander correction functions.

4.9.3.6.1 Scrambler/Descrambler (100BASE-TX Only)

The purpose of the scrambler is to spread the signal power spectrum and further reduce EMI using an 11-bit, non-data-dependent polynomial. The receiver automatically decodes the polynomial whenever IDLE symbols are received. The scrambler/descrambler can be bypassed by setting Register bit 16.12 = 1. The scrambler is automatically bypassed when the fiber port is enabled. Scrambler bypass is provided for diagnostic and test support.

4.9.3.6.2 Baseline Wander Correction

The LXT9785/LXT9785E provides a baseline wander correction function which makes the device robust under all network operating conditions. The MLT3 coding scheme used in 100BASE-TX is, by definition, “unbalanced”. This means that the DC average value of the signal voltage can “wander” significantly over short time intervals (tenths of seconds). This wander may cause receiver errors, particularly in less robust designs, at long line lengths (100 meters). The exact characteristics of the wander are completely data dependent. The LXT9785/LXT9785E baseline wander correction characteristics allow the device to recover error-free data while receiving worst-case “killer” packets over all cable lengths.

4.9.3.6.3 Polarity Correction

The LXT9785/LXT9785E automatically detects and corrects for the condition where the receive signal (TPFIP/N) is inverted. Reversed polarity is detected if eight inverted link pulses or four inverted End-of-Frame (EOF) markers are received consecutively. If link pulses or data are not received by the maximum receive time-out period, the polarity state is reset to a non-inverted state. Before the polarity switch occurs, every frame is inverted and causes RxER to assert. The specific number of RxER events observed depends on how many link pulses occur between packets.

4.9.3.7 Fiber PMD Sublayer

The LXT9785/LXT9785E provides an LVPECL interface for connection to an external 3.3 V or 5 V fiber-optic transceiver. (The external transceiver provides the PMD function for the optical medium.) The LXT9785/LXT9785E uses a 125 Mbaud NRZI format for the fiber interface, and does not support 10BASE-FL applications. Note: The BGA15 package does not support fiber interface.

4.9.3.7.1 Far End Fault Indications

The LXT9785/LXT9785E Signal Detect pins independently detect signal faults from the local fiber transceivers via the SD pins. The device also uses Register bit 1.4 to report Remote Fault indications received from its link partner. The device “ORs” both fault conditions to set bit 1.4. Register bit 1.4 is set once and clears when read.

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Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 The far-end fault detection process in fiber operation requires idles to establish link. Link will not establish if a far-end fault pattern is the initial signal detected. Either fault condition causes the LXT9785/LXT9785E to drop the link unless Forced Link Pass is selected (16.14 = 1). Link down condition is then reported via interrupts and status bits. In response to locally detected signal faults (SD activated by the local fiber transceiver), the affected port can transmit the far end fault code if fault code transmission is enabled by Register bit 16.2.

When Register bit 16.2 = 1, transmission of the far end fault code is enabled. The LXT9785/ LXT9785E transmits far end fault code if fault conditions are detected by the Signal Detect pins.
When Register bit 16.2 = 0, the LXT9785/LXT9785E does not transmit far end fault code. It continues to transmit idle code and may or may not drop link depending on the setting for Register bit 16.14. The occurrence of a Far End Fault causes all transmission of data from the Reconciliation Sublayer to stop and the Far End fault code to begin. The Far End Fault code consists of 84 ones’s followed by a single “0” and is repeated until the Far End Fault condition is removed. 4.10 10 Mbps Operation The LXT9785/LXT9785E operates as a standard 10BASE-T transceiver and supports all the standard 10 Mbps functions. During 10BASE-T (10T) operation, the LXT9785/LXT9785E transmits and receives Manchester-encoded data across the network link. When the MAC is not actively transmitting data, the device sends out link pulses on the line. In 10T mode, the polynomial scrambler/descrambler is inactive. Manchester-encoded signals received from the network are decoded by the LXT9785/LXT9785E and sent across the MII to the MAC. Note: The LXT9785/LXT9785E does not support fiber connections at 10 Mbps.

4.10.1 Preamble Handling

The LXT9785/9785E offers two options for preamble handling, which are selected by Register bit 16.5. In 10BASE-T mode, when Register bit 16.5 = 0, the device strips the preamble off the received packets. In RMII and the SMII modes, the CRS signal is asserted based upon receive activity. In the SMII modes, Out-of-Band (OOB) signaling is present until the SFD is output. The DV signal is initially asserted in the frame that the SFD is output. In RMII mode, zeros are output after receive activity is detected until the SFD is output. The packet is output following the SFD. When Register bit 16.5 = 1 in 10BASE-T mode, the LXT9785/LXT9785E passes the preamble through the RMII and the SMII interfaces. In RMII and the SMII modes, the CRS signal is asserted based upon receive activity. In the SMII modes, OOB signaling is continued until preamble is available from the receive FIFO. After the preamble, the SFD is output with the initial assertion of the DV signal. The RMII interface outputs zeros after receive activity is detected until preamble is available from the FIFO. The number of zero nibbles output before preamble is based upon the FIFO initial fill settings (Register bits 18.15:14). The preamble is followed by the SFD and the packet body. Register bit 16.5 has no effect in 100 Mbps operation.

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4.10.2 Dribble Bits

The LXT9785/LXT9785E device handles dribble bits in all modes. If one through four dribble bits are received, the nibble is passed across the RMII. If five through seven dribble bits are received, the second nibble is not sent onto the RMII bus.

4.10.3 Link Test

The LXT9785/LXT9785E always transmits link pulses in 10T mode. When enabled, the link test function monitors the connection for link pulses. Once link pulses are detected, data transmission is enabled and remains enabled as long as either the link pulses or data transmission continue. If link pulses stop, the data transmission is disabled. If the link test function is disabled, the LXT9785/LXT9785E transmits to the connection regardless of detected link pulses. The link test function is disabled by setting Register bit 16.14 = 1.

4.10.3.1 Link Failure

Link failure occurs if Link Test is enabled and link pulses or packets stop being received. If this condition occurs, the LXT9785/LXT9785E returns to the auto-negotiation phase if auto- negotiation is enabled.

4.10.4 Jabber

If a transmission exceeds the jabber timer, the LXT9785/LXT9785E disables the transmit and loopback functions and the Collision Status bit (Register bit 17.11) is set regardless of duplex. The jabber timer, according to the IEEE standard, must be between 20 ms to 150 ms. The RMII does not include a Jabber pin, but the MAC may read Register 1 to determine jabber status. The LXT9785/LXT9785E automatically exits jabber mode after the unjab time expires. This function is disabled by setting Register bit 16.10 = 1.

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4.11 DTE Discovery Process

100 Mbps MLT3 signals and 10 Mbps Manchester-encoded signals, and must be bypassed when

power is applied to the IP phone. Figure 29 shows a typical IP telephone system connection.

4.11.1 Definitions

Figure 29. Typical IP Telephone System Connection

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4.11.2 Interaction between Processor, MAC, and PHY

The state machines that control the mechanics of the Discovery process reside within the LXT9785E device. However, control of the power supply and overall system control reside in the system processor. The processor communicates with the power supply unit (PSU) and switches it on and off dependant on the data that is supplied by the PHY . The PHY register data is read by the MAC using the MDIO interface. The required control bits are contained in the PHY device register map and are discussed in detail in the section labeled “Management Interface and Control” on page 153. Note: The details of the processor/MAC interface and the processor/PSU interface are implementation specific and therefore are out of the scope of this specification. The following is an overview of the system control for a successful Remote-Power DTE discovery: 1. The discovery process is enabled by the DTE Di scovery Process Enable (Dis_EN) Register bit 27.6 and the Auto-Negotiation Enable Register bit 0.12. Writing Register bit 27.6 immediately affects the Auto-Negotiation Base Page. If already enabled, auto-negotiation should be restarted after this bit is written to ensure proper operation. Register bit 4.15 is used for manual control of auto-negotiation next pages and should be left in the default state (cleared). 2. The LXT9785E PHY then tests to see if a Remote -Power DTE is present as the link partner. If a Remote-Power DTE is found, the Power Enable (Power_EN) Register bit 27.4 is set. The processor polls this signal via the MAC. 3. Upon detecting a Remote-Power DTE, the processor instructs the power supply to switch on. Once power has been applied to the DTE, normal negotiation takes place. The processor must enable the required negotiation process by restarting auto-negotiation, or by setting forced speed mode after power has been applied. The processor must poll the link-up Register bit 1.2 for the corresponding LXT9785E port, or the link status change interrupt, to ensure that the link has been established. 4. A time-out must be connected wi th this feature so that if link is not established within a pre- determined time period (system dependant), the processor instructs the power supply to switch off. If link is not established prior to the expiration of the “link fail inhibit timer”, the LXT9785E restarts negotiation with DTE detection if auto-negotiation mode was used to establish link with the phone, and the DTE process is still enabled. The LXT9785E restarts negotiation without DTE detection if either forced speed mode is used to establish link with the phone, or the DTE process is disabled. 5. If power is applied and link is established, the system must still poll the Link Status Register bit 1.2 for the corresponding LXT9785E port or the link status change interrupt. This is required since link status is the only way to know when the Remote-Power DTE is removed or unplugged. On seeing the Link_Down condition, the processor instructs the power supply to switch off, and the DTE Discovery begins again or is disabled.

4.11.3 Management Interface and Control

The management and control of the DTE discovery process is via the MDIO port. Each port on the LXT9785E is capable of running the discovery process, thus each port is independently controlled. This is achieved by each port having a dedicated set of control and status bits. These bits are found in Register 27 as follows:

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Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 DTE DISCOVERY PROCESS ENABLE - Register Bit 27.6 (Dis_EN) R/W Default value = 0: Disabled. Register bit 27.6 controls the operation of the process. The discovery process is disabled when Register bit 27.6 = 0, and enabled when Register bit 27.6 = 1. The MAC controller sets Register bit 27.6 to a 1 when a port search for a DTE requiring power is desired. Once set, Register bit 27.6 remains = 1 until the MAC clears it, either by directly clearing it or by resetting the PHY . This allows the discovery process to continue to function if unsuccessful in detecting a DTE, without being continually re-enabled by the MAC. If Register bit 27.6 is set after link is established, no action is taken until after the link goes down. POWER ENABLE - Register Bit 27.4 (Power_EN) R Default value = 0: No Remote-Power DTE found. Register bit 27.4 contains the result of the discovery process. When Register bit 27.4 = 0, the discovery process has not found Remote-Power DTE, and when Register bit 27.4 = 1, the discovery process has potentially found a DTE requiring power. This indicates power should be applied to the Category 5 cable. Register bit 27.4 is polled by the MAC during the discovery process, and is cleared when the PHY is reset, when auto-negotiation is restarted, or when auto- negotiation is disabled. In the event of a discovery process being interrupted due to detection of an already powered link partner (auto-negotiation completion or Parallel Detection), Register bit 27.4 = 0. STANDARD LINK PARTNER DETECTED - Register Bit 27.3 (SLP_Det) R/W Clear on Read Default value = 0: No link partner found. When Register bit 27.3 = 1, a standard link partner has been detected by the LXT9785E (NLPs, MLT3 data, FLPs without next page support, or FLPs with non-matching next pages). This indicates power should not be applied to the Category 5 cable. When Register bit 27.3 = 0, other bits are checked to determine overall status of the link partner. Register bit 27.3 is cleared on read, or DTE discovery is disabled, link is established, or auto-negotiation is either restarted or disabled. LINK FAIL TIMEOUT - Register Bit 27.2 (LFIT Expired) R/W Clear on Read Default value = 0 (Link Fail Inhibit timer has expired without establishment of link with a standard link partner). Valid only when Standard Link Partner Detected Register bit 27.3 = 1. Register bit 27.2 is set if link is not established prior to the Link Fail Inhibit Timer expiring. This indicates that the Discovery process has restarted and the Standard Link Partner Detected Register bit may no longer be valid. Register bit 27.2 is cleared on read, or DTE discovery is disabled, link is established, or auto-negotiation is either restarted or disabled.

4.11.4 DTE Discovery Process Flow

The following section describes the DTE Discovery process.See Figure 30, “Intel® LXT9785E Negotiation Flow Chart” on page 156 for a flow chart of the discovery process.When DTE Discovery (27.6) and auto-negotiation (0.12) are enabled (auto-negotiation mode is required), the LXT9785E transmits the auto-negotiation base page with the next page ability bit set (“Auto- Negotiation Advertisement Register (Address 4)” on page 204). System software polls Register 27 to determine if or when a Remote-Power DTE is detected. The receiver monitors the line to determine if NLPs, MLT3 data, or FLP bursts are being received. If the receive activity is FLP bursts, the status of the next page ability bit is checked. If the detected “link partner” also supports next page, then the LXT9785E transmits out the next page sequence

in the logic (the LXT9785E ignores any data written into Register 7) and are outlined in Table 47. DTE Discovery process is stopped and the base page is used to determine the capability options. negotiation process (auto-negotiation or forced-speed mode). detect this non-link state and disable power.

4.11.5 DTE Discovery Behavior

Table 47. Next Page Message #5 Code Word Definitions

a is the acknowledge bit; t is the toggle bit; L is the LFSR

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Figure 30. Intel® LXT9785E Negotiation Flow Chart

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4.12 Monitoring Operations

4.12.1 Monitoring Au to-Negotiation

Auto-negotiation may be monitored as follows:

Bits 1.2 and 17.10 = 1 once the link is established.
Additional bits in Register 1 (refer to Table 84, “Status Register (Address 1)” on page 201) and Register 17 (refer to Table 93, “Quick Status Register (Address 17, Hex 11)” on page 209) can be used to determine the link operating conditions and status.

4.12.2 Per-Port LED Driver Functions

The LXT9785/LXT9785E incorporates three direct drive LEDs per port (LEDn_1, LEDn_2, and LEDn_3). Note: The BGA15 package only supports two LEDs per port (LEDn_1 and LEDn_2). On power up, all the LEDs lights up for approximately one second after reset de-asserts. Each LED may be programmed to one of several different display modes using the LED Configuration Register. Each per-port LED may be programmed (refer to Table 96, “LED Configuration Register (Address 20, Hex 14)” on page 213) to indicate one of the following conditions:

Operating Speed
Transmit Activity
Receive Activity
Collision Condition
Link Status
Duplex Mode
Isolate Condition The LEDs can also be programmed to display various combined status conditions. For example, setting bits 20.15:12 = 1101 produces the following combination of Link and Activity indications:
If Link is down, LED is off.
If Link is up, LED is on.
If Link is up AND activity is detected, the LED blinks at the stretch interval selected by bits 20.3:2 and continues to blink as long as activity is present. The LED driver pins are open drain circuits (10mA max current rating). Refer to “LED Circuit” on page 167 under the Application Information Section for LED circuit design details. The LED Configuration Register also provides optional LED pulse stretching to 30, 60, or 100 ms. If during this pulse stretch period, the event occurs again, the pulse stretch time is further extended (see Table 96, “LED Configuration Register (Address 20, Hex 14)” on page 213). When an event such as receiving a packet occurs, it is edge detected and starts the stretch timer. The LED driver remains asserted until the stretch timer expires. If another event occurs before the stretch timer expires, the stretch timer is reset and the stretch time extended.

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When a long event (such as duplex status) occurs, it is edge detected and starts the stretch timer. driver to remain asserted. Figure 31 on page 158 shows how the stretch operation functions.

4.12.3 Out-of-Band Signaling

signaling is disabled when Isolate mode is enabled by setting Register 0.10. Note: The BGA15 package does not support Out-of-Band Signaling nor the RMII interface. Table 98, “RMII Out-of-Band Signaling Register (Address 25, Hex 19)” on page 215). LXT9785/LXT9785E replaces the zeros with selected status bits during the IPG . Figure 31. Intel® LXT9785/LXT9785E LED Pulse Stretching Note: The direct drive LED outputs in this diagram are shown as active Low. Figure 32. Intel® LXT9785/LXT9785E RMII Programmable Out-of-Band Signaling

When network activity is detected, the LXT9785/LXT9785E asserts CRS_DV asynchronously with respect
After CRS_DV is asserted, the LXT9785/LXT9785E zero-stuffs the RxData bits until the received data has

been processed through the FIFO.

When network activity ceases, the LXT9785/LXT9785E de-asserts CRS_DV synchronously with respect

The LXT9785/LXT9785E includes an IEEE 1149.1 boundary scan test port for board level testing. All digital input, output, and input/output pins are accessible.

4.12.4 Boundary Scan Interface

TCK pin is internally pulled down. TDO does not have an internal pull-up or pull-down.

4.12.5 State Machine

4.12.6 Instruction Register

instructions are listed in Table 49.

4.12.7 Boundary Scan Register

Table 48. Refer to the Identification Information section in the LXT9785/LXT9785E Specification Update (document number 249357) for the JTAG ID numbers. Table 48. BSR Mode of Operation

1 Capture

3 Update

4 System Function

Table 49. Supported JTAG Instructions

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4.13 Cable Diagnostics Overview

Debugging cable problems increases the overall cost of owning and operating a local area network. Cable Diagnostic tools were incorporated into the LXT9785 device to help customers debug network cable problems. The Cable Diagnostic tools provide the ability to detect severe cable problems, such as open and short circuits, and determine the distance to the discontinuity.

4.13.1 Features

The following are three cases to consider for Cable Diagnostics:

Distance to a short circuit between wires of a single twisted-pair
An open circuit
Detection of an improperly terminated cable by the link partner. An improperly terminated cable will not meet IEEE 802.3 return loss requirements. Register 29 has been added to control cable testing and report cable testing results. Cable Diagnostics provides a method to determine the distance to opens and shorts when the link partner is inactive on the twisted-pair under test. The cable tests produce undefined results if the link partner is transmitting signals. Implementation methods may vary depending upon the system use requirements of Cable Diagnostics.

4.13.2 Operation

Cable Diagnostics utilizes the PHY transmit drivers and receivers to test a single twisted-pair. A transmit pulse is driven down the twisted-pair under test and the reflected signal is analyzed. Link partners transmitting NLP, FLP, MLT3, or other TDR pulses may interfere with the ability of the LXT9785 to properly analyze the reflected Cable Diagnostic pulse. Implementation algorithms must take these potential situations into consideration.

4.13.2.1 Short and Long Cable Testing Requirements

Implementing Cable Diagnostic tests, by enabling short and long cable tests sequentially, allows more accurate measurements to a detected fault. Both tests are necessary to reach full precision. The short and long cable tests can be run by writing 0x7400h and 0x6C00h to Register 29, respectively. See Section 4.13.4, “Basic Implementation” on page 161 for implementation details.

4.13.2.2 Precision

Cable Diagnostics estimates the distance to a fault up to 150 m. Category 5 or better cable produces the most accurate test results. Less than Category 5 cable may produce less accurate results on long cable lengths. Cable Diagnostics returns the distance to the closest fault, if a fault is present. Cable Diagnostic tests report the distance to a cable fault based on the velocity of signal propagation, which is used to determine the electrical length to the fault. The electrical length may vary slightly from the physical cable length. The measurement accuracy may vary by +/- 2 m. The following basic equation is used to calculate the distance to a fault: Distance_to_Fault = (Reg29[7:0] - 3.5) / 1.16

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4.13.3 Implementation Considerations

Before performing Cable Diagnostics, the twisted-pair to be tested may be verified to be inactive. All applicable link configurations should be attempted. Cable Diagnostic tests may be started if the attempts indicate no link partners are active. If link partners are detected, additional tests and decisions as to next steps may need to be implemented in the cable testing algorithm to ensure the most accurate results. Intel recommends that a 100BASE-TX link be attempted with MDI and MDIX enabled sequentially, prior to performing Cable Diagnostic testing, to determine if a 100BASE-TX-only link partner is present. If a link partner is in forced 100BASE-TX operation, transmitting MLT3, the Cable Diagnostic test result will be undefined due to the interference MLT3 causes in attempting to process the reflected Cable Diagnostic pulse. Auto MDI/MDIX on the link partner should be accounted for in deriving the cable testing algorithm. Intel recommends auto MDI/MDIX be disabled when running the cable tests. The transmit and receive twisted-pairs must be tested one at a time with both short and long cable test suites. The MDI/MDIX control bits in Table 99, “Trim Enable Register (Address 27, Hex 1B)” on page 216 can be used to select the twisted-pair to be tested. This requirement creates a minimum of four test permutations that must be completed to determine if the fault exists, the distance to the fault. If Cable Diagnostics testing is completed using a powered down LXT9785 device as the link partner, specific results can be expected. The results will indicate an open connection when the PWRDWN hardware configuration pin is used. These power-down methods disable the internal termination resistors to create a high impedance connection equivalent to an open circuit. If Transmit Disable (Register bit 16.13) or software controlled Power-Down (Register bit 0.11) is used, the powered down device transmit logic will look like an open circuit and the receive circuit will look like a 100 Ω terminated connection. The Transmit Disable bit and the software Power- Down bit disable the transmit circuit but do not affect the receive circuit. The result of Cable Diagnostic tests using an IP Phone indicate an open or a short fault at a gross approximation of the distance to the IP Phone. The termination resistors are not powered and do not create a proper termination. The filter circuit used by some manufacturers adversely affects the test results. Transmission and reception of packets is disabled when Cable Diagnostics is enabled. Internal loopback must be disabled for Cable Diagnostics to operate properly. Internal loopback disables the analog interface.

4.13.4 Basic Implementation

Register 29 is used to control and report the Cable Diagnostics test results. The function tests one pair of the twisted-pair cable at a time. The basic process flow is described as follows (see Table 100, “Cable Diagnostics Register (Address 29, Hex 1D)” on page 217 for Register 29 bit definitions): 1. Disable auto-negotiation by clearing Register bit 0.12, set to MDI by clearing Register bits 27.9:8, and ensure internal loopback is disabled, Register bit 0.14 = 0. 2. Write 0x7400h to Register 29. Setting these bits places the device in short cable Cable Diagnostics mode and forces link to drop. The device waits a specific amount of time (1.2 s to 1.5 s) to ensure link drops on any connected link partner, and initiates the Cable Diagnostics test on the selected twisted-pair.

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Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 3. Poll Register bit 29.9. When this bit is set, the test is complete and Register bits 29.7:0 contain a value used to determine if a cable fault was found and the distance to that fault. A value of 0xFFh indicates no fault was found. Any other value indicates a fault was found, that value should be stored for later use. 4. Write 0x6C00h to Register 29. Setting these bits places the device in long cable Cable Diagnostics mode. 6. If a fault is present, a calculation is used to determine the distance to the fault. Insert the smallest value recorded from Register bits 29.7:0 in steps 3 and 5 above into the following formula: Distance_to_Fault = (Reg29[7:0] - 3.5) / 1.16 Register bit 29.8 is set if the fault is detected as a short circuit and is cleared if the fault is detected as an open circuit. Register bits 29.12:11 are cleared when read and are cleared during the same read cycle when Register bit 29.9 is read, indicating a fault condition exists. 7. Normal PHY operation can be resumed by writing 0x4000h to Register 29 or by software or hardware reset. The test suite can be run again by resuming at step 2 above.

4.14 Link Hold-Off Overview

The PHY link is established as soon as the system platform powers-up. In many cases, the system platform is not capable of supporting network operation until configuration firmware is loaded. It is desirable in such cases to prevent the PHY from establishing a link until the system platform is fully configured and ready for network operation. Link Hold-Off was incorporated into the LXT9785 device to satisfy these requirements. Enabling Link Hold-Off disables the PHY Link capability until the system platform is fully capable of supporting network operation. The feature is enabled by hardware control at power-up or software control during normal operation.

4.14.1 Features

Link Hold-Off prevents the LXT9785 from establishing a link by disabling the analog transmit and receive capability. The digital capabilities of the PHY are unaffected including register access and LED operation. Link Hold-Off can be enabled by an external hardware pin for all ports or by software register access for individual ports. When Link Hold-Off is enabled, the transmitter and receiver on the selected ports are forced into software power-down mode (see Section 4.5.3, “Power-Down Mode” on page 127) to block signal activity from establishing a link and passing packets through the PHY . The hardware enabled Link Hold-Off is controlled by the LINKHOLD pin. Internal pull-down resistors hold the pin in the inactive state. Connecting a 5k pull-up resistor to the pin enables the feature at power-up reset or external hardware pin Reset. Once a PHY port is programmed as desired, clearing Register bit 0.11 will re-enable that port. Each port must be individually re- enabled. When a port is software reset, by setting Register 0.15, the state of the hardware configuration pin captured by the last hardware or power-up reset determines the default register values for the specific function for that port. Link Hold-Off, once enabled by hardware configuration, is re- enabled on a port by issuing a software reset for that port. It is not necessary to reset the entire PHY or switch system to re-enable Link Hold-Off.

LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Datasheet 163 Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 Link Hold-Off software control is enabled or disabled on individual ports by respectively setting or clearing Register bit 0.11, the power-down bit, during normal operation. It is not required to have previously enabled Link Hold-Off by hardware configuration. Link Hold-Off is disabled if the external pin MDDIS is active. The MDDIS pin disables the MDIO interface required to re-enable normal transmit and receive link operation. MDDIS is intended to disable the MDIO management interface for unmanaged applications. Internal loopback circuitry is unaffected in Link Hold-Off mode.

4.14.2 Operation

Link Hold-Off is implemented in one of the following two ways:

Using a hardware pin at power-up or hardware reset
Using software control through the MII Management (MDC/MDIO) interface. Link Hold-Off use by an external hardware pin is as follows: 1. Pull the LINKHOLD pin High with a pull-up resistor (approximately 5 k Ohms). 2. Power up the system or drive the reset pin active. 3. All ports are link disabled. 4. Program all ports to the desired configuration. 5. Clear Register Bit 0.11, power -down for each individual port. 6. Normal operation resumes on each port after Register bit 0.11 is cleared (see Table 83 for the recovery time). Link Hold-Off is enabled on a per port basis by software control using the following two methods: Method One: This method requires that Link Hold-Off is enabled by the LINKHOLD pin during the last power- up or hardware reset. 1. Set Register bit 0.15 to reset and re-enable Link Hold-Off for the desired port. 2. Program the PHY to th e desired configuration. 3. Clear Register bit 0.11 (power-down) to disable Link Hold-Off. 4. Normal operation resumes. Method Two: This method enables Link Hold-Off regardless of the LINKHOLD hardware configuration state. 1. Set Register bit 0.11(power-down) to enable Link Hold-Off for the desired port. 2. Program the PHY to th e desired configuration. 3. Clear Register bit 0.11 (power-down) to disable Link Hold-Off. 4. Normal operation resumes. Note: High is defined by the IO voltage supply level selected (2.5V or 3.3V).

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5.0 Application Information

5.1 Design Recommendations

The LXT9785/LXT9785E is designed to comply with IEEE 802.3 requirements to provide outstanding receive Bit Error Rate (BER), and long-line-length performance. To achieve maximum performance from the LXT9785/LXT9785E, attention to detail and good design practices are required. Refer to the LXT9785 Design and Layout Guide application note for detailed design and layout information.

5.2 General Design Guidelines

Adherence to generally accepted design practices is essential to minimize noise levels on power and ground planes. Up to 50 mV maximum of noise is considered acceptable. High-frequency switching noise can be reduced, and its effects eliminated, by following these simple guidelines throughout the design:

Fill in unused areas of the signal planes with solid copper and attach them with vias to a VCC or ground plane that is not located adjacent to the signal layer.
Use ample bulk and decoupling capacitors throughout the design (a value of 0.01µF is recommended for decoupling caps).
Provide ample power and ground planes.
Provide termination on all high-speed switching signals and clock lines.
Provide impedance matching on long traces to prevent reflections.
Route high-speed signals next to a continuous, unbroken ground plane.
Filter and shield DC-DC converters, oscillators, etc.
Do not route any digital signals between the LXT9785/LXT9785E and the RJ-45 connectors at the edge of the board.
Do not extend any circuit power and ground plane past the center of the magnetics or to the edge of the board. Use this area for chassis ground, or leave it void.

5.2.1 Power Supply Filtering

Power supply ripple and digital switching noise on the VCC plane may cause EMI problems and degrade line performance. The best approach to this problem is to minimize ground noise as much as possible using good general techniques and by filtering the VCC plane. It is generally difficult to predict in advance the performance of any design, although certain factors greatly increase the risk of having problems:

Poorly-regulated or over-burdened power supplies.
Wide data busses (32-bits+) running at a high clock rate.
DC-to-DC converters.

LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Datasheet 165 Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 Intel recommends filtering the power supply to the analog VCC pins of the LXT9785/LXT9785E. This has two benefits. First, it keeps digital switching noise out of the analog circuitry inside the LXT9785/LXT9785E, helping with line performance. Second, if the VCC planes are laid out correctly, digital switching noise is kept away from external connectors, reducing EMI problems. The recommended implementation is to break the VCC plane into two sections. The digital section supplies power to the VCCD and VCCIO pins of the LXT9785/LXT9785E. The analog section supplies power to the VCCA pins. The break between the two planes should run underneath the device. In designs with more than one the LXT9785/LXT9785E, a single continuous analog VCC plane can be used to supply them all. The digital and analog VCC planes should be joined at one or more points by ferrite beads. The beads should produce at least a 100 Ω impedance at 100 MHz. Beads should be placed so that current flow is evenly distributed. The maximum current rating of the beads should be at least 150% of the current that is actually expected to flow through them. A bulk cap (2.2 -10µF) should be placed on each side of each bead. In addition, a high-frequency bypass cap (0.01 µF) should be placed near each analog VCC pin.

5.2.2 Power and Ground Plan e Layout Considerations

Great care needs to be taken when laying out the power and ground planes.

Follow the guidelines in the LXT9785 Design and Layout Guide (formerly Application Note 151) for locating the split between the digital and analog VCC planes.
Keep the digital VCC plane away from the TPFOP/N and TPFIP/N signals, the magnetics, and the RJ-45 connectors.
Place the layers so that the TPFOP/N and TFPIP/N signals can be routed near or next to the ground plane. For EMI reasons, it is more important to shield TPFOP/N than TPFIP/N.

5.2.2.1 Chassis Ground

For ESD reasons, it is a good design practice to create a separate chassis ground that encircles the board and is isolated via moats and keep-out areas from all circuit-ground planes and active signals. Chassis ground should extend from the RJ-45 connectors to the magnetics, and can be used to terminate unused signal pairs (Bob Smith termination). In single-point grounding applications, provide a single connection between chassis and circuit grounds with a 2 kV isolation capacitor. In multi-point grounding schemes (chassis and circuit grounds joined at multiple points), provide 2 kV isolation to the Bob Smith termination.

5.2.3 MII Terminations

Series termination resistors are required on all the SS-SMII output signals driven by the LXT9785/ LXT9785E. Special trace layout consideration should be used when using the SMII interface. Keep all traces orthogonal and as short as possible. Whenever possible, route the clock and sync traces evenly between the longest and shortest data routes. This minimizes round-trip, clock-to-data delays and allows a larger margin to the setup and hold requirements.

5.2.4 Twisted-Pair Interface

Use the following standard guidelines for a twisted-pair interface:

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Place the magnetics as close as possible to the LXT9785/LXT9785E.
Keep transmit pair traces as short as possible; both traces should have the same length.
Avoid vias and layer changes as much as possible.
Keep the transmit and receive pairs apart to avoid cross-talk.
Route the transmit pair adjacent to a ground plane. The optimum arrangement is to place the transmit traces two to three layers from the ground plane, with no intervening signals.
Improve EMI performance by filtering the TPO center tap. A single ferrite bead rated at 400 mA may be used to supply center tap current to all ports.

5.2.4.1 Magnetic Requirements

application. Table 50 provides the magnetics requirements.

5.2.5 The Fiber Interface

interface designs and recommendations for Intel PHYs.

The transmit pair should be AC-coupled with 2.5 V supplies and re-biased to 3.3 V LVPECL levels

Table 50. Intel ® LXT9785/LXT9785E Magnetics Requirements

The transmit pair should contain a balance offset in the pull-up resistors to prevent PHY-to- fiber transceiver crosstalk amplification in power-down, loopback, and reset states (see fiber interface application note)
The receive pair should be DC-coupled with an emitter current path for the fiber transceiver
The signal detect pin should be DC-coupled with an emitter current path for the fiber transceiver Refer to the fiber transceiver manufacturer’s recommendations for termination circuitry. Figure 36 shows a typical example of an LXT9785/LXT9785E-to-3.3 V fiber transceiver interface. The following occurs in 5 V fiber transceiver applications as shown in Figure 37:
The transmit pair should be AC-coupled and re-biased to 5 V PECL input levels
The transmit pair should contain a balance offset in the pull-up resistors to prevent PHY-to- fiber transceiver crosstalk amplification in power-down, loopback, and reset states (see fiber interface application note)
The receive pair should be AC-coupled with an emitter current path for the fiber transceiver and re-biased to 1.2 V
The signal detect pin on a 5 V fiber transceiver interface should use the logic translator circuitry as shown in Figure 38. Refer to the fiber transceiver manufacturer’s recommendations for termination circuitry. Figure 37 shows a typical example of an LXT9785/LXT9785E-to-5 V fiber transceiver interface, while Figure 38 shows the interface circuitry for the logic translator.

5.2.6 LED Circuit

Figure 33 for a circuit illustration. Figure 33. LED Circuit

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5.3 Typical Application Circuits

LXT9785E. Figure 38 on page 172 shows the interface circuitry for the logic translator. Figure 34. Intel® LXT9785/LXT9785E Power and Ground Supply Connections

Figure 35. Intel® LXT9785/LXT9785E Typical Twisted-Pair Interface

The 100 Ω transmit load termination resistor typica lly required is integrated in the LXT9785/
The 100 Ω receive load termination resistor typically required is integrated in the LXT9785/

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Figure 36. Recommended Intel® LXT9785/LXT9785E-to-3.3 V Fiber Transceiver Interface

Refer to the transceiver manufacturers’ recommendations for termination circuitry.

Figure 37. Recommended Intel® LXT9785/LXT9785E-to-5 V Fiber Transceiver Interface

Refer to the transceiver manufacturers’ recommendations for termination circuitry.
See Figure 38 on page 172 for recommended logic translator interface circuitry.

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Figure 38. ON Semiconductor Triple PECL-to-LVPECL Translator

6.0 Test Specifications

recommended operating conditions specified in Table 52. Table 51. Intel ® LXT9785/LXT9785E Absolute Maximum Ratings for extended periods may affect device reliability. Table 52. Intel ® LXT9785/LXT9785E Operating Conditions (Sheet 1 of 2)

Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
Voltages with respect to ground unless otherwise specified.
Values are aggregated for all eight ports.

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Table 53. Intel ® LXT9785/LXT9785E Digital I/O DC Electrical Characteristics (VCCIO = 2.5 V +/-

Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

Table 52. Intel ® LXT9785/LXT9785E Operating Conditions (Sheet 2 of 2)

Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
Voltages with respect to ground unless otherwise specified.
Values are aggregated for all eight ports.

Table 54. Intel ® LXT9785/LXT9785E Digital I/O DC Electrical Characteristics (VCCIO = 3.3 V +/-

Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

Table 55. Intel ® LXT9785/LXT9785E Digital I/O DC Electrical Characteristics – SD Pins

2.5 V Operation

3.3 V Operation

Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
For 2.5 V operation, SD_2P5V = VCCPECL and VCCPECL=2.5 V.
For 3.3 V operation, SD_2P5V = GNDPECL or Floating and VCCPECL=3.3 V.

Table 56. Intel ® LXT9785/LXT9785E Required Clock Characteristics

Parameter is guaranteed by design; not subject to production testing.
Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

176 Datasheet

Table 57. Intel ® LXT9785/LXT9785E 100BASE-TX Transceiver Characteristics

Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
Measured at the line side of the transformer, line replaced by 100Ω (+/-1%) resistor.

Table 58. Intel ® LXT9785/LXT9785E 100BASE-FX Transceiver Characteristics

Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
20 - 80 percent into 100 Ω equivalent load of a typical fiber transceiver.

Table 59. Intel ® LXT9785/LXT9785E 10BASE-T Transceiver Characteristics

Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
Parameter is guaranteed by design; not subject to production testing.
After line model specified by IEEE 802.3 for 10BASE-T MAU.

178 Datasheet

Figure 39. Intel® LXT9785/LXT9785E SMII - 100BASE-TX Receive Timing Table 60. Intel ® LXT9785/LXT9785E SMII - 100BASE-TX Receive Timing Parameters

Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
“BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using

default configuration of 00 (32 bits of initial fill).

Figure 40. Intel® LXT9785/LXT9785E SMII - 100BASE-TX Transmit Timing Table 61. Intel ® LXT9785/LXT9785E SMII - 100BASE-TX Transmit Timing Parameters

Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
“BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using

default configuration of 00 (32 bits of initial fill).

180 Datasheet

Figure 41. Intel® LXT9785/LXT9785E SMII - 100BASE-FX Receive Timing Table 62. Intel ® LXT9785/LXT9785E SMII - 100BASE-FX Receive Timing Parameters

Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
“BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using

default configuration of 00 (32 bits of initial fill).

Figure 42. Intel® LXT9785/LXT9785E SMII - 100BASE-FX Transmit Timing Table 63. Intel ® LXT9785/LXT9785E SMII - 100BASE-FX Transmit Timing Parameters

Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
“BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using

default configuration of 00 (32 bits of initial fill).

182 Datasheet

Figure 43. Intel® LXT9785/LXT9785E SMII - 10BASE-T Receive Timing Table 64. Intel ® LXT9785/LXT9785E SMII - 10BASE-T Receive Timing Parameters

3 Synchronous sampling of SMII2

Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
Assumes each SMII segment is sampled for CRS.
“BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using

default configuration of 00 (32 bits of initial fill).

Figure 44. Intel® LXT9785/LXT9785E SMII - 10BASE-T Transmit Timing Table 65. Intel ® LXT9785/LXT9785E SMII-10BASE-T Transmit Timing Parameters

Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
“BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using

default configuration of 00 (32 bits of initial fill).

184 Datasheet

Figure 45. Intel® LXT9785/LXT9785E SS-SMII - 100BASE-TX Receive Timing Table 66. Intel ® LXT9785/LXT9785E SS-SMII - 100BASE-TX Receive Timing Parameters

Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
“BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using

default configuration of 00 (32 bits of initial fill).

Figure 46. Intel® LXT9785/LXT9785E SS-SMII - 100BASE-TX Transmit Timing Table 67. Intel ® LXT9785/LXT9785E SS-SMII - 100BASE-TX Transmit Timing

Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
“BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using

default configuration of 00 (32 bits of initial fill).

186 Datasheet

Figure 47. Intel® LXT9785/LXT9785E SS-SMII - 100BASE-FX Receive Timing Table 68. Intel ® LXT9785/LXT9785E SS-SMII - 100BASE-FX Receive Timing Parameters

Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
“BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using

default configuration of 00 (32 bits of initial fill).

Figure 48. Intel® LXT9785/LXT9785E SS-SMII - 100BASE-FX Transmit Timing Table 69. Intel ® LXT9785/LXT9785E SS-SMII - 100BASE-FX Transmit Timing Parameters

Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
“BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using

default configuration of 00 (32 bits of initial fill).

188 Datasheet

Figure 49. Intel® LXT9785/LXT9785E SS-SMII - 10BASE-T Receive Timing Table 70. Intel ® LXT9785/LXT9785E SS-SMII - 10BASE-T Receive Timing Parameters

Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
Assumes each SMII segment is sampled for CRS.
“BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using

default configuration of 00 (32 bits of initial fill).

Figure 50. Intel® LXT9785/LXT9785E SS-SMII - 10BASE-T Transmit Timing Table 71. Intel ® LXT9785/LXT9785E SS-SMII - 10BASE-T Transmit Timing Parameters

Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
“BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using

default configuration of 00 (32 bits of initial fill).

190 Datasheet

Figure 51. Intel® LXT9785/LXT9785E RMII - 100BASE-TX Receive Timing Table 72. Intel ® LXT9785/LXT9785E RMII - 100BASE-TX Receive Timing Parameters

Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
“BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
Values and conditions from RMII Specification, Rev. 1.2.

default configuration of 00 (32 bits of initial fill).

Figure 52. Intel® LXT9785/LXT9785E RMII - 100BASE-TX Transmit Timing Table 73. Intel ® LXT9785/LXT9785E RMII - 100BASE-TX Transmit Timing Parameters

Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
“BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using

default configuration of 00 (32 bits of initial fill).

192 Datasheet

Figure 53. Intel® LXT9785/LXT9785E RMII - 100BASE-FX Receive Timing Table 74. Intel ® LXT9785/LXT9785E RMII - 100BASE-FX Receive Timing Parameters

Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
“BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
Values and conditions from RMII Specification, Rev. 1.2.

default configuration of 00 (32 bits of initial fill).

Figure 54. Intel® LXT9785/LXT9785E RMII - 100BASE-FX Transmit Timing Table 75. Intel ® LXT9785/LXT9785E RMII - 100BASE-FX Transmit Timing Parameters

Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
“BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using

default configuration of 00 (32 bits of initial fill).

194 Datasheet

Figure 55. Intel® LXT9785/LXT9785E RMII - 10BASE-T Receive Timing Table 76. Intel ® LXT9785/LXT9785E RMII - 10BASE-T Receive Timing Parameters

Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
“BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
Values and conditions from RMII Specification, Rev. 1.2.

default configuration of 00 (32 bits of initial fill).

Figure 56. Intel® LXT9785/LXT9785E RMII - 10BASE-T Transmit Timing Table 77. Intel ® LXT9785/LXT9785E RMII - 10BASE-T Transmit Timing Parameters

Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
“BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using

default configuration of 00 (32 bits of initial fill).

196 Datasheet

Figure 57. Intel® LXT9785/LXT9785E Auto-Negotiation and Fast Link Pulse Timing Figure 58. Intel® LXT9785/LXT9785E Fast Link Pulse Timing Table 78. Intel ® LXT9785/LXT9785E Auto-Negotiation and Fast Link Pulse Timing Parameters

Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

198 Datasheet

Figure 61. Intel® LXT9785/LXT9785E Power-Up Timing Table 80. Intel ® LXT9785/LXT9785E Power-Up Timing Parameters

Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production
The minimum time required between bringing up consecutive ports powered down by Register bit 0.11, or

a software or hardware reset. Figure 62. Intel® LXT9785/LXT9785E Reset Recovery Timing Table 81. Intel ® LXT9785/LXT9785E Reset Recovery Timing Parameters

Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production

7.0 Register Definitions

The LXT9785/LXT9785E register set includes multiple 16-bit registers, 18 registers per port. provides a consolidated memory map of all registers. Negotiation” sections of the IEEE 802.3 standard. standard for adding unique chip functions. and in the table notes in individual register tables. Table 82. Intel ® LXT9785/LXT9785E Register Set (Sheet 1 of 2)

15 Extended Status Not Implemented

26 Reserved N/A

200 Datasheet

28 Reserved N/A

Table 83. Control Register (Address 0) (Sheet 1 of 2)

15 RESET 0 = Normal operation

14 Loopback

13 Speed Selection

12 Auto-Negotiation

11 Power-Down

10 Isolate

9 Restart

8 Duplex Mode 0 = Half-duplex

R/W = Read/Write, SC = Self Clearing when operation complete.
During a hardware reset, all LHR information is latched in from the pins. During a software reset (0.15), the

reset bit should be polled to see when the part has completed reset.

LSHR = Default value is derived from a single device input pin state or a group of device input pin states as

the pin(s) are latched at startup or hardware reset.

Default value of Register bits 0.12, 0.13, and 0.8 are determined by the CFG pins as described in Table 42,

“Intel® LXT9785/9785E Global Hardware Configuration Settings” on page 129.

Default value of Register bit 0.11 is determined by the LINKHOLD configuration pin.

Table 82. Intel ® LXT9785/LXT9785E Register Set (Sheet 2 of 2)

7 Collision Test

6 Speed Selection

1000 Mbps

Table 84. Status Register (Address 1)

8 Extended Status 0 = No extended status information in Register 15

7 Reserved Write as 0, ignore on Read R 0

6 MF Preamble

Bits that Latch High (LH) or Latch Low (LL) automatically clear when read.

Table 83. Control Register (Address 0) (Sheet 2 of 2)

R/W = Read/Write, SC = Self Clearing when operation complete.
During a hardware reset, all LHR information is latched in from the pins. During a software reset (0.15), the

reset bit should be polled to see when the part has completed reset.

LSHR = Default value is derived from a single device input pin state or a group of device input pin states as

the pin(s) are latched at startup or hardware reset.

Default value of Register bits 0.12, 0.13, and 0.8 are determined by the CFG pins as described in Table 42,

“Intel® LXT9785/9785E Global Hardware Configuration Settings” on page 129.

Default value of Register bit 0.11 is determined by the LINKHOLD configuration pin.

202 Datasheet

5 Auto-Negotiation

4 Remote Fault 0 = No remote fault condition detected

3 Auto-Negotiation

2 Link Status 0 = Link is down

1 Jabber Detect 0 = Jabber condition not detected

0 Extended Capability 0 = Basic register capabilities

Bits that Latch High (LH) or Latch Low (LL) automatically clear when read.

Table 85. PHY Identification Register 1 (Address 2) Table 86. PHY Identification Register 2 (Address 3)

0 Model Variant

Refer to the Identification Information section in the Intel® LXT9785/LXT9785E Specification Update.

Figure 63. PHY Identifier Bit Mapping The Intel OUI is 00207B hex.

204 Datasheet

Table 87. Auto-Negotiation Advertisement Register (Address 4)

15 Next Page

14 Reserved Write as 0, ignore on Read R 0

6 Remote Fault 0 = No remote fault

12 Reserved Write as 0, ignore on Read R/W 0

11 Asymmetric

10 Pause 5

NOTE: Default for the BGA15 package is 0. 0 = Port is not 100BASE-T X full-duplex capable.

R/W = Read/Write, R = Read Only
LSHR = Default value is derived from a single device input pin state or a group of device input pin states as

the pin(s) are latched at startup or hardware reset.

The default setting of Register bit 4.10 is determined by the PAUSE pin. The BGA15 package does not

have a Pause hardware configuration pin and has a default of 0.

Default settings for bits 4.5:8 are determined by CFG pins as described in Table 42, “Intel® LXT9785/

9785E Global Hardware Configuration Settings” on page 129.

Pause operation is only valid for full-duplex modes.
If Register bit 4.13 is set to advertise a fault, Register bit 1.4 will be set.

NOTE: Restart the auto-negotiation process whenever Register 4 is written/modified.

Table 88. Auto-Negotiation Link Partner Base Page Ability Register (Address 5)

15 Next Page 0 = Link partner has no ability to send multiple pages

14 Acknowledge

13 Remote Fault 0 = No remote fault

12 Reserved Write as 0, ignore on Read R 0

10 Pause 0 = Link partner is not Pause capable

Default value at the start of auto-negotiation code word transmission.

206 Datasheet

Table 89. Auto-Negotiation Expansion Register (Address 6)

4 Parallel

3 Link Partner

2 Next Page Able 0 = Local device is not next page able

1 Page Received

0 Link Partner

R = Read Only, LH = Latching High – cleared when read

Table 90. Auto-Negotiation Next Page Transmit Register (Address 7)

13 Message Page

12 Acknowledge 2

11 Toggle

R/W = Read Write, R = Read Only

Table 91. Auto-Negotiation Link Partner Next Page Receive Register (Address 8)

Default value at the start of auto-negotiation code word transmission.

Table 92. Port Configuration Register (Address 16, Hex 10) (Sheet 1 of 2)

15 Reserved Write as 0, ignore on Read R/W 0

14 Link Disable

13 Transmit Disable 0 = Normal operation

12 Bypass Scramble

11 Reserved Write as 0, ignore on Read R/W 0

10 Jabber

LSHR = Default value is derived from a single device input pin state or a group of device input pin states as

the pin(s) are latched at startup or hardware reset.

The default value of Register bit 16.0 is determined by the G_FX/TP

value of Register bit 16.0 = 1. The BGA15 package does not have a G_FX/TP hardware configuration pin.

The default value of Register bit 16.5 is determined by the PREASEL pin. The BGA15 package does not

have a PREASEL hardware configuration pin and has a default of 0.

The BGA15 package does not support fiber. Default for the BGA15 package is 0.
NA means the bits do not have a default value and may initially contain any value.

208 Datasheet

8 TP Loopback

Note: Valid function in SMII and S-SMII modes only.

6 Reserved Write as 0, ignore on Read R/W 0

5 Preamble Enable

10 Mbps

4 Reserved Write as 0, ignore on Read R/W 0

3 Reserved Write as 0, ignore on Read R/W 0

BGA15 Write as '0', ignore on Read (BGA15). Write as '0', ignore on Read (BGA15). NOTE: Default for BGA15 is 0. Table 92. Port Configuration Register (Address 16, Hex 10) (Sheet 2 of 2)

LSHR = Default value is derived from a single device input pin state or a group of device input pin states as

the pin(s) are latched at startup or hardware reset.

The default value of Register bit 16.0 is determined by the G_FX/TP pin.

value of Register bit 16.0 = 1. The BGA15 package does not have a G_FX/TP hardware configuration pin.

The default value of Register bit 16.5 is determined by the PREASEL pin. The BGA15 package does not

have a PREASEL hardware configuration pin and has a default of 0.

The BGA15 package does not support fiber. Default for the BGA15 package is 0.
NA means the bits do not have a default value and may initially contain any value.

Table 93. Quick Status Register (Address 17, Hex 11) (Sheet 1 of 2)

15 Reserved Write as 0, ignore on Read R 0

NOTE: The status is valid for TX and FX operation.

13 Transmit Status 0 = The LXT9785/LXT9785E is not transmitting a packet

12 Receive Status 0 = Packet has not been received since last read

11 Collision Status

10 Link 0 = Link is down

9 Duplex Mode 0 = Half-duplex

8 Auto-Negotiation

This signal is based upon Register bit 0.12.

7 Auto-Negotiation

6 FIFO Error 0 = No FIFO error occurred

R = Read Only, LH = Latching High – cleared when read.
The default values are updated on completion of reset and reflect the status or change in status at that

time. Intel recommends that the register status be read on completion of reset.

The default value is determined by the default value of Register bit 0.12.
LSHR = Default value is derived from a single device input pin state or a group of device input pin states as

the pin(s) are latched at startup or hardware reset.

Default values are set by the hardware configuration PAUSE pin. The BGA15 package does not have a

Pause hardware configuration pin. The default for the BGA15 package is 0.

210 Datasheet

4 Pause

NOTE: This bit is not affected by Register bit 4.10. NOTE: The default for the BGA15 package is 0. generated the error condition are read. Table 93. Quick Status Register (Address 17, Hex 11) (Sheet 2 of 2)

R = Read Only, LH = Latching High – cleared when read.
The default values are updated on completion of reset and reflect the status or change in status at that

time. Intel recommends that the register status be read on completion of reset.

The default value is determined by the default value of Register bit 0.12.
LSHR = Default value is derived from a single device input pin state or a group of device input pin states as

the pin(s) are latched at startup or hardware reset.

Default values are set by the hardware configuration PAUSE pin. The BGA15 package does not have a

Pause hardware configuration pin. The default for the BGA15 package is 0.

Table 94. Interrupt Enable Register (Address 18, Hex 12) aligned, and preamble is suppressed.

100 Mbps

8 CNTRMSK

6 SPEEDMSK

5 DUPLEXMSK

4 LINKMSK

3 ISOLMSK

2 Reserved Write as 0, ignore on Read R/W 0

In 10 Mbps operation, Register bit 18.13 = 1 cannot be used when Register bits 18.15:14 = “11” and in

becomes less than specified in the *IEEE 802.3 specification.

SFD Frame Alignment is applicable to SMII and SS-SMII only.
LSHR = Default value is derived from a single device input pin state or a group of device input pin states as
Default values are set by hardware configuration pins FIFOSEL1 and FIFOSEL0 (see Table 17, “Intel®

LXT9785/LXT9785E Receive FIFO Depth Considerations” on page 50).

212 Datasheet

Table 95. Interrupt Status Register (Address 19, Hex 13)

6 SPEEDCHG

5 DUPLEXCHG

4 LINKCHG

3 Isolate

R = Read Only, LH = Latching High – cleared when read
The default values are updated on completion of reset and reflect the status or change in status at that

time. Intel recommends that the register status be read on completion of reset.

Table 96. LED Configuration Register (Address 20, Hex 14) (Sheet 1 of 2)

Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up.

The secondary LED driver (Receive, Activity, or Error) causes the LED to change state (blink).

Combined event LED settings are not affected by Pulse Stretch Register bit 20.1. These display settings

are stretched regardless of the value of 20.1.

Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full-duplex.

Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs.

214 Datasheet

1 PULSE-

0 Reserved Write as 0, ignore on Read R/W 0

Table 97. Receive Error Count Register (Address 21, Hex 15) 16-bit counter remains full until cleared.

R = Read Only, LH = Latching High – cleared when read

NOTE: Intel recommends reading this register once every time link is established to clear the register. Table 96. LED Configuration Register (Address 20, Hex 14) (Sheet 2 of 2)

Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up.

The secondary LED driver (Receive, Activity, or Error) causes the LED to change state (blink).

Combined event LED settings are not affected by Pulse Stretch Register bit 20.1. These display settings

are stretched regardless of the value of 20.1.

Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full-duplex.

Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs.

Table 98. RMII Out-of-Band Signaling Register (Address 25, Hex 19) available on the RxData(1) bit of the RMII bus. available on the RxData(0) bit of the RMII bus.

0 PROGRMII

0 = Disable Out-of-Band signaling. Isolate mode is enabled by setting Register bit 0.10. NOTE: The BGA15 package does not support RMII operation.

216 Datasheet

Table 99. Trim Enable Register (Address 27, Hex 1B) (Sheet 1 of 2) NOTE: Values represent nominal load conditions.

7 Analog

NOTE: In fiber mode, SD for the port must be asserted.

6 D i s _ E N

DTE Discovery Process Enable.

4 Power_EN

turn on power over the cable.

LSHR = Default value is derived from a single device input pin state or a group of device input pin states as

the pin(s) are latched at startup or hardware reset.

Default values for Register bits 27.11:10 are determined by the TxSLEW pins.
Default value for Register bit 27.9 is determined by the AMDIX_EN pin.
Default value for Register bit 27.8 is determined by the MDIX pin. BGA15 does not support the MDIX

hardware configuration. The BGA15 default = 0.

R/W = Read/Write, R = Read Only, LH = Latching High – cleared when read.

3 SLP_Det

Standard Link Partner Detected. Note: This bit is only valid while link is down.

2 LFIT

Table 99. Trim Enable Register (Address 27, Hex 1B) (Sheet 2 of 2)

LSHR = Default value is derived from a single device input pin state or a group of device input pin states as

the pin(s) are latched at startup or hardware reset.

Default values for Register bits 27.11:10 are determined by the TxSLEW pins.
Default value for Register bit 27.9 is determined by the AMDIX_EN pin.
Default value for Register bit 27.8 is determined by the MDIX pin. BGA15 does not support the MDIX

hardware configuration. The BGA15 default = 0.

R/W = Read/Write, R = Read Only, LH = Latching High – cleared when read.

Table 100. Cable Diagnostics Register (Address 29, Hex 1D) (Sheet 1 of 2) settings are reserved and should not be used.

10 CD_EN

R/W = Read/Write, R = Read only, LH = Latching High, cleared when read
Recommended default value.

218 Datasheet

9 Test_Done

8 Fault_Type 0 = Open condition has been detected

Table 100. Cable Diagnostics Register (Address 29, Hex 1D) (Sheet 2 of 2)

R/W = Read/Write, R = Read only, LH = Latching High, cleared when read
Recommended default value.

LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Datasheet 219 Document Number: 249241 Revision Number: 007 Reg Title Bit Fields Addr B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Control Register (Address 0) Control Reset Loopback Speed Select A/N Enable Power Down Isolate Re-start A/N Duplex Mode COL Test Speed Select Reserved 0 Status Register (Address 1) Status 100Base-T4 100Base- X Full- Duplex 100Base-X Half-Duplex Fault A/N Ability Link Status Jabber Detect Extended Capability 1 PHY ID Registers (Address 2 and 3) PHY ID 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2 PHY ID2 PHY ID No MFR Model No MFR Rev No Model Va r i a n t 3 Auto-Negotiation Advertisement Register (Address 4) A/N Advertise Next Page Reserved Remote Fault Reserved Asymm Pause Pause 100Base-T4 100Base- TX Full- Duplex 100Base- TX 10Base-T Full-Duplex 10Base-T IEEE Selector Field 4 Auto-Negotiation Link Partner Base Page Ability Register (Address 5) A/N Link Ability Next Page Ack Remote Fault Reserved Asymm Pause Pause 100Base-T4 100Base- TX Full- Duplex 100Base- TX 10Base-T Full-Duplex 10Base-T IEEE Selector Field 5 Auto-Negotiation Expansion Register (Address 6) A/N Expansion Reserved Base Page Parallel Detect Fault Link Partner Next Page Able Next Page Able Page Received Link Partner A/N Able Auto-Negotiation Next Page Transmit Register (Address 7) A/N Next Page Txmit Next Page Reserved Message Page Ack 2 Toggle Message / Unformatted Code Field 7 Auto-Negotiation Link Partner Next Page Ability Register (Address 8) A/N Link Next Page Next Page Ack Message Page Ack 2 Toggle Message / Unformatted Code Field 8 Port Configuration Register (Address 16)

220 Datasheet

Table 101. Intel® LXT9785/LXT9785E Register Bit Map (Sheet 2 of 2)

8.0 Package Specifications

Figure 64. Intel® LXT9785/LXT9785E 208-Pin PQFP Plastic Package Specification

Part Number LXT9785HC, LXT9785EHC, LXT9785HE
Commercial Temperature Range (0°C to 70°C)
Extended Temperature Range (-40°C to +85°C)

222 Datasheet

Figure 65. Intel® LXT9785/LXT9785E 241-Ball BGA23 Package Specs - Top/Side View

14.70 REF

Figure 66. Intel® LXT9785/LXT9785E 241-Ball BGA23 Package Specs - Bottom View

241 BGA

LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers

224 Datasheet

Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 Intel® LXT9785/LXT9785E 241-Ball BGA23 Package Dimensions Symbol Min Nominal Max Units Note A 2.19 2.38 2.57 mm A1 0.50 0.60 0.70 mm A2 1.12 1.17 1.22 mm D 22.90 23.00 23.10 mm D1 19.30 19.50 19.70 mm E 22.90 23.00 23.10 mm E1 19.30 19.50 19.70 mm e 1.27 (solder ball pitch) mm I 1.34 REF. mm J 1.34 REF. mm M 17 x 17 Matrix mm b 0.60 0.75 0.90 mm c 0.52 0.56 0.60 mm e 1.27 mm All dimensions and tolerances conform to ANSI Y14.5-1982. Dimension is measured at maximum solder ball diameter parallel to primary datum (-C-). Primary datum (-C-) and seating plane are defined by the spherical crowns of the solder balls.

Figure 67. Intel® LXT9785MBC 196-Ball BGA15 Package Specs - Top/Side View (LXT9785MBC)

226 Datasheet

Table 102. Intel® LXT9785MBC 196-Ball BGA15 Package Dimensions defined by the spherical crowns of the solder balls.

9.0 Ordering Information

Table 103. Product Information

228 Datasheet

Figure 68. Ordering Information - Sample

Product Information

FAIXEPCD0SE000 specifications and overview.

Summary

Advanced 8-Port 10/100 Mbps PHY Transceivers

Description

Advanced 8-Port 10/100 Mbps PHY Transceivers

Source title FAIXEPCD0SE000 Datasheet(PDF) - Intel Corporation

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